CN118034479A - Control method and device - Google Patents

Abstract

The application discloses a control method and a control device, wherein the method comprises the following steps: in response to target equipment operating in a target mode, triggering a first object in the target equipment to execute target operation at a target triggering moment; the target mode and the target trigger moment have a specified corresponding relation; the target trigger moment corresponds to a stage in a power-on time sequence of the target equipment; responding to the target operation, triggering a second object in the target equipment to control a third object in the target equipment to be in a target state at a target adjustment moment; wherein the second object is the same as or different from the first object.

Description

Control method and device

Technical Field

The present application relates to the field of computer technologies, but not limited to, and in particular, to a control method and apparatus.

Background

As the process of computer chip approaches physical limits, the related art mostly adopts a way of increasing the number of chip cores to improve the chip performance. However, the increase in the number of chip cores results in an increase in power consumption of the computer, which in turn increases the instantaneous current required at the time of computer start-up. Thus, for a factory or office environment where computers are deployed on a large scale, a large instantaneous current is generated if the computers are started at the same time, which presents a great challenge to a power supply system, and the large instantaneous current can impact other devices in the same circuit network. In this regard, it is proposed how to solve the problem that the instantaneous current generated by the simultaneous start of a plurality of computers in the same office environment is high.

Disclosure of Invention

In view of this, the present application provides at least a control method and apparatus.

The technical scheme of the application is realized as follows:

In one aspect, the present application provides a control method, the method comprising:

In response to target equipment operating in a target mode, triggering a first object in the target equipment to execute target operation at a target triggering moment; the target mode and the target trigger moment have a specified corresponding relation; the target trigger moment corresponds to a stage in a power-on time sequence of the target equipment;

responding to the target operation, triggering a second object in the target equipment to control a third object in the target equipment to be in a target state at a target adjustment moment; wherein the second object is the same as or different from the first object.

In some embodiments, the target mode includes at least one of a first mode and a second mode; the target trigger time comprises at least one of a first trigger time and a second trigger time; the first trigger time corresponds to a stage after the verification of a basic input/output system of the target equipment is completed in a power-on time sequence of the target equipment; the second trigger time corresponds to a stage before starting a main board power supply of the target equipment in a power-on time sequence of the target equipment;

The method comprises the steps of responding to the operation of target equipment in a target mode, triggering a first object in the target equipment to execute target operation at a target triggering moment, and at least one of the following steps:

Triggering the first object to execute the target operation at the first triggering moment when the target mode comprises the first mode;

and triggering the first object to execute the target operation at the second triggering moment when the target mode comprises the second mode.

In some embodiments, the target operation is to delay the initiation of the third object; the third object comprises a main board power supply of the target device; the target state includes a start-up state;

The triggering the first object to execute the target operation at the first triggering moment comprises the following steps:

Triggering the first object to generate first duration data; wherein the first time length data represents delay time length data corresponding to the delay operation;

the responding to the target operation, triggering a second object in the target equipment to control a third object in the target equipment to be in a target state at a target adjustment moment, and comprises the following steps:

triggering the second object to start the third object after the first time length data; wherein the second object is identical to the first object.

In some embodiments, the triggering the first object to generate first duration data includes:

Triggering the first object to determine the first duration data by using a specified first random number algorithm; the first time length data is smaller than the second time length data, and the second time length data represents the maximum time delay time length data corresponding to the target operation.

In some embodiments, the second duration data is read from a target storage device by the first object and stored to a storage space of the first object when the target device last entered a shutdown procedure.

In some embodiments, the target operation is to delay the initiation of the third object; the third object comprises a main board power supply of the target device; the target state includes a start-up state;

The triggering the first object to execute the target operation at the second triggering moment comprises the following steps:

Triggering the first object to generate fourth proportion data; wherein the fourth proportion data represents delay proportion data corresponding to the delay operation;

the responding to the target operation, triggering a second object in the target equipment to control a third object in the target equipment to be in a target state at a target adjustment moment, and comprises the following steps:

Triggering the second object to control the third object to be in a starting state at a target adjustment moment based on the fourth proportion data; wherein the second object is different from the first object.

In some embodiments, the triggering the first object to generate fourth scale data includes:

triggering the first object to determine the fourth proportion data by utilizing fifth data and a specified second random number algorithm; wherein the fifth data includes one of: real-time data related to a start-up procedure of the target device, identification data related to the target device, and any random number.

In some embodiments, the second trigger time includes one of a third trigger time and a fourth trigger time; the third triggering moment corresponds to a stage before a user triggers a power control key of the target device in a power-on time sequence of the target device; the fourth triggering moment corresponds to a stage after the user triggers the power control key in the power-on time sequence of the target equipment;

and when the second trigger time includes the third trigger time, the triggering the second object to control the third object to be in a start state at a target adjustment time based on the fourth proportion data includes:

and responding to the triggering of the power control key by a user, triggering the second object to control the third object to be in a starting state at the target adjustment moment based on the fourth proportion data.

In some embodiments, the triggering the second object to control the third object to be in a start state at a target adjustment time based on the fourth scale data includes one of:

Triggering the control circuit to determine sixth duration data based on the fourth scale data and maximum delay duration data stored in the second object, if the second object includes the control circuit; triggering the control circuit to start the third object after the sixth time length data;

Triggering the first object to determine seventh duration data based on the fourth proportion data and the maximum delay duration data of the delay circuit stored in the first object under the condition that the second object comprises the delay circuit; triggering the first object to control a target pin in the delay circuit to be at a first potential in the seventh time length data, so that the third object is in the starting state after the seventh time length data.

In another aspect, the present application provides a data processing apparatus, the apparatus comprising:

The triggering module is used for responding to the operation of the target equipment in the target mode and triggering a first object in the target equipment to execute target operation at the target triggering moment; the target mode and the target trigger moment have a specified corresponding relation; the target trigger moment corresponds to a stage in a power-on time sequence of the target equipment;

The adjusting module is used for responding to the target operation and triggering a second object in the target equipment to control a third object in the target equipment to be in a target state at the target adjusting moment; wherein the second object is the same as or different from the first object.

In yet another aspect, the application provides a computer device comprising a memory and a processor, the memory storing a computer program executable on the processor, the processor implementing some or all of the steps of the above method when the program is executed.

In yet another aspect, the application provides a computer readable storage medium having stored thereon a computer program which when executed by a processor performs some or all of the steps of the above method.

In yet another aspect, the present application provides a computer program comprising computer readable code which, when run in a computer device, causes a processor in the computer device to perform some or all of the steps for carrying out the above method.

In yet another aspect, the application provides a computer program product comprising a non-transitory computer readable storage medium storing a computer program which, when read and executed by a computer, performs some or all of the steps of the above method.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the aspects of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.

FIG. 1 is a schematic diagram of an implementation flow of a control method according to the present application;

FIG. 2 is a schematic flow chart illustrating an implementation of one embodiment of a control method according to the present application;

FIG. 3 is a schematic flow chart of another embodiment of a control method according to the present application;

FIG. 4 is a schematic flow chart of a control method according to another embodiment of the present application;

FIG. 5 is a schematic diagram of the composition structure of a control device according to the present application;

fig. 6 is a schematic diagram of a hardware entity of a computer device according to the present application.

Detailed Description

The technical solution of the present application will be further elaborated with reference to the accompanying drawings and examples, which should not be construed as limiting the application, but all other embodiments which can be obtained by one skilled in the art without making inventive efforts are within the scope of protection of the present application.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.

The term "first/second/third" is merely to distinguish similar objects and does not represent a particular ordering of objects, it being understood that the "first/second/third" may be interchanged with a particular order or precedence, as allowed, to enable embodiments of the application described herein to be implemented in other than those illustrated or described herein.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing the application only and is not intended to be limiting of the application.

In order to better understand the control method provided by the embodiment of the present application, a description will be given of a solution adopted in the related art.

In the related art, in order to solve the problem that a plurality of computers are simultaneously started to generate high instantaneous current in the same office environment, the following two main solutions are proposed:

The first scheme is to increase the power supply capacity of a power supply system so as to support the simultaneous starting of a corresponding number of computers;

Scheme II: in a factory or office environment where multiple computers are deployed, programmable logic controllers (Programmable Logic Controller, PLCs) are introduced to control the computers to start up in batches, thereby reducing the number of computers that are simultaneously started up, and reducing instantaneous current.

Both of the above solutions have problems: in the first scheme, the cost is increased due to the increased power supply capability of the functional system, and the computer only has a problem of large current impact at the moment of simultaneous starting, so that the increased power supply capability is in an idle state most of the time, resulting in redundant power supply capability; in the second scheme, additional PLC equipment is required, and maintenance is required for professional PLC programmers, which also has the problem of increasing cost.

Based on this the application provides a control method which can be executed by a computer device. The computer device may be a server, a notebook computer, a tablet computer, a desktop computer, an intelligent television, a set-top box, or other devices with data processing capability.

Fig. 1 is a schematic implementation flow chart of a control method provided by the present application, as shown in fig. 1, the method includes steps S101 to S102 as follows:

step S101, in response to target equipment running in a target mode, triggering a first object in the target equipment to execute target operation at a target triggering moment; the target mode and the target trigger moment have a specified corresponding relation; the target trigger time corresponds to a stage in a power-on time sequence of the target device.

Here, the target device refers to a controlled object in the control method provided by the present application, and is also a subject for executing the control method.

The target operation is a preset operation. In some embodiments, the target operation includes a latency operation initiated for the target device.

The target trigger time refers to the starting time of executing the target operation. Here, the target trigger time corresponds to a stage in the power-on timing of the target device, that is, the target time is a specified stage before the target device completes the startup.

In some embodiments, the target trigger time may be determined based on each significant power-up node in the target device power-up timing.

For example, before a power adapter of the target device connects to a power supply, providing RTC power to a south bridge of the target device by a Real Time Clock (RTC) power supply within the target device; after the adapter is connected with a power supply, 5V voltage is provided for an embedded controller (Embeded Controller, EC), a field programmable logic array (Field Programmable GATE ARRAY, FPGA), a complex programmable logic device (Complex Programmable logic device, CPLD) and the like, so that the adapter can work, and target equipment enters a standby state; after the user presses the power control key, the EC checks the Basic Input/Output System (BIOS) to determine the integrity of the BIOS; after the integrity of the BIOS is confirmed, the power supply of the main board is controlled to be powered on, and 12V or 19V voltage is provided for a memory, a display card, a central processing unit (Center Processing Unit, CPU) and the like, so that the power-on is completed.

In this way, the time when the power adapter of the target device connects to the power supply, the time when the user presses the power control key, and the time when the EC checks the integrity of the BIOS can be used as the time node for dividing the time phase where the target trigger time is located.

The target mode refers to a manner of triggering a target operation in the electronic device. Here, the target pattern has a specified correspondence with the target trigger time, that is, the target trigger time at which the first object in the target device performs the target operation may be determined based on the target pattern corresponding to the target device.

In some embodiments, the target mode may be a default mode in the target device, or may be a mode of configuration by the user in a configuration option.

The first object is a component in the target device for executing the underlying control logic, for example, the first object is a component in the target device for executing the control before the motherboard power is started.

In some embodiments, the first object may include EC, FPGA, CPLD or a Super Input/Output chip (SIO) or the like.

Step S102, in response to the target operation, triggering a second object in the target equipment to control a third object in the target equipment to be in a target state at a target adjustment moment; wherein the second object is the same as or different from the first object.

Here, the second object in the target device is the same or different object from the first object.

In some embodiments, the second object is determined based on a target pattern corresponding to the target device, i.e., the target pattern has a specified correspondence with the second object controlling the state of the third target object.

In some embodiments, the second object may include EC, FPGA, CPLD, an embedded control super input Output chip (Embedded controller Super Input/Output, eSIO), or a micro control unit (Microcontroller Unit, MCU) or delay circuit in the motherboard power supply, etc.

The third object is a different object in the target device than the first object.

In some embodiments, the third object may include a motherboard power supply, BIOS, CPU, graphics card, and/or memory of the target device.

The target state is different power supply states and/or starting states corresponding to the target equipment.

In some embodiments, the target state may include a power-up state, a start-up state, a sleep state, or a power-down state, etc., corresponding to the target device.

The target adjustment time refers to a time determined based on the target operation for adjusting the state of the third object.

For example, when the target operation is a start-up delay operation for the third object, the target adjustment time refers to the start-up time of the third object determined based on the delay operation.

In the control method provided by the application, the first object in the target equipment is triggered to execute the target operation at the target triggering moment by responding to the target equipment running in the target mode, and then the second object in the target equipment is triggered to control the third object in the target equipment to be in the target state at the target adjusting moment by responding to the target operation, wherein the second object is the same as or different from the first object. The above processes are all controlled at the equipment end rather than the power supply end, on one hand, the state adjustment of the third object in the target equipment is automatically completed by using the first object in the target equipment, and the state adjustment process is realized without using an additional control circuit or equipment, so that the method has the effects of easiness in realization and cost saving; on the other hand, different operation modes are set for the target equipment, and the different operation modes correspond to different target trigger moments and target adjustment moments, so that a user can select a proper equipment operation mode according to actual operation requirements, and further the use experience of the user is improved.

In some embodiments, the target mode includes at least one of a first mode and a second mode; the target trigger time comprises at least one of a first trigger time and a second trigger time; the first trigger time corresponds to a stage after the verification of a basic input/output system of the target equipment is completed in a power-on time sequence of the target equipment; the second trigger time corresponds to a stage before starting a main board power supply of the target equipment in a power-on time sequence of the target equipment;

In this way, in response to the target device operating in the target mode, triggering the first object in the target device to perform the target operation at the target trigger time, that is, the above step S101, may be implemented as at least one of the following steps S1011 and S1012:

step S1011 of triggering the first object to execute the target operation at the first trigger time in a case where the target mode includes the first mode;

step S1012, where the target mode includes the second mode, triggering the first object to execute the target operation at the second triggering time.

Here, verifying the BIOS means that when the firmware system of the electronic device is started, the firmware system is measured and security verified, and if there is an error or security problem in the firmware system, a recovery operation is performed. Therefore, the BIOS is verified in the power-on time sequence of the electronic equipment to complete the characterization of the firmware system of the electronic equipment in a complete and safe state.

The first trigger time corresponds to a stage after the BIOS of the target device is checked in the power-on time sequence of the target device, namely, in the first mode, the first object in the target device executes the target operation after the completion and safety of the BIOS system are determined.

The main board power supply is started, and the characterization starts to supply power for parts with higher power consumption such as a CPU. As shown above, the voltage required for the CPU, graphics card, memory, and hard disk during part of the operation phase is 12V, which is higher than the voltage required for other components on the target device motherboard. Therefore, when the main board power supply is started, a high instantaneous current is generated.

The second trigger time corresponds to a stage before the main board power supply of the target device starts in the power-on time sequence of the target device, that is, in the second mode, the first object in the target device executes the target operation before the main board power supply starts.

In the above embodiment, in the case where the target mode includes only the first mode or only the second mode, the first object performs the target operation only at the first trigger timing or only at the second trigger timing; in the case where the target pattern includes both the first pattern and the second pattern, the first object performs the target operation at both the first trigger time and the second trigger time, and accordingly, in step S102, in response to the two target operations, the later adjustment time determined based on the two target operations is taken as the target adjustment time.

In some embodiments, the target operation is to delay the initiation of the third object; the third object comprises a main board power supply of the target device; the target state includes a start-up state;

The triggering the first object to perform the target operation at the first triggering time, that is, the above step S1011, may be implemented as the following step S1013:

Step S1013, triggering the first object to generate first duration data; wherein the first time length data represents delay time length data corresponding to the delay operation.

Here, the first time length data represents delay time length data for controlling the main board power supply in the target device to delay to enter the starting state.

In some embodiments, the first duration data may be determined based on a number of devices in a cluster of devices including the target device. For example, in the case that the number of devices in the device cluster is N, the first object may determine the first time length data to be an arbitrary value smaller than N, so as to perform the decentralized processing on the start-up time of each device in the device cluster under the condition that the start-up time of the devices in the device cluster is not too long, thereby reducing the problem of excessive instantaneous current caused by simultaneous start-up of a large number of electronic devices.

In some embodiments, the first duration data is determined based on power information of a power source powering the device cluster and a maximum instantaneous power information at start-up of each electronic device in the device cluster. For example, in the case where the power of the power source that supplies power to the device cluster is P and the maximum instantaneous power at the time of starting up each electronic device is P, the maximum number of electronic devices that can be started up simultaneously may be calculated based on the instantaneous power P corresponding to each electronic device and the power P of the power source; then, grouping the electronic devices in the device cluster, wherein the number of the electronic devices contained in each group is equal to or less than the maximum number; and further determining delay time length data corresponding to the electronic equipment in each group, namely, first time length data.

The triggering the second object in the target device to control the third object in the target device to be in the target state at the target adjustment time in response to the target operation, that is, the step S102 may be implemented as the following step S1021:

Step S1021, triggering the second object to start the third object after the first duration data; wherein the second object is identical to the first object.

Here, after the first object generates the first time-length data, the first time-length data is transmitted to the second object so that the second object starts the third object after the first time-length data.

In some embodiments, where the second object includes control circuitry, the control circuitry may be utilized to control the second object to launch the third object after the first time period data; in the case where the second object does not include control circuitry, a delay circuit may be used to control the third object to start after the first duration data.

Here, the first object is the same as the second object, that is, when the power supply motherboard of the target device is subjected to start-up delay control, control with a logic control circuit may be utilized without modifying the hardware structure of the target device. In some embodiments, the first object and the second object are EC, FPGA, CPLD or eSIO.

In some embodiments, the step S1013 described above may be implemented as the following step S1014:

Step S1014, triggering the first object to determine the first duration data by using a specified first random number algorithm; the first time length data is smaller than the second time length data, and the second time length data represents the maximum time delay time length data corresponding to the target operation.

Here, the first random number algorithm may include any one of a linear congruence algorithm, a merson rotation algorithm, a lafite-rosenfeld algorithm, and the like. Here, the first random number algorithm is not particularly limited.

In some embodiments, the first time-length data may be determined based on any real-time data associated with a boot process of the target device and the first random number algorithm.

In some embodiments, the first time-length data may be determined based on any identification data associated with a boot process of the target device and the first random number algorithm.

In some embodiments, the first time-length data may be determined based on any random data obtained by the first object and the first random number algorithm.

Here, the second time length data is pre-stored maximum delay time length data corresponding to the target operation, and the second time length data is not smaller than the first time length data. Therefore, by setting the maximum time delay duration data, the main board power supply of the target device can be ensured to be started within the maximum time delay duration acceptable to the user. The second duration data may be configured individually by the user based on the requirement, or may be configured by default, which is not limited in this embodiment.

In some embodiments, the second duration data is read from a target storage device by the first object and stored to a storage space of the first object when the target device last entered a shutdown procedure.

Here, the target storage device may be a device that can be accessed by the first object before the main board power supply of the target device enters the start-up state.

In some embodiments, the target storage device may be a BIOS chip storage device of the target device, or may be a hard disk device that may be accessed by the first object before the motherboard power supply enters the startup state, or the like.

In some embodiments, the target storage device stores default second duration data, and may also store second duration data set by the user. In this way, under the condition that the second duration data set by the user is not available, when the target device enters the shutdown program last time, the first object reads and stores default second duration data from the target storage device; or under the condition that the user does not set the customized second time length data, when the target device enters the shutdown program last time, after confirming that the user does not set the customized second time length data, the first object does not read the default second time length data from the target storage device, but executes subsequent operation by utilizing the default second time length data stored in the first object; and under the condition that the user sets the customized second time length data, the first object reads and stores the second time length data set by the user from the target storage device when the target device enters the shutdown program last time.

In some embodiments, the first time duration data may also be determined based on the second time duration data and the first random number algorithm.

In the above embodiment, after the target device completes the verification of the BIOS, the first object is triggered to generate the first duration data, and the second object controls the main board power supply of the target device to enter the start state after generating the first duration data, so as to realize the effect of controlling the delay start of the target device.

In some embodiments, the target operation is to delay the initiation of the third object; the third object comprises a main board power supply of the target device; the target state includes a start-up state;

The triggering the first object to perform the target operation at the second triggering time, that is, the step S1012 may be implemented as the following step S1015:

Step S1015, triggering the first object to generate fourth scale data; wherein the fourth proportion data characterizes delay proportion data corresponding to the delay operation.

Here, the first object is triggered to generate fourth scale data in response to the motherboard power supply of the target device being in an inactive phase.

In some embodiments, the first object may include one of EC, FPGA, CPLD and eSIO.

The fourth ratio data characterizes the ratio data of the delay time length of the delay operation for the main board power supply relative to the longest delay time length.

In some embodiments, the fourth ratio data may be percentage example data, i.e., the longest delay time is divided into 100 parts, and the fourth ratio data is determined based on the divided 100 parts.

In some embodiments, the fourth scale data may be any scale data, i.e., the longest delay time may be divided into M parts and the fourth scale data may be determined based on the divided M parts.

In some embodiments, the value of M may be determined based on byte data in the logic control circuitry of the first object and/or the second object for storing delay time duration information. For example, if the delay time length information is stored in the logic control circuit of the first object and/or the second object using 8 bytes, since the maximum value that can be stored for 8 bytes is 256, the value of M can be determined to be 256.

In some embodiments, the triggering the first object to generate the fourth scale data, i.e., the step S1015, may be implemented as the following step S1016:

step S1016, triggering the first object to determine the fourth proportion data by utilizing fifth data and a specified second random number algorithm; wherein the fifth data includes one of: real-time data related to a start-up procedure of the target device, identification data related to the target device, and any random number.

Here, the second random number algorithm may include any one of a linear congruence algorithm, a merson rotation algorithm, a lafite-rosenfeld algorithm, and the like. Here, the first random number algorithm is not particularly limited.

The second random number algorithm may be the same as or different from the first random number algorithm described above.

In some embodiments, the fifth data includes real-time data related to a boot process of the target device, such as time information for a user to connect a power adapter of the target device to a power source, time information for a user to press a power button, and so forth.

In some embodiments, the fifth data includes identification data related to the target device, for example, physical number information of devices such as a motherboard, a motherboard power supply, a CPU, a display card, a memory, and a hard disk of the target device, number information of the target device in a device cluster, and so on.

In some embodiments, the fifth data includes any random number, e.g., the first object of the target device reads random data from an empty pin of the first object that is not connected to other devices, and so on.

Thus, in response to the second trigger time, the first object is triggered to determine fourth scale data using the fifth data and the second random number algorithm.

In this way, in response to the target operation, triggering the second object in the target device to control the third object in the target device to be in the target state at the target adjustment time, that is, the step S102 described above may be implemented as the following step S1022:

step S1022, triggering the second object to control the third object to be in a starting state at the target adjustment moment based on the fourth proportion data; wherein the second object is different from the first object.

Here, the second object is different from the first object, that is, in the second mode, fourth scale data is generated in response to the first object, the fourth scale data is received from the first object by the second object in the target device, and the start-up state of the main board power supply is controlled based on the fourth scale data.

In some embodiments, the second object may include a motherboard power supply in the target device. Thus, in the second mode, logic control circuitry, delay circuitry, or other circuitry in the motherboard power supply is utilized to control the state of the motherboard power supply.

In some embodiments, the second trigger time includes one of a third trigger time and a fourth trigger time; the third triggering moment corresponds to a stage before a user triggers a power control key of the target device in a power-on time sequence of the target device; the fourth triggering moment corresponds to a stage after the user triggers the power control key in the power-on time sequence of the target equipment;

in this way, in the case where the second trigger time includes the third trigger time, the triggering the second object to control the third object to be in the activated state at the target adjustment time based on the fourth scale data, that is, the above step S1022 may be implemented as the following step S1023:

Step S1023, responding to the triggering of the power control key by a user, triggering the second object to control the third object to be in a starting state at the target adjustment moment based on the fourth proportion data.

Here, in the case where the second trigger time includes a third trigger time, that is, the second trigger time corresponds to a stage before the user triggers the power control key of the target device in the power-on timing of the target device, the first object generates fourth scale data before the user triggers the power control key of the target device and transmits the fourth scale data to the second object.

In this way, the second object interrupts the start-up delay operation process for the main board power supply because the user has not triggered the power control key when the second object receives the fourth proportion data, i.e. the user has not started the action of the main board power supply, and continues the start-up delay operation process after waiting for the user to trigger the power control key.

And then, responding to the trigger of the power control key by the user, the second object continues to execute the process of starting the delay operation, namely, the third object is controlled to be in a starting state at the target adjustment moment based on the fourth proportion data.

In the case that the second trigger time includes a fourth trigger time, that is, the second trigger time corresponds to a stage after the user triggers the power control key of the target device in the power-on timing of the target device, the first object generates fourth scale data after the user triggers the power control key of the target device, and transmits the fourth scale data to the second object. At this time, since the user has issued an action to start the main board power, the second object may perform the start-up delay operation immediately after receiving the fourth scale data.

In some embodiments, the triggering the second object to control the third object to be in the start state at the target adjustment time based on the fourth scale data, that is, the step S1022 may be implemented as one of the following steps S1024 and S1025:

Step S1024, in the case that the second object includes a logic control circuit, triggering the logic control circuit to determine sixth duration data based on the fourth proportion data and the maximum delay duration data stored in the second object; triggering the logic control circuit to start the third object after the sixth time length data.

Here, the logic control circuit is a circuit having calculation and control functions. In some embodiments, the second object may include an MCU in the motherboard power supply of the target device, or other logic control circuitry.

In the case where the second object includes logic control circuitry, the second object has data storage capabilities, and thus the maximum delay time duration data is stored in the second object.

In some embodiments, the second object may multiply the fourth scale data with the maximum delay time duration data to determine the sixth time duration data.

In some embodiments, the second object may weight the fourth scale data and multiply the fourth scale data with the maximum delay time length data to determine the sixth time length data.

In some embodiments, the second object may multiply the fourth scale data with the maximum delay time length data and determine the sixth time length data after adding the multiplication result to a specified constant.

Thus, after the sixth time length data is determined, the second object starts the third object after timing the sixth time length based on the current time, that is, the main board power supply is controlled to be in a start state.

In the above embodiment, since the second object includes the logic control circuit, the start time of the main board power supply can be precisely controlled by using the logic control circuit, so as to realize precise start delay of the main board power supply.

Step S1025, in the case that the second object includes a delay circuit, triggering the first object to determine seventh duration data based on the fourth proportion data and the maximum delay duration data of the delay circuit stored in the first object; triggering the first object to control a target pin in the delay circuit to be at a first potential within the seventh time length data so that the third object is in the starting state after the seventh time length data

Here, in the case where the second object includes a delay circuit, the on and off of the delay circuit may be controlled by the potential control of the target pin in the delay circuit by the first object, thereby realizing the state control of the third object.

In some embodiments, the delay time of the delay circuit can be controlled by controlling the charge and discharge time of the capacitor of the delay circuit; the delay time length of the delay circuit can also be controlled by controlling the delay switch of the delay circuit.

In some embodiments, the delay circuit may include an RC delay circuit, a master-slave JK trigger delay circuit, a monostable trigger delay circuit, a voltage comparator delay circuit, and so forth. Here, the specific implementation of the delay circuit is not limited.

Here, the maximum delay time length data of the delay circuit may be stored in the first object, and the seventh time length data may be determined based on the maximum delay time length data and the fourth ratio data. Here, the method for determining the seventh delay time may refer to the method for determining the sixth delay time, which is not described herein.

After the seventh time length data is determined, the target pin of the delay circuit is controlled to be at the first potential within the seventh time length data through the first object, so that the delay circuit is in an on state, and the main board power supply is in an unactuated state.

In some embodiments, the first object generates a pulse width modulation (Pulse Width Modulation, PWM) signal based on the seventh duration data and controls the delay circuit using the PWM signal.

In the above embodiment, in the case that the second object includes the delay circuit, the first object determines the seventh duration data based on the fourth proportion data, and controls the delay circuit to keep the on state by using the PWM signal in the seventh duration, so that the main board power supply is in the on state after the seventh duration data, and the purpose of starting the main board power supply in a delayed manner is achieved.

Next, an application example of the control method provided according to the present application will be described with reference to fig. 2 to 4.

As shown in fig. 2, in a stage after the BIOS verification of the target device is completed in the power-on time sequence of the target device corresponding to the target trigger time when the target device operates in the first mode, the first object and the second object both include EC, and the third object includes a motherboard power supply, an application embodiment of the control method provided by the present application includes the following steps S201 to S205:

Step S201, in response to the user connecting the power adapter of the target device to the power supply, the EC checks the BIOS; after that, step S202 is performed;

Step S202, in response to completion of BIOS verification, the EC judges whether the maximum delay time length data N set by a user is stored; if yes, go to step S203; if not, executing step S204;

Step S203, EC reads the maximum time delay time length data N set by the user, and determines the time delay time length for starting the main board power supply based on the maximum time delay time length data N and a specified random number algorithm; after that, step S205 is performed;

step S204, EC reads the default maximum delay time length data N 'and determines the delay time length for starting the main board power supply based on the maximum delay time length data N' and a specified random number algorithm; after that, step S205 is performed;

in step S205, after the determined delay time for starting the motherboard power supply, the EC makes the motherboard power supply in a starting state.

As shown in fig. 3, in a stage after a power control key is triggered by a user in a power-on time sequence of a target device corresponding to a target trigger time when the target device operates in a second mode, a first object includes EC, a second object includes an MCU in a main board power supply, and a third object includes the main board power supply, an application embodiment of the control method provided by the present application includes the following steps S301 to S304:

step S301, responding to the triggering of a power control key by a user, and reading time information of the triggering of the power control key by the user by the EC; after that, step S302 is performed;

step S302, based on time information of a user triggering a power control key and a specified random number algorithm, EC generates delay proportion data and sends the delay proportion data to MCU; after that, step S303 is performed;

Step S303, the MCU receives delay proportion data from the EC and determines delay time for starting a main board power supply based on the delay proportion data and the longest delay time data stored in the MCU; after that, step S304 is performed;

in step S304, the MCU enables the motherboard power supply to be in a start state after determining the delay time for starting the motherboard power supply.

As shown in fig. 4, in a stage after a power control key is triggered by a user in a power-on time sequence of a target device corresponding to a target trigger time when the target device operates in a second mode, a first object includes EC, a second object includes a delay circuit in a main board power supply, and a third object includes the main board power supply, an application embodiment of the control method provided by the present application includes the following steps S401 to S405:

Step S401, in response to the user triggering a power control key, the EC reads random data from an empty pin of the EC; after that, step S402 is performed;

step S402, based on the read random data and a specified random number algorithm, EC generates delay ratio data; after that, step S403 is performed;

Step S403, the delay proportion data generated and the longest delay time length data stored in the EC are expected, and the EC determines the delay time length for starting the mainboard power supply; after that, step S404 is performed;

step S404, based on the determined delay time length for starting the main board power supply, the EC generates a PWM signal, and the delay circuit is controlled to be in an on state within the delay time length by utilizing the PWM signal; after that, step S405 is performed;

In step S405, after the determined delay time period for starting the motherboard power supply, the EC stops sending the PWM signal to the delay circuit, so that the delay circuit is in an off state, and the motherboard power supply is in a start state.

Based on the foregoing embodiments, the embodiments of the present application provide a control apparatus, where the apparatus includes units included, and modules included in the units may be implemented by a processor in a computer device; of course, the method can also be realized by a specific logic circuit; in an implementation, the Processor may be a central processing unit (Central Processing Unit, CPU), a microprocessor (Microprocessor Unit, MPU), a digital signal Processor (DIGITAL SIGNAL Processor, DSP), or a field programmable gate array (Field Programmable GATE ARRAY, FPGA), or the like.

Fig. 5 is a schematic diagram of a composition structure of a control device according to an embodiment of the present application, and as shown in fig. 5, a control device 500 includes: a trigger module 510 and an adjustment module 520, wherein:

A triggering module 510, configured to trigger, in response to a target device operating in a target mode, a first object in the target device to perform a target operation at a target trigger time; the target mode and the target trigger moment have a specified corresponding relation; the target trigger moment corresponds to a stage in a power-on time sequence of the target equipment;

An adjustment module 520, configured to trigger, in response to the target operation, a second object in the target device to control a third object in the target device to be in a target state at a target adjustment time; wherein the second object is the same as or different from the first object.

In some embodiments, the target mode includes at least one of a first mode and a second mode; the target trigger time comprises at least one of a first trigger time and a second trigger time; the first trigger time corresponds to a stage after the verification of a basic input/output system of the target equipment is completed in a power-on time sequence of the target equipment; the second trigger time corresponds to a stage before starting a main board power supply of the target equipment in a power-on time sequence of the target equipment;

the module 510 is configured to perform at least one of:

Triggering the first object to execute the target operation at the first triggering moment when the target mode comprises the first mode;

and triggering the first object to execute the target operation at the second triggering moment when the target mode comprises the second mode.

In some embodiments, the target operation is to delay the initiation of the third object; the third object comprises a main board power supply of the target device; the target state includes a start-up state;

the triggering module 510 is configured to trigger the first object to generate first duration data; wherein the first time length data represents delay time length data corresponding to the delay operation;

the adjustment module 520 is configured to trigger the second object to start the third object after the first duration data; wherein the second object is identical to the first object.

In some embodiments, the triggering module 510 is configured to trigger the first object to determine the first duration data using a specified first random number algorithm; the first time length data is smaller than the second time length data, and the second time length data represents the maximum time delay time length data corresponding to the target operation.

In some embodiments, the second duration data is read from a target storage device by the first object and stored to a storage space of the first object when the target device last entered a shutdown procedure.

In some embodiments, the target operation is to delay the initiation of the third object; the third object comprises a main board power supply of the target device; the target state includes a start-up state;

the triggering module 510 is configured to trigger the first object to generate fourth scale data; wherein the fourth proportion data represents delay proportion data corresponding to the delay operation;

The adjustment module 520 is configured to trigger the second object to control the third object to be in a start state at a target adjustment time based on the fourth proportion data; wherein the second object is different from the first object.

In some embodiments, the triggering module 510 is configured to trigger the first object to determine the fourth scale data using fifth data and a specified second random number algorithm; wherein the fifth data includes one of: real-time data related to a start-up procedure of the target device, identification data related to the target device, and any random number.

In some embodiments, the second trigger time includes one of a third trigger time and a fourth trigger time; the third triggering moment corresponds to a stage before a user triggers a power control key of the target device in a power-on time sequence of the target device; the fourth triggering moment corresponds to a stage after the user triggers the power control key in the power-on time sequence of the target equipment;

in the case that the second trigger time includes the third trigger time, the adjustment module 520 is configured to trigger, in response to a user triggering the power control key, the second object to control the third object to be in a start state at a target adjustment time based on the fourth scale data.

In some embodiments, the adjustment module 520 is configured to perform one of:

triggering a logic control circuit to determine sixth duration data based on the fourth proportion data and the maximum delay duration data stored in the second object when the second object comprises the logic control circuit; triggering the logic control circuit to start the third object after the sixth time length data;

Triggering the first object to determine seventh duration data based on the fourth proportion data and the maximum delay duration data of the delay circuit stored in the first object under the condition that the second object comprises the delay circuit; triggering the first object to control a target pin in the delay circuit to be at a first potential in the seventh time length data, so that the third object is in the starting state after the seventh time length data.

The description of the apparatus embodiments above is similar to that of the method embodiments above, with similar advantageous effects as the method embodiments. In some embodiments, the functions or modules included in the apparatus provided by the embodiments of the present disclosure may be used to perform the methods described in the embodiments of the methods, and for technical details that are not disclosed in the embodiments of the apparatus of the present disclosure, please refer to the description of the embodiments of the methods of the present disclosure for understanding.

It should be noted that, in the embodiment of the present application, if the control method is implemented in the form of a software functional module, and sold or used as a separate product, the control method may also be stored in a computer readable storage medium. Based on such understanding, the technical solution of the embodiments of the present application may be essentially or some of contributing to the related art may be embodied in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read Only Memory (ROM), a magnetic disk, an optical disk, or other various media capable of storing program codes. Thus, embodiments of the application are not limited to any specific hardware, software, or firmware, or any combination of hardware, software, and firmware.

The embodiment of the application provides a computer device, which comprises a memory and a processor, wherein the memory stores a computer program capable of running on the processor, and the processor realizes part or all of the steps in the method when executing the program.

Embodiments of the present application provide a computer readable storage medium having stored thereon a computer program which, when executed by a processor, performs some or all of the steps of the above-described method. The computer readable storage medium may be transitory or non-transitory.

Embodiments of the present application provide a computer program comprising computer readable code which, when run in a computer device, causes a processor in the computer device to perform some or all of the steps for carrying out the above method.

Embodiments of the present application provide a computer program product comprising a non-transitory computer-readable storage medium storing a computer program which, when read and executed by a computer, performs some or all of the steps of the above-described method. The computer program product may be realized in particular by means of hardware, software or a combination thereof. In some embodiments, the computer program product is embodied as a computer storage medium, and in other embodiments, the computer program product is embodied as a software product, such as a software development kit (Software Development Kit, SDK), or the like.

It should be noted here that: the above description of various embodiments is intended to emphasize the differences between the various embodiments, the same or similar features being referred to each other. The above description of apparatus, storage medium, computer program and computer program product embodiments is similar to that of method embodiments described above, with similar advantageous effects as the method embodiments. For technical details not disclosed in the embodiments of the apparatus, the storage medium, the computer program and the computer program product of the present application, reference should be made to the description of the embodiments of the method of the present application.

It should be noted that fig. 6 is a schematic diagram of a hardware entity of a computer device according to an embodiment of the present application, and as shown in fig. 6, the hardware entity of the computer device 600 includes: a processor 601, a communication interface 602, and a memory 603, wherein:

The processor 601 generally controls the overall operation of the computer device 600.

The communication interface 602 may enable a computer device to communicate with other terminals or servers over a network.

The memory 603 is configured to store instructions and applications executable by the processor 601, and may also cache data (e.g., image data, audio data, voice communication data, and video communication data) to be processed or processed by various modules in the processor 601 and the computer device 600, which may be implemented by a FLASH memory (FLASH) or a random access memory (Random Access Memory, RAM). Data transfer may be performed between the processor 601, the communication interface 602, and the memory 603 via the bus 604.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present application, the sequence number of each step/process described above does not mean that the execution sequence of each step/process should be determined by its functions and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The foregoing embodiment numbers of the present application are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

In the several embodiments provided by the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above described device embodiments are only illustrative, e.g. the division of the units is only one logical function division, and there may be other divisions in practice, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the various components shown or discussed may be coupled or directly coupled or communicatively coupled to each other via some interface, whether indirectly coupled or communicatively coupled to devices or units, whether electrically, mechanically, or otherwise.

The units described above as separate components may or may not be physically separate, and components shown as units may or may not be physical units; can be located in one place or distributed to a plurality of network units; some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may be separately used as one unit, or two or more units may be integrated in one unit; the integrated units may be implemented in hardware or in hardware plus software functional units.

Those of ordinary skill in the art will appreciate that: all or part of the steps for implementing the above method embodiments may be implemented by hardware related to program instructions, and the foregoing program may be stored in a computer readable storage medium, where the program, when executed, performs steps including the above method embodiments; and the aforementioned storage medium includes: a mobile storage device, a Read Only Memory (ROM), a magnetic disk or an optical disk, or the like, which can store program codes.

Or the above-described integrated units of the application may be stored in a computer-readable storage medium if implemented in the form of software functional modules and sold or used as separate products. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the related art in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a removable storage device, a ROM, a magnetic disk, or an optical disk.

The foregoing is merely an embodiment of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application.

Claims (10)

1. A control method, comprising:

In response to target equipment operating in a target mode, triggering a first object in the target equipment to execute target operation at a target triggering moment; the target mode and the target trigger moment have a specified corresponding relation; the target trigger moment corresponds to a stage in a power-on time sequence of the target equipment;

responding to the target operation, triggering a second object in the target equipment to control a third object in the target equipment to be in a target state at a target adjustment moment; wherein the second object is the same as or different from the first object.

2. The method of claim 1, wherein the target mode comprises at least one of a first mode and a second mode; the target trigger time comprises at least one of a first trigger time and a second trigger time; the first trigger time corresponds to a stage after the verification of a basic input/output system of the target equipment is completed in a power-on time sequence of the target equipment; the second trigger time corresponds to a stage before starting a main board power supply of the target equipment in a power-on time sequence of the target equipment;

The method comprises the steps of responding to the operation of target equipment in a target mode, triggering a first object in the target equipment to execute target operation at a target triggering moment, and at least one of the following steps:

Triggering the first object to execute the target operation at the first triggering moment when the target mode comprises the first mode;

and triggering the first object to execute the target operation at the second triggering moment when the target mode comprises the second mode.

3. The method of claim 2, wherein the target operation is to delay initiation of the third object; the third object comprises a main board power supply of the target device; the target state includes a start-up state;

The triggering the first object to execute the target operation at the first triggering moment comprises the following steps:

Triggering the first object to generate first duration data; wherein the first time length data represents delay time length data corresponding to the delay operation;

the responding to the target operation, triggering a second object in the target equipment to control a third object in the target equipment to be in a target state at a target adjustment moment, and comprises the following steps:

triggering the second object to start the third object after the first time length data; wherein the second object is identical to the first object.

4. A method according to claim 3, wherein the triggering the first object to generate first duration data comprises:

Triggering the first object to determine the first duration data by using a specified first random number algorithm; the first time length data is smaller than the second time length data, and the second time length data represents the maximum time delay time length data corresponding to the target operation.

5. The method of claim 4, wherein the second duration data is read from a target storage device by the first object and stored to a storage space of the first object when the target device last entered a shutdown procedure.

6. The method of claim 2, wherein the target operation is to delay initiation of the third object; the third object comprises a main board power supply of the target device; the target state includes a start-up state;

The triggering the first object to execute the target operation at the second triggering moment comprises the following steps:

Triggering the first object to generate fourth proportion data; wherein the fourth proportion data represents delay proportion data corresponding to the delay operation;

the responding to the target operation, triggering a second object in the target equipment to control a third object in the target equipment to be in a target state at a target adjustment moment, and comprises the following steps:

Triggering the second object to control the third object to be in a starting state at a target adjustment moment based on the fourth proportion data; wherein the second object is different from the first object.

7. The method of claim 6, wherein the triggering the first object to generate fourth scale data comprises:

triggering the first object to determine the fourth proportion data by utilizing fifth data and a specified second random number algorithm; wherein the fifth data includes one of: real-time data related to a start-up procedure of the target device, identification data related to the target device, and any random number.

8. The method of claim 6, wherein the second trigger time comprises one of a third trigger time and a fourth trigger time; the third triggering moment corresponds to a stage before a user triggers a power control key of the target device in a power-on time sequence of the target device; the fourth triggering moment corresponds to a stage after the user triggers the power control key in the power-on time sequence of the target equipment;

and when the second trigger time includes the third trigger time, the triggering the second object to control the third object to be in a start state at a target adjustment time based on the fourth proportion data includes:

and responding to the triggering of the power control key by a user, triggering the second object to control the third object to be in a starting state at the target adjustment moment based on the fourth proportion data.

9. The method of claim 6, wherein the triggering the second object to control the third object to be in a startup state at a target adjustment time based on the fourth scaling data comprises one of:

triggering a logic control circuit to determine sixth duration data based on the fourth proportion data and the maximum delay duration data stored in the second object when the second object comprises the logic control circuit; triggering the logic control circuit to start the third object after the sixth time length data;

Triggering the first object to determine seventh duration data based on the fourth proportion data and the maximum delay duration data of the delay circuit stored in the first object under the condition that the second object comprises the delay circuit; triggering the first object to control a target pin in the delay circuit to be at a first potential in the seventh time length data, so that the third object is in the starting state after the seventh time length data.

10. A control apparatus comprising:

The triggering module is used for responding to the operation of the target equipment in the target mode and triggering a first object in the target equipment to execute target operation at the target triggering moment; the target mode and the target trigger moment have a specified corresponding relation; the target trigger moment corresponds to a stage in a power-on time sequence of the target equipment;

The adjusting module is used for responding to the target operation and triggering a second object in the target equipment to control a third object in the target equipment to be in a target state at the target adjusting moment; wherein the second object is the same as or different from the first object.