CN118033360A - Reading circuit and method for test vector of low-pin chip - Google Patents

Abstract

The invention provides a reading circuit and a method for a test vector of a low-pin chip, wherein the reading circuit comprises a mode switching module, a clock module, a storage module, a counting module and a feedback module; the mode switching module enables the chip pins to realize a conventional mode and a test vector reading mode in a pin multiplexing mode, input and output interfaces of the testability circuit are reduced, and the mode switching module realizes the mutual switching of the modes by judging the voltage threshold range of the input test control signals, so that the utilization rate of the chip pins is improved. When the test vectors are read, the mode switching module outputs an enabling signal to control the clock module to transmit the internal clock signals to the storage module and the counting module, and the counting module counts the rising or falling edge time of the internal clock and controls the storage module to read and store the corresponding test vectors. After the reading is finished, the counting module outputs a feedback signal through the feedback module to control the counting module to stop counting, repeated reading is avoided, and the accuracy of reading the test vector is improved.

Description

Reading circuit and method for test vector of low-pin chip

Technical Field

The present invention relates to the field of electronic chips, and more particularly, to a circuit and a method for reading test vectors of a low-pin chip.

Background

Design for Test (DFT) is a technical method of adding additional circuits in a circuit Design stage in order to improve Test efficiency and reduce Test cost. The design of the testability circuit increases a certain chip area, so that a plurality of test items are designed as much as possible to improve the utilization rate, and each individual test item is distinguished by binary coding. For selection and switching of test items, a corresponding test circuit is required. With respect to the test circuit, the input of the test control signal and the extraction of the test result signal are generally performed through pins of the chip. For example, the test station applies a predetermined signal to the relevant pins of the chip through the test probes, and the chip can be configured in a test vector reading mode so as to perform mass production test. How to correctly read different test patterns, it is an important aspect of ensuring system reliability that the configuration circuit enters different test vector read modes.

The traditional test code reading circuit is usually integrated in a state machine of the test control circuit, and can recognize and read certain test codes and instructions, but the input and output interfaces of the testability circuit are numerous, the circuit power consumption is large, the circuit is complex, and the circuit is not suitable for small-scale chips with deficient pin resources.

Disclosure of Invention

The invention provides a reading circuit and a reading method for a test vector of a low-pin chip in order to overcome the defects of the prior art.

In order to achieve the above object, the present invention provides a read circuit for a test vector of a low pin chip, comprising: the system comprises a mode switching module, a clock module, a storage module, a counting module and a feedback module.

And the input end of the mode switching module judges whether the voltage of the input test control signal is within the voltage threshold range corresponding to the test mode so as to control whether the test vector reading mode is entered.

The clock module comprises two input ends, one input end is connected with the output end of the mode switching module, the other input end receives an external test clock signal, and the clock module generates an internal clock signal which is used as the clock signals of the storage module and the counting module according to the output signal of the mode switching module and the external test clock signal.

The storage module comprises at least one register, the registers are mutually connected in parallel, the input ends of the registers are all used for receiving the test vectors, the corresponding test vectors are read and stored, and the stored test vectors are output through the output end.

And the counting module is connected with the clock module and the storage module and is used for counting the number of rising or falling edges of the internal clock signal and enabling the corresponding register so as to enable the corresponding register to read the test vector with the corresponding bit number.

The feedback module comprises a time sequence trigger, an input end receives an external test clock signal and an enabling signal of a last bit register in the storage module, and an output end outputs a reading end signal to control the counting module to stop counting.

Preferably, the mode switching module includes a normal mode and a test mode; in the normal mode, the test vector reading mode is turned off, and in the test mode, the test vector reading mode is turned on.

Preferably, the read circuit is integrated in a chip, three pins of which receive an external test clock signal, a test vector and a test control signal; in the normal mode or the test mode, the three pins are functionally multiplexed.

Preferably, the mode switching module enters the test mode by identifying method that the mode switching module judges that the voltage range is larger than the working voltage threshold range of the normal mode.

The invention provides a reading circuit for a test vector of a low-pin chip, which comprises: the system comprises a mode switching module, a clock module, a storage module, a counting module and a feedback module.

And the input end of the mode switching module judges whether the voltage of the input test control signal is within the voltage threshold range corresponding to the test mode so as to control whether the test vector reading mode is entered.

The clock module comprises three input ends, one input end is connected with the output end of the mode switching module, the other input end receives an external test clock signal, and the other input end is connected with the output end of the feedback module; the clock module controls whether to transmit an internal clock signal to the storage module and the counting module according to the output signal of the mode switching module, and controls whether the counting module stops counting according to the output signal of the feedback module.

The storage module comprises at least one register, the registers are mutually connected in parallel, the input ends of the registers are all used for receiving the test vectors, the corresponding test vectors are read and stored, and the stored test vectors are output through the output end.

And the counting module is connected with the clock module and the storage module and is used for counting the number of rising or falling edges of the internal clock signal and enabling the corresponding register so as to enable the corresponding register to read the test vector with the corresponding bit number.

The feedback module comprises a time sequence trigger, an input end receives an external test clock signal and an enabling signal of a last register in the storage module, and an output end outputs a reading end signal to the clock module so as to control the counting module to stop counting.

Preferably, the external test clock signal received by the input end of the clock module is a signal at the moment of rising or falling edge; the clock trigger edge of the time sequence trigger in the feedback circuit is opposite to the clock trigger edge of the counting module.

Preferably, the reading circuit further includes: and the input end of the first NOT circuit is connected with the output end of the mode switching module, the output end of the first NOT circuit is connected with the reset end of each register and the counting module in the storage module, a reset signal is provided for each register and the counting module, and the first NOT circuit is used when the phase of an external test clock signal is opposite to the trigger clock phase of the register.

Preferably, the feedback module further comprises:

and the second NOT circuit is characterized in that the input end of the second NOT circuit receives an external test clock signal, the output end of the second NOT circuit is connected with the clock signal end of the time sequence trigger, the external test clock signal controls the time sequence trigger to output a reading end signal through an inverted signal output by the second NOT circuit, and the second NOT circuit is used when the phase of the external test clock signal is opposite to the trigger clock phase of the register.

And the input end of the third NOT circuit is connected with the output end of the time sequence trigger, the output end of the third NOT circuit is connected with the enabling end of the counting module, the time sequence trigger controls the counting module to stop counting through an inverted signal output by the third NOT circuit, and the third NOT circuit is used when the phase of an external test clock signal is opposite to the trigger clock phase of the register.

The invention provides a method for reading test vectors of a low-pin chip, which comprises the following steps:

S1: the mode switching module detects that the test control signal enters a preset voltage threshold range of the test mode, and switches the mode into a test vector reading mode.

S2: the clock module transmits an external test clock signal to the memory module and the counting module.

S3: the storage module feeds back the internal clock signal to the counting module, the counting module counts the number of rising or falling edges of the internal clock signal, and the storage module reads the test vector.

S4: and after the reading is finished, the enabling signal of the last bit register of the storage module triggers the feedback module to output a reading finishing signal to enable the counting module to stop counting.

The invention provides a method for reading test vectors of a low-pin chip, which comprises the following steps:

S5: the mode switching module detects that the test control signal enters a preset voltage threshold range, and switches the mode into a test vector reading mode;

S6: the clock module transmits an external test clock signal to the storage module and the counting module;

s7: the storage module feeds back the internal clock signal to the counting module, the counting module counts the number of rising or falling edges of the internal clock signal, and the storage module reads the test vector;

s8: and after the reading is finished, the last-bit register enable signal of the storage module triggers the feedback module to output a reading finishing signal to the clock module, and the clock module transmits the reading finishing signal to the counting module to stop counting.

The beneficial effects of the invention are as follows: the invention provides a circuit and a method for reading test vectors of a low-pin chip, which comprises a mode switching module, wherein the mode switching module divides the working modes of the circuit into a normal mode and a test mode, the mode switching is realized by judging the voltage threshold range of an input test control signal, and when the mode switching module enters the test mode, whether the test vector reading mode is started or not is controlled by judging whether the control signal is in the voltage threshold range of the test vector reading mode. In the testing process of the mode switching module, a pin multiplexing mode is adopted to enable the chip pins to realize testing functions and conventional functions, and the two working functions are not interfered with each other, so that input and output interfaces of the testability circuit are reduced, and the utilization rate of the chip pins is improved. When the chip pins enter a test vector reading mode, the mode switching module outputs an enabling signal to the back-stage circuit to control the back-stage circuit to read the test vector. The clock module generates an internal clock signal according to the output signal of the mode switching module and an external test clock signal, transmits the internal clock signal to the storage module and the counting module, and controls a corresponding register in the storage module to read and store a corresponding test vector while counting at the moment of rising or falling edges of the internal clock, so that the input test vector is ensured to be unified with the data recorded by the counting module, the accuracy of the data is improved, and then the stored test vector is transmitted to a subsequent circuit. After the test vector is read, the counting module outputs a feedback signal through the feedback module to control the counting module to stop counting, repeated reading is avoided, the accuracy of the test vector reading is improved, and meanwhile dynamic power consumption generated in a subsequent circuit is also saved.

Drawings

FIG. 1 is a circuit diagram of a first embodiment of a read circuit for a test vector of a low pin chip according to the present invention;

FIG. 2 is a timing diagram of a read circuit for a test vector of a low pin chip according to the present invention;

FIG. 3 is a schematic diagram of a read circuit for testing vectors of a low-pin chip according to the present invention, wherein the read circuit is connected with off-chip pins in the chip;

FIG. 4 is a diagram showing a connection between a read circuit for testing vectors of a low-pin chip and an off-chip pin in a normal mode;

FIG. 5 is a diagram showing a connection between a read circuit for testing vectors of a low-pin chip and an off-chip pin in a test mode;

FIG. 6 is a circuit diagram of a second embodiment of a read circuit for a test vector of a low pin chip according to the present invention;

FIG. 7 is a flowchart of a first embodiment of a method for reading test vectors of a low pin chip according to the present invention;

fig. 8 is a flowchart of a second embodiment of a method for reading a test vector of a low-pin chip according to the present invention.

Detailed Description

The following describes the embodiments of the present invention in detail with reference to the drawings.

Example 1

As shown in fig. 1, the present invention provides a reading circuit for a test vector of a low pin chip, which comprises a mode switching module 1, a clock module 2, a storage module 3, a counting module 4 and a feedback module 5. The input end of the mode switching module 1 judges whether the voltage of the input test control signal Vcontrol is within the voltage threshold range corresponding to the test mode or not to control whether to enter the test vector reading mode or not. The clock module 2 includes two input terminals, one of which is connected to the output terminal of the mode switching module 1, and the other of which receives the external test clock signal TCK, and the clock module 2 generates the internal clock signal CLK as the clock signals of the memory module 3 and the counting module 4 according to the output signal of the mode switching module 1 and the external test clock signal TCK. The memory module 3 comprises at least one register, which are connected in parallel with each other and which each receive a test vector TDI at an input, reads and stores the corresponding test vector TDI, and outputs the stored test vector TDI via an output. The counting module 4 is connected to the clock module 2 and the storage module 3, and is configured to count the number of rising or falling edges of the internal clock signal CLK and enable the corresponding register, so that the corresponding register reads the test vector of the corresponding bit number. The feedback module 5 includes a timing flip-flop 51, whose input receives the external test clock signal TCK and the enable signal final_en of the last register in the memory module 3, and whose output outputs a read end signal to control the counting module 4 to stop counting.

Specifically, when the test control signal Vcontrol is input to the input end of the mode switching module 1, the mode switching module 1 determines whether the current voltage is within the voltage threshold range corresponding to the test mode by identifying the voltage of the test control signal Vcontrol, so as to control whether to enter the test vector reading mode. If the input test control signal Vcontrol is within the voltage threshold range of the test mode, the test vector reading mode is entered, and the enable signal TCBEN output by the mode switching module 1 enables the post-stage circuit to execute the vector reading function. The enable signal TCBEN output by the mode switching module 1 is at a high level. After the test vector read mode is turned on, the clock module 2 generates an internal clock signal CLK according to the enable signal TCBEN and the external test clock signal TCK output from the mode switching module 1, and transfers the internal clock signal CLK to each register and counting module 4 in the memory module 3. The number of registers in the memory module 3 is preferably 5, and each register may be a timing flip-flop of a rising edge or a falling edge. The storage module 3 acquires the internal clock signal CLK and feeds the internal clock signal CLK back to the counting module 4, the counting module 4 enables the corresponding registers in the storage module 3 to sequentially read and store the test vectors TDI with corresponding digits according to the feedback signal at the rising edge time of the internal clock signal CLK, and transmits the stored test vectors TDI to the subsequent circuits through the output end, and when the reading is finished, the enabling signal final_en output by the last register in the storage module 3 is a falling edge time signal. The last register refers to the last register in the transmission direction of the signal. The timing trigger edge of the counting module 4 is determined by the timing trigger edge of the register, and the timing trigger edge of the register is triggered at the rising edge time, so the counting module 4 is triggered at the rising edge time as well. In this embodiment, the counting module 4 may also enable a corresponding register in the memory module 3 at the time of the falling edge of the internal clock signal CLK, and the current register is a timing trigger triggered at the time of the falling edge of the clock signal CLK. After the reading is finished, the enabling signal Final_EN output by the last-bit register of the storage module 3 is a rising edge moment signal, and the storage module 3 and the counting module 4 can be matched with trigger signals at different moments according to requirements so as to trigger the feedback circuit 5 to finish the reading process.

For ease of understanding, the first Bit register Bit4 in the memory module 3 is described below as an example. After the clock module 2 transmits the external test clock signal TCK and the internal clock signal CLK generated by the enable signal TCBEN output by the mode switching module 1 to the first Bit register Bit4, the internal clock signal CLK is fed back to the counting module 4 through the enable end, at this time, the counting module 4 is at the rising edge time of the internal clock signal CLK, the count value num=0 of the counting end thereof, and the corresponding output end outputs the enable signal to control the first Bit register Bit4 to read and store the first Bit test vector, and the stored test vector is transmitted to the subsequent circuit through the output end. Similarly, the principle of the remaining registers is the same as that of the first Bit register Bit 4. After the first test vector is read, the rest registers sequentially read the test vectors with corresponding bit numbers according to the sequence, and the stored test vectors are transmitted to the subsequent circuits through the output end until the reading is finished.

The change process of each signal is shown in FIG. 2, wherein numerals 0-4 represent the current values of the counting module 4, and bits [4] to [0] represent test vectors of corresponding digits read by each corresponding register. In this embodiment, the count module 4 counts the number of rising edges or falling edges of the internal clock signal CLK to determine whether the input test vectors are all read by the memory module 3, thereby improving the accuracy and stability of reading the test vectors TDI. When the reading is finished, the judgment condition that the count value of the counting module 4 reaches a preset value is taken as an end mark, wherein the preset value is determined according to the number of the test data bits and corresponds to the number of the registers. In this embodiment, when the count value num=4 of the count module 4, it is regarded as reaching the preset value, and the counting is stopped. After the end of the test vector read of the last Bit register Bit0, the enable end outputs the enable signal final_en to the input end of the timing flip-flop 51, and triggers the timing flip-flop 51 together with the internal clock signal CLK received by the clock signal end of the timing flip-flop 51, so that the output read end signal thereof controls the count module 4 to stop counting. After the test vector TDI is read, the enable signal final_en is a clock falling edge timing signal.

In this embodiment, the mode switching module 1 includes a normal mode and a test mode, wherein the test mode includes a test vector reading mode and a test mode of other functions; the normal mode refers to a mode when a general user normally uses the device; the test mode is a special mode for testing the reliability of the chip by a professional staff. When the mode switching module 1 is in the normal mode, the test vector reading mode is in a closed state, namely a rear-stage circuit of the mode switching module 1 does not work; if the mode switching module 1 is in the test mode, the mode switching module 1 controls the test vector reading mode to be started, and outputs an enable signal TCBEN to the subsequent circuit so as to control the subsequent circuit to execute the test vector TDI reading function. The mode switching module 1 is preferably a voltage window comparator, and determines whether the voltage is within a voltage threshold range corresponding to the test vector reading mode by comparing the voltage of the input test control signal Vcontrol, so as to control whether to enter the test vector reading mode.

In order to solve the problem of lack of chip Pin resources, a Low Pin test mode is adopted to detect the reliability of the chip, wherein a Low Pin (Low Pin Count) refers to an input Pin and an output Pin which are multiplexed into a test signal (test control signal Vcontrol, test vector TDI, external test clock TCK) in a test mode. In this embodiment, the read circuit is integrated in a chip, and three pins of the chip receive an external test clock signal TCK, a test vector TDI and a test control signal Vcontrol; in either the normal mode or the test mode, three pins are multiplexed. Specifically, the reading circuit is integrated in a chip, and in a test vector reading mode, three pins are multiplexed as inputs only in the test vector reading mode, and in a test mode after the reading is finished, three pins are multiplexed as outputs.

Fig. 3 is a schematic diagram of the circuit in connection with the off-chip pins in the chip. The structure in the dotted line frame is a chip internal circuit, and the outside of the dotted line frame is a chip external structure; the chip is provided with 6 pins, and the left side pins are respectively a transmitting data pin TXD, a testing control signal pin Vcontrol and a receiving data pin RXD; the right Pinl-Pin 3 are the output pins. The chip comprises an original circuit Working circuit and a test control module Test Control Block; the original circuit refers to a circuit operated in a chip normal mode, and an input control module InputControl and an output control module OutputControl are included in the original circuit. The test control module Test Control Block includes a read circuit for a test vector of the low-pin chip and a Decoder, which operates after the end of reading and outputs an internal test control signal.

The working principle of the read circuit multiplexing chip pin for the test vector of the low pin chip is that; as shown in fig. 4, in the normal mode, the transmit data Pin TXD, the test control signal Vcontrol Pin, and the receive data Pin RXD are used as inputs of the original circuit Working circuit, and the Pinl to Pin3 pins on the right side of the chip are used as outputs. As shown in fig. 5, in the test mode, the transmit data Pin TXD, the test control signal Vcontrol Pin, and the receive data Pin RXD are connected to the original circuit Working circuit and the read circuit for the test vector of the low Pin chip, and in the read process, the transmit data Pin TXD, the test control signal Vcontrol Pin, and the receive data RXD Pin on the left side of the chip are taken as inputs, and the Pinl-Pin 3 pins on the right side of the chip can be regarded as idle; after the reading is finished, the left transmitting data Pin TXD and the right receiving data Pin RXD of the chip are taken as output, and the right Pinl to Pin3 pins can be regarded as idle. The switching between the normal mode and the test mode depends on the test control signal Vcontrol and the mode switching module 1. The input control module InputControl and the output control module OutputControl in the original circuit Working circuit have the function of signal selection, the test vector TDI and the external test clock signal TCK are controlled not to be output to the test control module Test Control Block in the normal mode, the output control module OutputControl works at the stage after the reading of the test mode is finished, and the output signals after the Working are output through the two groups of switch circuits 7 through the transmitting data pin TXD and the receiving data pin RXD. The two groups of switch modules 7 are push-pull output structures composed of PMOS tubes and NMOS tubes, and the NMOS tubes are cascaded at the lower ends of the PMOS tubes.

In this embodiment, the mode switching module 1 identifies the mode of entering the test vector reading mode by determining that the voltage range is greater than the operating voltage range of the normal mode. Specifically, the mode switching module 1 enters the test vector reading mode in a manner of identifying the test vector reading mode by using a voltage range as a judgment standard. Because of the multiplexing of the pins of the chip, in order to ensure that a user cannot enter the test vector reading mode by mistake in the using process, when the working voltage threshold range of the test vector reading mode is set, the working voltage threshold range of the test vector reading mode is set to be larger than the working voltage threshold range of the conventional mode; if the working voltage threshold range of the normal mode is 0-3.3V, and the working voltage threshold range of the test vector reading mode is 5-7V; the phenomenon that the pin mode is triggered by mistake when a common user uses the pin can be avoided. It should be noted that, the mode switch module 1 recognizes the mode of entering the test vector read mode, including but not limited to a voltage threshold range, single voltage threshold detection, pulse feature detection, or other modes to perform the mode recognition function.

In this embodiment, the external test clock signal TCK received at the input end of the clock module 2 is a signal at the rising or falling edge time. Specifically, the valid signal of the external test clock signal TCK in the read circuit for the test vector of the low pin chip may be a clock rising edge timing signal or a falling edge timing signal. When the rising edge time of the external test clock signal TCK is valid, the valid clock edge signal transmitted to the register in the memory module 3 and the counter module 4 by the clock module 2 is also a rising edge time signal, and after the reading is finished, the valid clock signal of the enable signal final_en output by the last register Bit0 is a falling edge time signal. On the contrary, when the falling edge time of the external test clock signal TCK is valid, the valid clock edge signal transmitted to the register in the memory module 3 and the counter module 4 by the clock module 2 is also a falling edge time signal, and after the reading is finished, the valid clock signal of the enable signal final_en output by the last register Bit0 is a rising edge time signal. Different external test clock signals TCK are matched in a mode of converting clock signals triggered by the circuit, so that the application range of the reading circuit is widened, and the universality is strong.

In this embodiment, the clock trigger edge of the timing trigger 51 in the feedback module 5 should be opposite to the clock trigger edge of the counting module 4, specifically, after the last rising or falling edge of the counting module 4 is counted, a certain time is required to stabilize the output enable signal final_en, if the clock trigger edge of the counting module 4 is the same as the clock trigger edge of the timing trigger 51, the counting module 4 does not have time to output the stable enable signal final_en to trigger the timing trigger 51, so that the timing trigger 51 cannot read the enable signal final_en, and the counting module 4 cannot stop counting. Therefore, the timing trigger edges should be opposite, and the timing trigger 51 should be half a period apart to ensure that the last enable signal final_en from the counting module 4 has stabilized before the trigger edge arrives. When the trigger signal of the counting module 4 is a rising edge, the timing trigger edge of the timing trigger 51 is a falling edge, whereas when the trigger signal of the counting module 4 is a falling edge, the timing trigger edge of the timing trigger 51 is a rising edge.

In this embodiment, a reading circuit for a test vector of a low pin chip further includes: a first not gate 6. The input end of the first NOT circuit 6 is connected to the output end of the mode switching module 1, the output end is connected to the reset end of each register and counting module 4 in the storage module 3, a reset signal is provided for each register and counting module 4, and the first NOT circuit 6 is used when the phase of the external test clock signal TCK is opposite to the trigger clock phase of the register. Specifically, after the test measurement reading mode is started, the enable signal TCBEN output by the mode switching module 1 enables the reset ports of the registers and the counting module 4, and provides reset signals for the registers and the counting module 4 to start working. In addition, the first not circuit 6 is used when the phase of the external test clock signal TCK is opposite to the trigger clock phase of the register, and if the two clock phases are identical, the first not circuit 6 may be omitted.

In this embodiment, the feedback module 5 further includes a second not gate 52 and a third not gate 53. The input end of the second not gate 52 receives the external test clock signal TCK, the output end is connected to the clock signal end of the timing flip-flop 51, and the external test clock signal TCK controls the timing flip-flop 51 to output the read end signal through the inverted signal output from the second not gate 52. The input end of the third NOT circuit 53 is connected to the output end of the time sequence trigger 51, the output end is connected to the enabling end of the counting module 4, and the time sequence trigger 51 controls the counting module 4 to stop counting through the inverted signal output by the third NOT circuit 53. The second and third NOT circuits 52 and 53 are operated in the same manner as the first NOT circuit 6, and are used when the phase of the external test clock signal TCK is opposite to the trigger clock phase of the register, and otherwise omitted.

Example two

In this embodiment, the output signal of the feedback module 5 in the first embodiment is connected to the input end of the clock module 2, so that the output signal is coupled with the external test clock signal TCK and the enable signal TCBEN outputted by the mode switching module 1, and then the reading of the test vector TDI is ended by locking the clock signal.

As shown in fig. 6, a read circuit for a test vector of a low pin chip provided in this embodiment includes: a mode switching module 1, a clock module 2, a storage module 3, a counting module 4 and a feedback module 5. The input end of the mode switching module 1 judges whether the voltage of the input test control signal is in the voltage threshold range corresponding to the test mode to control whether the test vector reading mode is entered. The clock module 2 comprises three input ends, one input end is connected with the output end of the mode switching module 1, the other input end receives an external test clock signal TCK, and the other input end is connected with the output end of the feedback module 5; the clock module 2 controls whether to transmit the internal clock signal CLK to the storage module 3 and the counting module 4 according to the output signal of the mode switching module 1, and the clock module 2 controls whether the counting module 4 stops counting according to the output signal of the feedback module 5. The memory module 3 comprises at least one register, each of which is connected in parallel with each other and the input receives the test vector TDI, reads and stores the corresponding test vector TDI, and outputs the stored test vector TDI via the output. The counting module 4 is connected to the clock module 2 and the storage module 3, and is configured to count the number of rising or falling edges of the internal clock signal CLK and enable the corresponding register, so that the corresponding register reads the test vector TDI with the corresponding number of bits. The feedback module 5 includes a timing trigger 51, an input terminal receives the external test clock signal TCK and the enable signal final_en of the last register in the memory module 3, and an output terminal outputs a read end signal to the clock module 2 to control the counting module 4 to stop counting.

Specifically, when the test vector mode is started, the mode conversion module 1 outputs an enable signal TCBEN to the clock module 2, and the clock module 2 generates an internal clock CLK according to the external test clock signal TCK, the enable signal TCBEN output by the mode switching module 1, and the end read signal, and transmits the internal clock CLK to the storage module 3 and the counting module 4; the register in the storage module 3 sequentially outputs feedback signals to the counting module 4; based on the feedback signal, the counting module 4 controls the corresponding register to sequentially read the test vectors TDI with the corresponding bit numbers, and transmits the stored test vectors TDI to the subsequent circuits through the output end. After the last Bit register Bit0 in the memory module 3 is read, the enable end outputs the enable signal final_en, and the enable signal final_en and the internal clock signal CLK input from the clock signal end of the clock trigger 51 trigger the clock trigger 51 together, so that the enable end outputs the read end signal to the input end of the clock module 2. The clock module 2 outputs the same signals as the end reading signals to each register in the storage module 3 and the counting module 4 after the end reading signals are summed with the external test clock signal TCK and the enabling signals TCBEN output by the mode switching module 1, so that the counting module 4 stops counting and simultaneously controls each register to stop reading, and the locking function of the clock signals is realized. After the test vector TDI is read, the logic state of the output of the internal clock signal CLK is always kept to be 0, so that the dynamic power consumption of a subsequent circuit is saved, wherein the dynamic power consumption refers to the low-resistance path from a power supply to the ground in the digital circuit due to the switching-on and switching-off transition of MOS (metal oxide semiconductor) during signal inversion all the time, and the reliability of the read circuit of the test vector for the low-pin chip is further improved.

As shown in fig. 7, the present invention further relates to a method for reading test vectors of a low pin chip, wherein the first method comprises the following steps:

s1: the mode switching module 1 detects that a test control signal Vcontrol enters a preset voltage threshold range of a test mode, and switches the mode into a test vector reading mode;

The mode switching module 1 judges whether the current voltage is within a preset voltage range of the test mode according to the test control signal Vcontrol at the input end, and if the current voltage is within the preset voltage range of the test mode, the mode switching module 1 switches to the test vector reading mode.

S2: the clock module 2 transmits an external test clock signal TCK to the storage module 3 and the counting module 4;

After the test vector reading mode is started, the output enabling signal final_en controls the clock module 2 to transmit an external test clock signal TCK received by the input end of the enabling signal final_en and an internal clock signal CLK generated by the enabling signal final_en output by the mode switching module 1 to the storage module 3 and the counting module 4, and meanwhile, the mode switching module 1 outputs a reset signal to the storage module 3 and the counting module 4 through the first NOT circuit 6 to control the starting of the storage module 3 and the counting module 4.

S3: the memory module 3 feeds back an internal clock signal CLK to the counting module, the counting module 4 counts the number of rising or falling edges of the clock signal, and the memory module 3 reads the test vector;

The storage module 3 feeds back the clock signal end internal clock signal CLK to the counting module 4 through the enabling end, and controls the corresponding register to sequentially read and store the test vectors with corresponding digits based on the feedback signal when the counting module 4 counts the rising edge time of the internal clock signal CLK, and transmits the stored test vectors to the subsequent circuit through the output end. Similarly, the counting module 4 counts the falling edge of the internal clock signal CLK in the same manner as the control triggered by the rising edge of the internal clock signal CLK.

S4: the last-bit register output enable signal final_en of the memory module 3 triggers the feedback module 5 to output the read end signal enable counting module 4 to stop counting after the read is ended.

When the count value of the count module 4 reaches a preset value, the test vector TDI reading ends. After the memory module 3 finishes reading, the enable end of the last Bit register Bit0 outputs the enable signal final_en to the timing trigger 51 in the feedback module 5 at the rising or falling edge time of the internal clock signal CLK, and the timing trigger 51 is triggered together with the internal clock signal CLK received by the clock signal end to output the reading end signal, so that the counting module 4 is enabled to stop counting.

As shown in fig. 8, the present invention provides a method for reading test vectors of a low-pin chip, and the other method includes the following steps:

S5: the mode switching module 1 detects that the test control signal Vcontrol enters a preset threshold voltage range of the test mode, and switches the mode to the test vector reading mode.

The mode switching module 1 judges whether the current voltage is within a preset voltage range of the test mode according to the test control signal Vcontrol at the input end, and if the current voltage is within the preset voltage range of the test mode, the mode switching module 1 switches the mode into a test vector reading mode.

S6: the clock module 2 passes the external test clock signal TCK to the memory module 3 and the counting module 4.

After the test vector reading mode is started, the output enabling signal final_en controls the clock module 2 to transmit an external test clock signal TCK received by the input end of the enabling signal final_en and an internal clock signal CLK generated by the enabling signal final_en output by the mode switching module 1 to the storage module 3 and the counting module 4, and meanwhile, the mode switching module 1 outputs a reset signal to the storage module 3 and the counting module 4 through the first NOT circuit 6 to control the starting of the storage module 3 and the counting module 4.

S7: the memory module 3 feeds back the internal clock signal to the counting module 4, the counting module 4 counts the number of rising or falling edges of the internal clock signal, and the memory module 3 reads the test vector.

The storage module 3 feeds back the clock signal end internal clock signal CLK to the counting module 4 through the enabling end, and controls the corresponding register to sequentially read and store the test vectors with corresponding digits based on the feedback signal when the counting module 4 counts the rising edge time of the internal clock signal CLK, and transmits the stored test vectors to the subsequent circuit through the output end. Similarly, the counting module 4 counts the falling edge of the internal clock signal CLK in the same manner as the control triggered by the rising edge of the internal clock signal CLK.

S8: and after the reading is finished, the last-bit register output enable signal of the storage module triggers the feedback module to output a reading finishing signal to the clock module, and the clock module transmits the reading finishing signal to the counting module to stop counting.

When the count value of the count module 4 reaches a preset value, the test vector TDI reading ends. After the reading of the memory module 3 is finished, the enabling end of the last Bit register Bit0 outputs an enabling signal final_en to the time sequence trigger 51 in the feedback module 5 at the time of the falling edge of the internal clock signal CLK, the internal clock signal CLK received by the last Bit register Bit triggers the time sequence trigger to output a reading finishing signal to the clock module 2 together, the clock module 2 generates the same signal as the reading finishing signal with the external test clock signal TCK and the enabling signal TCBEN output by the mode switching module, and the counting module is controlled to stop counting. Similarly, when the counting module 4 counts at the rising edge, the output enable signal final_en is controlled in the same manner as the enable signal final_en output at the falling edge.

In summary, the invention provides a circuit and a method for reading a test vector of a low-pin chip, which includes a mode switching module for dividing a working mode into a normal mode and a test mode, wherein the mode switching module is used for realizing the mode switching by judging a voltage threshold range to which a voltage of an input test control signal belongs, and when the mode switching module enters the test mode, whether the test vector reading mode is started or not is controlled by judging whether the control signal is within the voltage threshold range of the test vector reading mode. In the testing process of the mode switching module, a pin multiplexing mode is adopted to enable the chip pins to realize testing functions and conventional functions, and the two working functions are not interfered with each other, so that input and output interfaces of the testability circuit are reduced, and the utilization rate of the chip pins is improved. When the chip pins enter a test vector reading mode, the mode switching module outputs an enabling signal to the back-stage circuit to control the back-stage circuit to read the test vector. The clock module generates an internal clock signal according to the output signal of the mode switching module and an external test clock signal, transmits the internal clock signal to the storage module and the counting module, and controls a corresponding register in the storage module to read and store a corresponding test vector while counting at the moment of rising or falling edges of the internal clock, so that the input test vector is ensured to be unified with the data recorded by the counting module, the accuracy of the data is improved, and then the stored test vector is transmitted to a subsequent circuit. After the test vector is read, the counting module outputs a feedback signal through the feedback module to control the counting module to stop counting, repeated reading is avoided, the accuracy of the test vector reading is improved, and meanwhile dynamic power consumption generated in a subsequent circuit is also saved.

The foregoing is merely a preferred embodiment of the present invention, and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the concept of the present invention, and such modifications and adaptations are intended to be comprehended within the scope of the present invention.

Claims (10)

1. A read circuit for a test vector of a low pin die, comprising: the system comprises a mode switching module, a clock module, a storage module, a counting module and a feedback module;

the input end of the mode switching module judges whether the voltage of the input test control signal is in the voltage threshold range corresponding to the test mode or not to control whether the test vector reading mode is entered or not;

the clock module comprises two input ends, one input end is connected with the output end of the mode switching module, the other input end receives an external test clock signal, and the clock module generates an internal clock signal which is used as the clock signals of the storage module and the counting module according to the output signal of the mode switching module and the external test clock signal;

The storage module comprises at least one register, the registers are connected in parallel, the input ends of the registers are all used for receiving the test vectors, the corresponding test vectors are read and stored, and the stored test vectors are output through the output end;

The counting module is connected with the clock module and the storage module and is used for counting the number of rising or falling edges of the internal clock signal and enabling the corresponding register so as to enable the corresponding register to read the test vector with the corresponding bit number;

The feedback module comprises a time sequence trigger, an input end receives an external test clock signal and an enabling signal of a last bit register in the storage module, and an output end outputs a reading end signal to control the counting module to stop counting.

2. The read circuit for test vectors of low pin chips of claim 1, wherein the mode switching module comprises a normal mode and a test mode; in the normal mode, the test vector reading mode is turned off, and in the test mode, the test vector reading mode is turned on.

3. The read circuit for test vectors of a low pin die of claim 2, wherein the read circuit is integrated in a die, three pins of the die receiving external test clock signals, test vectors and test control signals; in the normal mode or the test mode, the three pins are functionally multiplexed.

4. The circuit of claim 2, wherein the mode switch module identifies the mode switch module as entering the test mode by determining that the voltage range is greater than the operating voltage threshold range for the normal mode.

5. A read circuit for a test vector of a low pin die, comprising: the system comprises a mode switching module, a clock module, a storage module, a counting module and a feedback module;

the input end of the mode switching module judges whether the voltage of the input test control signal is in the voltage threshold range corresponding to the test mode or not to control whether the test vector reading mode is entered or not;

The clock module comprises three input ends, one input end is connected with the output end of the mode switching module, the other input end receives an external test clock signal, and the other input end is connected with the output end of the feedback module; the clock module controls whether to transmit an internal clock signal to the storage module and the counting module according to the output signal of the mode switching module, and controls whether the counting module stops counting according to the output signal of the feedback module;

The storage module comprises at least one register, the registers are connected in parallel, the input ends of the registers are all used for receiving the test vectors, the corresponding test vectors are read and stored, and the stored test vectors are output through the output end;

The counting module is connected with the clock module and the storage module and is used for counting the number of rising or falling edges of the internal clock signal and enabling the corresponding register so as to enable the corresponding register to read the test vector with the corresponding bit number;

The feedback module comprises a time sequence trigger, an input end receives an external test clock signal and an enabling signal of a last register in the storage module, and an output end outputs a reading end signal to the clock module so as to control the counting module to stop counting.

6. The circuit for reading test vectors of a low pin die of claim 1 or 5, wherein,

The external test clock signal received by the input end of the clock module is a signal at the moment of rising or falling edge; the clock trigger edge of the time sequence trigger in the feedback circuit is opposite to the clock trigger edge of the counting module.

7. The low pin chip read test vector circuit of claim 1 or 5, further comprising:

And the input end of the first NOT circuit is connected with the output end of the mode switching module, the output end of the first NOT circuit is connected with the reset end of each register and the counting module in the storage module, a reset signal is provided for each register and the counting module, and the first NOT circuit is used when the phase of an external test clock signal is opposite to the trigger clock phase of the register.

8. The read circuit for test vectors of low pin chips of claim 1 or 5, wherein the feedback module further comprises:

The input end of the second NOT circuit receives an external test clock signal, the output end of the second NOT circuit is connected with the clock signal end of the time sequence trigger, the external test clock signal controls the time sequence trigger to output a reading end signal through an inverted signal output by the second NOT circuit, and the second NOT circuit is used when the phase of the external test clock signal is opposite to the trigger clock phase of the register;

And the input end of the third NOT circuit is connected with the output end of the time sequence trigger, the output end of the third NOT circuit is connected with the enabling end of the counting module, the time sequence trigger controls the counting module to stop counting through an inverted signal output by the third NOT circuit, and the third NOT circuit is used when the phase of an external test clock signal is opposite to the trigger clock phase of the register.

9. A method of reading a test vector for a low pin die, the method comprising:

s1: the mode switching module detects that a test control signal enters a preset voltage threshold range of a test mode, and switches the mode into a test vector reading mode;

S2: the clock module transmits an external test clock signal to the storage module and the counting module;

S3: the storage module feeds back the internal clock signal to the counting module, the counting module counts the number of rising or falling edges of the internal clock signal, and the storage module reads the test vector;

S4: and after the reading is finished, the last-bit register output enabling signal of the storage module triggers the feedback module to output a reading finishing signal to enable the counting module to stop counting.

10. A method of reading a test vector for a low pin die, the method comprising:

S5: the mode switching module detects that a test control signal enters a preset voltage threshold range of a test mode, and switches the mode into a test vector reading mode;

S6: the clock module transmits an external test clock signal to the storage module and the counting module;

s7: the storage module feeds back the internal clock signal to the counting module, the counting module counts the number of rising or falling edges of the internal clock signal, and the storage module reads the test vector;

s8: and after the reading is finished, the last-bit register output enable signal of the storage module triggers the feedback module to output a reading finishing signal to the clock module, and the clock module transmits the reading finishing signal to the counting module to stop counting.