CN1180265A - Ferroelectric latch technique of non-volattilizing logic circuit - Google Patents

Abstract

The present invention relates to a ferroelectric latching technology for non-volatile logic circuit. In the field of existent electronic technology except for non-volatile memory, the logic circuit is volatile. Said invention uses two ferroelectric capacitors and two MOS transistors, and connects one end point of each of them to the output of latch circuit and its complementary output to form non-volatile latch circuit. Said invention implements the non-volatility of logic circuit, and combines the non-volatile logic circuit together with high-speed non-volatile memory so as to can implement a non-volatile digital computer system.

Description

The ferroelectric latch technique of non-volattilizing logic circuit

The invention belongs to circuit structure field in the electronic information.

The logical circuit that adopts in all electronic instruments, equipment, the electrical equipment is except nonvolatile memory (E at present ²PROM) outside, all be volatile, promptly behind dump, information can not keep.

Conventional computer system comprises that microprocessor, microcontroller etc. are usually by CPU, memory, input/output interfaces etc. are partly formed, wherein CPU is made of ALU (ALU) and control unit, memory is divided into that main storage-it can be directly by the control unit access, and other are external memory.

Classical main storage has volatile register (register); Dynamic random access memory (DRAM), static RAM (SRAM); Usually also comprise nonvolatile read-only memory (ROM), it is used for for example basic output system (BIOS) of storage computation machine start-up routine.Main storage is stored data and address when operate as normal, but when power supply disconnects, the logic state of its data, address and system is always lost, though some computer has nonvolatile RAM (NV-RAM) or nonvolatile SRAM (ShadowRAM), but register (triggering the type memory) is always volatile, this means that the information in the register will lose when power supply disconnects, also is like this for advanced person's microprocessor architecture situation.

Conventional nonvolatile memory has significant limitation.From history, the nonvolatile memory unit for example disk always with main storage and CPU in relevant logical circuit (as register, calculator) separate, this is that read or write speed is more much lower than CPU because their size is big.Even the semiconductor nonvolatile memory has been arranged, also have only ROM, only readable, can not write, can be used for the hard sign indicating number of main storage stored BIOS, be with Electrically Erasable Read Only Memory (E ²PROM) or the Flash memory main read/writable memory device that is used for computer be still unpractically, this is because its time of writing is oversize, is about DRAM and writes 10,000 times of time, for example E ²The time of typically writing of PROM and DRAM is respectively 5ms and 50ns.Another critical limitation of common semiconductor nonvolatile memory is that the number of times of its read/writable is limited, and its maximum read/write number of times is about 10 usually ⁵, therefore, conventional semiconductor nonvolatile memory can not integrate with logical circuit and realize non-volatile logic function.

The objective of the invention is to design that a kind of can to write number of times height, access time shorter, the ferroelectric latch technique of non-volattilizing logic circuit low in energy consumption.

Circuit of the present invention mainly is made up of ferroelectric capacitor and latch cicuit.Utilize 2 ferroelectric capacitors and two MOS transistor, each end points with them is connected with the output Q and the complementary output Q thereof of any latch cicuit, just can constitute non-volatile latch cicuit, and another end points of 2 electric capacity connects together.Fig. 1 illustrates its structure, and wherein F is conventional sequence circuit piece, and it can be any latching.T1, T2, T3, and T4 be general n ditch MOS transistor, C _F1And C _F2It is ferroelectric capacitor, the input signal of F piece can be data, clock, setting (Set), reset (Reset) or other control signals, the output signal of F piece is Q and Q, and PCH is the control signal that is used for precharge Q and Q when needs recover.WL is the control signal of a T1 and T2.PL writes ferroelectric capacitor with information or from the required control signal of ferroelectric capacitor read message, GND is a circuit ground, because to latch and trigger is for example building block of register, counter of sequential logical circuit, therefore that sequential logical circuit and register file will be become will be nonvolatile for the fixedness that latchs and trigger.

The notion of non-volattilizing logic circuit of the present invention is actually the operation principle of the ferroelectric nonvolatile memory in 2T-2C unit and extends.Operation principle such as Fig. 2 of the ferroelectric nonvolatile memory in 2T-2C unit illustrate.Explanation comprises the line map of the 2T-2C memory cell of sense amplifier among this figure, and WL and PL are respectively word line and printed line among the figure, and BL and BL are pair of bit lines, T ₁～T ₆And T ₈～T ₁₂All be conventional n channel MOS field effect transistor, T ₇Be the P channel MOS tube, C1 and C2 are ferroelectric capacitor, and SP and SN are the clock of sense amplifier.Memory cell is by T ₁, T ₂And C ₁, C ₂Form, sense amplifier is by T ₇～T ₁₂Form.At " 1 " or " 0 " state, C1 is in opposite polarized state all the time with C2.The state of memory cell can define like this: C ₁Be " 0 " (the D point among Fig. 5), C ₂Be one state; Claim that memory cell is in one state.Otherwise then be " 0 " state.Before reading information, by positive pulse pairs of bit line BL and the BL precharge that precharge produces,, choose the unit of reading then as the stage among Fig. 50, WL and PL current potential are raise, force C ₁Move to C point, C from the D point ₂Move to the C point from the A point.Note C at this moment ₁What experience is non-switching manipulation, C ₂What experience is switching manipulation (being the state counter-rotating), and be the stage 1 this moment.Then the clock SP of sense amplifier and SN raise, in order to open sense amplifier.Because C ₂The experience switching manipulation is so compare C ₁Produce more electric charge and make voltage ratio on the BL, BL comes highly, and sense amplifier can be urged to V with the high voltage person _DdAnd low voltage person is become ground connection.Therefore at stage 2, V _BL→ V _Dd, V _BL→ 0, C ₁And C ₂Each is at C and D point.C ₂State originally is destroyed, and destructiveness that Here it is is read the cause of (DRO) title.So far, the information of BL and BL can be used for having exported, and Here it is the stage 3.In order to make C ₂Revert to reset condition, make PL ground connection, WL remains on high level.During the stage 4, C ₁And C ₂Bias variations make them be in the position of D and E respectively.Φ then _ReadReduction is to close sense amplifier, Φ _PrechargePositive pulse allows BL, and BL ground connection is discharged, and be the stage 5 this moment, C ₁With C ₂Be in the position of D and A respectively, promptly got back to the preceding position of the information that reads.Last WL ground connection, thus whole read operation finished.Be in " 0 " state, i.e. C if memory cell is original ₁Be " 1 " (A point), C ₂Be " 0 " (D point) that it is similar fully with process that it reads principle.Similar about the method for operation of writing " 0 " and one writing, will not carefully state.

The present invention is when normal running such as Fig. 1, and PCH is low level always, and any moment changes to when high from low when clock, and after certain propagation delay time (TPHL), the Q of F piece and Q will be lockable and stablize.Then, PL and WL add high level, because Q is opposite with Q, and according to the principle of 2T-2C ferroelectric memory, opposite data will be incorporated into C _F1And C _F2If Q is a high level, Q is a low level, C _F1Polarization state after writing, will be inverted and C _F2Polarization state nonreversible, therefore 2 opposite binary conditions are written into C _F1(logic state upset) and C _F2(logic state is not overturn), if Q is a low level, Q is a high level, the result will be opposite.If we can define ferroelectric capacitor (C _F1Or C _F2) the high level driving, then be in one state, for example C in this example _F1Drive by Q.Another then is " 0 " attitude, when clock from hypermutation after low, PL and WL connect low level with C _F1, C _F2Keep apart with Q and Q, so just finish one-period, when next clock arrives, will repeat identical ablation process.

Because the data of Q and Q are stored in C in each clock cycle _F1And CF ₂, sequential logical element F just becomes nonvolatile, because C _F1And C _F2Be nonvolatile, when power supply interruption suddenly or middle the interruption, data will still be stored in C _F1And C _F2In, behind power up, clock should be arranged at low level earlier, control signal PCH gives T3 and positive pulse of T4 then, therefore Q and q will be set to low level simultaneously, Q and Q are unstable because of being in low level simultaneously like this, are set at high level at the trailing edge WL and the PL of PCH pulse, if C _F2Be " 1 ", C _F1Be " 0 ", then C _F2To be inverted C _F1Nonreversible, in other words, C _F2To provide more that multiple current removes to drive Q, and C _F1Can not, non-stable Q of result and Q are driven to its stable state high level and low level respectively.Conversely, stable Q and Q will write back them state to C _F1And C _F2In above-mentioned write operation, PL and WL need have enough pulse durations, so C _F1To be inverted to " 1 ", and C _F2Keep non-counter-rotating.This step is called from recovering (Self-restoring).When PL and WL were set to low level, whole moving commentaries on classics finished, and system restoration is to normal condition, i.e. state before the power interruptions.Because C _F1And C _F2Write time and time for reading be about 10nS, it is consistent with typical C mos logic circuit speed, these non-volatile devices are used for latching of routine or flip-flop circuit and the complete operation of its speed of not obvious reduction mean that PCH is the signal of system's control, under normal operation, WL and PL are the signals of partial controllable system.But WL and PL are the controllable signals of system when power-on or recovery power supply.

The manufacturing of ferroelectric memory then with the CMOS process compatible of routine, the key component of ferroelectric memory---the ferroelectric capacitor manufacturing process is carried out after CMOS technology is finished, and then carries out interconnected, passivation etc., is the integrated circuit common process.

Non-volatile latch cicuit of the present invention has significant advantage.(1) though its system-level formation with conventional identical, new non-volatile computer system can be protected all data when dump; To each clock or instruction cycle, it all can keep all logic states.Recover if power supply interrupts probable back suddenly, it all is stored in all logical states in the circuit that comprises memory.For example, when someone on computers during editing files, in 10 minutes, do not preserve and power supply interrupts suddenly, power up after 2 hours, the computer with non-volatile logic function will provide with 2 hours before identical result.This holding property is also extremely important for tester.For example, when the test of the common testing equipment of certain human needs circuit that follow-on test whole night just can finish or system, if interrupt and test is interrupted in the test intermediate power supplies, though restore electricity after 10 minutes, observation test in second day is as a result the time, discovery stops because of outage makes test, if use non-volatile digital system, power interruptions is just like the effect of a time-out, when power up, each process of carrying out continues automatically, and each data loses never.(2) non-volatile computer system (employing non-volattilizing logic circuit) can be saved the energy.No matter when, when after the start for example 10 minutes not during contact system for some time, whole system was except the unit of low-power consumption for example keyboard or the mouse, all will close automatically, when contacting any key or mouse, whole system activates automatically, and identical result before demonstrating and closing.This characteristic is very useful in portable system.(3) new non-volatile computer system can be selected the startup installation steps arbitrarily.No matter when, when we open or start computer, command code be installed usually be the main storage much higher for example DRAM or SRAM from the BIOS ROM of low access speed to speed.In fact, for the most computers system, reading and BIOS is transferred to main storage is the main task that starts, and installing generally speaking needs time a few minutes, and depends on the complexity of BIOS.Adopt new non-volatile computer system, this step can be selected arbitrarily, i.e. the BIOS direct coding can be entered main storage during chip manufacturing, must use the ferroelectric nonvolatile memory of read/write fast certainly, and it is shorter therefore to start institute's time.Just in case BIOS damaged or when losing in main memory, it can provide an optional conventional BIOS ROM in the system.

Non-volatile ferroelectric latch technique of the present invention can make various logic circuitry all have non-volatile function, and this will produce significant impact to fields such as computer technologies.The present invention compares it with semiconductor memory can write the number of times height again, can reach 10 ¹⁰～10 ¹², and the latter only is 10 ⁴～10 ⁵Its access time is short, is 50ns～100ns, and the latter such as E ²PROM is 5ms; It is low in energy consumption, and at 3～5V even more can work under the low-voltage, and latter's operating voltage is much higher.Present technique can be used for the computer system of all kinds, because the characteristic of its low-power consumption is more suitable for being used for various portable system, hand-held computer for example, individual digital information system, portable PCS Personal Communications System, smart card, data acquisition system, tester etc.

Fig. 1 is a structure chart of the present invention.

Fig. 2 is the fundamental diagram of ferroelectric memory.

Fig. 3 is the circuit structure diagram that the present invention is used for cmos latch.

Fig. 4 is the circuit structure diagram that the present invention is used for d type flip flop.

Fig. 5 is the ferroelectric memory schematic diagram in 2T-2C unit.

Embodiment 1 is that the present invention is used for cmos latch, as Fig. 3.Embodiment 2 is that the present invention is used for d type flip flop, as Fig. 4.

Claims (1)

1, a kind of ferroelectric latch technique that is used for non-volattilizing logic circuit mainly is made up of ferroelectric capacitor and latch cicuit, it is characterized in that two ferroelectric capacitor C _F1, C _F2With two MOS transistor, each end points with them is connected with the output and the complementary output thereof of latch cicuit, and another end points of two electric capacity links together, and constitutes non-volattilizing logic circuit.

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