CN118018200A - Encryption and decryption realization method and device - Google Patents
Encryption and decryption realization method and device Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
- H04L9/0861—Generation of secret information including derivation or calculation of cryptographic keys or passwords
- H04L9/0877—Generation of secret information including derivation or calculation of cryptographic keys or passwords using additional device, e.g. trusted platform module [TPM], smartcard, USB or hardware security module [HSM]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
- H04L9/0816—Key establishment, i.e. cryptographic processes or cryptographic protocols whereby a shared secret becomes available to two or more parties, for subsequent use
- H04L9/0819—Key transport or distribution, i.e. key establishment techniques where one party creates or otherwise obtains a secret value, and securely transfers it to the other(s)
- H04L9/0825—Key transport or distribution, i.e. key establishment techniques where one party creates or otherwise obtains a secret value, and securely transfers it to the other(s) using asymmetric-key encryption or public key infrastructure [PKI], e.g. key signature or public key certificates
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Abstract
The invention discloses an encryption and decryption implementation method and device, wherein the device comprises an encryption module and a decryption module, the encryption module is used for obtaining plaintext data and a public key, encrypting the plaintext data by using the public key to obtain an original ciphertext, judging whether the bit length of the original ciphertext is larger than a preset value, if so, reporting errors, otherwise, inputting a compression signal, a first parameter and the original ciphertext to an arithmetic unit for compression processing to obtain a final ciphertext; and the decryption module is used for acquiring the ciphertext data and the private key, judging whether the bit length of the ciphertext data is larger than a preset value, if yes, reporting errors, otherwise, inputting the decompression signal, the second parameter and the ciphertext data to the arithmetic unit for decompression processing to obtain an intermediate ciphertext, and decrypting the intermediate ciphertext by using the private key to obtain plaintext data. The invention combines the multiplier and the adder with the selector, realizes the compression and decompression processes adaptable to various parameters, completes the encryption and decryption processes, saves the hardware cost and improves the efficiency.
Description
Technical Field
The present invention relates to the field of information security, and in particular, to an encryption and decryption implementation method and device.
Background
With the progress of science and technology, users pay more and more attention to the security of personal information, so that some processes, such as encryption and decryption, need to be performed on the personal information. The encryption and decryption technology can involve compression and decompression processes, in the prior art, division operation is used in the compression and decompression processes, the cost of the division operation is too high for the realization of a circuit, and the efficiency of the encryption and decryption process can be influenced, so that an implementation scheme capable of improving the encryption and decryption processing rate is needed to be provided.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides an encryption and decryption implementation method and device.
In a first aspect, an embodiment of the present invention provides an encryption and decryption implementation apparatus, including an encryption module and a decryption module, where the encryption module and the decryption module are implemented by combining a program running on a CPU with an arithmetic unit;
The encryption module is used for obtaining plaintext data and a public key, encrypting the plaintext data by using the public key to obtain an original ciphertext, judging whether the bit length of the original ciphertext is larger than a preset value, if so, reporting errors, otherwise, inputting a compression signal, a first parameter and the original ciphertext to an arithmetic unit for compression processing to obtain a final ciphertext;
the decryption module is used for acquiring ciphertext data and a private key, judging whether the bit length of the ciphertext data is larger than a preset value, if yes, reporting errors, otherwise, inputting a decompression signal, a second parameter and the ciphertext data to an arithmetic unit for decompression processing to obtain an intermediate ciphertext, and decrypting the intermediate ciphertext by using the private key to obtain plaintext data;
the arithmetic unit includes: a first selector, a multiplier, a second selector, and an adder;
The first selector is used for selecting input data according to a received signal, storing the input data in a first register, and storing original data in a second register, wherein the original data is the original ciphertext or the ciphertext data;
the multiplier is used for multiplying the data in the first register and the data in the second register to obtain a multiplication result and storing the multiplication result in a third register;
The second selector is configured to select a parameter according to the received signal, obtain preset data according to the received signal, generate a first preset length according to the parameter and the preset data, obtain data of the first preset length from a high order of the data in the third register, obtain intercepted data, and store the intercepted data in the fourth register;
and the adder is used for carrying out addition operation on the data in the fourth register and a preset constant to obtain an addition result, extracting final data from the addition result according to the received signal and outputting the final data.
In a second aspect, an embodiment of the present invention further provides an encryption and decryption implementation method, including an encryption implementation process and a decryption implementation process, where the encryption implementation process and the decryption implementation process are implemented by combining software running on a CPU with an arithmetic unit;
The encryption implementation process comprises the following steps: the CPU acquires plaintext data and a public key, encrypts the plaintext data by using the public key to obtain an original ciphertext, judges whether the bit length of the original ciphertext is larger than a preset value, if yes, reports errors, otherwise, inputs a compression signal, a first parameter and the original ciphertext to an arithmetic unit to perform compression processing to obtain a final ciphertext;
The decryption implementation process comprises the following steps: the CPU acquires ciphertext data and a private key, judges whether the bit length of the ciphertext data is larger than a preset value, if yes, reports errors, otherwise inputs a decompression signal, a second parameter and the ciphertext data to an arithmetic unit for decompression processing to obtain an intermediate ciphertext, and decrypts the intermediate ciphertext by using the private key to obtain plaintext data;
The process of inputting the compressed signal, the first parameter and the original ciphertext to the arithmetic unit for compression processing to obtain a final ciphertext is the same as the process of inputting the decompressed signal, the second parameter and the ciphertext data to the arithmetic unit for decompression processing to obtain an intermediate ciphertext, and the method specifically comprises the following steps:
step S1: the CPU selects input data according to the received signals through a first selector, stores the input data in a first register, and stores original data in a second register, wherein the original data is original ciphertext or ciphertext data;
Step S2: the CPU uses a multiplier to operate the data in the first register and the data in the second register to obtain a multiplication result and stores the multiplication result in a third register;
Step S3: the CPU selects parameters according to the received signals through a second selector, acquires preset data according to the received signals, generates a first preset length according to the parameters and the preset data, acquires the data with the first preset length from the high order of the data in the third register, acquires intercepted data and stores the intercepted data in a fourth register;
Step S4: and the CPU uses an adder to operate the data in the fourth register and a preset constant to obtain an addition result, and extracts final data from the addition result according to the received signal and outputs the final data.
In a third aspect, an embodiment of the present invention further provides an electronic device, where the electronic device includes at least one processor, a memory, and instructions stored on the memory and executable by the at least one processor, and the at least one processor executes the instructions to implement the encryption and decryption implementation method described above.
In a fourth aspect, an embodiment of the present invention further provides a chip system, including a chip, where the chip is coupled to a memory, and is configured to execute a computer program stored in the memory, so as to execute the foregoing encryption and decryption implementation method.
Compared with the prior art, the invention has the following advantages: the invention combines the multiplier and the adder with the selector, realizes the compression and decompression processes adaptable to various parameters, completes the encryption and decryption processes, saves the hardware cost and improves the efficiency.
Drawings
Fig. 1 is a block diagram of an encryption and decryption implementation device according to a first embodiment of the present invention;
FIG. 2 is a flowchart of an arithmetic unit processing procedure in an encryption and decryption implementation method according to a second embodiment of the present invention;
fig. 3 is a flowchart of an encryption implementation method according to a third embodiment of the present invention;
fig. 4 is a flowchart of a decryption implementation method according to a fourth embodiment of the present invention.
Detailed Description
The application provides an encryption and decryption implementation method and device, and a detailed description of a specific embodiment of the application is given below with reference to the accompanying drawings. Examples of which are illustrated in the accompanying drawings. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the application.
It will be understood by those skilled in the art that all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs unless defined otherwise. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in further detail with reference to the accompanying drawings.
Example 1
The first embodiment of the invention provides an encryption and decryption implementation device, as shown in fig. 1, where the encryption and decryption implementation device includes an encryption module and a decryption module, where the encryption module and the decryption module are implemented by combining a program running on a CPU with an arithmetic unit;
The encryption module is used for obtaining plaintext data and a public key, encrypting the plaintext data by using the public key to obtain an original ciphertext, judging whether the bit length of the original ciphertext is larger than a preset value, if so, reporting errors, otherwise, inputting a compression signal, a first parameter and the original ciphertext to the arithmetic unit for compression processing to obtain a final ciphertext;
The decryption module is used for acquiring ciphertext data and a private key, judging whether the bit length of the ciphertext data is larger than a preset value, if yes, reporting errors, otherwise, inputting a decompression signal, a second parameter and the ciphertext data to an arithmetic unit for decompression processing to obtain an intermediate ciphertext, and decrypting the intermediate ciphertext by using the private key to obtain plaintext data;
the preset value in this embodiment is set according to the bit length of the multiplier, preferably 12;
The operator in the present embodiment includes: a first selector, a multiplier, a second selector, and an adder;
A first selector for selecting input data according to the received signal and storing the selected input data in a first register, and storing the original data in a second register;
in this embodiment, the original data is an original ciphertext or ciphertext data;
If the received signal is a compressed signal, the first selector is specifically configured to select the first input data according to the compressed signal, store the first input data in the first register, and store the original ciphertext in the second register; if the received signal is a decompressed signal, the first selector is specifically configured to select second input data according to the decompressed signal, store the second input data in the first register, and store ciphertext data in the second register;
In this embodiment, the data is stored in the register from the lower bit, and the data with the bit length smaller than the capacity of the register is default to 0;
preferably, the capacity of the first register is set to 22 bits and the capacity of the second register is set to 12 bits according to the multiplier;
For example, the first input data selected by the first selector in the arithmetic unit of the encryption module is 0x275f6f, and the second input data selected by the first selector in the arithmetic unit of the decryption module is 0xd01;
The multiplier is used for multiplying the data in the first register and the data in the second register to obtain a multiplication result and storing the multiplication result in the third register;
specifically, the multiplier is a 22-bit by 12-bit multiplier;
preferably, the capacity of the third register is set to 34 bits according to the multiplier, if the bit length of the multiplication result is smaller than the capacity of the third register, the high-order data in the third register defaults to 0;
the second selector is used for selecting parameters according to the received signals, acquiring preset data according to the received signals, generating a first preset length according to the selected parameters and the preset data, acquiring the data with the first preset length from the high order of the data in the third register, acquiring intercepted data and storing the intercepted data in the fourth register;
Optionally, if the received signal is a compressed signal, the second selector is specifically configured to select a first parameter according to the compressed signal, obtain first preset data according to the compressed signal, and obtain a first preset length by adding the first preset data to the first parameter;
For example, the first preset data is 2, the first parameter may be any value between 2 and 11, and in this embodiment, specifically, 4,5, 10, and 11 are taken as examples, and the corresponding first preset length is 6 bits, 7 bits, 12 bits, or 13 bits; preferably, the first parameter is 4, and the first preset data is 2, and the first preset length is 6 bits;
Optionally, if the received signal is a decompressed signal, the second selector is specifically configured to select a second parameter according to the decompressed signal, obtain second preset data according to the decompressed signal, and subtract the second parameter from the second preset data to obtain the first preset length;
For example, the second preset data is 35, the second parameter may be any value between 2 and 11, in this embodiment, the second parameter specifically takes 4, 5, 10, and 11 as examples, and the first preset length is 31 bits or 30 bits or 25 bits or 24 bits; preferably, the second parameter is 4, the second preset data is 35, and the first preset length is 31 bits;
Preferably, the capacity of the fourth register is set to 33 bits according to the number of bits of the adder;
The adder is used for carrying out addition operation on the data in the fourth register and a preset constant to obtain an addition result, extracting final data from the addition result according to the received signal and outputting the final data;
specifically, the preset constant in this embodiment is 1, and the adder is a 33-bit plus 1-bit adder;
If the received signal is a compressed signal, extracting final data from the addition result according to the received signal and outputting the final data, specifically: the least significant bit and the most significant bit in the addition result are removed according to the compressed signal to obtain final data and output;
If the received signal is a decompressed signal, final data is extracted from the addition result according to the received signal and output, specifically: and the least significant bit in the addition result is truncated according to the decompressed signal to obtain final data and output.
The invention uses the circuit of the multiplier and the adder combined with the selector to realize the compression and decompression processes adaptable to various parameters, complete the encryption and decryption processes, save the hardware cost and improve the efficiency.
Example two
The second embodiment of the invention provides an encryption and decryption implementation method, which comprises an encryption implementation process and a decryption implementation process, wherein the encryption implementation process and the decryption implementation process are implemented by combining software running on a CPU with an arithmetic unit;
The encryption realization process comprises the following steps: CPU (Chinese full name: central processing unit; english full name: central Processing Unit) obtains plaintext data and public key, and encrypts the plaintext data by using public key to obtain original ciphertext, judges whether the bit length of the original ciphertext is larger than a preset value, if yes, reports error, otherwise, inputs compressed signal, first parameter and original ciphertext to an arithmetic unit to perform compression processing to obtain final ciphertext;
the preset value in this embodiment is set according to the bit length of the multiplier, preferably 12;
The decryption implementation process comprises the following steps: the CPU acquires ciphertext data and a private key, judges whether the bit length of the ciphertext data is larger than a preset value, if yes, the error is reported, otherwise, a decompression signal, a second parameter and the ciphertext data are input to an arithmetic unit for decompression processing to obtain an intermediate ciphertext, and the intermediate ciphertext is decrypted by using the private key to obtain plaintext data;
The process of inputting the compressed signal, the first parameter and the original ciphertext to the arithmetic unit for compression processing to obtain the final ciphertext in the encryption process is the same as the process of inputting the decompressed signal, the second parameter and the ciphertext data to the arithmetic unit for decompression processing to obtain the intermediate ciphertext in the decryption process, and the specific process is as shown in fig. 2, and includes:
Step S1: the CPU selects input data according to the received signals through a first selector, stores the selected input data in a first register, and stores the original data in a second register;
The original data in this embodiment is original ciphertext or ciphertext data;
In this embodiment, step S1 includes: the CPU selects first input data according to the received compression signal through a first selector, stores the first input data in a first register, and stores an original ciphertext in a second register;
or, the CPU selects the second input data according to the received decompression signal through the first selector and stores the second input data in the first register, and stores the ciphertext data in the second register;
The data in the first register is first input data, the original data in the second register is original ciphertext or the original data in the first register is second input data, and the original data in the second register is ciphertext data;
In this embodiment, the data is stored in the register from the lower bit, and the data with the bit length smaller than the capacity of the register is default to 0;
For example, the first input data is 0x275f6f, and the second input data is 0xd01;
Step S2: the CPU uses the multiplier to operate the data in the first register and the data in the second register to obtain a multiplication result and stores the multiplication result in the third register;
specifically, the multiplier is a 22-bit by 12-bit multiplier;
Preferably, the capacity of the third register is set to 34 bits according to the multiplier;
Step S3: the CPU selects parameters according to the received signals through the second selector, acquires preset data according to the received signals, generates a first preset length according to the selected parameters and the preset data, acquires the data with the first preset length from the high order of the data in the third register, acquires intercepted data and stores the intercepted data in the fourth register;
Optionally, the CPU selects parameters according to the received signal through the second selector, obtains preset data according to the received signal, and generates a first preset length according to the selected parameters and the preset data, including: the CPU selects a first parameter according to the compressed signal through a second selector, acquires first preset data according to the compressed signal, and adds the first preset data to the first parameter to acquire a first preset length;
For example, the first preset data is 2, the first parameter may be any value between 2 and 11, and in this embodiment, specifically, 4,5, 10, and 11 are taken as examples, and the corresponding first preset length is 6 bits, 7 bits, 12 bits, or 13 bits; preferably, the first parameter is 4, and the first preset data is 2, and the first preset length is 6 bits;
Optionally, the CPU selects parameters according to the received signal through the second selector, obtains preset data according to the received signal, and generates a first preset length according to the selected parameters and the preset data, including: the CPU selects a second parameter according to the decompression signal through a second selector, acquires second preset data according to the decompression signal, and subtracts the second parameter from the second preset data to obtain a first preset length;
For example, the second preset data is 35, the second parameter may be any value between 2 and 11, in this embodiment, the second parameter is specifically illustrated by 4,5, 10, and 11, and the corresponding first preset length is 31 bits or 30 bits or 25 bits or 24 bits; preferably, the second parameter is 4, the second preset data is 35, and the first preset length is 31 bits;
step S4: the CPU uses the adder to operate the data in the fourth register and the preset constant to obtain an addition result, and extracts and outputs final data from the addition result according to the received signal;
specifically, the preset constant in this embodiment is 1, and the adder is a 33-bit plus 1-bit adder;
Preferably, the capacity of the fourth register is set to 33 bits according to the number of bits of the adder;
optionally, in this embodiment, extracting final data from the addition result according to the received signal and outputting the final data includes: and the lowest bit and the highest bit in the addition result are truncated according to the received compressed signal to obtain final data and output, or the lowest bit in the addition result is truncated according to the received decompressed signal to obtain final data and output.
Example III
An embodiment of the present invention provides an encryption implementation method, as shown in fig. 3, including:
step 301: the CPU acquires plaintext data and a public key, and encrypts the plaintext data by using the public key to obtain an original ciphertext;
step 302: the CPU judges whether the bit length of the original ciphertext is larger than a preset value, if yes, the error is reported, otherwise, the step 303 is executed;
the preset value in this embodiment is set according to the bit length of the multiplier, preferably 12;
Step 303: the CPU inputs the compressed signal, the first parameter and the original ciphertext to the arithmetic unit for compression processing to obtain a final ciphertext;
Preferably, the original ciphertext is 12-bit long data;
the operator in the present embodiment includes a first selector, a multiplier, a second selector, and an adder;
Specifically, in this embodiment, step 303 includes:
Step 3031: the CPU selects first input data according to the compression signal through a first selector, stores the first input data in a first register, and stores an original ciphertext in a second register;
for example, in the present embodiment, the first input data is 0x275f6f, the original ciphertext is 0x3ac, the data in the first register is 10 0111 0101 1111 0110 1111, and the data in the second register is 0011 1010 1100;
Step 3032: the CPU uses the multiplier to operate the data in the first register and the data in the second register to obtain a first multiplication result and stores the first multiplication result in a third register;
Specifically, the multiplier is a 22-bit by 12-bit multiplier, and the capacity of the third register is set to 34 bits according to the bit length of the multiplier;
For example, in this embodiment, the first multiplication result 1001 0000 1001 0010 0110 1011 1001 0100 obtained by using the multiplier to calculate the data 10 0111 0101 1111 0110 1111 in the first register and the data 0011 1010 1100 in the second register is: 00 1001 0000 1001 0010 0110 1011 1001 0100;
Step 3033: the CPU selects a first parameter according to the compressed signal through a second selector, acquires first preset data according to the compressed signal, acquires a first preset length by adding the first preset data to the first parameter, acquires data of the first preset length from the high order of the data in a third register, acquires first intercepted data and stores the first intercepted data in a fourth register;
Preferably, the capacity of the fourth register is set to 33 according to the bit length of the adder;
For example, the first preset data is 2, the first parameter may be any value between 2 and 11, in this embodiment, the first parameter is specifically illustrated by 4, 5, 10, and 11, and the corresponding first preset length is 6 bits or 7 bits or 12 bits or 13 bits;
Preferably, the first parameter is4, the first preset data is2, the first preset length is 6, the first intercepted data obtained by acquiring 6-bit data (001001) from the high order of the data 0010010000100100100110101110010100 in the third register is 0x09 and stored in the fourth register, and the data in the fourth register is 000 0000 0000 0000 0000 0000 0000 0000 1001;
Step 3034: the CPU uses an adder to calculate the data in the fourth register and a preset constant to obtain a first addition result, and the lowest bit and the highest bit in the first addition result are truncated according to the compressed signal to obtain a final ciphertext and output the final ciphertext;
specifically, the preset constant in this embodiment is 1, and the adder is a 33-bit plus 1-bit adder;
for example, the CPU uses the adder to calculate the data 000 0000 0000 0000 0000 0000 0000 0000 1001 in the fourth register with the preset constant 1 to obtain a first addition result of 0x0a (000 0000 0000 0000 0000 0000 0000 0000 1010), truncates the most significant bit and the least significant bit in 000 0000 0000 0000 0000 0000 0000 0000 1010 to obtain 00000 0000 0000 0000 0000 0000 0000 0101, and outputs a final ciphertext of 0x5.
Example IV
A fourth embodiment of the present invention provides a decryption implementation method, as shown in FIG. 4, including:
step 401: the CPU acquires ciphertext data and a private key, judges whether the bit length of the ciphertext data is larger than a preset value, if yes, the error is reported, otherwise, the step 402 is executed;
Step 402: the CPU inputs the decompressed signal, the second parameter and the ciphertext data to the arithmetic unit for decompression processing to obtain an intermediate ciphertext;
Step 403: the CPU uses the private key to decrypt the intermediate ciphertext to obtain plaintext data;
the operator in the present embodiment includes a first selector, a multiplier, a second selector, and an adder;
Specifically, in this embodiment, step 402 includes:
Step 4021: the CPU selects second input data according to the decompression signal through the first selector and stores the second input data in the first register, and stores ciphertext data in the second register;
preferably, in the present embodiment, the capacity of the first register is set to 22 bits and the capacity of the second register is set to 12 bits according to the bit length of the multiplier;
For example, in the present embodiment, the second input data is 0xd01, the ciphertext data is 0x5, the data in the first register is 00 0000 0000 1101 0000 0001, and the data in the second register is 0000 0000 0101;
Step 4022: the CPU uses the multiplier to operate the data in the first register and the data in the second register to obtain a second multiplication result and stores the second multiplication result in a third register;
Specifically, the multiplier is a 22-bit by 12-bit multiplier, and the capacity of the third register is set to 34 bits according to the bit length of the multiplier;
For example, in step 4022, the CPU uses the multiplier to calculate the data 00 0000 0000 1101 0000 0001 in the first register and the data 0000 0000 0101 in the second register to obtain a second multiplication result of 100 0001 0000 0101, and the data in the third register is 00 0000 0000 0000 0000 0100 0001 0000 0101;
Step 4023: the CPU selects a second parameter according to the decompression signal through a second selector, acquires second preset data according to the decompression signal, subtracts the second parameter from the second preset data to acquire a first preset length, acquires the data of the first preset length from the highest bit of the data in a third register to acquire second intercepted data and stores the second intercepted data in a fourth register;
Preferably, the capacity of the fourth register is set to 33 bits according to the adder;
For example, the second preset data is 35, the second parameter may be any value between 2 and 11, in this embodiment, the second parameter is specifically illustrated by 4, 5, 10, and 11, and the corresponding first preset length is 31 or 30 or 25 or 24;
Preferably, the second preset data is 35, the second parameter is 4, the first preset length is 31 bits, the second intercepted data obtained in the step is 000 0000 0000 0000 0000 1000 0010 0000, and the data in the fourth register is 00000 0000 0000 0000 0000 1000 0010 0000;
Step 4024: the CPU uses an adder to operate the data in the fourth register and a preset constant to obtain a second addition result, and the lowest bit in the first addition result is truncated according to the decompression signal to obtain an intermediate ciphertext and output the intermediate ciphertext;
specifically, the preset constant in this embodiment is 1, and the adder is a 33-bit plus 1-bit adder;
For example, in this step, the CPU uses the adder to calculate the data 000 0000 0000 0000 0000 0000 1000 0010 0000 in the fourth register with the preset constant 1 to obtain a second addition result of 000 000 0000 0000 0000 0000 1000 0010 0001, truncates the lowest order in 000 000 0000 0000 0000 0000 1000 0010 0001 to obtain 00000 0000 0000 0000 0000 0100 0001 0000, and outputs the intermediate ciphertext of 0x410.
The encryption and decryption implementation method of the embodiment can be applied to different scenes, for example, encryption steps related to signature, decryption processes related to signature verification, encryption and decryption processes related to identity authentication, and the like, and are not described herein.
Optionally, an embodiment of the present application further provides an electronic device, where the electronic device includes at least one processor, a memory, and instructions stored on the memory and executable by the at least one processor, and the at least one processor executes the instructions to implement the encryption and decryption implementation method in the foregoing embodiment. When the electronic device is a chip system, the electronic device may be formed by a chip, or may include a chip and other discrete devices, which is not particularly limited in the embodiment of the present application; the chip is coupled to the memory and is used for executing the computer program stored in the memory to execute the encryption and decryption implementation method disclosed in the above embodiment.
In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using a software program, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs. The processes or functions described in accordance with the embodiments of the present application are all or partially generated when the computer program is loaded and executed on an electronic device. The computer program may be stored in or transmitted from one computer readable storage medium to another, for example, the computer instructions may be transmitted from one base station, electronic device, server, or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means to another base station, electronic device, server, or data center. The computer readable storage medium may be any available medium that can be accessed by an electronic device or a data storage device including one or more servers, data centers, etc. that can be integrated with the medium. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid State Disk (SSD)), etc. In an embodiment of the present application, an electronic device may include the foregoing apparatus.
Although the application is described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
Although the application has been described in connection with specific features and embodiments thereof, it will be apparent that various modifications and combinations can be made without departing from the spirit and scope of the application. Accordingly, the specification and drawings are merely exemplary illustrations of the present application as defined in the appended claims and are considered to cover any and all modifications, variations, combinations, or equivalents that fall within the scope of the application. It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (10)
1. The encryption and decryption realizing device is characterized by comprising an encryption module and a decryption module, wherein the encryption module and the decryption module are realized by combining a program running on a CPU with an arithmetic unit;
The encryption module is used for obtaining plaintext data and a public key, encrypting the plaintext data by using the public key to obtain an original ciphertext, judging whether the bit length of the original ciphertext is larger than a preset value, if so, reporting errors, otherwise, inputting a compression signal, a first parameter and the original ciphertext to an arithmetic unit for compression processing to obtain a final ciphertext;
the decryption module is used for acquiring ciphertext data and a private key, judging whether the bit length of the ciphertext data is larger than a preset value, if yes, reporting errors, otherwise, inputting a decompression signal, a second parameter and the ciphertext data to an arithmetic unit for decompression processing to obtain an intermediate ciphertext, and decrypting the intermediate ciphertext by using the private key to obtain plaintext data;
the arithmetic unit includes: a first selector, a multiplier, a second selector, and an adder;
The first selector is used for selecting input data according to a received signal, storing the input data in a first register, and storing original data in a second register, wherein the original data is the original ciphertext or the ciphertext data;
the multiplier is used for multiplying the data in the first register and the data in the second register to obtain a multiplication result and storing the multiplication result in a third register;
The second selector is configured to select a parameter according to the received signal, obtain preset data according to the received signal, generate a first preset length according to the parameter and the preset data, obtain data of the first preset length from a high order of the data in the third register, obtain intercepted data, and store the intercepted data in the fourth register;
and the adder is used for carrying out addition operation on the data in the fourth register and a preset constant to obtain an addition result, extracting final data from the addition result according to the received signal and outputting the final data.
2. The encryption and decryption implementation device according to claim 1, wherein the first selector is specifically configured to select first input data according to a compressed signal, store the first input data in a first register, and store the original ciphertext in a second register;
The first selector is specifically further configured to select second input data according to the decompression signal, store the second input data in the first register, and store the ciphertext data in the second register.
3. The encryption and decryption implementation device according to claim 1, wherein the second selector is specifically configured to select a first parameter according to the compressed signal, obtain first preset data according to the compressed signal, obtain a first preset length by adding the first preset data to the first parameter, obtain data with the first preset length from a high order of the data in the third register, obtain intercepted data, and store the intercepted data in a fourth register;
The second selector is specifically further configured to select a second parameter according to the decompression signal, obtain second preset data according to the decompression signal, subtract the second parameter from the second preset data to obtain a first preset length, obtain data with the first preset length from a high bit of the data in the third register to obtain intercepted data, and store the intercepted data in the fourth register.
4. The encryption and decryption implementation device according to claim 1, wherein the adder is specifically configured to perform an addition operation on the data in the fourth register and a preset constant to obtain an addition result, discard a least significant bit and a most significant bit in the addition result according to the compression signal to obtain final data, and output the final data;
The adder is specifically further configured to perform an addition operation on the data in the fourth register and a preset constant to obtain an addition result, discard the lowest bit in the addition result according to the decompression signal, obtain final data, and output the final data.
5. The encryption and decryption implementation method is characterized by comprising an encryption implementation process and a decryption implementation process, wherein the encryption implementation process and the decryption implementation process are implemented by combining software running on a CPU with an arithmetic unit;
The encryption implementation process comprises the following steps: the CPU acquires plaintext data and a public key, encrypts the plaintext data by using the public key to obtain an original ciphertext, judges whether the bit length of the original ciphertext is larger than a preset value, if yes, reports errors, otherwise, inputs a compression signal, a first parameter and the original ciphertext to an arithmetic unit to perform compression processing to obtain a final ciphertext;
The decryption implementation process comprises the following steps: the CPU acquires ciphertext data and a private key, judges whether the bit length of the ciphertext data is larger than a preset value, if yes, reports errors, otherwise inputs a decompression signal, a second parameter and the ciphertext data to an arithmetic unit for decompression processing to obtain an intermediate ciphertext, and decrypts the intermediate ciphertext by using the private key to obtain plaintext data;
The process of inputting the compressed signal, the first parameter and the original ciphertext to the arithmetic unit for compression processing to obtain a final ciphertext is the same as the process of inputting the decompressed signal, the second parameter and the ciphertext data to the arithmetic unit for decompression processing to obtain an intermediate ciphertext, and the method specifically comprises the following steps:
step S1: the CPU selects input data according to the received signals through a first selector, stores the input data in a first register, and stores original data in a second register, wherein the original data is original ciphertext or ciphertext data;
Step S2: the CPU uses a multiplier to operate the data in the first register and the data in the second register to obtain a multiplication result and stores the multiplication result in a third register;
Step S3: the CPU selects parameters according to the received signals through a second selector, acquires preset data according to the received signals, generates a first preset length according to the parameters and the preset data, acquires the data with the first preset length from the high order of the data in the third register, acquires intercepted data and stores the intercepted data in a fourth register;
Step S4: and the CPU uses an adder to operate the data in the fourth register and a preset constant to obtain an addition result, and extracts final data from the addition result according to the received signal and outputs the final data.
6. The encryption and decryption implementation method according to claim 5, wherein the step S1 includes: the CPU selects first input data according to the received compression signal through a first selector, stores the first input data in a first register and stores the original ciphertext in a second register;
Or, the CPU selects the second input data according to the received decompression signal through the first selector, stores the second input data in the first register, and stores the ciphertext data in the second register.
7. The encryption and decryption implementation method according to claim 5, wherein the CPU selects parameters according to the received signal through the second selector, obtains preset data according to the received signal, and generates a first preset length according to the parameters and the preset data, including:
The CPU selects a first parameter according to the compressed signal through a second selector, obtains first preset data according to the compressed signal, and adds the first preset data to the first parameter to obtain a first preset length; or, the CPU selects a second parameter according to the decompression signal through a second selector, acquires second preset data according to the decompression signal, and subtracts the second parameter from the second preset data to obtain a first preset length.
8. The encryption and decryption implementation method according to claim 5, wherein the extracting final data from the addition result according to the received signal and outputting includes: and the final data is obtained by truncating the least significant bit and the most significant bit in the addition result according to the received compressed signal and is output, or the final data is obtained by truncating the least significant bit in the addition result according to the received decompressed signal and is output.
9. An electronic device comprising at least one processor, a memory, and instructions stored on the memory and executable by the at least one processor, the at least one processor executing the instructions to implement the encryption and decryption implementation method of any one of claims 5 to 8.
10. A chip, wherein the chip is coupled to a memory for executing a computer program stored in the memory to perform the encryption and decryption implementation method according to any of claims 5 to 8.
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| CN116137564A (en) * | 2021-11-18 | 2023-05-19 | 合肥本源量子计算科技有限责任公司 | Ciphertext decryption method and related equipment |
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