CN118018172B - Domain controller time synchronization system - Google Patents
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Abstract
The invention provides a time synchronization system of a domain controller, which comprises an application processor and a vehicle-mounted processor which are communicated with each other, wherein after an operating system of the application processor is started, if a time correction application program is not operated, the first time is determined as system time; if the timing application program is operated, determining the current time as the system time at intervals of a first preset time length, generating a heartbeat message at intervals of a second preset time length, and sending the heartbeat message to the vehicle-mounted processor; after receiving the heartbeat message, the vehicle-mounted processor acquires the system time included in the heartbeat message, and if the system time is within a first preset period, the system time is determined to be the current time of the real-time clock chip; otherwise, the first time is determined as the system time of the vehicle-mounted processor. The method and the device avoid the occurrence of the situation that the time before restarting is synchronized into the vehicle-mounted processor before the effective time is not corrected after the abnormal restarting of the application processor, so that the time of the vehicle-mounted processor is abnormal, and the time of the whole vehicle is abnormal.
Description
Technical Field
The invention relates to the field of vehicle information control, in particular to a time synchronization system of a domain controller.
Background
The hardware architecture of a domain controller of a vehicle typically includes the following two types of processors:
One type is a processor that communicates with a vehicle-side non-intelligent ECU (Electronic Control Unit, electronic controller) via a CAN bus, called VP (Vehicle Processor, onboard processor), which is typically an MCU processor that runs an RTOS system (Real Time Operating System, real-time operating system) that starts faster (about 100-300 ms), and typically does not have a direct networking function.
One type is a processor which communicates with a vehicle-side intelligent ECU through vehicle-mounted Ethernet and a TSP cloud platform and a national standard platform, and is called an AP (Application Processor ), wherein the AP is generally an MPU processor, is slower in starting (about 30-60 s), generally has a networking function (whether networking can be successfully performed depends on a network environment), and has a GPS positioning module (whether normal use can be performed depends on the environment).
Other ECUs on the whole vehicle, such as VCU (core electronic control unit for implementing control decision of the whole vehicle), meters, autopilot domain, BMS (BATTERY management system) and the like, also need time information to implement control strategies and functions thereof, and these ECUs usually have no capability of directly accessing the internet or GPS, so that active timing cannot be performed, and thus the ECU with active timing function, such as a domain controller, is required to perform timing (typically, VP of the domain controller will send a message containing the current time to the whole vehicle through a CAN network period).
However, when the domain controller needs to be restarted under the scenes of abnormal power failure or abnormal watchdog reset of an internal program in the normal operation process, the VP cannot acquire correct time after the VP is started, and at the moment, wrong time can be sent to the whole vehicle because the AP is started slowly. When the vehicle is in an underground garage, a mountain area and other environments with poor network and GPS signals, the AP cannot acquire reliable real-time and cannot synchronize the reliable time to the VP, and at the moment, the VP may also send the wrong time to the whole vehicle. If the wrong time is sent to the whole vehicle, the control strategy of other ECUs is abnormal, if the battery state of the BMS is abnormal, the instrument display is abnormal, and if the battery state of the BMS is abnormal, the situation of false failure of the ECU, the instrument display failure lamp and the like can be caused when the battery state of the BMS is serious, even the operation of an automatic driving domain is abnormal, and the normal operation of the vehicle can be influenced.
Disclosure of Invention
Aiming at the technical problems, the invention adopts the following technical scheme:
According to one aspect of the application, there is provided a domain controller time synchronization system, comprising a domain controller and a plurality of electronic control units, wherein the domain controller comprises an application processor and a vehicle-mounted processor which are communicated with each other, the vehicle-mounted processor comprises a real-time clock chip and a vehicle-mounted timer, the vehicle-mounted timer is used for recording the local time of the vehicle-mounted processor, and the vehicle-mounted processor is connected with each electronic control unit through a CAN bus.
Wherein the application processor is configured to perform the steps of:
in response to receiving a starting signal of an operating system of an application processor, acquiring an operation identifier of a timing application program of the application processor;
If the operation identifier of the timing application program of the application processor indicates that the timing application program is not operated, determining the first time as the system time of the application processor; if the operation identifier of the timing application program of the application processor indicates that the timing application program is operated, acquiring the current time every a first preset time length and determining the current time as the system time of the application processor;
Generating heartbeat messages every second preset time length according to the current system time of the application processor; the second preset time period is smaller than the first preset time period;
And sending the heartbeat message to the vehicle-mounted processor.
Wherein, the on-board processor executes the following steps after receiving the heartbeat message:
acquiring the system time of the application processor included in the heartbeat message in response to receiving the heartbeat message sent by the application processor;
If the system time of the application processor is within the first preset period, determining the system time of the application processor as the current time of the real-time clock chip; otherwise, determining the first time as the system time of the vehicle-mounted processor; the starting time of the first preset time period is located after the first time, and the length of the first preset time period is greater than the first preset time period.
In an exemplary embodiment of the application, the on-board processor is further configured to perform the steps of:
updating the local time recorded by the vehicle-mounted timer to the current time of the real-time clock chip at intervals of a third preset time length; the third preset time period is longer than the second preset time period and shorter than the first preset time period.
In an exemplary embodiment of the present application, updating the local time recorded by the on-board timer to the current time of the real-time clock chip every a third preset duration, further includes:
acquiring the current time of the real-time clock chip and the local time recorded by the vehicle-mounted timer every third preset time length;
If the difference value between the current time of the real-time clock chip and the local time recorded by the vehicle-mounted timer is smaller than a first time difference threshold value, updating the local time recorded by the vehicle-mounted timer into the current time of the real-time clock chip; the first time difference threshold is the product of the timing error of the vehicle-mounted timer and a third preset duration.
In an exemplary embodiment of the present application, if the system time of the application processor is within the first preset period, determining the system time of the application processor as the current time of the real-time clock chip further includes:
If the system time of the application processor is within a first preset period, acquiring the current local time recorded by the vehicle-mounted timer;
If the difference value between the current local time recorded by the vehicle-mounted timer and the system time of the application processor is larger than a preset second time difference threshold value, determining the system time of the application processor as the current time of the real-time clock chip;
and updating the local time recorded by the vehicle-mounted timer into the current time of the real-time clock chip.
In one exemplary embodiment of the application, when the domain controller wakes up in a sleep state, the onboard processor is configured to perform the steps of:
acquiring the current time of a real-time clock chip;
If the current time of the real-time clock chip is within the first preset period, updating the local time recorded by the vehicle-mounted timer to the current time of the real-time clock chip; otherwise, the first time is determined as the local time recorded by the vehicle-mounted timer.
In one exemplary embodiment of the application, after the in-vehicle processor is reset by a reboot, the in-vehicle processor is configured to perform the steps of:
acquiring a restart reset reason of the vehicle-mounted processor;
If the reset source of the vehicle-mounted processor is power-on reset, the first time is determined to be the current time of the real-time clock chip.
In an exemplary embodiment of the present application, if the reset factor of the on-vehicle processor is a power-on reset, determining the first time as the current time of the real-time clock chip further includes:
if the reset reason of the vehicle-mounted processor is not power-on reset, acquiring the current time of the real-time clock chip;
If the current time of the real-time clock chip is within the first preset period, determining the current time of the real-time clock chip as the system time of the vehicle-mounted processor; otherwise, the first time is determined as the system time of the vehicle-mounted processor.
In an exemplary embodiment of the present application, the on-board processor sends timing message information to each electronic control unit every fourth preset time length; the time correction message information comprises the current system time of the vehicle-mounted processor.
In an exemplary embodiment of the application, each electronic control unit, upon receiving the time-of-day message information, is configured to perform the steps of:
Acquiring the current system time of the vehicle-mounted processor included in the time correction message information;
if the current system time of the vehicle-mounted processor is within the first preset period, determining the current system time of the vehicle-mounted processor as the system time of the corresponding electronic control unit; otherwise, a time anomaly signal is sent out.
In an exemplary embodiment of the present application, the starting time of the first preset period is a release time of a software version of the on-vehicle processor, and the length of the first preset period is an average usage duration of a vehicle corresponding to the on-vehicle processor.
The invention has at least the following beneficial effects:
After an operating system of an application processor in the domain controller time synchronization system is started, determining whether a timing application program of the application processor is operated or not by acquiring an operation identifier of the timing application program of the application processor, if the timing application program is not operated, determining a preset first time as a system time of the application processor, wherein the first time is a preset default invalid time; if the time correction application program is operated, acquiring the current time at intervals of a first preset time length, determining the current time as the system time of the application processor, generating heartbeat messages at intervals of a second preset time length according to the current system time of the application processor, and sending the heartbeat messages to the vehicle-mounted processor; after receiving the heartbeat message, the vehicle-mounted processor acquires the system time of the application processor included in the heartbeat message, and if the system time of the application processor is within a first preset period, the system time of the application processor is determined to be the current time of the real-time clock chip; otherwise, the first time is determined as the system time of the vehicle-mounted processor. The method and the device can avoid the situation that the time of the vehicle-mounted processor is abnormal and the time of the whole vehicle is abnormal by synchronizing the time before restarting or at random into the vehicle-mounted processor before the effective time is not corrected after the application processor is abnormally restarted.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a block diagram of a domain controller time synchronization system according to an embodiment of the present invention;
FIG. 2 is a flowchart of a time synchronization method of an application processor of a domain controller time synchronization system according to an embodiment of the present invention;
Fig. 3 is a flowchart of a first embodiment of a method performed by an on-board processor of a domain controller time synchronization system after receiving a heartbeat message according to an embodiment of the present invention;
Fig. 4 is a flowchart of a second embodiment of a method performed by an on-board processor of the domain controller time synchronization system after receiving a heartbeat message according to an embodiment of the present invention;
FIG. 5 is a flowchart of a method executed by a vehicle-mounted processor when a domain controller of the domain controller time synchronization system provided by an embodiment of the present invention is awakened in a sleep state;
fig. 6 is a flowchart of a method performed after a vehicle-mounted processor of the domain controller time synchronization system provided by an embodiment of the present invention is reset.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
The domain controller Time synchronization system of the application, as shown in fig. 1, comprises a domain controller and a plurality of electronic control units, wherein the domain controller comprises an Application Processor (AP) and a vehicle-mounted processor (VP) which are mutually communicated, the vehicle-mounted processor comprises a Real Time Clock (RTC) chip and a vehicle-mounted timer, and the vehicle-mounted processor is connected with each electronic control unit through a CAN bus.
An application processor is the main processor of the operating system running the application and is mainly responsible for executing high-level tasks such as application programs, processing user interfaces, and interacting with users.
On-board processors are typically processors for low-level control and real-time operation of an automobile, for performing tasks related to vehicle hardware and underlying control, responsible for vehicle-level control, monitoring, and communication tasks, such as vehicle networks, underlying hardware interfaces, and the like.
The comprehensive intelligent function of the vehicle is provided through the cooperation of the application processor and the vehicle-mounted processor in the automobile.
The vehicle-mounted timer is used for recording the local time of the vehicle-mounted processor and maintaining the time in the local system.
The real-time clock chip is a chip for synchronizing time to the electronic control unit.
The electronic control units connected with the vehicle-mounted processor are other ECUs of the vehicle except the domain controller, the ECUs are passive timing, and the time is synchronized to each electronic control unit through the vehicle-mounted processor.
As shown in fig. 2, the time synchronization method of the application processor includes steps S110 to S140:
Step S110, responding to a received starting signal of an operating system of an application processor, and acquiring an operation identifier of a timing application program of the application processor;
Step S120, if the operation identifier of the timing application program of the application processor indicates that the timing application program is not operated, determining the first time as the system time of the application processor;
If the operation identifier of the timing application program of the application processor indicates that the timing application program is operated, acquiring the current time every a first preset time length and determining the current time as the system time of the application processor;
Step S130, generating heartbeat messages every second preset time length according to the current system time of the application processor;
the second preset time period is smaller than the first preset time period.
Step S140, sending the heartbeat message to the vehicle-mounted processor.
After the operation system of the application processor runs and before the time correction application program of the application processor starts, which means that the application processor does not acquire the real and accurate time at this time, the first time is determined as the system time of the application processor, and the preset first time is the default invalid time, which may be 1970 as a possible embodiment.
If the operating system and the timing application program of the application processor are started, the time that the application processor can acquire the true and reliable time at the moment is indicated, and therefore the current acquired time is determined to be the system time of the application processor.
The first preset duration is a period duration of the current time acquired by the application processor, and the application processor can periodically acquire real-time through a network or a GPS (global positioning system), so that as a feasible embodiment, the value range of the first preset duration can be 5-30 minutes.
After the system time of the application processor is obtained, filling the current determined system time into the heartbeat message every a second preset time length, and sending the heartbeat message to the vehicle-mounted processor, wherein the value range of the second preset time length can be 1-20 seconds as a feasible embodiment.
As shown in fig. 3, the on-board processor executes steps S210-S220 after receiving the heartbeat message:
step S210, responding to the received heartbeat message sent by the application processor, and acquiring the system time of the application processor included in the heartbeat message;
Step S220, if the system time of the application processor is within a first preset period, determining the system time of the application processor as the current time of the real-time clock chip; otherwise, determining the first time as the system time of the vehicle-mounted processor;
The starting time of the first preset period is located after the first time, and the length of the first preset period is greater than the first preset duration, which is a feasible embodiment, where the starting time of the first preset period is a release time of a software version of the vehicle-mounted processor, and the length of the first preset period is an average usage time of a vehicle corresponding to the vehicle-mounted processor (generally, the usable life of the vehicle is between 20 and 30 years).
Since the system time of the application processor included in the heartbeat message may be the first time, and the first time is outside the first preset period, when the system time of the heartbeat message received by the vehicle-mounted processor is the first time, the application processor does not acquire the real and reliable time at the moment, so the first time is also determined as the system time of the vehicle-mounted processor, otherwise, if the system time of the heartbeat message received by the vehicle-mounted processor is within the first preset period, the acquired time of the application processor is reliable, so the acquired system time of the application processor is written into the real-time clock chip, and the current time is sent to each electronic control unit by the CAN bus.
After receiving the timing heartbeat message of the application processor, the vehicle-mounted processor checks the validity of time by taking the release year of the software version as a reference, so that the situation that the time of the vehicle-mounted processor is abnormal and the whole vehicle is abnormal due to the fact that the time before restarting or the random time is put into the vehicle-mounted processor before the effective time is not checked after the application processor is abnormally restarted is avoided.
Further, as shown in fig. 4, if the system time of the application processor is within the first preset period in step S220, the system time of the application processor is determined as the current time of the real-time clock chip, and steps S221-S223 are further included:
Step S221, if the system time of the application processor is within a first preset period, acquiring the current local time recorded by the vehicle-mounted timer;
step S222, if the difference value between the current local time recorded by the vehicle-mounted timer and the system time of the application processor is greater than a preset second time difference threshold value, determining the system time of the application processor as the current time of the real-time clock chip;
Step S223, the local time recorded by the vehicle-mounted timer is updated to the current time of the real-time clock chip.
As a possible embodiment, the second time difference threshold may be 2 seconds.
After the time stamp verification in the heartbeat message is effective, the vehicle-mounted processor reads the time stamp maintained locally, judges whether the current error is larger than a second time difference threshold value, writes time information into the real-time clock chip if the current error is larger than the second time difference threshold value, and updates the time maintained in the local system of the vehicle-mounted processor at the same time, and the local time of the vehicle-mounted processor and the time synchronization interval of the real-time clock chip restart calculation.
Because the accuracy of the local on-board timer of the on-board processor is low (generally about 1-2 seconds in half hour error according to component differences and environmental temperature), the local on-board timer is not suitable for long-time timing and generally needs to be synchronized with a real-time clock chip.
The operation of the vehicle-mounted timer on the real-time clock chip needs to call the IIC bus interface, the interface generally needs to be blocked and call, the time consumption is about 2-10ms, the overall performance of the vehicle-mounted timer system can be affected by frequent operation, and even the watchdog reset and other anomalies can be caused when the vehicle-mounted timer system is busy, so that other services are affected. Therefore, by setting the second time difference threshold, frequent operation of the real-time clock chip is avoided, and the stability of the whole system of the vehicle-mounted timer is improved.
Further, the vehicle-mounted processor updates the local time recorded by the vehicle-mounted timer to the current time of the real-time clock chip every third preset time length.
The third preset time period is longer than the second preset time period and shorter than the first preset time period, and as a feasible embodiment, the third preset time period may be 10 minutes.
The on-board processor reads time from the real-time clock chip every third preset time length to update the time stamp maintained by the local on-board timer, so that the time of the local on-board timer is synchronized with the time in the real-time clock chip.
As a further embodiment, the current time of the real-time clock chip and the local time recorded by the vehicle-mounted timer are obtained every third preset time length, and if the difference between the current time of the real-time clock chip and the local time recorded by the vehicle-mounted timer is smaller than the first time difference threshold, the local time recorded by the vehicle-mounted timer is updated to be the current time of the real-time clock chip; otherwise, the current time of the real-time clock chip is considered to be abnormal, and the time is discarded.
The first time difference threshold is a product of a timing error of the vehicle-mounted timer and a third preset time length, if the timing error of the vehicle-mounted timer is generally within 5%, the third preset time length is 10 minutes, and then the first time difference threshold is 30 seconds.
Due to reasons such as manufacturing process reasons or vibration in the running process of a vehicle, the running of the real-time clock chip is abnormal, the problems of inaccurate timing, even stop timing and the like are usually caused, so that the time read in the real-time clock chip is not always reliable, the vehicle-mounted processor reads the time from the real-time clock chip every third preset time length, if the time in the real-time clock chip stops timing, the time is the last written time, if the verification is not performed, the time is retracted to the time before the third preset time length, and although the time in heartbeat messages synchronized by the application processor can still repair the time, the abnormal time before repair is sent to the whole vehicle end, and the problems of time jump of a whole vehicle instrument, time dependence strategy confusion and the like are also caused. Therefore, the time abnormality of the vehicle-mounted processor and the time abnormality of the whole vehicle are avoided by limiting the maximum error between the time of the local maintenance of the vehicle-mounted processor and the time of the real-time clock chip when the real-time clock chip runs abnormally.
As shown in fig. 5, when the domain controller is awakened in the sleep state, the in-vehicle processor performs steps S310 to S320:
Step S310, obtaining the current time of a real-time clock chip;
Step S320, if the current time of the real-time clock chip is within a first preset period, updating the local time recorded by the vehicle-mounted timer to the current time of the real-time clock chip; otherwise, the first time is determined as the local time recorded by the vehicle-mounted timer.
Because the vehicle-mounted processor and the application processor in the domain controller are dormant, the local vehicle-mounted timer of the domain controller cannot work, the time maintained in the vehicle-mounted processor cannot be automatically counted, the real-time clock chip is not dormant, and the real-time clock chip of the vehicle-mounted processor is still automatically counted. Therefore, when the domain controller is awakened, the local time of the vehicle-mounted processor is the time before dormancy, which results in a time error of the timing message sent to the whole vehicle at this time, and therefore, the problem is solved through steps S310-S320: when the domain controller is awakened, the vehicle-mounted processor firstly reads and synchronizes the time from the real-time clock chip, only judges whether the time of the real-time clock chip meets the requirement in a first preset time period, if so, the time is considered to be effective, the maximum error between the local time of the vehicle-mounted processor and the time of the real-time clock chip is not limited any more, and if the time of the real-time clock chip is not read or the time of the chip is not checked, the local time of the vehicle-mounted processor is set to be the first time of the default invalid time.
When the vehicle-mounted processor is awakened, the time is synchronized from the real-time clock chip immediately, and after synchronization failure, the local time (the local time is the time before dormancy) is not used any more, and the time is set to a default invalid value, so that the wrong time is prevented from being sent to other ECUs of the whole vehicle, and time abnormal faults are avoided.
As shown in fig. 6, after the in-vehicle processor is reset, the in-vehicle processor performs steps S410 to S440:
step S410, obtaining a restart reset reason of the vehicle-mounted processor;
step S420, if the reset source of the vehicle-mounted processor is power-on reset, determining the first time as the current time of the real-time clock chip;
step S430, if the reset reason of the vehicle-mounted processor is not power-on reset, acquiring the current time of the real-time clock chip;
step S440, if the current time of the real-time clock chip is within the first preset period, determining the current time of the real-time clock chip as the system time of the vehicle-mounted processor; otherwise, the first time is determined as the system time of the vehicle-mounted processor.
When the vehicle-mounted processor is reset and started, judging a reset reason, if the vehicle-mounted processor is in power-on reset, initializing the real-time clock chip time to be the first time of default invalid time, otherwise, reading the real-time clock chip time, verifying whether the real-time clock chip time is in a first preset period, if the verification is successful, using the real-time clock chip time as system time, otherwise, setting the time to be the first time of default invalid time.
Because the vehicle-mounted processor can restart according to other strategies in the operation process, the time of internal maintenance after restarting each time is lost, on the same hardware, the real-time clock chip and the vehicle-mounted processor chip use the same power supply, the time of the real-time clock chip can be automatically timed as long as the power is not interrupted under the general condition, the reset reason inside the vehicle-mounted processor chip is read when the vehicle-mounted processor is started, if the reset reason is power-on reset, the real-time clock chip is also interrupted, the time inside the real-time clock chip is considered unreliable at the moment, the first time of default invalid time is directly used, and the time correction is carried out through a network or a GPS after the application processor is started. If the time is not valid (within the first preset period), the time of the real-time clock chip is used as the default system time, otherwise, the first time of the default invalid time is used.
The time verification method after restarting and resetting the vehicle-mounted processor recorded in step S410-step S440 identifies the resetting reason of the vehicle-mounted processor chip in the initialization stage of the vehicle-mounted processor to judge whether the time of the real-time clock chip is effective or not, uses the effective time and ensures that the correct time is sent to other ECUs of the whole vehicle in real time to the maximum extent.
In addition, the vehicle-mounted processor sends time correction message information to each electronic control unit every fourth preset time length.
The time correction message information comprises the current system time of the vehicle-mounted processor.
Each electronic control unit acquires the current system time of the vehicle-mounted processor included in the time correction message information after receiving the time correction message information, and if the current system time of the vehicle-mounted processor is within a first preset period, the current system time of the vehicle-mounted processor is determined to be the system time of the corresponding electronic control unit; otherwise, sending out a time exception signal or making a corresponding exception handling strategy.
After an operating system of an application processor in the domain controller time synchronization system is started, determining whether a timing application program of the application processor is operated or not by acquiring an operation identifier of the timing application program of the application processor, if the timing application program is not operated, determining a preset first time as a system time of the application processor, wherein the first time is a preset default invalid time; if the time correction application program is operated, acquiring current time at intervals of a first preset time length, determining the current time as the system time of the application processor, generating a heartbeat message according to the current system time of the application processor at intervals of a second preset time length, and sending the heartbeat message to the vehicle-mounted processor, wherein the vehicle-mounted processor acquires the system time of the application processor included in the heartbeat message after receiving the heartbeat message, and if the system time of the application processor is within the first preset time length, determining the system time of the application processor as the current time of the real-time clock chip; otherwise, the first time is determined as the system time of the vehicle-mounted processor. The method and the device are used for preventing the situation that the time of the vehicle-mounted processor is abnormal and the time of the whole vehicle is abnormal due to the fact that the time of the vehicle-mounted processor is abnormal because the time of the vehicle-mounted processor is synchronized to the time of the vehicle-mounted processor before the effective time is not corrected after the application processor is abnormally restarted or the time of the application processor is not corrected after the application processor is abnormally restarted, avoiding the abnormal operation of the domain controller and the unexpected abnormal time to the whole vehicle and avoiding the abnormal operation of the whole vehicle due to the fact that the time of the whole vehicle is unsynchronized.
Embodiments of the present invention also provide a computer program product comprising program code for causing an electronic device to carry out the steps of the method according to the various exemplary embodiments of the invention as described in the specification, when said program product is run on the electronic device.
Furthermore, although the steps of the methods in the present disclosure are depicted in a particular order in the drawings, this does not require or imply that the steps must be performed in that particular order, or that all illustrated steps be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step to perform, and/or one step decomposed into multiple steps to perform, etc.
From the above description of embodiments, those skilled in the art will readily appreciate that the example embodiments described herein may be implemented in software, or may be implemented in software in combination with the necessary hardware. Thus, the technical solution according to the embodiments of the present disclosure may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (may be a CD-ROM, a U-disk, a mobile hard disk, etc.) or on a network, including several instructions to cause a computing device (may be a personal computer, a server, a mobile terminal, or a network device, etc.) to perform the method according to the embodiments of the present disclosure.
In an exemplary embodiment of the present disclosure, an electronic device capable of implementing the above method is also provided.
Those skilled in the art will appreciate that the various aspects of the invention may be implemented as a system, method, or program product. Accordingly, aspects of the invention may be embodied in the following forms, namely: an entirely hardware embodiment, an entirely software embodiment (including firmware, micro-code, etc.) or an embodiment combining hardware and software aspects may be referred to herein as a "circuit," module "or" system.
An electronic device according to this embodiment of the invention. The electronic device is merely an example, and should not impose any limitations on the functionality and scope of use of embodiments of the present invention.
The electronic device is in the form of a general purpose computing device. Components of an electronic device may include, but are not limited to: the at least one processor, the at least one memory, and a bus connecting the various system components, including the memory and the processor.
Wherein the memory stores program code that is executable by the processor to cause the processor to perform steps according to various exemplary embodiments of the invention described in the "exemplary methods" section of this specification.
The storage may include readable media in the form of volatile storage, such as Random Access Memory (RAM) and/or cache memory, and may further include Read Only Memory (ROM).
The storage may also include a program/utility having a set (at least one) of program modules including, but not limited to: an operating system, one or more application programs, other program modules, and program data, each or some combination of which may include an implementation of a network environment.
The bus may be one or more of several types of bus structures including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processor, or a local bus using any of a variety of bus architectures.
The electronic device may also communicate with one or more external devices (e.g., keyboard, pointing device, bluetooth device, etc.), with one or more devices that enable a user to interact with the electronic device, and/or with any device (e.g., router, modem, etc.) that enables the electronic device to communicate with one or more other computing devices. Such communication may be through an input/output (I/O) interface. And, the electronic device may also communicate with one or more networks such as a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network, such as the Internet, through a network adapter. The network adapter communicates with other modules of the electronic device via a bus. It should be appreciated that other hardware and/or software modules may be used in connection with an electronic device, including but not limited to: microcode, device drivers, redundant processors, external disk drive arrays, RAID systems, tape drives, data backup storage systems, and the like.
From the above description of embodiments, those skilled in the art will readily appreciate that the example embodiments described herein may be implemented in software, or may be implemented in software in combination with the necessary hardware. Thus, the technical solution according to the embodiments of the present disclosure may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (may be a CD-ROM, a U-disk, a mobile hard disk, etc.) or on a network, including several instructions to cause a computing device (may be a personal computer, a server, a terminal device, or a network device, etc.) to perform the method according to the embodiments of the present disclosure.
In an exemplary embodiment of the present disclosure, a computer-readable storage medium having stored thereon a program product capable of implementing the method described above in the present specification is also provided. In some possible embodiments, the various aspects of the invention may also be implemented in the form of a program product comprising program code for causing a terminal device to carry out the steps according to the various exemplary embodiments of the invention as described in the "exemplary methods" section of this specification, when said program product is run on the terminal device.
The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium can be, for example, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium would include the following: an electrical connection having one or more wires, a portable disk, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
The computer readable signal medium may include a data signal propagated in baseband or as part of a carrier wave with readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A readable signal medium may also be any readable medium that is not a readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Program code for carrying out operations of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device, partly on a remote computing device, or entirely on the remote computing device or server. In the case of remote computing devices, the remote computing device may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computing device (e.g., connected via the Internet using an Internet service provider).
Furthermore, the above-described drawings are only schematic illustrations of processes included in the method according to the exemplary embodiment of the present invention, and are not intended to be limiting. It will be readily appreciated that the processes shown in the above figures do not indicate or limit the temporal order of these processes. In addition, it is also readily understood that these processes may be performed synchronously or asynchronously, for example, among a plurality of modules.
It should be noted that although in the above detailed description several modules or units of a device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit in accordance with embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into a plurality of modules or units to be embodied.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the present invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.
Claims (10)
1. The domain controller time synchronization system is characterized by comprising a domain controller and a plurality of electronic control units, wherein the domain controller comprises an application processor and a vehicle-mounted processor which are communicated with each other, the vehicle-mounted processor comprises a real-time clock chip, and the vehicle-mounted processor is connected with each electronic control unit through a CAN bus;
the application processor is used for executing the following steps:
acquiring an operation identifier of a timing application program of the application processor in response to receiving a starting signal of an operating system of the application processor;
If the operation identifier of the timing application program of the application processor indicates that the timing application program is not operated, determining the first time as the system time of the application processor; if the operation identifier of the timing application program of the application processor indicates that the timing application program is operated, acquiring the current time every a first preset duration and determining the current time as the system time of the application processor;
generating heartbeat messages every second preset time length according to the current system time of the application processor; the second preset time period is smaller than the first preset time period;
sending the heartbeat message to the vehicle-mounted processor;
the vehicle-mounted processor is used for executing the following steps:
Acquiring the system time of the application processor included in the heartbeat message in response to receiving the heartbeat message sent by the application processor;
if the system time of the application processor is within a first preset period, determining the system time of the application processor as the current time of the real-time clock chip; otherwise, determining the first time as the system time of the vehicle-mounted processor; the starting time of the first preset time period is located after the first time, and the length of the first preset time period is greater than the first preset time period.
2. The domain controller time synchronization system of claim 1, wherein the in-vehicle processor further comprises an in-vehicle timer for recording a local time of the in-vehicle processor;
the on-board processor is further configured to perform the steps of:
Updating the local time recorded by the vehicle-mounted timer to the current time of the real-time clock chip every a third preset time length; the third preset time period is longer than the second preset time period and shorter than the first preset time period.
3. The domain controller time synchronization system of claim 2, wherein the updating the local time recorded by the vehicle-mounted timer to the current time of the real-time clock chip every third preset duration further comprises:
Acquiring the current time of the real-time clock chip and the local time recorded by the vehicle-mounted timer every third preset time length;
If the difference value between the current time of the real-time clock chip and the local time recorded by the vehicle-mounted timer is smaller than a first time difference threshold value, updating the local time recorded by the vehicle-mounted timer to the current time of the real-time clock chip; the first time difference threshold is the product of the timing error of the vehicle-mounted timer and the third preset duration.
4. The domain controller time synchronization system of claim 3, wherein if the system time of the application processor is within a first preset period, determining the system time of the application processor as the current time of the real-time clock chip further comprises:
If the system time of the application processor is within a first preset period, acquiring the current local time recorded by the vehicle-mounted timer;
if the difference value between the current local time recorded by the vehicle-mounted timer and the system time of the application processor is larger than a preset second time difference threshold value, determining the system time of the application processor as the current time of the real-time clock chip;
And updating the local time recorded by the vehicle-mounted timer to the current time of the real-time clock chip.
5. The domain controller time synchronization system of claim 4, wherein when the domain controller wakes up in a sleep state, the onboard processor is configured to perform the steps of:
Acquiring the current time of the real-time clock chip;
if the current time of the real-time clock chip is within the first preset period, updating the local time recorded by the vehicle-mounted timer to the current time of the real-time clock chip; otherwise, the first time is determined to be the local time recorded by the vehicle-mounted timer.
6. The domain controller time synchronization system of claim 5, wherein the onboard processor is configured to perform the following steps when the onboard processor is reset by a restart:
acquiring a restarting reset reason of the vehicle-mounted processor;
And if the reset source of the vehicle-mounted processor is power-on reset, determining the first time as the current time of the real-time clock chip.
7. The domain controller time synchronization system of claim 6, wherein the determining the first time as the current time of the real time clock chip if the reset cause of the on-board processor is a power-on reset, further comprises:
If the reset reason of the vehicle-mounted processor is not power-on reset, acquiring the current time of the real-time clock chip;
If the current time of the real-time clock chip is within the first preset period, determining the current time of the real-time clock chip as the system time of the vehicle-mounted processor; otherwise, determining the first time as the system time of the vehicle-mounted processor.
8. The domain controller time synchronization system of claim 7, wherein the onboard processor sends timing message information to each of the electronic control units every fourth preset duration; the time correction message information comprises the current system time of the vehicle-mounted processor.
9. The domain controller time synchronization system of claim 8, wherein each of the electronic control units, upon receiving the timing message information, is configured to perform the steps of:
Acquiring the current system time of the vehicle-mounted processor included in the timing message information;
if the current system time of the vehicle-mounted processor is within the first preset period, determining the current system time of the vehicle-mounted processor as the corresponding system time of the electronic control unit; otherwise, a time anomaly signal is sent out.
10. The domain controller time synchronization system of claim 9, wherein the start time of the first preset period is a release time of a software version of the on-board processor, and the length of the first preset period is an average usage duration of a vehicle corresponding to the on-board processor.
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| CN113110160B (en) * | 2021-04-09 | 2023-03-21 | 黑芝麻智能科技(上海)有限公司 | Time synchronization method and device of domain controller, domain controller and storage medium |
| CN113422665B (en) * | 2021-08-23 | 2021-11-12 | 奥特酷智能科技(南京)有限公司 | Method and system for realizing time synchronization of vehicle-mounted system based on IPC mechanism |
| CN113992295B (en) * | 2021-10-29 | 2024-04-02 | 世邦通信股份有限公司 | Multi-NTP server timing realization method and system, computer equipment and storage medium |
| CN116931536A (en) * | 2022-04-01 | 2023-10-24 | 北京三快在线科技有限公司 | System abnormal restarting detection method, device, system, aircraft and storage medium |
| CN117639991A (en) * | 2023-11-14 | 2024-03-01 | 小米汽车科技有限公司 | Time synchronization method and device for vehicle |
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Non-Patent Citations (2)
| Title |
|---|
| IoT and smart infrastructure;George Lu;《Internet of things and data analytics handbook》;20161223;全文 * |
| 基于IEEE 1588协议的网络时钟同步系统;许国强;陈皓瑜;张永刚;周小林;;上海师范大学学报(自然科学版);20170215(01);全文 * |
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