CN117997686A - Analog assisted feedforward equalizer - Google Patents

Abstract

An analog auxiliary feedforward equalizer. The technology described herein relates to analog assisted feedforward equalizers. An example apparatus includes a first charge element digital-to-analog converter (DAC) including a first plurality of charge storage elements configured to store first charge samples based on respective first portions of a digital input signal and generate a first analog output signal proportional to the first portions based on the first samples. The apparatus further includes a second charge element DAC coupled to the first charge element DAC and including a second plurality of charge storage elements configured to store second charge samples based on respective second portions of the digital input signal and generate a second analog output signal proportional to the second portions based on the second samples, and wherein the coupling of the first output to the second output generates a third analog output signal based on a combination of the first analog output signal and the second analog output signal.

Description

Analog assisted feedforward equalizer

RELATED APPLICATIONS

This patent claims priority from U.S. provisional application No.63/381,944, entitled "Analog ASSISTED FEED-forward Equalizer," filed on month 2 of 2022, and U.S. patent application No.18/477,471, filed on month 9 of 2023, the entire contents of which are incorporated herein by reference.

Technical Field

The technology described herein relates generally to communication channel equalization, and more particularly to analog-assisted feedforward equalizers.

Background

Channel equalization is the process of adjusting an electrical signal at a transmitter or receiver to compensate for inter-symbol interference caused by the channel at the receiver and improve signal integrity. An exemplary channel equalization technique is feed forward equalization, which may be used to reduce distortion of a communication channel implemented by a transmitter and a receiver due to channel loss impairment.

Disclosure of Invention

In accordance with the disclosed subject matter, an exemplary analog assisted feedforward equalizer is provided.

Some embodiments relate to an apparatus for feed forward equalization. The apparatus includes a first charge element digital-to-analog converter (DAC), the first charge element DAC having a first output, the first charge element DAC including a first plurality of charge storage elements, the first charge element DAC configured to: storing a first charge sample based on a respective first portion of the digital input signal; and generating a first analog output signal proportional to a first portion of the digital input signal based on the first charge sample; and a second charge-element DAC having a second output coupled to the first output, the second charge-element DAC comprising a second plurality of charge storage elements, the second charge-element DAC configured to: storing a second charge sample based on a respective second portion of the digital input signal; and generating a second analog output signal proportional to a second portion of the digital input signal based on the second charge sample; and wherein the first output and the second output are coupled at a node to combine the first analog output signal and the second analog output signal to generate a third analog output signal.

Some embodiments relate to another apparatus. The apparatus includes a plurality of capacitor digital-to-analog converters (CDACs) having respective CDAC outputs, the plurality of CDACs configured to generate a first analog output signal proportional to a first portion of a digital input signal; a comparator circuit having a comparator input coupled to one or more of the respective CDAC outputs and a comparator output configured to determine whether a respective one of the first analog output signals meets a voltage threshold; successive Approximation (SAR) logic having a SAR logic input coupled to the comparator output and a SAR logic output configured to pass the comparator output and control sampling of the plurality of CDACs; digital logic having a digital logic output, the digital logic configured to generate a second analog output signal representing a product of a second portion of the digital input signal and the coefficient; and an adder circuit having a first adder input coupled to the SAR logic output and a second adder input coupled to the digital logic output, and configured to output samples of the digital input signal based on a combination of the first analog output signal and the second analog output signal.

Some embodiments relate to yet another apparatus. The device comprises: a receiver front-end circuit configured to convert a first analog signal to a digital signal, the first analog signal being associated with a first clock; a retimer circuit coupled to the receiver front-end circuit, the retimer circuit configured to output a copy of the digital signal based on a second clock different from the first clock; a plurality of capacitor digital-to-analog converters (CDACs) coupled to the retimer circuit, the plurality of CDACs configured to generate a second analog signal proportional to a portion of the digital signal; an analog adder circuit configured to generate a third analog signal based on a combination of analog signals in the second analog signal; and an analog-to-digital converter configured to output samples of the digital signal based on the third analog signal.

The above summary is not intended to be limiting. Furthermore, various aspects of the disclosure may be implemented alone or in combination with other aspects.

Drawings

In the drawings, each identical or nearly identical component that is illustrated in various figures is represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating various aspects of the technology and devices described herein.

FIG. 1 depicts an example data receiver system including an example analog auxiliary feedforward equalizer including a digital-to-analog converter.

Fig. 2 depicts an example implementation of the analog assisted feedforward equalizer of fig. 1.

Fig. 3 depicts an example implementation of the digital-to-analog converter of fig. 1.

Fig. 4 is a timing diagram illustrating an example operation of the digital-to-analog converter of fig. 3.

Fig. 5 depicts another example implementation of the digital-to-analog converter of fig. 1.

Fig. 6 is a table of example coefficients.

Fig. 7 depicts another example implementation of the digital-to-analog converter of fig. 1.

Fig. 8 depicts another example implementation of the analog assisted feedforward equalizer of fig. 1.

Fig. 9 depicts yet another example implementation of the analog assisted feedforward equalizer of fig. 1.

Fig. 10 depicts another example implementation of the analog assisted feedforward equalizer of fig. 1.

Detailed Description

Data communication refers to the transmission and reception of data in the form of digitized analog signals (such as digital bit streams) sent over a point-to-point or point-to-multipoint communication channel. In some cases, the networked electronic device may transmit data across the network via one or more other networked electronic devices. In other cases, the data may be sent within the same device, e.g., between integrated circuits (INTEGRATED CIRCUIT, ICs) on the same printed circuit board (printed circuit board, PCB).

Data may be transmitted (e.g., across a network, within the same device, etc.) using a communication link implemented by a transmitter generating a signal, a channel carrying the signal, and a receiver receiving and correctly decoding a content and/or data representation of the signal. Non-limiting examples of channels carrying signals include channels implemented over the air, via copper media, and via fiber optic media. In order to properly decode the signal, it is necessary to maintain the integrity of the signal between the transmitter and the receiver. For example, if a logic high signal (such as a "1" or digital "1") is sent from the transmitter and through the channel, the receiver should also determine that the signal is a "1". As data communication applications require increased signaling speeds, signal processing hardware and corresponding techniques are required to maintain signal integrity.

The signal integrity of a signal communicated through a communication channel may be affected by a number of factors. Some factors include atmospheric and/or environmental noise, artifacts, and the like. Other factors are deterministic in nature, such as signal transmission being affected by the limited bandwidth of the particular physical medium being used and crosstalk from adjacent channels. For example, signal integrity associated with communication channels implemented using copper-based signaling may be adversely affected by the limited bandwidth of the copper channel and crosstalk from neighboring copper channels. In some cases, signal integrity associated with an optical communication channel may be affected by frequency independent loss of optical power as the optical signal travels through the optical fiber and by induced dispersion based on the type of optical fiber used. Such signal integrity issues may result in inter-symbol interference (ISI) at the receiver. ISI is a distorted form of a signal in which one symbol interferes with a subsequent symbol and may increase as the data rate and length of the communication channel increases. The symbols may represent one or more digital bits determined by a digital modulation format. For example, a symbol may be a waveform, state, or condition of importance of a communication channel that lasts for a fixed period of time.

Some receiver devices may use equalization techniques, such as channel equalization techniques, to maintain signal integrity of signals transmitted over a communication channel by canceling and/or otherwise reducing ISI. Some such receiver devices may be implemented using an analog-to-digital converter (ADC) based receiver architecture, which allows equalization techniques to be implemented. Equalization refers to the process of adjusting an electrical signal at a transmitter or receiver to compensate for channel-induced ISI. In particular, some ADC-based receiver architectures may use digital feed-forward equalization (FFE) techniques to reduce ISI.

FFE may be implemented by a filter (e.g., linear filter, digital finite impulse response (finite impulse response, FIR) filter, etc.) that creates multiple delayed versions of the input signal and adds the delayed versions back to the input signal with appropriate coefficients (e.g., weights). For example, a digital feedforward equalizer may include a multiplier implemented with digital logic to create a delayed version by multiplying an input signal with corresponding coefficients. The digital feedforward equalizer may include an adder implemented with digital logic to add the delayed version back to the input signal to output samples of the input signal. Some FFE implementations include multiple tap filters and multiple tap coefficients, where the taps are either pre-cursors or post-cursors. The coefficients of these taps may be positive or negative, depending on whether they are pre-cursor or post-cursor.

One challenge in reducing ISI using digital FFE is latency. The digital FFE may use a large number of taps (e.g., 32 taps) (also referred to as delay elements) to achieve low ISI noise, but the large number of taps results in a significantly higher delay. For example, each tap may be implemented using digital logic that performs multiplication and/or addition operations using sequential operations (e.g., all inputs need to be available for evaluation), which results in higher latency. Some digital FFE implementations may include a clock data recovery (clock data recovery, CDR) circuit to recover an embedded clock in the received signal. However, CDR circuits are delay sensitive, which limits the maximum bandwidth of the receiver. The CDR circuit may reduce the maximum bandwidth achievable by the receiver due to the significantly higher latency caused by the sequential digital logic of the large number of taps.

Some digital FFE implementations may use a pre-filter in the feedback path of the receiver to reduce the delay caused by the large number of FFE taps. One challenge with using a pre-filter is that the pre-filter introduces more ISI noise in the CDR circuit, which results in signal-to-noise ratio (SNR) degradation associated with the receiver.

Another challenge with using digital FFE in a receiver is that digital equalization (such as implementing multiplication and addition operations using digital logic) consumes a significant portion of the receiver's power. Yet another challenge with using digital FFE is that digital logic consumes a significant portion of area on the IC and/or PCB implementing the digital FFE.

The inventors have recognized that conventional receivers suffer from reduced bandwidth and increased latency, power consumption, and area consumption. The inventors have recognized that conventional equalization techniques, such as the digital FFE techniques described above, do not overcome the above-described challenges. The inventors have developed techniques to overcome the above challenges using an exemplary analog assisted feedforward equalizer as disclosed herein.

The exemplary analog-assisted feedforward equalizer disclosed herein is analog-assisted in that they can utilize digital data, but perform arithmetic operations (e.g., multiplication, addition) in the analog domain. For example, the analog-assisted feedforward equalizer disclosed herein may include a digital-to-analog converter (DAC) to convert digital words to analog signals. The analog assisted feedforward equalizer may perform multiplication operations by scaling the reference voltage of the DAC to achieve instantaneous multiplication with a relatively small delay. Advantageously, the power consumed by the multiplication operation is scaled down at a lower coefficient. The analog-assisted feedforward equalizer may perform addition (e.g., an addition operation) by adding the signal generated by the multiplication operation in the analog domain. For example, an analog-assisted feedforward equalizer may perform charge and/or current signal addition, and advantageously, the addition may be performed simultaneously without delay.

In some embodiments, the disclosed analog-assisted feedforward equalizer may be implemented using a hybrid approach. For example, one or more cursors (which may include a primary cursor) of the input signal may be processed with digital logic, and other cursors of the input signal may be processed in the analog domain. Advantageously, a cursor with a maximum amplitude term (amplitude term) may be removed from the ADC conversion to achieve a reduction in area while limiting adverse latency effects. For example, maintaining several maximum amplitude terms in the digital domain does not have excessive adverse effects on time delay, as most other cursors can be handled using low latency techniques that perform multiplication and addition operations in the analog domain.

Turning to the drawings, the illustrated example of fig. 1 depicts an example data receiver system 100 including an example analog auxiliary feedforward equalizer 102. In some implementations, the analog auxiliary feedforward equalizer 102 is configured to perform channel equalization with reduced latency and ISI noise while maintaining a relatively low level of area and power consumption. For example, the analog-aided feedforward equalizer 102 is analog-aided in that it can receive digital data and perform arithmetic operations (e.g., multiplication, addition) in the analog domain to output samples of the digital data with reduced delay and ISI noise.

The data receiver system 100 of the illustrated example is a wired receiver (e.g., a data communication wired receiver) that can receive communication data, such as data represented by the input signal 104, over one or more wired connections. For example, the input signal 104 may be an analog signal representing data transmitted over a communication channel. Non-limiting examples of wired receivers include ethernet interfaces, peripheral component interconnect (PERIPHERAL COMPONENT INTERCONNECT, PCI) interfaces, serial digital interfaces (SERIAL DIGITAL INTERFACE, SDI), universal serial bus (Universal Serial Bus, USB) interfaces, and High-definition multimedia interfaces (High-Definition Multimedia Interface, HDMI). Alternatively, the data receiver system 100 may be a wireless receiver. Non-limiting examples of wireless receivers include wireless fidelity (WIRELESS FIDELITY, wi-Fi) receivers, bluetooth receivers, near-field communication (NFC) receivers, radio-frequency identification (radio-frequency identification, RFID) receivers, and satellite receivers (e.g., beyond-line-of-site (BLOS) satellite receivers, line-of-site (LOS) satellite receivers, etc.).

In some implementations, the data receiver system 100 is included in an electronic device. Non-limiting examples of electronic devices include gateways, routers, switches, laptops, tablet computers, cellular phones (e.g., smartphones), televisions (e.g., smarttelevisions), set-top boxes, streaming devices, and wearable devices (e.g., headphones, headsets, smartwatches, smart glasses, etc.).

The data receiver system 100 includes a receiver front-end 106 (identified by RXFE) that may be implemented by one or more receiver front-end circuits (e.g., receiver front-end circuits). The receiver front end 106 of this example includes a continuous-time linear equalizer (CTLE) circuit 108 (also referred to as a continuous-time linear equalizer), a Variable Gain Amplifier (VGA) 110 (also referred to as a voltage-controlled amplifier), and a plurality of first analog-to-digital converters (ADCs) 112.

In some implementations, CTLE circuit 108 is a linear filter that can correct for losses and distortions caused by high frequency transmission lines. For example, CTLE circuit 108 may be configured to receive input signal 104, attenuate low frequency signal components of input signal 104, amplify components of input signal 104 near the nyquist frequency, and filter out higher frequencies of input signal 104.

In some implementations, VGA 110 is an electronic amplifier whose gain can be changed in response to a control voltage. For example, VGA 110 can be configured as a signal conditioning amplifier having an electronically settable voltage gain. An input of VGA 110 is coupled to an output of CTLE circuit 108. For example, CTLE circuit 108 and VGA 110 can be coupled together using one or more electrical connections. Non-limiting examples of electrical connections include opto-isolators, pads, traces, wires, and vias.

In some embodiments, the first ADC 112 is configured to convert the input signal 104, or a portion thereof, into a digital signal 124 (identified by d0[ m:0], d1[ m:0],..dn [ m:0 ]). For example, the first ADC 112 may be configured to receive a continuous electrical signal and output a discontinuous electrical signal, such as one or more electrical pulses, to represent samples of the continuous electrical signal. The respective inputs of the first ADC 112 are coupled to the output of the VGA 110.

The data receiver system 100 includes a retimer circuit 114 to recover (e.g., fully recover) the data represented by the input signal 104, extract the embedded clock in the input signal 104, and send a copy of the data to the analog auxiliary feedforward equalizer 102 using the new clock. In some implementations, the new clock is different from the embedded clock such that the retimer circuit 114 can use the clock without distortion and/or interference to send a new copy of the data. An input of the retimer circuit 114 is coupled to a corresponding output of the first ADC 112.

The analog-assisted feedforward equalizer 102 of the illustrated example includes a plurality of digital-to-analog converters (DACs) 116, an analog summing circuit 118, and a second ADC 120. A respective input of DAC 116 is coupled to an output of retimer circuit 114. The output of DAC 116 is coupled to analog summing circuit 118. The output of the analog add circuit 118 is coupled to the input of the second ADC 120. The output of the second ADC 120 is configured to be coupled to additional circuitry. For example, the second ADC 120 may output samples 122 of the input signal 104 to one or more programmable processors. Non-limiting examples of programmable processors include central processing units (central processing unit, CPU), digital signal processors (DIGITAL SIGNAL processor, DSP) and field programmable gate arrays (field programmable GATE ARRAY, FPGA).

In some implementations, DAC 116 is a charge element DAC. For example, DAC 116 may be implemented using a plurality of charge storage elements to store a first charge sample based on a first portion of the digital signal output from ADC 112. Non-limiting examples of charge storage elements include capacitors, resistors, transformers, and transistors. In some implementations, DAC 116 may be configured to generate an analog output signal proportional to the first portion of the digital signal and based on the charge samples.

For example, a first ADC of the first ADCs 112 may convert the input signal 104 into a digital signal 124, e.g., a signal representing one or more bits. In some implementations, a digital bit (such as one or more bits represented by digital signal 124) may have a value of 0 or a voltage reference (voltage reference, VREF) to represent a binary value of 0 or 1, respectively. The digital signals of the illustrated examples may be D0[ m:0], D1[ m:0],. And/or Dn [ m:0], etc., where n and m may be integers. For example, D0[2:0] may represent a first digital word having 3 bits (e.g., bit 0, bit 1, bit 2). For example, a first ADC of the first ADCs 112 may convert the input signal 104 into a 3-bit digital signal (although any other number of bits is contemplated). The retimer circuit 114 may retransmit the new copy of the 3-bit digital signal using a different clock than the clock embedded in the input signal 104. A first one of DACs 116 may perform multiplication operations on a 3-bit digital signal in the analog domain. For example, a first one of the DACs 116 may perform a coarse step multiplication operation (coarse step multiplication operation) by shifting the position of bits of a 3-bit digital signal using analog circuitry as disclosed herein. In some implementations, a first one of the DACs 116 may perform the fine step multiplication operation (fine step multiplication operation) by changing a reference Voltage (VREF) 126 of the first one of the DACs 116 using analog circuitry as disclosed herein.

For example, a first one of the DACs 116 may perform coarse and/or fine step multiplications on the 3-bit digital signal to generate a first analog signal (e.g., an analog output signal) and output the first analog signal to the analog summing circuit 118. In some implementations, the analog addition circuit 118 may output the second analog signal based on a combination (e.g., sum, total, subtraction) of the first analog signal and other analog signals output from other ones of the DACs 116. For example, analog summing circuit 118 may sum the outputs of DAC 116 using analog circuitry. The analog adding circuit 118 may output the second analog signal to the second ADC 120. The second ADC 120 may convert the second analog signal to a digital signal such that the digital signal may implement the samples 122 of the input signal 104.

Advantageously, the analog auxiliary feedforward equalizer 102 may be configured to cancel and/or otherwise reduce ISI associated with the input signal 104. In some implementations, the analog auxiliary feedforward equalizer 102 may be configured to provide programmability to interface with different communication channels implemented by the receiver front end 106.

Advantageously, the analog-assisted feedforward equalizer 102 may move multiplication and addition operations previously performed using digital logic in a conventional digital feedforward equalizer to the analog domain to achieve reduced latency, area consumption, and power consumption associated with the digital feedforward equalizer. For example, DAC 116 may perform multiplication operations in substantially parallel using analog circuitry, while a digital feedforward equalizer performs multiplication operations using sequential operations. By performing the multiplication operations substantially in parallel, the analog auxiliary feedforward equalizer 102 may generate samples with reduced latency as compared to a digital feedforward equalizer. Further, implementing at least a portion of the analog auxiliary feedforward equalizer 102 in the analog domain may reduce power and area consumed by the analog auxiliary feedforward equalizer 102 (e.g., area of an integrated circuit (INTEGRATED CIRCUIT, IC) or chip, printed circuit board (printed circuit board, PCB), etc.).

Fig. 2 depicts an example analog auxiliary feedforward equalizer 200. In some implementations, the analog auxiliary feedforward equalizer 200 may correspond to the analog auxiliary feedforward equalizer 102 of fig. 1 and/or implement the analog auxiliary feedforward equalizer 102 of fig. 1. The analog-assisted feedforward equalizer 200 of the illustrated example may be configured to receive a digital signal 202. In this example, the digital signal 202 is represented by digital words (e.g., D0[6:0], D1[6:0],. The.once. For example, the digital word D0[6:0] may represent a digital signal using 7 bits. Alternatively, one or more of the digital signals 202 of this example may be represented by a different number of bits.

The analog assisted feedforward equalizer 200 of this example includes an analog circuit 204. The analog circuit 204 includes a plurality of analog multipliers 206 (such as analog multiplier circuits) and a plurality of analog adders 208 (such as analog adder circuits). For example, analog multiplier 206 may respectively implement a multiplication of one of digital signals 202 with one of a plurality of coefficients 210 (identified by h0, h1, h2, etc.). For example, the coefficients 210 may be implemented by the configuration of the analog multiplier 206 to output an analog signal.

In the example shown, the output of the analog multiplier 206 is coupled to an input of an analog adder 208. In some implementations, the analog adder 208 is implemented by a plurality of adder circuits. In some implementations, the analog adder 208 is implemented by a single adder circuit and/or more generally an adder circuit. The analog adder 208 of the illustrated example generates samples 212 (identified by y [0 ]) based on a combination (e.g., sum, total, subtraction) of the outputs of the analog multipliers 206.

The samples 212 of the illustrated example are output to a feedforward equalizer (or feedforward equalization) analog-to-digital converter (FFE ADC) 214.FFE ADC 214 may convert an analog signal (such as samples 212) into digital output 216 (identified by FFE digital output). Digital output 216 may be provided to other circuitry, such as one or more programmable processors, to accomplish electrical and/or computational tasks.

Advantageously, an analog assisted feedforward equalizer as disclosed herein (such as analog assisted feedforward equalizer 200 of fig. 2) may achieve reduced ADC conversion latency relative to conventional equalizers. For example, a conventional main path FFE for a 112 gigabit per second (gbps) system may be implemented with 32 taps implemented using digital logic. In some conventional implementations, 8 of the 32 taps may have 7-bit inputs and 24 of the 32 taps may have 4-bit inputs. To complete the ADC conversion with 32 digitally implemented taps, the total delay may be three time periods (3T) (e.g., three clock cycles) or about 3.43 nanoseconds (ns) (e.g., about 3.43 ns=3 x (128/112 gbps), where 128 is calculated by 2 ⁷ for a 7-bit input). Advantageously, to implement the conventional main path FFE with analog multiplier and adder disclosed herein, which may be operated to perform both multiplication and addition operations, the total delay may be one time period (1T) (e.g., one clock cycle) or about 1.14ns (e.g., about 1.14 ns=1 x (128/112 gbps), which is an approximately three-fold improvement over the delay).

Fig. 3 depicts an example multi-bit DAC 300. In some implementations, multi-bit DAC 300 may correspond to and/or implement one of the plurality of DACs 116 of fig. 1. In some implementations, multi-bit DAC 300 may correspond to and/or implement one or more of analog multipliers 206 and one or more of analog adders 208 of fig. 2. The multi-bit DAC 300 of the illustrated example is a 3-bit DAC. Alternatively, multi-bit DAC 300 may be implemented to represent input signal 302 using any number of bits (e.g., 2 bits, 4 bits, 7 bits, etc.). For example, the input signal 302 may correspond to and/or implement one of the digital signal 124 of fig. 1 and/or the digital signal 202 of fig. 2.

The multi-bit DAC 300 of the illustrated example is a charge element DAC (CHARGE ELEMENT DAC, CDAC) that includes a plurality of charge storage elements 304, 306, 308 to store a first charge sample based on a plurality of portions of the input signal 302. The charge element DAC may generate an analog output signal 309 (identified by VTOP), the analog output signal 309 being proportional to the multiple portions of the input signal 302 and based on samples of the charge. For example, the equivalent capacitance established after storing the first charge sample may correspond to the coefficients of a filter implemented by multi-bit DAC 300.

The charge storage elements 304, 306, 308 of the illustrated example are capacitors coupled together in parallel. Alternatively, one or more of the charge storage elements 304, 306, 308 may be different types of discrete electronic components, such as resistors, transformers, or transistors. The charge storage elements 304, 306, 308 each have a different storage capacity. For example, a first charge storage element 304 of the charge storage elements 304, 306, 308 has a first capacitance (identified by 1C), a second charge storage element 306 of the charge storage elements 304, 306, 308 has a second capacitance (identified by 2C), and a third charge storage element 308 of the charge storage elements 304, 306, 308 has a third capacitance (identified by 3C). For example, the second capacitance of the second charge storage element 306 may be twice as large as the first capacitance of the first charge storage element 304.

The multi-bit DAC 300 of the illustrated example includes a plurality of switching circuits 310, 312, 314 coupled to respective ones of the charge elements 304, 306, 308. The switching circuits 310, 312, 314 include a first switch 316 and a second switch 318, respectively, coupled to a first plate (e.g., a bottom plate) of a respective one of the charge storage elements 304, 306, 308. The multi-bit DAC 300 also includes a third switch 320 coupled to a second plate (e.g., top plate) of the charge storage elements 304, 306, 308.

In some implementations, the first switch 316, the second switch 318, and/or the third switch 320 are implemented by one or more transistors. Non-limiting examples of transistors include field-effect transistors (FETs), bipolar junction transistors (bipolar junction transistor, BJTs) (e.g., NPN BJTs, PNP BJTs), and Insulated Gate Bipolar Transistors (IGBTs). Non-limiting examples of FETs include power FETs and metal-oxide-semiconductor field effect transistors (MOSFETs) (e.g., p-channel MOSFETs, n-channel MOSFETs, etc.). Any other type of transistor is envisaged.

In an example operation, a first clock signal 322 (identified by phi 1) that may be a control signal may be asserted to close the first switch 316 and the third switch 320 to reset the multi-bit DAC 300. For example, during phi1, both the top and bottom plates of the charge storage elements 304, 306, 308 are discharged and/or otherwise reduced to a reference voltage 324, which reference voltage 324 is 0V in this example (any other reference voltage may be used).

In an example operation, second clock signal 326 (identified by phi 2) may be asserted and first clock signal 322 may be de-asserted. For example, first clock signal 322 and second clock signal 326 may be complementary signals that alternate in amplitude and/or polarity. In response to deassertion of the first clock signal 322, the first switch 316 and the third switch 320 may be opened. In response to assertion of the second clock signal 326, the second switch 318 may be closed. In an example operation, the bottom plates of the charge storage elements 304, 306, 308 are coupled to a logic high signal (e.g., VDD, VREF) or a logic low signal (e.g., 0V) according to a digital word. Due to the charge distribution, the top plates of the charge storage elements 304, 306, 308 may generate the analog output signal 309 as a voltage that is a ratio of a logic high signal proportional to the digital word described in connection with fig. 4. For example, multi-bit DAC 300 of fig. 3 may perform multiplication operations by adjusting, changing, and/or otherwise scaling VREF, which may be used to represent a logic high signal for input signal 302. In an example operation, a first output associated with the first charge storage element 304 and a second output associated with the second charge storage element 306 are coupled at node 328, where the first output and the second output are combined (e.g., added, subtracted) to generate an analog output signal 309.

Fig. 4 is a timing diagram 400 illustrating an example operation of the multi-bit DAC 300 of fig. 3. The timing diagram 400 depicts exemplary waveforms 402, 404, 406 of the first clock signal 322, the input signal 302, and the analog output signal 309 of fig. 3, respectively. The x-axis of the timing diagram 400 is time and the y-axis of the timing diagram 400 is voltage (V). For example, timing diagram 400 may depict multi-bit DAC 300 performing a multiplication operation to generate an analog output signal 309 that is proportional to input signal 302. The first waveform 402 alternates between a logic low signal (0V in this example) and a logic high signal (VDD in this example). The second waveform 404 may represent the value of the input signal 302 as a digital word.

As an example, prior to a first time 408 (identified by T ₁), first clock signal 322 is asserted to VDD, which closes first switch 316 and third switch 320 of fig. 3 to reset the output of multi-bit DAC 300 (such as analog output signal 309) to 0. At a first time 408, the first clock signal 322 is deasserted (and thus the second clock signal 326 is asserted) such that the first switch 316 and the third switch 320 of fig. 3 are open and the second switch 318 is closed. At a first time 408, the digital word to be sampled represented by the input signal 302 is d=2 or 010 in binary form (identified as b' 010). In some embodiments, when d=2, then in fig. 3, D [0] =0, D [1] =1, and D [2] =0, and cause a logic low signal, a logic high signal, and a logic low signal to be applied to the bottom plates of charge storage elements 304, 306, 308, respectively. In this example, analog output signal 309 is 2/8 VREF and is thus a voltage proportional to VREF (due to the charge distribution and equivalent capacitance of charge storage elements 304, 306, 308). For example, analog output signal 309 may be generated as an effective product of VREF multiplied by a coefficient (e.g., 2/8 (or 0.25 or 1/4)). In this example, multi-bit DAC 300 of fig. 3 may perform a multiplication operation corresponding to the fine gain step by scaling VREF. For example, when VREF is scaled higher or lower, analog output signal 309 may be 2/8 x VREF or a different value to achieve a different fine gain multiplication step.

At a second time 410 (identified by T ₂), multi-bit DAC 300 is reset in response to the assertion of first clock signal 322 and the deassertion of second clock signal 326. For example, the analog output signal 309 is reduced and approaches 0V.

At a third time 412 (identified by T ₃), the digital word to be sampled represented by the input signal 302 is d=5 or 101 (identified as b' 101) in binary form. In some embodiments, when d=5, then in fig. 3, D [0] =1, D [1] =0, and D [2] =1, and cause a logic high signal, a logic low signal, and a logic high signal to be applied to the bottom plates of charge storage elements 304, 306, 308, respectively. In this example, analog output signal 309 is 5/8 VREF and is thus a voltage proportional to VREF (due to the charge distribution and equivalent capacitance of charge storage elements 304, 306, 308). For example, analog output signal 309 may be generated as an effective product of VREF multiplied by a coefficient (e.g., 5/8 (or 0.625)).

Fig. 5 depicts another example multi-bit DAC 500. In some implementations, multi-bit DAC 500 may correspond to and/or implement one of the plurality of DACs 116 of fig. 1. In some implementations, the multi-bit DAC 500 of fig. 5 may correspond to and/or implement one or more of the analog multipliers 206 and one or more of the analog adders 208 of fig. 2. The multi-bit DAC 500 of the illustrated example is a 3-bit DAC that can implement digital word shifting. Alternatively, multi-bit DAC 5000 may be implemented to represent input signal 302 of fig. 3 using any number of bits (e.g., 2 bits, 4 bits, 7 bits, etc.).

The multi-bit DAC 500 of the illustrated example includes the charge storage elements 304, 306, 308, the switching circuits 310, 312, 314, the first switch 316, the second switch 318, and the third switch 320 of fig. 3. Further depicted are analog output signal 309, reference voltage 324, and node 328 of fig. 3.

The multi-bit DAC 500 of this example may perform multiplication (or multiplier) operations using reference voltage scaling and/or digital word shifting. For example, multi-bit DAC 500 may perform a coarse gain step by shifting the digital word by one position, two positions, and so on. As an example, the unit coarse gain step may be implemented without bit shifting. As another example, a gain step of 0.5 times may be achieved by shifting the bits of the digital word represented by the input signal 302 by one position such that D [2] is provided to the second switching circuit 312 and D [1] is provided to the first switching circuit 310. As yet another example, a gain step of 0.25 times may be achieved by shifting the bits of the digital word represented by input signal 302 by two positions such that D [2] is provided to first switch circuit 310 and D [1] and D [0] are not connected. In some implementations, the multi-bit DAC 300 of fig. 3 may perform multiplication operations using digital word shifting as disclosed herein.

Additionally or alternatively, the multi-bit DAC 500 may perform a multiplication (or multiplier) operation using voltage scaling (e.g., reference voltage scaling). For example, multi-bit DAC 500 may perform a fine gain step by scaling VREF (e.g., reference voltage 126 of fig. 1). For example, multi-bit DAC 500 may scale the voltage of a logic high signal representing input signal 302.

Fig. 6 is a table 600 of example coefficients (identified by Ctot). For example, the coefficients may correspond to weights of filters (e.g., high pass filters, low pass filters, band pass filters, etc.) implemented by an analog-assisted feedforward equalizer as disclosed herein. In some such examples, the coefficients may be implemented using the total capacitance (and/or equivalent capacitance) of the charge element DAC, such as the total capacitance of the charge storage elements 304, 306, 308 of fig. 3.

In some implementations, the coefficients may be implemented by an analog-assisted feedforward equalizer as disclosed herein, such as analog-assisted feedforward equalizer 102 of fig. 1 and/or analog-assisted feedforward equalizer 200 of fig. 2. For example, the coefficients in table 600 may correspond to the coefficients of fig. 2 (e.g., h0, h1, etc., hm1, hm2, etc.).

In some implementations, the table 600 corresponds to a DAC transfer function. For example, the coefficients in table 600 may be implemented by analog multipliers as disclosed herein. For example, the coefficients may be implemented by the multiple DACs 116 of FIG. 1, the multiplier 206 of FIG. 2, the multi-bit DAC 300 of FIG. 3, and/or the multi-bit DAC 500 of FIG. 5.

The DAC transfer function represented by table 600 of fig. 6 is an example of an 11-bit coefficient multiplier for a 7-bit data representation. For example, a row of table 600 may represent 7 steps of a shift multiplication, which may implement a Coarse gain step (identified by Ctrim Coarse). For n shifts, the gain is 2 ^-n (from 1 to 2 ^-6). For example, shifting a digital word by 1 in fig. 5 may correspond to a shift from 1 (e.g., coeff 15) to 0.5 (e.g., coeff 31) in table 600 of fig. 6.

The columns of table 600 may represent reference voltage scaling (e.g., VREF scaling), which may enable Fine gain steps (identified by Trim Fine). For reference control (or reference code) R from 0 to 15, VREF may be determined based on an example of the following equation (1):

In the example of equation (1) above, the VREF level ranges from VREF to VREF (17/32). Thus, the coefficient product value may be determined based on the example of the following equation (2):

In the example of the above formula (2), n is the number of shifts, and R is a reference code of 0 to 15.

Fig. 7 depicts a first example multi-bit DAC 700 and a second example multi-bit DAC 702. In some embodiments, the first multi-bit DAC 700 may correspond to and/or implement one or more of the DACs 116 of fig. 1. In some implementations, the second multi-bit DAC 702 may correspond to and/or implement one or more of the DACs 116 of fig. 1. In some implementations, the first multi-bit DAC 700 may correspond to and/or implement a first one of the DACs 116, and the second multi-bit DAC 702 may correspond to and/or implement a second one of the DACs 116.

The multi-bit DAC 700, 702 of this example is a 3-bit DAC. For example, the multi-bit DAC 700, 702 may be configured to convert the digital words 704, 706 (identified by D0[2:0] and D1[2:0 ]) into a 3-bit analog representation. Alternatively, the first multi-bit DAC 700 and/or the second multi-bit DAC 702 may use a different number of bits to represent the digital signal.

In some implementations, each of the multi-bit DACs 700, 702 may represent taps of an analog auxiliary feedforward equalizer (such as the analog auxiliary feedforward equalizer 102 of fig. 1 and/or the analog auxiliary feedforward equalizer 200 of fig. 2). In some implementations, each of the multi-bit DACs 700, 702 may be configured to set its own multiplier coefficients and/or set by external control circuitry. Non-limiting examples of external control circuitry include programmable processors and hardware-implemented state machines. In some implementations, the first multi-bit DAC 700 may perform shifting and/or reference voltage scaling separately and/or independently of shifting and/or reference voltage scaling of the second multi-bit DAC 702.

The multi-bit DAC 700, 702 of this example includes a plurality of charge storage elements 708, 710, 712, respectively, to store charge samples of charge based on one or more portions (such as one or more bits) of the digital words 704, 706. The charge storage elements 708, 710, 712 may be configured to generate an analog output signal 714 (identified by VTOP) at a node 726, the analog output signal 714 being proportional to a portion of the digital word 704, 706 and based on the stored charge samples. The charge storage elements 708, 710, 712 of the illustrated example are capacitors coupled in parallel. Alternatively, one or more of the charge storage elements 708, 710, 712 may be a different component, such as a resistor, transistor, or inductor. The charge storage elements 708, 710, 712 each have a different storage capacity. For example, a first one of the charge storage elements 708, 710, 712 has a capacitance of 1C, a second one of the charge storage elements 708, 710, 712 has a capacitance of 2C, and a third one of the charge storage elements 708, 710, 712 has a capacitance of 3C. Alternatively, one or more of the charge storage elements 708, 710, 712 may have a different storage capacity than that depicted in this example.

The multi-bit DAC 700, 702 of this example includes a plurality of switching circuits 716, 718, 720, respectively. Switching circuits 716, 718, 720 are coupled to the charge storage elements 708, 710, 712, respectively. For example, the output of the first switch circuit 716 of the switch circuits 716, 718, 720 is coupled to a first plate (e.g., a bottom plate) of the first charge storage element 708 of the charge storage elements 708, 710, 712. The switching circuits 716, 718, 720 of this example are implemented by one or more multiplexers (or multiplexer circuits). Alternatively, one or more of the switching circuits 716, 718, 720 may be implemented by one or more switches, one or more latches, one or more flip-flops, etc., and/or any combination thereof. The switching circuits 716, 718, 720 may be configured to switch the outputs of the switching circuits 716, 718, 720 between a reference voltage 722 (identified by VREF0 or VREF 1) and a ground voltage 724 (identified by GND). In this example, the first multi-bit DAC 700 is configured to use a first reference voltage (VREF 1) and the second multi-bit DAC 702 is configured to use a second reference voltage (VREF 2). In some embodiments, VREF1 and VREF2 are the same, while in other embodiments, VREF1 and VREF2 are different.

In the illustrated example, the analog output signal 714 may be generated based on a combination (e.g., sum, total, subtraction) of a first term associated with the first multi-bit DAC 700 and a second term associated with the second multi-bit DAC 702. For example, the analog output signal 714 may be generated based on an example of the following equation (3):

The example of formula (3) above may be simplified and/or reduced to an example of formula (4) below:

Vtop= (0.5×vref1×d1) + (0.5×vref0×d0) formula (4)

In an example operation, the first multi-bit DAC 700 may receive a first digital word 704, which may have a value of d=2 or a binary form of value 010 (e.g., b' 010). Thus, D0[0] may be 0, D0[1] may be 1, D0[2] may be 0, where 0 may correspond to a logic low signal (e.g., ground voltage 724), and 1 may correspond to a logic high signal (e.g., reference voltage 722). In response to D0[0] being 0, the first switching circuit 716 selects a ground voltage 724 to be output to the first charge storage element 708. In response to D0[1] being 1, the second switch circuit 718 of the switch circuits 716, 718, 720 selects the reference voltage 722 to be output to the second charge storage element 710 of the charge storage elements 708, 710, 712. In response to D0[2] being 0, the third switch circuit 720 of the switch circuits 716, 718, 720 selects the ground voltage 724 of the third charge storage element 712 to be output to the charge storage elements 708, 710, 712.

In an example operation, the second multi-bit DAC 700 may receive a second digital 706, and the second digital 706 may have a value of d=5 or a binary form of the value 101 (e.g., b' 101). Thus, D1[0] may be 1, D1[1] may be 0, and D1[2] may be 1, where 0 may correspond to a logic low signal (e.g., ground voltage 724), and 1 may correspond to a logic high signal (e.g., reference voltage 722). In response to D1[0] being 1, the first switching circuit 716 of the second multi-bit DAC 702 may select VREF1 to be output to the first charge storage element 708 of the second multi-bit DAC 702. In response to D1[1] being 0, the second switching circuit 718 of the second multi-bit DAC 702 may select a ground voltage 724 to be output to the second charge storage element 710 of the second multi-bit DAC 702. In response to D1[2] being 1, the third switching circuit 720 of the second multi-bit DAC 702 may select VREF1 to be output to the third charge storage element 712 of the second multi-bit DAC 702.

In example operations, the term (0.5×vref×d0) in the example of the above formula (4) may be 1/14×vref (e.g., 0.5×vref×2C/14C)). In example operations, the term (0.5×vref×d1) in the example of formula (4) above may be 5/14×vref (e.g., 0.5×vref×5C/14C)). In an example operation, due to charge redistribution and equivalent capacitance of the charge storage elements 708, 710, 712, the analog output signal 714 may be determined based on a combination of 1/14 x vref and 5/14 x vref (e.g., sum, total, subtraction), which is 3/7 x vref. For example, an analog output signal 714 may be generated and/or otherwise output by combining a first analog output of 1/14 vref and a second analog output of 5/14 vref at node 726.

Advantageously, since the first multi-bit DAC 700 and the second multi-bit DAC 702 perform multiplication and addition simultaneously (without sequential logic), the number of taps can be scaled up without affecting the delay, whereas in digital implementations more taps require more gates in series, thereby increasing the delay.

Fig. 8 depicts another example analog auxiliary feedforward equalizer 800. In some implementations, the analog auxiliary feedforward equalizer 800 may correspond to and/or implement the analog auxiliary feedforward equalizer 102 of fig. 1 and/or the analog auxiliary feedforward equalizer 200 of fig. 2.

Analog assisted feedforward equalizer 800 is an example of an FFE implementation with a main tap 802 (which may also be referred to as a main tap, a main cursor, or a main cursor), 7 front cursor taps 804, and 24 rear cursor taps 806. Taps 802, 804, 806 of this example are each implemented by a CDAC 807, which CDAC 807 may have a different number of bits depending on the type and/or position of the cursor. For example, the main tap 802 is a 7 bit CDAC. The second tap (identified by the digital word Dm2 and the coefficient hm 2) of the pre-cursor tap 804 is a 6-bit CDAC. The twenty-fourth tap (identified by the digital word D24 and the coefficient h 24) of the post-cursor taps 806 is a 3-bit CDAC. Alternatively, one or more of the taps 802, 804, 806 may be implemented by a CDAC having a different number of bits than shown in fig. 8.

The analog assisted feedforward equalizer 800 of the illustrated example includes a comparator circuit 810 and a successive approximation (successive approximation, SAR) logic circuit 812. The outputs of taps 802, 804, 806 are coupled to inputs of comparator circuit 810. The output of comparator circuit 810 is coupled to an input of SAR logic 812. The output of SAR logic 812 is coupled to subsequent circuitry, which may include one or more programmable processors.

In an example operation, the comparator circuit 810 may compare the outputs of taps 802, 804, 806 combined at one or more nodes 809 to a voltage threshold (e.g., repeatedly comparing, iteratively comparing). The comparator circuit 810 may output a signal representing the comparison result to the SAR logic circuit 812. SAR logic 812 can use binary search techniques to convert the continuous analog waveform to a discrete digital representation through all possible quantization levels, then converge to a digital output for each conversion and output the digital output as digital code 814 (identified by AAFFE OUT). For example, the output of SAR logic 812 can be a digital signal (e.g., a digital output signal), a digital representation of an analog signal, and the like. For example, for each bit, SAR logic 812 may output a binary code to taps 802, 804, 806 that depends on the current bit under evaluation and the previous bit that has been approximated. Comparator circuit 810 may determine the state of the current bit under evaluation. After all bits have been approximated, a digital approximation is output at the end of the conversion as digital code 814.

As an example, SAR logic 812 may select the first bit (e.g., the most significant bit) for evaluation and output a 7-bit binary code of 1000000 (or b' 1000000) to taps 802, 804, 806 such that bit 7 of each of taps 802, 804, 806 is set to 1 (if taps 802, 804, 806 are 7-bit taps) and otherwise set to 0. Taps 802, 804, 806 generate analog output signals for evaluation by comparator circuit 810 using analog multipliers and adders as disclosed herein. The comparator circuit 810 may compare the analog output signal with a threshold voltage. If the output does not meet and/or is less than the threshold voltage, the comparator circuit 810 may output a signal to the SAR logic circuit 812 that is the same, and the SAR logic circuit 812 may approximate bit 7 as a logic low representation (such as 0).

After determining that the analog output signal meets and/or is greater than the threshold voltage, the comparator circuit 810 may output a signal to the SAR logic circuit 812 that is representative of the same. SAR logic 812 can approximate bit 7 as a logic high representation (such as a 1). SAR logic 812 can loop through the remaining bits to approximate the remaining portion of the 7-bit binary code and output the approximation as digital code 814.

Fig. 9 depicts yet another example analog auxiliary feedforward equalizer 900. In some implementations, the analog auxiliary feedforward equalizer 900 may correspond to and/or implement the analog auxiliary feedforward equalizer 102 of fig. 1 and/or the analog auxiliary feedforward equalizer 200 of fig. 2.

Analog assisted feedforward equalizer 900 is an example of a hybrid approach of analog assisted FFE implementation with a main tap 902 implemented using digital logic and 7 pre-cursor taps 904 and 24 post-cursor taps 906 implemented in the analog domain. The pre-cursor tap 904 and the post-cursor tap 906 of this example are implemented by the CDAC 907, respectively, and the CDAC 907 may have a different number of bits depending on the type and/or position of the cursor. Alternatively, one or more of the front cursor tap 904 and/or the rear cursor tap 906 may be implemented by a CDAC having a different number of bits than shown in fig. 9.

The analog assisted feedforward equalizer 900 of the illustrated example includes a comparator circuit 910 and SAR logic 912. In some implementations, the comparator circuit 910 of fig. 9 may correspond to and/or implement the comparator circuit 810 of fig. 8. In some implementations, SAR logic 912 of fig. 9 may correspond to and/or implement SAR logic 812 of fig. 8. The output of the front cursor tap 904 and the output of the rear cursor tap 904 are combined at one or more nodes 909. The outputs of the front cursor tap 904 and the rear cursor tap 906 are coupled to inputs of a comparator circuit 910. The output of the comparator circuit 910 is coupled to an input of the SAR logic 912. The output of SAR logic 912 is coupled to subsequent circuitry, which may include one or more programmable processors. For example, SAR logic 912 may output an approximation of the input signal as digital code 914 (identified by AAFFE OUT) to one or more programmable processors.

The analog assisted feedforward equalizer 900 of the illustrated example includes an adder circuit 916, the adder circuit 916 to generate a digital code 914 based on a combination (e.g., sum, total, subtraction) of an approximate determination (which may be a first digital output) of the SAR logic 912 and an output (which may be a second digital output) of the multiplier circuit 918. Multiplier circuit 918 may be configured to output an approximation of main tap 902 as a second digital output.

Advantageously, by implementing the main tap 902 in the digital domain, substantially large amplitude terms are removed from the ADC conversion, and FFE ADC area and range can be relaxed. In some implementations, the gain block may be reused as an ADC gain calibration and/or control. Advantageously, the addition of multiplier circuit 918 does not cause timing problems because multiplier circuit 9180 is evaluating main tap 902 in parallel with the evaluation of pre-cursor tap 904 and/or post-cursor tap 906.

Fig. 10 depicts another example analog auxiliary feedforward equalizer 1000. In some implementations, the analog auxiliary feedforward equalizer 1000 may correspond to and/or implement the analog auxiliary feedforward equalizer 102 of fig. 1. Analog-assisted feedforward equalizer 1000 is another example of a hybrid approach of analog-assisted FFE implementation, in which one or more taps are implemented using digital logic and one or more taps are implemented in the analog domain. Hybrid approaches can be used to manage the tradeoff between analog domain implementation and digital domain implementation. For example, implementing taps in the digital domain may achieve benefits such as reduced noise, and implementing taps in the analog domain may achieve benefits such as reduced area, power consumption, and latency. By implementing one or more taps in the analog domain (such as taps not associated with relatively large ADC amplitude terms) and one or more taps in the digital domain (such as taps associated with relatively large ADC amplitude terms), reduced area, power consumption, and latency can be achieved with less noise impact. Advantageously, the mixing method may achieve a smaller scale, thereby better quantifying noise. Advantageously, the hybrid approach may produce smaller capacitors (because larger amplitude terms may be implemented using digital logic rather than multiple capacitors and/or related circuitry), which may enable smaller areas than may be achieved by the non-hybrid approach.

The analog assisted feedforward equalizer 1000 of the illustrated example may be configured to receive a digital signal 1002. In this example, the digital signal 1002 is represented by digital words (e.g., D0[6:0], D1[6:0],. The.. For example, the digital word D0[6:0] may represent a digital signal using 7 bits. Alternatively, one or more of the digital signals 1002 of this example may be represented by a different number of bits.

The analog assisted feedforward equalizer 1000 includes an analog circuit 1004, such as a plurality of analog multipliers 1006 (such as analog multiplier circuits) and a plurality of analog adders 1008 (such as analog adder circuits). For example, analog multiplier 1006 may respectively implement a multiplication of one of digital signals 1002 with one of a plurality of coefficients 1010 (identified by h2, h3, hm2, etc.). For example, the coefficients 1010 may be implemented by a configuration of analog multipliers 1006 to output analog signals. In some implementations, the coefficients 1010 may correspond to the coefficients in the table 600 of fig. 6.

In the example shown, the output of analog multiplier 1006 is coupled to an input of analog adder 1008. In some implementations, the analog adder 1008 is implemented by a plurality of adder circuits. In some implementations, the analog adder 1008 is implemented by a single adder circuit and/or more generally an adder circuit. The analog adder 1008 of the illustrated example generates samples 1012 (identified by y [0 ]) based on a combination (e.g., sum, total, subtraction) of the outputs of the analog multipliers 1006.

The samples 1012 of the illustrated example are output to an ADC 1014. The ADC 1014 may be configured to convert the samples 1012 from the analog domain to the digital domain. For example, ADC 1014 may convert an analog representation of the sum of analog multipliers 1006 to a digital representation. The output of ADC 1014 is coupled to an input of digital logic 1016. The digital logic 1016 of this example includes an adder circuit 1018 (e.g., an adder implemented by digital logic) and a plurality of multiplier circuits 1020 (e.g., a plurality of multiplier circuits implemented by digital logic). The output of multiplier circuit 1020 is coupled to adder circuit 1018. Multiplier circuit 1020 may generate a digital output based on a respective product of one of digital signals 1002 and a corresponding one of coefficients 1010. Adder circuit 1018 may generate digital outputs based on a combination (e.g., sum, total, subtraction) of samples 1012 and digital outputs from multiplier circuit 1020. Adder circuit 1018 may provide digital output to other circuits, such as one or more programmable processors, to perform electrical tasks and/or computing tasks. Advantageously, by implementing larger ADC conversion terms (such as main taps) in the digital domain, they can be removed from the ADC conversion and a relaxation of FFE ADC area and range is achieved.

Embodiments have been described in which these techniques are implemented in circuitry and/or machine-executable instructions. It should be appreciated that some embodiments may be in the form of methods, wherein at least one example has been provided. Acts performed as part of the method may be ordered in any suitable manner. Thus, embodiments may be constructed in which acts are performed in a different order than shown, which may include performing some acts simultaneously, even though shown as sequential acts in the illustrative embodiments.

The various aspects of the above-described embodiments may be used alone, in combination, or in a variety of arrangements not specifically discussed in the embodiments described in the foregoing and is therefore not limited in its application to the details and arrangement of components set forth in the foregoing description or illustrated in the drawings. For example, aspects described in one embodiment may be combined in any manner with aspects described in other embodiments.

The phrase "and/or" as used herein in the specification and claims should be understood to mean "either or both" of the elements so connected (e.g., elements that are in some cases present in combination and in other cases present separately). The use of "and/or" of a plurality of elements listed should be interpreted in the same manner as, for example, "one or more" of such elements. Other elements besides those specifically identified by the "and/or" clause may optionally be present, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, a reference to "a and/or B" when used in conjunction with an open language (such as "comprising") -can refer in one embodiment to a alone (optionally including elements other than B); in another embodiment reference is made to B only (optionally including elements other than a); in yet another embodiment both a and B (optionally including other elements) and the like.

The indefinite articles "a" and "an" as used herein in the specification and claims should be understood to mean "at least one" unless explicitly indicated to the contrary.

As used herein in the specification and claims, the phrase "at least one" in connection with a list of one or more elements should be understood to mean at least one element selected from any one or more elements in the list of elements, but not necessarily including at least one element in each element specifically listed within the list of elements and not excluding any combination of elements in the list of elements. The definition also allows that elements other than the specifically identified elements within the list of elements recited by the phrase "at least one" may optionally be present, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, "at least one of a and B" (or equivalently, "at least one of a or B," or equivalently, "at least one of a and/or B") may refer, in one embodiment, to at least one (optionally including more than one) a, with no B present (and optionally including elements other than B); in another embodiment, at least one (optionally including more than one) B is referred to, while no a is present (and optionally including elements other than a); in yet another embodiment, at least one (optionally including more than one) a and at least one (optionally including more than one) B (and optionally including other elements), and so forth.

Use of ordinal terms such as "first," "second," "third," etc., in the claims to modify a claim element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a certain name from another element having a same name (but for use of the ordinal term) to distinguish the claim elements.

Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of "including," "comprising," "having," "containing," "involving," and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.

All definitions as defined and used herein should be understood to mean definitions controlled by a dictionary, definitions in documents incorporated by reference, and/or ordinary meanings of the defined terms.

The word "exemplary" is used herein to mean serving as an example, instance, or illustration. Thus, any embodiments, implementations, processes, features, etc. described herein as exemplary should be construed as exemplary and should not be construed as preferred or advantageous examples unless otherwise specified.

Having thus described several aspects of at least one embodiment, it is to be appreciated various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and scope of the principles described herein. Accordingly, the foregoing description and drawings are by way of example only.

Claims (20)

1. An apparatus for feed forward equalization, the apparatus comprising:

a first charge element digital-to-analog converter DAC having a first output, the first charge element DAC comprising a first plurality of charge storage elements, the first charge element DAC configured to:

storing a first charge sample based on a respective first portion of the digital input signal; and

Generating a first analog output signal proportional to the first portion of the digital input signal and based on the first charge sample; and

A second charge-element DAC having a second output coupled to the first output, the second charge-element DAC comprising a second plurality of charge-storage elements, the second charge-element DAC configured to:

Storing a second charge sample based on a respective second portion of the digital input signal; and

Generating a second analog output signal proportional to the second portion of the digital input signal and based on the second charge sample; and wherein the first and second heat sinks are disposed,

The first output and the second output are coupled at a node to combine the first analog output signal and the second analog output signal to generate a third analog output signal.

2. The apparatus of claim 1, wherein the first charge element DAC has a first input, the second charge element DAC has a second input, the first input is configured to be coupled to a third output of a retimer circuit associated with a receiver, and the second input is configured to be coupled to the third output or a fourth output of the retimer circuit.

3. The apparatus of claim 1, wherein the first charge element DAC comprises:

a multiplier circuit configured to generate the first analog output signal based on a product of a reference voltage and a coefficient; and

An adder circuit configured to generate the third analog output signal based on a combination of outputs of the multiplier circuits.

4. The apparatus of claim 3, wherein the multiplier circuit is configured to at least one of:

Scaling the reference voltage; or alternatively

An input of the first portion of the digital input signal to be provided is shifted.

5. The apparatus of claim 1, wherein the first charge element DAC comprises:

a first switching circuit coupled to the first charge element; and

A second switching circuit coupled to a second charge element coupled to the first charge element.

6. The device of claim 5, wherein at least one of the first charge element or the second charge element is a capacitor.

7. The apparatus of claim 5, wherein the first charge element is a first capacitor having a first capacitance and the second charge element is a second capacitor having a second capacitance different from the first capacitance.

8. The apparatus of claim 5, wherein the first switching circuit comprises:

A first switch configured to receive a first voltage representative of a first bit of the digital input signal; and

A second switch configured to receive a reference voltage.

9. The apparatus of claim 8, wherein:

the first switch is turned on at a first time to charge the first charge element to a first voltage;

the second switch is turned off at the first time;

the first switch is turned off at a second time subsequent to the first time; and

The second switch is turned on at the second time to discharge the first charge element.

10. The apparatus of claim 1, wherein the first charge element DAC comprises:

a first multiplexer coupled to the first charge element; and

A second multiplexer coupled to a second charge element coupled to the first charge element.

11. The apparatus of claim 10, wherein:

The first multiplexer is configured to select a first voltage when a first bit of the digital input signal is a logic high signal; and

The first multiplexer is configured to select a second voltage when the first bit of the digital input signal is a logic low signal, the second voltage being less than the first voltage.

12. The apparatus of claim 10, wherein the second charge element DAC comprises:

A third charge element coupled in parallel with the first charge element and the second charge element; and

A fourth charge element coupled in parallel with the first charge element, the second charge element, and the third charge element.

13. The apparatus of claim 1, the apparatus further comprising:

A comparator circuit having a comparator input and a comparator output, the comparator input coupled to the first output and the second output; and

A successive approximation SAR circuit having a SAR input and a SAR output, the SAR input coupled to the comparator output.

14. The apparatus of claim 13, wherein the SAR circuit is configured to output a first digital output signal, and the apparatus further comprises:

a multiplier circuit having a multiplier input and a multiplier output, the multiplier input configured to multiply a third portion of the digital input signal with coefficients using digital logic to generate a second digital output signal; and

An adder circuit having a first adder input coupled to the SAR output and a second adder input coupled to the multiplier output, the adder circuit configured to output samples of the digital input signal based on a combination of the first digital output signal and the second digital output signal.

15. An apparatus, the apparatus comprising:

A plurality of capacitor digital-to-analog converters, CDACs, having respective CDAC outputs, the plurality of CDACs configured to generate a first analog output signal proportional to a first portion of a digital input signal;

A comparator circuit having a comparator input coupled to one or more of the respective CDAC outputs and a comparator output, the comparator circuit configured to determine whether a respective one of the first analog output signals meets a voltage threshold;

Successive approximation SAR logic having a SAR logic input coupled to the comparator output and a SAR logic output configured to pass the comparator output and control sampling of the plurality of CDACs;

digital logic having a digital logic output, the digital logic configured to generate a second analog output signal representative of a product of a second portion of the digital input signal and a coefficient; and

An adder circuit having a first adder input coupled to the SAR logic output and a second adder input coupled to the digital logic output, and configured to output samples of the digital input signal based on a combination of the first analog output signal and the second analog output signal.

16. The apparatus of claim 15, wherein the digital logic is configured to receive a primary cursor of the digital input signal.

17. The apparatus of claim 16, wherein a first CDAC of the plurality of CDACs is configured to sample a portion of the first portion of the digital input signal based on a first number of bits, and the digital logic is to sample the primary cursor based on a second number of bits, the second number of bits being greater than the first number of bits.

18. The apparatus of claim 15, wherein the coefficient is a first coefficient and the digital logic is configured to generate a third analog output signal representative of a product of a third portion of the digital input signal and a second coefficient.

19. An apparatus, the apparatus comprising:

Receiver front-end circuitry configured to convert a first analog signal to a digital signal, the first analog signal associated with a first clock;

A retimer circuit coupled to the receiver front-end circuit, the retimer circuit configured to output a copy of the digital signal based on a second clock different from the first clock;

a plurality of capacitor digital-to-analog converters, CDACs, coupled to the retimer circuit, the plurality of CDACs configured to generate a second analog signal proportional to a portion of the digital signal;

An analog adder circuit configured to generate a third analog signal based on a combination of analog signals in the second analog signal; and

An analog-to-digital converter configured to output samples of the digital signal based on the third analog signal.

20. The apparatus of claim 19, wherein the combination is a first combination, the analog-to-digital converter comprises digital logic configured to generate a fourth analog signal representative of a product of a second portion of the digital signal and a coefficient, and the sample is based on the second combination of the third analog signal and the fourth analog signal.