CN117995931A - PIN diode ultraviolet photoelectric detector and preparation method thereof - Google Patents
PIN diode ultraviolet photoelectric detector and preparation method thereof Download PDFInfo
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Abstract
The invention discloses a PIN diode ultraviolet photoelectric detector and a preparation method thereof. The PIN diode ultraviolet photoelectric detector comprises: the PIN structure comprises a P-type semiconductor layer, an intrinsic semiconductor layer and an N-type semiconductor layer which are sequentially stacked along a designated direction; a first electrode electrically connected to the P-type semiconductor layer; a second electrode electrically connected to the N-type semiconductor layer; the material of the N-type semiconductor layer comprises gallium oxide, and a plurality of nanometer holes which are spaced from each other are distributed on the first surface of the N-type semiconductor layer far away from the intrinsic semiconductor layer; and the material of the intrinsic semiconductor layer is selected from materials with hexagonal crystal structures. According to the invention, through precisely controlling the epitaxial temperature, a uniform nano-pore array is formed on the surface of Ga 2O3 by utilizing the self-reaction corrosion principle of Ga, so that a higher surface area ratio is obtained, and meanwhile, an intrinsic semiconductor layer is inserted between a substrate and a Ga 2O3 layer, so that the manufacture of a PIN heterostructure device of n-type Ga 2O3 is realized.
Description
Technical Field
The invention particularly relates to a PIN diode ultraviolet photoelectric detector and a preparation method thereof, belonging to the technical field of semiconductors.
Background
The novel wide bandgap semiconductor gallium oxide (Ga 2O3) material has the advantages of large band gap, high breakdown electric field intensity, high saturated electron drift speed, large heat conductivity, small dielectric constant, strong radiation resistance and good chemical stability, and is suitable for the semiconductor devices with radiation resistance, high frequency, high power and high density integration.
Ga 2O3 has a plurality of isomers of alpha, beta, gamma, delta, epsilon and the like, and the absorption peak of Ga 2O3 is in an ultraviolet band because of different crystal structures and different forbidden bandwidths (4.2-5.3 eV) of optical anisotropism, so the Ga 2O3 is a first-choice semiconductor material in the field of deep ultraviolet detection at present. In the visible light band, gallium oxide is also a transparent material, and is very suitable for manufacturing transparent conductive materials. The epsilon-Ga 2O3 crystal structure belongs to a highly symmetrical hexagonal system of the P6 3mc space group, has higher symmetry and lower anisotropic structure, and makes epsilon-Ga 2O3 more attractive for device application. Due to the lack of p-type Ga 2O3 and the small size and high price of the homogeneous Ga 2 O material, the development of Ga 2O3 materials and devices is limited.
Due to the crystal quality limited by Ga 2O3 heteroepitaxy, ga 2O3 materials are mainly used in optoelectronic devices, especially solar blind uv detectors. Currently, solar blind ultraviolet detectors based on gallium oxide materials mainly comprise a thin film detector, a single crystal detector and a nanowire detector, wherein the nanowire detector has better photoelectric performance due to the characteristics of large surface body ratio and the like. Thus, to obtain higher detector photoelectric performance, preparing Ga 2O3 nano-pore arrays with large surface area ratio is a potential solution.
The PIN junction is an improved structure developed after the development of the PN junction, that is, a special type of PN junction formed by purposely adding an intrinsic semiconductor layer (I-type layer) between a p-type semiconductor and an n-type semiconductor. In order to improve the EQE, the p-I-n photodiode is a preferable structure because the insertion of the intrinsic semiconductor layer (I-type layer) at a position between the p and n regions can significantly increase the photosensitive region, thereby improving the responsivity. Furthermore, the selectivity of the target wavelength of light can be well defined by selecting a type I layer, since the photocurrent is mainly activated by the type I layer. However, too thick a layer of type I may adversely affect the performance of the device because the conductivity of the layer of type I is much lower than that of either p-type or n-type semiconductors, and therefore it is necessary to find a suitable layer thickness of type I that can allow for high absorbance without increasing resistance.
Currently, homoepitaxial materials are expensive and have smaller sizes, and heteroepitaxial research has great significance, and materials such as silicon, sapphire (Al 2O3), gaN, gaAs, coGa and Ni are commonly used as substrates for growth of Ga 2O3. The gallium oxide materials applied to the solar blind ultraviolet detector at present are mainly a Ga 2O3 film and a Ga 2O3 nanowire, but the photoelectric performance of the prepared detector is poor due to the poor quality of a heteroepitaxial film crystal and the low surface area ratio of the nanowire. The research on the aspect of the nanopore array ultraviolet detector is relatively few, wherein, cao Xu et al manufacture the MSM type nanopore array ultraviolet photodetector, and the responsivity and the response speed of the MSM type nanopore array ultraviolet photodetector are obviously improved compared with those of the common photoconductive ultraviolet photodetector. The SiC layer is inserted into the p-Si and Ga 2O3 in 2016-Yuehua-An et al to form a p-Si/SiC/Ga 2O3 heterojunction, and the p-Si/SiC/Ga 2O3 heterojunction is used for manufacturing a PIN ultraviolet photoelectric detector, and the insertion of the intrinsic semiconductor layer effectively reduces dark current of the detector and improves the responsivity and quantum effect of the detector.
As is known to those skilled in the art, different substrates have a significant effect on the surface morphology of the Ga 2O3 growth, such as size, density, etc. Heteroepitaxy refers to epitaxial layers in which the epitaxially grown thin film material and substrate material are different, or in other words the growth chemistry is even entirely different in physical structure and substrate. However, when another single crystal layer is grown on a single crystal substrate, stress is generated near the growth interface due to the difference in the two lattice constants, and thus crystal defect-misfit dislocation is generated. There is a problem of lattice mismatch on heteroepitaxy, which is the most important issue that hinders the quality of heteroepitaxial thin film crystals.
The PN structure is free of a barrier layer and most of the depleted electrons and holes will absorb energy from the strong electric field and collide with lattice atoms of the barrier region, producing conductive electrons and positively charged holes. Avalanche effect occurs in the depletion layer and generates a large number of carriers, resulting in enhancement of reverse current, and Ga 2O3 has low thermal conductivity, and self-heating effect occurs in operation of the device, affecting electrical characteristics of the device.
Disclosure of Invention
The invention mainly aims to provide a PIN diode ultraviolet photoelectric detector and a preparation method thereof, thereby overcoming the defects in the prior art.
In order to achieve the purpose of the invention, the technical scheme adopted by the invention comprises the following steps:
in one aspect, the present invention provides a PIN diode ultraviolet photodetector, comprising:
The PIN structure comprises a P-type semiconductor layer, an intrinsic semiconductor layer and an N-type semiconductor layer which are sequentially stacked along a designated direction;
a first electrode electrically connected to the P-type semiconductor layer;
a second electrode electrically connected to the N-type semiconductor layer;
The material of the N-type semiconductor layer comprises gallium oxide, and a plurality of nanometer holes which are spaced from each other are distributed on the first surface of the N-type semiconductor layer far away from the intrinsic semiconductor layer; and the material of the intrinsic semiconductor layer is selected from materials with hexagonal crystal structures.
The invention also provides a preparation method of the PIN diode ultraviolet photoelectric detector, which comprises the steps of manufacturing a PIN structure and manufacturing a first electrode and a second electrode, wherein the first electrode and the second electrode are respectively and electrically connected with a P-type semiconductor layer and an N-type semiconductor layer in the PIN structure; wherein, the step of making the PIN structure comprises:
Providing a semiconductor structure, wherein the semiconductor structure comprises a P-type semiconductor layer, an intrinsic semiconductor layer and an N-type semiconductor layer which are sequentially stacked along a specified direction, the N-type semiconductor layer is a gallium oxide layer, and the intrinsic semiconductor layer is made of a material with a hexagonal system structure;
And depositing gallium metal on the first surface of the gallium oxide layer, and corroding the gallium oxide layer by using the gallium metal, so that a plurality of nanometer holes which are spaced from each other are formed on the first surface of the gallium oxide layer.
Compared with the prior art, the invention has the advantages that:
1) According to the PIN diode ultraviolet photoelectric detector, the problem of hot corrosion reaction of p-Si and Ga sources is solved by arranging the intrinsic semiconductor layer;
2) According to the PIN diode ultraviolet photoelectric detector provided by the invention, the Ga 2O3 layer material and the intrinsic semiconductor layer material are both hexagonal crystal structures, the lattice mismatch is small, the quality of the crystal of an epitaxial film is higher, the defects are fewer, and the obtained device has higher responsivity and lower dark current;
3) The PIN diode ultraviolet photoelectric detector provided by the invention solves the problem that the working efficiency of the device is affected by self-heating effect due to low heat conductivity of epsilon-Ga 2O3, and also because the heat conductivity of pure Ga 2O3 material is very low, by adopting the structure provided by the invention, si/AlN with high heat conductivity is combined, so that the heat dissipation of the device is facilitated, and the negative influence on the device caused by self-heating effect is reduced;
4) According to the PIN diode ultraviolet photoelectric detector provided by the invention, the surface area ratio of the Ga 2O3 layer is greatly improved by the nanopore array, and the photoelectric characteristic of the device is improved;
5) According to the preparation method of the PIN diode ultraviolet photoelectric detector, provided by the invention, the Ga 2O3 film is etched by utilizing the Ga metal etching characteristic, so that the pollution caused by introducing other element impurity sources is avoided.
Drawings
FIG. 1 is a schematic diagram of a structure of an aluminum source layer pre-laid on a second surface of a P-type semiconductor layer according to an exemplary embodiment of the present invention;
FIG. 2 is a schematic diagram showing the structure of an intrinsic semiconductor layer grown on a second surface of a P-type semiconductor layer according to an exemplary embodiment of the present invention;
FIG. 3 is a schematic diagram of a structure after forming an intrinsic semiconductor layer on a second surface of a P-type semiconductor layer according to an exemplary embodiment of the present invention;
FIG. 4 is a schematic diagram of an exemplary embodiment of the present invention after an N-type semiconductor layer is formed on an intrinsic semiconductor layer;
FIG. 5 is a schematic diagram of a structure after forming a silicon oxide mask on a first surface of an N-type semiconductor layer according to an exemplary embodiment of the present invention;
FIG. 6 is a schematic diagram of the structure of a PMMA formed on a silicon oxide mask in an exemplary embodiment of the present invention;
FIG. 7 is a schematic diagram of a structure after forming a nanopore array in PMMA in an exemplary embodiment of the present invention;
FIG. 8 is a schematic diagram of a structure of a nano-pore array formed in a silicon oxide mask according to an exemplary embodiment of the present invention;
FIG. 9 is a schematic diagram of a structure of an N-type semiconductor layer etched with gallium to form a nano-pore array in the N-type semiconductor layer according to an exemplary embodiment of the present invention;
FIG. 10 is a schematic diagram of the structure after removal of the silicon oxide mask in an exemplary embodiment of the invention;
Fig. 11 is a schematic structural view of a PIN diode uv photodetector according to an exemplary embodiment of the present invention.
Detailed Description
In view of the shortcomings in the prior art, the inventor of the present invention has long studied and practiced in a large number of ways to propose the technical scheme of the present invention. The technical scheme, the implementation process, the principle and the like are further explained as follows.
The invention provides a PIN diode ultraviolet photoelectric detector and a preparation method thereof, wherein the epitaxial temperature is precisely controlled, and a uniform nano-pore array is formed on the surface of Ga 2O3 by utilizing the self-reaction corrosion principle of Ga, so that a higher surface area ratio is obtained, and meanwhile, an intrinsic semiconductor layer is inserted between a substrate and a Ga 2O3 layer, so that the manufacture of a PIN heterostructure device of n-type Ga 2O3 is realized.
In one aspect, the invention provides a PiN diode ultraviolet photoelectric detector, comprising:
The PIN structure comprises a P-type semiconductor layer, an intrinsic semiconductor layer and an N-type semiconductor layer which are sequentially stacked along a designated direction;
a first electrode electrically connected to the P-type semiconductor layer;
a second electrode electrically connected to the N-type semiconductor layer;
the material of the N-type semiconductor layer comprises gallium oxide, and a plurality of nanometer holes which are spaced from each other are distributed on the first surface of the N-type semiconductor layer far away from the intrinsic semiconductor layer; and the material of the intrinsic semiconductor layer is selected from materials with hexagonal crystal structures.
Further, the material of the intrinsic semiconductor layer includes AlN or Al 2O3, but is not limited thereto.
Furthermore, the thickness of the intrinsic semiconductor layer can be adjusted according to specific requirements, on one hand, the intrinsic semiconductor layer is used as an I layer, on the other hand, the crystal quality of the Ga 2O3 film on the P-type Si substrate can be improved, and further, the device performance is improved, and the thickness of the intrinsic semiconductor layer can be 1-100nm, preferably 10nm.
Further, the material of the N-type semiconductor layer includes epsilon-Ga 2O3, but is not limited thereto.
Further, the thickness of the N-type semiconductor layer is 10nm to 10 μm, preferably 600nm.
Further, the P-type semiconductor layer includes a P-type Si substrate, but is not limited thereto.
Further, the plurality of nanopores are periodically arranged and distributed.
Further, the plurality of nanopores are equally spaced apart.
Further, the distance between two adjacent nanopores is 1nm-1 μm.
Further, the aperture of the nano-pore is 1nm-1 μm.
Further, the plurality of nanopores may have the same or different depths.
Further, the depth of the nano holes is 1nm-1mm.
Further, the axial direction of the nano-hole is perpendicular to the first surface.
Further, the area ratio of the nano holes on the first surface of the N-type semiconductor layer is 10-90%.
The invention also provides a preparation method of the PIN diode ultraviolet photoelectric detector, which comprises the steps of manufacturing a PIN structure and manufacturing a first electrode and a second electrode, wherein the first electrode and the second electrode are respectively and electrically connected with a P-type semiconductor layer and an N-type semiconductor layer in the PIN structure; wherein, the step of making the PIN structure comprises:
Providing a semiconductor structure, wherein the semiconductor structure comprises a P-type semiconductor layer, an intrinsic semiconductor layer and an N-type semiconductor layer which are sequentially stacked along a specified direction, the N-type semiconductor layer is a gallium oxide layer, and the intrinsic semiconductor layer is made of a material with a hexagonal system structure;
And depositing gallium metal on the first surface of the gallium oxide layer, and corroding the gallium oxide layer by using the gallium metal, so that a plurality of nanometer holes which are spaced from each other are formed on the first surface of the gallium oxide layer.
Further, the material of the intrinsic semiconductor layer includes AlN or Al 2O3, but is not limited thereto.
Further, the preparation method specifically comprises the following steps: firstly, presetting an aluminum source layer on the second surface of the P-type semiconductor layer;
Introducing an aluminum source and a nitrogen source into a growth chamber in which the P-type semiconductor layer is positioned, and enabling the nitrogen source to react with the aluminum source and the aluminum source layer on the second surface of the P-type semiconductor layer to form an AlN layer, or introducing an aluminum source and an oxygen source into the growth chamber in which the P-type semiconductor layer is positioned, and enabling the oxygen source to react with the aluminum source and the aluminum source layer on the second surface of the P-type semiconductor layer to form an Al 2O3 layer; the second surface is a surface of the P-type semiconductor layer facing the intrinsic semiconductor layer along a designated direction, and the first surface is a surface of the N-type semiconductor layer facing away from the intrinsic semiconductor layer along the designated direction, wherein the designated direction may be a thickness direction or a longitudinal direction of the PIN structure.
Further, the thickness of the aluminum source layer may be consistent with that of the intrinsic semiconductor layer to be formed, and specifically, the thickness of the aluminum source layer is 1-100nm.
Further, the aluminum source layer and the aluminum source layer are made of the same material and each include TMA1 and/or TEA1, but are not limited thereto.
Further, the nitrogen source includes NH 3 and/or N 2, but is not limited thereto.
Further, the oxygen source includes at least one of O 2、H2O、N2 O, but is not limited thereto.
Further, the thickness of the intrinsic semiconductor layer may be 1 to 100nm, preferably 10nm.
Further, the preparation method further comprises the following steps: and annealing the P-type semiconductor layer with the intrinsic semiconductor layer formed on the second surface in an oxygen atmosphere, and then manufacturing an N-type semiconductor layer on the intrinsic semiconductor layer. Furthermore, the annealing treatment temperature is 800-1200 ℃, and it should be noted that the annealing treatment is favorable for better crystallization of AlN or Al 2O3 and has an effect of promoting growth of a high-quality Ga 2O3 film, wherein the AlN layer can be annealed in a nitrogen atmosphere environment and the Al 2O3 layer can be annealed in an oxygen atmosphere environment.
Further, the material of the N-type semiconductor layer includes epsilon-Ga 2O3, but is not limited thereto.
Further, the thickness of the N-type semiconductor layer is 10nm to 10 μm, preferably 600nm.
Further, the P-type semiconductor layer includes a P-type Si substrate, but is not limited thereto.
Further, the preparation method comprises the following steps: and covering a patterned mask on the first surface of the gallium oxide layer, and then depositing gallium metal on a plurality of areas of the first surface of the gallium oxide layer which are not covered by the mask, so as to form a plurality of nano holes in the gallium oxide layer.
Further, the preparation method comprises the following steps: the area of the nano holes on the first surface of the gallium oxide layer is 10-90%.
Further, the plurality of nanopores are periodically arranged and distributed.
Further, the plurality of nanopores are equally spaced apart.
Further, the distance between two adjacent nanopores is 1nm-1 μm.
Further, the aperture of the nano-pore is 1nm-1 μm.
Further, the plurality of nanopores may have the same or different depths.
Further, the depth of the nano holes is 1nm-1mm.
Further, an included angle between the axial direction of the nano hole and the second surface of the P-type semiconductor layer is 45-90 degrees.
The technical scheme, implementation process and principle thereof will be further explained with reference to the accompanying drawings and specific embodiments, and unless otherwise indicated, all the epitaxial devices such as MOCVD and ALD used in the embodiments of the present invention are known to those skilled in the art, and all the aluminum source, nitrogen source, oxygen source and gallium source used are commercially available.
Example 1
The structure of the PIN diode uv photodetector is shown in fig. 11, and includes a PIN structure including a P-type semiconductor layer 10, an intrinsic semiconductor layer 20, and an N-type semiconductor layer 30 sequentially stacked in a specified direction, and a first electrode 40 and a second electrode 50 mated with the PIN structure.
In this embodiment, the intrinsic semiconductor layer 20 and the N-type semiconductor layer 30 are sequentially stacked on the second surface of the P-type semiconductor layer 10, the first surface of the N-type semiconductor layer 30 has a nanopore array 31 including a plurality of nanopores distributed at intervals, and the first electrode 40 and the second electrode 50 are respectively and correspondingly electrically connected to the P-type semiconductor layer 10 and the N-type semiconductor layer 30, wherein the first surface of the N-type semiconductor layer 30 faces away from the second surface of the P-type semiconductor layer 10.
In this embodiment, the material of the intrinsic semiconductor layer 20 is a material with a hexagonal structure, for example, the material of the intrinsic semiconductor layer 20 may be AlN, al 2O3, etc., it should be noted that under a high-temperature environment, si and Ga may generate a hot corrosion reaction, so that it is difficult to directly grow a high-quality Ga-containing crystal film on the surface of the Si substrate, and the performance is particularly obvious in the epitaxial growth of a GaN film on the Si substrate, and the intrinsic semiconductor layer 20 is inserted between the P-type semiconductor layer 10 and the N-type semiconductor layer 30, so that the intrinsic semiconductor layer 20 not only can be used as an insulator layer of a PIN diode ultraviolet photodetector, but also can be used as a buffer layer for epitaxially growing a high-quality gallium oxide film on the surface of the P-type semiconductor layer, thereby avoiding the hot corrosion reaction between P-Si and metal Ga; meanwhile, compared with other semiconductor buffer layers, the materials such as AlN, al 2O3 and the like adopted by the semiconductor buffer layer and epsilon-Ga 2O3 are of hexagonal crystal structures, the lattice mismatch of the materials with epsilon-Ga 2O3 is small, and the materials such as AlN, al 2O3 and the like can guide epsilon-Ga 2O3 to grow along the c axis, so that a Ga 2O3 film with higher epitaxial quality is obtained, the semiconductor buffer layer is more suitable for epitaxial growth of the Ga 2O3 film, and the materials such as AlN, al 2O3 and the like have higher thermal conductivity, so that the device has good heat dissipation efficiency.
It should be noted that an excessively thick intrinsic semiconductor layer may adversely affect the device performance, since the conductivity of the intrinsic semiconductor layer is much lower than that of the p-type or n-type semiconductor, and therefore it is necessary to find a suitable intrinsic semiconductor layer thickness, which may allow for high absorbance without increasing the resistance, in this embodiment the thickness of the intrinsic semiconductor layer 20 may be 1-100nm.
In the embodiment, the PIN structure greatly improves the detection capability of the device, and the generation rate of photo-generated carriers is increased due to the arrangement of the I region (or called an I layer, an I type layer is an intrinsic semiconductor layer and is the same as the I layer, so that the responsivity and the quantum efficiency of the device are improved; the light-generated carriers drift towards the electrode at the fastest speed under the action of the strong electric field, so that the response speed is improved; meanwhile, the depletion layer is widened by arranging the I region, and the junction capacitance is reduced, so that the response frequency is improved; and dark current of the device in operation can be effectively reduced due to the arrangement of the I region.
In this embodiment, the material of the N-type semiconductor layer 30 includes epsilon-Ga 2O3, the thickness of the N-type semiconductor layer 30 is 10nm-10 μm, preferably 600nm, specifically, the plurality of nanopores included in the nanopore array 31 are periodically arranged and distributed, preferably, the plurality of nanopores are distributed at equal intervals, specifically, the distance between two adjacent nanopores is 1nm-1 μm, the pore diameter of the nanopore is 1nm-1 μm, the depths of the plurality of nanopores are the same or different, specifically, the depth of the nanopore is 1nm-1mm; the nano-pore array 31 improves the surface ratio of the surface of the N-type semiconductor layer 30, and further improves the photoelectric performance of the device, and specifically, the area ratio of the nano-pores on the first surface of the N-type semiconductor layer is 10-90%.
In this embodiment, the included angle between the axial direction of the nanopore and the second surface of the P-type semiconductor layer is 45 ° -90 °, that is, the nanopores may be vertically disposed in the N-type semiconductor layer 30 or may be obliquely disposed in the N-type semiconductor layer 30, and the directions of the inclinations of the nanopores may be the same or opposite, preferably, the inclination angle of the nanopores may be 45 ° or more and less than 90 ° compared to the first surface of the N-type semiconductor layer 30 or the second surface of the P-type semiconductor layer, so that the incident light may be better localized in the gallium oxide thin film having the nanopores.
Referring to fig. 1-11, a method for manufacturing a PIN diode ultraviolet photoelectric detector may include the following steps:
1) And taking the P-Si substrate as a P-type semiconductor layer, and processing the P-Si substrate.
1.1 Firstly, ultrasonically cleaning the p-Si substrate by acetone and the like to remove organic pollutants possibly existing; the p-Si substrate is immersed in hydrofluoric acid with the concentration of 2 percent to remove natural silicon dioxide possibly existing on the surface of the Si substrate or the natural silicon dioxide possibly existing on the surface of the Si substrate can be removed by a heat treatment mode; in order to optimize the epitaxial effect, oxygen sources are introduced into a part of the process in the substrate treatment process, namely, the surface treatment is carried out on the substrate under the high-temperature condition, impurities such as foreign matters on the surface of the substrate can be removed under the high-temperature condition and the oxygen environment, and the specific surface treatment process can be realized by adopting a process known by a person skilled in the art;
2) Epitaxially growing an intrinsic layer and a gallium oxide layer on the second surface of the p-Si substrate sequentially from bottom to top; the method specifically comprises the following steps:
2.1 An AlN layer is grown on the second surface of the p-Si substrate by MOCVD (metal organic chemical vapor deposition), atomic layer deposition (Atomic Layer Deposition, ALD) or the like to form an intrinsic semiconductor layer.
In this embodiment, referring to fig. 1-3, before growing an AlN layer, an aluminum source layer is pre-laid on the second surface of the p-Si substrate, then an aluminum source and a nitrogen source are simultaneously introduced into a growth chamber where the p-Si substrate is located, and the nitrogen source reacts with the aluminum source and the aluminum source layer on the second surface of the p-Si substrate to form an AlN layer, so as to ensure that the AlN layer grows uniformly and has good crystal quality; wherein the growth temperature of the AlN layer is 400 ℃, the thickness is 1-100nm, the aluminum source can be TMA1, TEAL and the like, and the nitrogen source can be NH 3、N2 and the like.
When the intrinsic semiconductor layer is an Al 2O3 layer, the nitrogen source is replaced by an oxygen source, which may be O 2、H2O、N2 O or the like.
2.2 The gallium oxide layer is epitaxially grown on the intrinsic semiconductor layer by MOCVD, ALD, or the like, as shown in fig. 4.
In the embodiment, before the gallium oxide layer starts to grow, oxygen is firstly introduced into a growth chamber, and high-temperature annealing is carried out on the p-Si substrate;
In the growth process, the growth temperature of the growth chamber is controlled to be 500 ℃, and the rate of the introduced reaction source is-O 2: 440sccm, TEGa:495sccm; the growth time was 2 hours, thereby forming an epsilon-Ga 2O3 layer with a thickness of about 600nm on the AlN layer;
it should be noted that other Ga-containing or pure metal sources such as TMGa may be used instead of TEGa as the gallium source.
3) PIN heteroepitaxy device preparation:
3.1 A SiO 2 mask 60 is deposited on the first surface of the gallium oxide layer facing away from the AlN intrinsic layer, as shown in FIG. 5; spin-coating PMMA70 on SiO 2 mask 60 as shown in FIG. 6; after electron beam exposure is carried out on PMMA70, a nanopore array comprising a plurality of ordered and uniform nanopores is formed in PMMA70 by selective etching, as shown in FIG. 7; transferring the array of nanopores in PMMA70 to a SiO 2 mask to obtain a SiO 2 mask with an ordered, uniform array of nanopores, as shown in FIG. 8, followed by removal of the PMMA70;
3.2 The temperature of the growth chamber is adjusted to 660 ℃, gallium metal is deposited on the first surface of the gallium oxide layer which is not covered by the SiO 2 mask 60, so that a plurality of areas of the first surface of the gallium oxide layer are corroded by the gallium metal, a nano hole array which comprises a plurality of nano holes perpendicular to the p-Si substrate is formed on the first surface of the gallium oxide layer, then the SiO 2 mask 60 is removed, as shown in fig. 9 and 10, specifically, the included angle between the axial direction of the nano holes and the first surface of the gallium oxide layer is 45-90 degrees, and the inclination angle of the nano holes can be regulated and controlled by controlling the angle of a slide table and controlling the angle of the Ga metal and the gallium oxide layer to react to generate the nano holes.
Wherein, the reaction equation of Ga 2O3 and metallic Ga includes: 4Ga (l) +Ga 2O3(s)→3Ga2O(g)、Ga(l)+Ga2O3(s) →3GaO (g).
3.3 A metal electrode is deposited on the third surface of the p-Si substrate and is used as a first electrode 40, and the first electrode 40 forms ohmic contact with the p-Si substrate; depositing a metal electrode on the first surface of the gallium oxide layer and serving as a second electrode 50, wherein the second electrode 50 and the gallium oxide layer form ohmic contact, so that a PIN diode ultraviolet photoelectric detector is obtained, and the structure of the PIN diode ultraviolet photoelectric detector is shown in figure 11; the third surface and the second surface are arranged opposite to each other.
Comparative example 1
Comparative example 1 is different from example 1 in that no intrinsic semiconductor layer is provided, i.e., comparative example 1 is a PN junction diode ultraviolet photodetector, i.e., a semiconductor layer is provided.
The comparison test shows that the frequency response speed of the PIN diode ultraviolet photodetector provided in the embodiment 1 of the invention is higher than that of the PN junction diode ultraviolet photodetector in the comparison example 1.
It should be noted that the PIN-type photodetector of the present invention is a three-layer structure device composed of an intrinsic semiconductor layer (or low doping) sandwiched between a heavily doped P layer and an N layer, and has the advantages that the i layer has a significant design space, the maximum response of the device to the band can be realized by controlling the width of the i layer to be equal to the reciprocal of the absorption coefficient of the wavelength to be measured, and the frequency response speed is much higher than that of the conventional PN junction photodetector because most of the photocurrent is generated in the i region, and the presence of the strong electric field epsilon in the depleted i region enables the photo-generated carriers to be efficiently and rapidly separated and collected, thereby obtaining a high frequency response.
Comparative example 2
The PIN ultraviolet photodetector in comparative example 2 was obtained by referring to the scheme disclosed in Yuehua-An et al in 2016, in which a SiC layer was interposed between a P-type semiconductor layer and a Ga 2O3 layer to form a P-Si/SiC/Ga 2O3 heterojunction, and then a PIN ultraviolet photodetector was fabricated.
Through test comparison, the i layer of the PIN diode ultraviolet photoelectric detector provided in the embodiment 1 of the invention is controllable, so that the regulation and control of device performance (crystal quality, defect, responsivity of a device, dark current and the like) can be realized, and as AlN or Al 2O3, a Si (111) substrate and epsilon-Ga 2O3 are in a hexagonal crystal system structure, the lattice mismatch with epsilon-Ga 2O3 is smaller, and high-quality AlN and Al 2O3 films formed after high-temperature annealing can guide epsilon-Ga 2O3 to grow along a c axis, so that high-quality Ga 2O3 is obtained through epitaxy.
It should be understood that the above embodiments are merely for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the present invention and implement the same according to the present invention without limiting the scope of the present invention. All equivalent changes or modifications made in accordance with the spirit of the present invention should be construed to be included in the scope of the present invention.
Claims (10)
1. A PIN diode ultraviolet photodetector comprising:
The PIN structure comprises a P-type semiconductor layer, an intrinsic semiconductor layer and an N-type semiconductor layer which are sequentially stacked along a designated direction;
a first electrode electrically connected to the P-type semiconductor layer;
a second electrode electrically connected to the N-type semiconductor layer;
the method is characterized in that: the material of the N-type semiconductor layer comprises gallium oxide, and a plurality of nanometer holes which are spaced from each other are distributed on the first surface of the N-type semiconductor layer far away from the intrinsic semiconductor layer; and the material of the intrinsic semiconductor layer is selected from materials with hexagonal crystal structures.
2. The PIN diode ultraviolet photodetector of claim 1, wherein: the material of the intrinsic semiconductor layer comprises AlN or Al 2O3, and/or the thickness of the intrinsic semiconductor layer is 1-100nm.
3. The PIN diode ultraviolet photodetector of claim 1, wherein: the N-type semiconductor layer is made of epsilon-Ga 2O3; and/or the thickness of the N-type semiconductor layer is 10nm-10 mu m;
and/or the P-type semiconductor layer comprises a P-type Si substrate.
4. A PIN diode ultraviolet photodetector according to claim 1 or 3, wherein: the plurality of nano holes are periodically arranged and distributed;
and/or the plurality of nanopores are equally spaced apart; preferably, the distance between two adjacent nanopores is 1nm-1 μm;
And/or the aperture of the nano-pore is 1nm-1 μm;
And/or the plurality of nanopores are the same or different in depth; preferably, the depth of the nano holes is 1nm-1mm;
and/or, an included angle between the axial direction of the nano hole and the first surface is 45-90 degrees.
5. The PIN diode ultraviolet photodetector according to claim 1 or 2, wherein: the area ratio of the nano holes on the first surface of the N-type semiconductor layer is 10-90%.
6. The preparation method of the PIN diode ultraviolet photoelectric detector comprises the steps of manufacturing a PIN structure and manufacturing a first electrode and a second electrode, wherein the first electrode and the second electrode are respectively and electrically connected with a P-type semiconductor layer and an N-type semiconductor layer in the PIN structure; the method is characterized in that the step of manufacturing the PIN structure comprises the following steps:
Providing a semiconductor structure, wherein the semiconductor structure comprises a P-type semiconductor layer, an intrinsic semiconductor layer and an N-type semiconductor layer which are sequentially stacked along a specified direction, the N-type semiconductor layer is a gallium oxide layer, and the intrinsic semiconductor layer is made of a material with a hexagonal system structure;
And depositing gallium metal on the first surface of the gallium oxide layer, and corroding the gallium oxide layer by using the gallium metal, so that a plurality of nanometer holes which are spaced from each other are formed on the first surface of the gallium oxide layer.
7. The method of manufacturing according to claim 6, wherein: the intrinsic semiconductor layer is made of AlN or Al 2O3;
preferably, the preparation method specifically comprises the following steps:
firstly, presetting an aluminum source layer on the second surface of the P-type semiconductor layer;
Introducing an aluminum source and a nitrogen source into a growth chamber in which the P-type semiconductor layer is positioned, and enabling the nitrogen source to react with the aluminum source and the aluminum source layer on the second surface of the P-type semiconductor layer to form an AlN layer, or introducing an aluminum source and an oxygen source into the growth chamber in which the P-type semiconductor layer is positioned, and enabling the oxygen source to react with the aluminum source and the aluminum source layer on the second surface of the P-type semiconductor layer to form an Al 2O3 layer;
Preferably, the thickness of the aluminum source layer is 1-100nm;
preferably, the aluminum source layer and the aluminum source are the same in material and each comprise TMAl and/or TEAl, and/or the nitrogen source comprises NH 3 and/or N 2; and/or the oxygen source comprises at least one of O 2、H2O、N2 O.
8. The method of manufacturing according to claim 6, further comprising: annealing the P-type semiconductor layer with the intrinsic semiconductor layer formed on the second surface in an oxygen and/or nitrogen atmosphere, and then manufacturing an N-type semiconductor layer on the intrinsic semiconductor layer;
Preferably, the temperature of the annealing treatment is 800-1200 ℃;
and/or the material of the N-type semiconductor layer comprises epsilon-Ga 2O3; and/or the thickness of the N-type semiconductor layer is 10nm-10 mu m nm;
and/or the P-type semiconductor layer comprises a P-type Si substrate.
9. The method of manufacturing according to claim 6, comprising: and covering a patterned mask on the first surface of the gallium oxide layer, and then depositing gallium metal on a plurality of areas of the first surface of the gallium oxide layer which are not covered by the mask, so as to form a plurality of nanopores on the gallium oxide layer.
10. The preparation method according to claim 6 or 9, characterized by comprising: the area ratio of the nano holes on the first surface of the gallium oxide layer is 10-90%;
and/or the plurality of nanopores are periodically arranged and distributed;
and/or the plurality of nanopores are equally spaced apart; preferably, the distance between two adjacent nanopores is 1nm-1 μm;
And/or the aperture of the nano-pore is 1nm-1 μm;
And/or the plurality of nanopores are the same or different in depth; preferably, the depth of the nano holes is 1nm-1mm;
And/or the axial direction of the nano hole is perpendicular to the second surface of the P-type semiconductor layer.
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