CN117995780A

CN117995780A - Semiconductor device and method for manufacturing the same

Info

Publication number: CN117995780A
Application number: CN202410146093.2A
Authority: CN
Inventors: 吴恒; 刘煜; 葛延栋; 王润声; 黎明; 黄如
Original assignee: Peking University
Current assignee: Peking University
Priority date: 2024-02-01
Filing date: 2024-02-01
Publication date: 2024-05-07

Abstract

The application provides a semiconductor device and a method for manufacturing the same. The preparation method comprises providing a substrate, wherein the substrate comprises a first substrate layer, an insulating layer and a second substrate layer which are sequentially stacked; forming a logic circuit based on the first substrate layer, wherein the logic circuit is positioned on one side of the insulating layer close to the first substrate layer; forming a silicon optical circuit based on the second substrate layer, wherein the silicon optical circuit is positioned on one side of the insulating layer close to the second substrate layer; and forming a connection structure penetrating at least the substrate, wherein the connection structure is respectively connected with the logic circuit and the silicon optical circuit.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The present application relates to the field of integrated circuits, and more particularly, to a semiconductor device and a method for fabricating the same.

Background

With the shrinking of chip manufacturing process, the problems of high delay, high power consumption, signal crosstalk and the like caused by electrical interconnection become important factors affecting the chip performance, and moore's law also faces the limit challenges of chip integration. Silicon photonics is regarded as a key technology for breaking through the bottleneck of the prior art and continuing moore's law because of the advantages of high bandwidth, low transmission loss, low power consumption and the like.

Silicon photonics is a new generation of technology for developing and integrating optical chips based on silicon and silicon-based substrate materials using complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, abbreviated CMOS) technology. However, the existing optical chip has the problems of large area, complex process and the like.

Disclosure of Invention

According to a first aspect of an embodiment of the present application, there is provided a method for manufacturing a semiconductor device, including:

Providing a substrate, wherein the substrate comprises a first substrate layer, an insulating layer and a second substrate layer which are sequentially stacked;

forming a logic circuit based on the first substrate layer, wherein the logic circuit is positioned on one side of the insulating layer close to the first substrate layer;

Forming a silicon optical circuit based on the second substrate layer, wherein the silicon optical circuit is positioned on one side of the insulating layer close to the second substrate layer;

And forming a connection structure penetrating at least the substrate layer, wherein the connection structure is respectively connected with the logic circuit and the silicon optical circuit.

In some embodiments, the method of making further comprises:

forming a first dielectric layer covering the first substrate layer and the logic circuit;

Forming a first interconnection structure in the first dielectric layer, wherein the first interconnection structure is respectively connected with the logic circuit and a first end of the connection structure;

forming a second dielectric layer covering the second substrate layer and the silicon optical circuit;

and forming a second interconnection structure in the second dielectric layer, wherein the second interconnection structure is respectively connected with the silicon optical circuit and the second end of the connection structure, and the second end of the connection structure and the first end of the connection structure are opposite along the thickness direction of the substrate.

In some embodiments, the substrate further comprises a sacrificial substrate layer and an epitaxial layer, the epitaxial layer being located between the sacrificial substrate layer and the second substrate layer; the preparation method further comprises the following steps:

Bonding the substrate with the first dielectric layer and the first interconnect structure formed to a carrier wafer prior to forming the second dielectric layer;

and rewinding and removing the sacrificial substrate layer and the epitaxial layer until the second substrate layer is exposed.

In some embodiments, the removing the sacrificial substrate layer and the epitaxial layer comprises:

Performing planarization treatment on the sacrificial substrate layer until the epitaxial layer is exposed;

And etching the epitaxial layer until the second substrate layer is exposed.

In some embodiments, the material of the sacrificial substrate layer comprises silicon and the material of the epitaxial layer comprises silicon germanium.

According to a second aspect of an embodiment of the present application, there is provided a semiconductor device including:

the substrate comprises a first substrate layer, an insulating layer and a second substrate layer which are sequentially stacked;

a logic circuit, wherein the logic circuit is positioned on one side of the insulating layer close to the first substrate layer, and a first active area of the logic circuit is positioned in the first substrate layer;

A silicon optical circuit, wherein the silicon optical circuit is positioned on one side of the insulating layer close to the second substrate layer, and a second active area of the silicon optical circuit is positioned in the second substrate layer;

and the connecting structure at least penetrates through the substrate layer and is respectively connected with the logic circuit and the silicon optical circuit.

In some embodiments, the front projection of the silicon optical circuit and the front projection of the logic circuit at least partially overlap.

In some embodiments, the semiconductor device further comprises:

a first dielectric layer covering the first substrate layer and the logic circuit;

A second dielectric layer covering the second substrate layer and the silicon optical circuit;

a first interconnect structure located in the first dielectric layer; wherein the first interconnection structure is connected with the logic circuit and a first end of the connection structure respectively;

A second interconnect structure in the second dielectric layer; the second interconnection structure is respectively connected with the silicon optical circuit and the second end of the connection structure, and the second end of the connection structure is opposite to the first end of the connection structure along the thickness direction of the substrate.

In some embodiments, the connection structure extends through the substrate layer and into the first and second dielectric layers, respectively.

In some embodiments, the silicon optical circuit includes at least one of a laser, an optical modulator, an optical amplifier, a photodetector.

In the preparation method provided by the embodiment of the application, the logic circuit and the silicon optical circuit are respectively formed on the two opposite sides of the insulating layer by providing the substrate comprising the first substrate layer, the insulating layer and the second substrate layer which are sequentially stacked, and the logic circuit and the silicon optical circuit are connected through the connecting structure based on the first substrate layer and the second substrate layer of the substrate. In the first aspect, the three-dimensional integration of the logic circuit and the silicon photoelectric circuit can be realized, which is beneficial to reducing the area of the semiconductor device; in the second aspect, the logic circuit and the silicon optical circuit are compatible in manufacturing process, thereby being beneficial to simplifying the process flow and reducing the manufacturing cost; in the third aspect, the three-dimensional integration of the logic circuit and the silicon optical circuit is beneficial to improving the integration density and the electrical performance of the photoelectric device and realizing functional diversity.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.

FIG. 1 is a schematic diagram of an optical chip according to an exemplary embodiment;

Fig. 2 is a flowchart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present application;

fig. 3 to 8 are schematic views illustrating a manufacturing process of a semiconductor device according to an embodiment of the present application;

fig. 9 is a schematic structural view of a semiconductor device according to an embodiment of the present application.

Reference numerals:

300. A semiconductor device; 310. a substrate; 311. a first substrate layer; 312. an insulating layer; 313. a second substrate layer; 314. an epitaxial layer; 315. sacrificial substrate layers; 320. a logic circuit; 321. an isolation structure; 330. a first dielectric layer; 331. a first spacer layer; 332. a first isolation layer; 333. a protective layer; 340. a first interconnect structure; 350. a carrier wafer; 360. a silicon optical circuit; 361. an active device; 362. a passive device; 363. a grating coupler; 370. a second dielectric layer; 371. a second spacer layer; 372. a second isolation layer; 380. a second interconnect structure; 390. and a connection structure.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application.

The optical chip comprises a logic device and a silicon optical device, wherein the logic device is mainly used for realizing at least one of generation of electric signals, processing of the electric signals and transmission of the electric signals, and the silicon optical device is mainly used for realizing at least one of generation of optical signals, processing of the optical signals, transmission of the optical signals and conversion of the optical signals into the electric signals. The integration of logic devices and silicon optical devices in the prior art is mainly planar, and the integration of logic devices and silicon optical devices in an optical chip and an optical chip will be exemplarily described with reference to fig. 1.

Fig. 1 is a schematic diagram showing a structure of an optical chip according to an exemplary embodiment. Referring to fig. 1, a logic device and a silicon optical device are typically fabricated in different regions on the same substrate, and are electrically connected to external circuits by performing a subsequent interconnection process. However, since the silicon optical device has a large area and occupies a large area of the substrate, the integrated logic device and the silicon optical device can realize photoelectric integration on a plane, but the required area is large, the cost is high, and the cost performance is low. In addition, the two processes are not compatible, so that the process of the optical chip is complex.

While moore's law is continually deepening, the continued push to shrink logic devices and silicon photonics is a hot spot problem currently being developed in the industry. The logic device and the silicon optical device can be integrated in a vertical space by three-dimensional stacking, which is helpful for further improving the integration density of the photoelectric device, improving the circuit performance and realizing functional diversity, and is considered as one of important technologies for continuing the miniaturization of the integrated circuit.

In view of the above, the present application provides a method for manufacturing a semiconductor device and a semiconductor device.

Fig. 2 is a flowchart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present application. Referring to fig. 2, the preparation method at least comprises the following steps:

s210: providing a substrate, wherein the substrate comprises a first substrate layer, an insulating layer and a second substrate layer which are sequentially stacked;

S220: forming a logic circuit based on the first substrate layer, wherein the logic circuit is positioned on one side of the insulating layer close to the first substrate layer;

s230: forming a silicon optical circuit based on the second substrate layer, wherein the silicon optical circuit is positioned on one side of the insulating layer close to the second substrate layer;

S240: and forming a connection structure penetrating at least the substrate, wherein the connection structure is respectively connected with the logic circuit and the silicon optical circuit.

It should be noted that the steps shown in fig. 2 are not exclusive and that other steps may be performed before, after, or between any of the steps in the illustrated operations; the steps shown in fig. 2 can be sequentially adjusted according to actual requirements.

Fig. 3 to 8 are schematic views illustrating a manufacturing process of a semiconductor device according to an embodiment of the present application. The method for manufacturing the semiconductor device according to the embodiment of the present application will be described in detail with reference to fig. 2 and fig. 3 to 8.

In step S210, referring to fig. 3, a substrate 310 is provided, and the substrate 310 includes a first substrate layer 311, an insulating layer 312, and a second substrate layer 313 stacked in this order.

In this embodiment, the substrate 310 includes, but is not limited to, a Silicon-On-Insulator (SOI) substrate, which typically includes an oxygen-buried layer (i.e., insulating layer 312) and a top substrate layer (i.e., first substrate layer 311) and a bottom substrate layer (i.e., second substrate layer 313) On opposite sides of the oxygen-buried layer.

In some embodiments, referring to fig. 3, the substrate 310 further includes a sacrificial substrate layer 315 and an epitaxial layer 314, the epitaxial layer 314 being located between the sacrificial substrate layer 315 and the second substrate layer 313, the thickness of the epitaxial layer 314 including 10 to 20nm. The materials of the sacrificial substrate layer 315 and the epitaxial layer 314 include semiconductor materials, such as elemental semiconductor materials (e.g., silicon (Si) or germanium (Ge), etc.), group III-V compound semiconductor materials (e.g., gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP), etc.), group II-VI compound semiconductor materials (e.g., zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), etc.), organic semiconductor materials, or other semiconductor materials known in the art. Because silicon and silicon germanium are more easily epitaxially grown on SOI, and silicon germanium can be used as a stop layer for subsequent bonding and post-bond CMP operations, and the choice of etching is relatively high and is more easily removed, the present embodiment will be described with respect to the process difficulty by taking the sacrificial substrate layer 315 as the silicon substrate and the epitaxial layer 314 as the silicon germanium layer as examples.

It should be noted that, the sacrificial substrate layer 315 and the epitaxial layer 314 are removed in a subsequent process to expose the second substrate layer 313 for the fabrication of the silicon optical circuit 360, and the epitaxial layer 314 may be used as a stop layer during the planarization process of the sacrificial substrate layer 315, so as to avoid damage to the second substrate layer 313. Of course, in other embodiments, a silicon-on-insulator substrate may be provided directly for use as substrate 310.

In one embodiment, the providing a substrate 310 includes: providing a silicon substrate; epitaxially growing the silicon substrate to form a silicon germanium layer; the silicon substrate with the silicon germanium layer formed is bonded to a silicon-on-insulator substrate to form the substrate 310. Epitaxial growth includes homoepitaxy or heteroepitaxy, and in this embodiment, heteroepitaxy may be performed on a silicon substrate to form a silicon germanium layer.

It will be appreciated that in the embodiment of the present application, by epitaxial growth and bonding, a composite substrate 310 may be formed, and the composite substrate 310 may provide a foundation for the fabrication of the front side logic circuit 320, and may also provide a suitable stop layer in the back side thinning process, providing a substrate including a buried oxide layer (Burried Oxide, abbreviated as BOX) for the back side silicon optical circuit 360. Of course, in other embodiments, a thin film deposition process may be used to sequentially deposit a silicon germanium layer, a second substrate layer, an insulating layer, and a first substrate layer on a silicon substrate to form the substrate 310. In practical applications, those skilled in the art can reasonably choose according to the actual process, and the present application is not limited thereto.

In step S220, as shown with reference to fig. 4, based on the first substrate layer 311, a logic circuit 320 is formed, the logic circuit 320 being located on the side of the insulating layer 312 close to the first substrate layer 311.

The logic circuit 320 includes a plurality of transistors, for example, logic units such as an inverter, an and gate, an or gate, a nand gate, a nor gate, and the like, which are composed of an N-type field effect transistor (hereinafter referred to as NFET) and a P-type field effect transistor (hereinafter referred to as PFET). In practical applications, the number of transistors in the logic circuit 320 is not limited to two as shown in fig. 4, and the logic circuit 320 may further include electronic components, such as capacitors, inductors, resistors, etc., that are known in the art to constitute a logic circuit. The forming process of the logic circuit 320 includes an etching process, a thin film deposition process, a doping process, and the like.

In some embodiments, the forming the logic circuit 320 based on the first substrate layer 311 includes: etching the first substrate layer 311 from the first surface of the substrate 310 by using the patterned mask layer as an etching mask to form a plurality of trenches, wherein the first substrate layer 311 between two adjacent trenches is used as an active region of the transistor; filling isolation materials into the grooves to form isolation structures 321; and forming a gate dielectric layer and a grid electrode which cover the active region, wherein the gate dielectric layer is positioned between a channel of the active region and the grid electrode. In this embodiment, the bottom of the trench may extend into the first substrate layer 311 or extend to the exposed insulating layer 312 (i.e., extend through the first substrate layer 311), as shown in fig. 4, the isolation structure 321 extends through the first substrate layer 311. The material of the isolation structure 321 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, and the like.

The doping ions of the active region of the transistor include P-type ions (e.g., boron ions, gallium ions, indium ions, etc.) and/or N-type ions (e.g., nitrogen ions, phosphorus ions, arsenic ions, etc.). The forming process of the gate dielectric layer comprises a film deposition process, a thermal oxidation process and the like, and the material of the gate dielectric layer comprises silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide and the like. In the thermal oxidation process, the exposed active region may be subjected to a thermal treatment to oxidize the surface of the active region to form a gate dielectric layer. The gate forming process includes a thin film deposition process. The material of the gate electrode includes a conductive material, for example, tungsten nitride, titanium nitride, tantalum nitride, tungsten, titanium, tantalum, polysilicon, doped polysilicon, and the like.

In some embodiments, referring to fig. 4, the preparation method further includes: forming a first dielectric layer 330 covering the first substrate layer 311 and the logic circuit 320; a first interconnect structure 340 is formed in the first dielectric layer 330, the first interconnect structure 340 connecting the logic circuit 320 and a first end of the connection structure 390 in fig. 8, respectively, the first end of the connection structure 390 may be an end of the connection structure 390 relatively close to the first interconnect structure 340.

The forming process of the first dielectric layer 330 includes a thin film deposition process. In a specific example, the forming process of the first dielectric layer 330 includes: forming a first spacer layer 331 covering the first substrate layer 311 and the logic circuit 320; a first isolation layer 332 is formed overlying the first spacer layer 331. Here, the first isolation layer 332 may be subjected to chemical mechanical polishing until the surface is flush. The material of the first spacer 331 includes silicon oxide, silicon nitride, silicon oxynitride, etc., and the material of the first spacer 332 includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxynitride, doped silicon carbonitride, doped silicon oxynitride, etc. It will be appreciated that the first dielectric layer 330 includes a composite film layer of the first spacer layer 331 and the first spacer layer 332, and of course, in other embodiments, the first dielectric layer 330 may be a single layer film or include other insulating film layers.

The formation process of the first interconnect structure 340 includes an etching process and a thin film deposition process. In a specific example, the forming of the first interconnect structure 340 includes: etching the first dielectric layer 330 to form a first interconnection hole; the first interconnect hole is filled with a conductive material to form a first interconnect structure 340. Here, the bottoms of the first interconnection holes expose portions of the logic circuit 320, for example, a plurality of first interconnection holes are formed, and the bottoms of the plurality of first interconnection holes expose the source and/or drain of the transistor, respectively. The material of the first interconnect structure 340 includes copper, aluminum, etc.

In a specific embodiment, the first interconnect structure 340 includes a first interconnect column and a first interconnect layer; wherein the first interconnect pillar is located between the logic circuit 320 and the first interconnect layer, the logic circuit 320 may be connected to the connection structure 390 in fig. 8 through the first interconnect pillar, the first interconnect layer.

In some embodiments, referring to fig. 5 to 7, the preparation method further includes: bonding the substrate 310 with the first dielectric layer 330 and the first interconnect structure 340 formed with the carrier wafer 350; the sacrificial substrate layer 315 and the epitaxial layer 314 are reworked and removed until the second substrate layer 313 is exposed. In this embodiment, the step of bonding the substrate 310 to the carrier wafer 350 may precede the step of forming the second dielectric layer 370 in fig. 8.

As shown in connection with fig. 4 and 5, the structure shown in fig. 4 and carrier wafer 350 are bonded and then inverted so that the second surface of substrate 310 faces upward. The carrier wafer 350 is used to provide physical support during thinning of the substrate 310, protecting other structures (e.g., logic circuitry 320, first interconnect structure 340, etc.) that have been formed. In practice, carrier wafer 350 may be removed after the semiconductor device fabrication is completed to reduce the package height of the semiconductor device.

In one embodiment, before bonding the structure shown in fig. 4 to the carrier wafer 350, a protective layer 333 covering the first dielectric layer 330 and the first interconnect structure 340 may be formed, as shown in fig. 5, where the protective layer 333 is used to protect the previously formed structure from damage to the formed structure during the bonding process, and the material of the protective layer 333 includes, but is not limited to, silicon oxide.

In some embodiments, removing the sacrificial substrate layer 315 and the epitaxial layer 314 described above includes: planarization is performed on the sacrificial substrate layer 315 until the epitaxial layer 314 is exposed, as shown in fig. 6; an etching process is performed on the epitaxial layer 314 until the second substrate layer 313 is exposed, as shown in fig. 7. The planarization process includes, but is not limited to, a chemical mechanical polishing process and the etching process includes, but is not limited to, a dry etching process.

In a specific example, the sacrificial substrate layer 315 may be removed by polishing using a chemical mechanical polishing process, and then the epitaxial layer 314 may be removed by etching using a dry etching process, so that the damage of the exposed surface of the second substrate layer 313 may be reduced to a great extent by step-thinning the substrate 310, which is beneficial to ensuring better performance of the subsequent silicon optical device. In addition, the combination of the cmp and dry etching processes to thin the substrate 310 is advantageous in terms of cost savings, as the cost of the cmp process is lower.

In step S230, referring to fig. 8, a silicon optical circuit 360 is formed based on the second substrate layer 313, the silicon optical circuit 360 being located on a side of the insulating layer 312 near the second substrate layer 313. The silicon optical circuit 360 includes at least one of an active device 361, a passive device 362, and a grating coupler 363. Illustratively, as shown in fig. 8, the silicon optical circuit 360 includes an active device 361, a passive device 362, and a grating coupler 363.

In this embodiment, the active device 361, the passive device 362, the grating coupler 363, and the like may be formed by a silicon photonics technique. The active device 361 is configured to perform functions such as generation of an optical signal (e.g., an active laser), modulation of an optical signal (e.g., an optical modulator), amplification of an optical signal (e.g., an optical amplifier), conversion of an optical signal into an electrical signal (e.g., a photodetector), the passive device 362 is configured to perform functions such as transmission of an optical signal (e.g., a beam splitter or a beam combiner), and the grating coupler 363 is configured to perform functions such as coupling of an optical signal. It is appreciated that the silicon optical circuit 360 may include at least one of a laser, an optical modulator, an optical amplifier, a photodetector, etc., so that the corresponding functions of optical signal generation, optical signal processing, optical signal transmission, etc. may be implemented.

In some embodiments, referring to fig. 8, the preparation method further includes: forming a second dielectric layer 370 covering the second substrate layer 313 and the silicon photo circuit 360; a second interconnect structure 380 is formed in the second dielectric layer 370, the second interconnect structure 380 connecting the silicon photo circuitry 360 and a second end of the connection structure 390, respectively, the second end of the connection structure 390 may be an end of the connection structure 390 relatively close to the second interconnect structure 380. It is understood that the second end of the connection structure 390 and the first end of the connection structure 390 are opposite in the thickness direction of the substrate 310.

The formation process of the second dielectric layer 370 includes a thin film deposition process. In a specific example, the forming of the second dielectric layer 370 includes: forming a second spacer layer 371 covering the second substrate layer 313 and the silicon optical circuit 360; a second spacer 372 is formed overlying the second spacer 371. Here, the second isolation layer 372 may be chemically mechanically polished until the surface is flush. The material of the second spacer 371 includes silicon oxide, silicon nitride, silicon oxynitride, etc., and the material of the second spacer 372 includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxynitride, doped silicon carbonitride, doped silicon oxynitride, etc. It will be appreciated that the second dielectric layer 370 comprises a composite film of the second spacer layer 371 and the second spacer layer 372, although in other embodiments the second dielectric layer 370 may be a single layer film or may comprise other insulating film layers as well.

The formation process of the second interconnect structure 380 includes an etching process and a thin film deposition process. In a specific example, the forming of the second interconnect structure 380 includes: etching the second dielectric layer 370 to form a second interconnect hole; the second interconnect hole is filled with a conductive material to form a second interconnect structure 380. Here, the bottom of the second interconnect hole exposes a portion of the silicon photo-circuit 360, e.g., the bottom of the second interconnect hole exposes an electrode in the silicon photo-circuit 360. The material of the second interconnect structure 380 includes copper, aluminum, and the like.

In a specific embodiment, the second interconnect structure 380 includes a second interconnect column and a second interconnect layer; wherein the second interconnect column is located between the silicon optical circuit 360 and the second interconnect layer, the silicon optical circuit 360 may be connected to the connection structure 390 in fig. 8 through the second interconnect column, the second interconnect layer.

In step S240, a connection structure 390 penetrating at least the substrate 310 is formed, and the connection structure 390 connects the logic circuit 320 and the silicon optical circuit 360, respectively. Illustratively, the second dielectric layer 370, the substrate 310, and the first dielectric layer 330 are etched sequentially until the first interconnect layer is exposed to form a through silicon via (Through Silicon Via, TSV); the through silicon vias are filled with a conductive material to form a connection structure 390. In this embodiment, the through silicon via may be formed before the second interconnect layer. It is understood that the connection structure 390 may enable interconnection of the logic circuit 320 and the silicon photo circuit 360.

Note that in the examples of fig. 3 to 8, the logic circuit 320 is formed based on the first substrate layer 311 first, and then the silicon optical circuit 360 is formed based on the second substrate layer 313. In other examples, the order of forming the logic circuit 320 and the silicon optical circuit 360 may be changed, for example, the silicon optical circuit 360 is formed based on the second substrate layer 313 and then the logic circuit 320 is formed based on the first substrate layer 311, which is not particularly limited by the present application.

In practical applications, the sequence of forming the logic circuit 320 and the silicon optical circuit 360 may be comprehensively considered based on the thermal budget of each of the logic circuit 320 and the silicon optical circuit 360, for example, if the temperature that the logic circuit 320 can withstand is higher than the temperature that the silicon optical circuit 360 can withstand, the logic circuit 320 may be formed first and then the silicon optical circuit 360 may be formed; conversely, if the temperature that the logic circuit 320 can withstand is lower than the temperature that the silicon optical circuit 360 can withstand, the silicon optical circuit 360 can be formed first and then the logic circuit 320 can be formed.

The embodiment of the application provides a preparation method of a semiconductor device, which comprises the steps of providing a substrate comprising a first substrate layer, an insulating layer and a second substrate layer which are sequentially stacked, forming a logic circuit and a silicon optical circuit on two opposite sides of the insulating layer respectively based on the first substrate layer and the second substrate layer of the substrate, and connecting the logic circuit and the silicon optical circuit through a connecting structure. In the first aspect, the three-dimensional integration of the logic circuit and the silicon photoelectric circuit can be realized, which is beneficial to reducing the area of the semiconductor device; in the second aspect, the logic circuit and the silicon optical circuit are compatible in manufacturing process, thereby being beneficial to simplifying the process flow and reducing the manufacturing cost; in the third aspect, the three-dimensional integration of the logic circuit and the silicon optical circuit is beneficial to improving the integration density and the electrical performance of the photoelectric device and realizing functional diversity.

Based on the above method for manufacturing the semiconductor device, the embodiment of the application provides a semiconductor device which can be applied to the next generation optoelectronic integrated circuit manufacturing process.

Fig. 9 is a schematic structural view of a semiconductor device according to an embodiment of the present application. Referring to fig. 9, the semiconductor device includes: a substrate 310, logic circuitry 320, silicon photo circuitry 360, and a connection structure 390.

The substrate 310 includes a first substrate layer 311, an insulating layer 312, and a second substrate layer 313 stacked in this order. In this embodiment, the substrate 310 includes, but is not limited to, a Silicon-On-Insulator (SOI) substrate, which typically includes an oxygen-buried layer (i.e., insulating layer 312) and a top substrate layer (i.e., first substrate layer 311) and a bottom substrate layer (i.e., second substrate layer 313) On opposite sides of the oxygen-buried layer. In this embodiment, the first substrate layer 311 and the second substrate layer 313 are both silicon substrates.

The logic circuit 320 is located on a side of the insulating layer 312 adjacent to the first substrate layer 311, and the first active region of the logic circuit 320 is located in the first substrate layer 311. The logic circuit 320 may include a plurality of transistors, for example, an inverter, an and gate, an or gate, a nand gate, a nor gate, and the like, which are formed of an N-type field effect transistor (hereinafter referred to as NFET) and a P-type field effect transistor (hereinafter referred to as PFET). In practical applications, the number of transistors in the logic circuit 320 is not limited to two as shown in fig. 9, and the logic circuit 320 may further include electronic components, such as capacitors, inductors, resistors, etc., that are known in the art to constitute the logic circuit. Here, the transistors include Fin Field-effect transistors (Fin Field-Effect Transistor, abbreviated as finfets), full-around gate transistors (gate-all-around FIELD EFFECT transistors, GAAFET), and the like.

The silicon optical circuit 360 is located on a side of the insulating layer 312 adjacent to the second substrate layer 313, and the second active region of the silicon optical circuit 360 is located in the second substrate layer 313. The silicon optical circuit 360 includes at least one of an active device 361, a passive device 362, and a grating coupler 363. Illustratively, as shown in fig. 8, the silicon optical circuit 360 includes an active device 361, a passive device 362, and a grating coupler 363, and the second active region may be an active region of the active device 361.

The connection structure 390 penetrates at least the substrate 310 and connects the logic circuit 320 and the silicon optical circuit 360, respectively, the connection structure 390 can interconnect the logic circuit 320 and the silicon optical circuit 360, and the material of the connection structure 390 includes a conductive material, such as copper, aluminum, and the like.

In some embodiments, referring to fig. 9, the front projection of the silicon optical circuit 360 and the front projection of the logic circuit 320 at least partially overlap, thus reducing the area of the semiconductor device.

In some embodiments, the semiconductor device further comprises:

a first dielectric layer 330, the first dielectric layer 330 covering the first substrate layer 311 and the logic circuit 320;

A second dielectric layer 370, the second dielectric layer 370 covering the second substrate layer 313 and the silicon photo circuit 360;

A first interconnect structure 340, the first interconnect structure 340 being located in the first dielectric layer 330; wherein the first interconnect structure 340 connects the logic circuit 320 and the first end of the connection structure 390, respectively;

a second interconnect structure 380, the second interconnect structure 380 being located in the second dielectric layer 370; wherein the second interconnection structure 380 connects the second ends of the silicon photo circuit 360 and the connection structure 390, respectively, the second ends of the connection structure 390 and the first ends of the connection structure 390 are opposite in the thickness direction of the substrate 310.

In some embodiments, the connection structure 390 extends through the substrate 310 and into the first dielectric layer 330 and the second dielectric layer 370, respectively.

In some embodiments, silicon photo-circuitry 360 includes at least one of a laser, an optical modulator, an optical amplifier, a photodetector.

The embodiment of the application provides a semiconductor device, which is characterized in that a logic circuit and a silicon optical circuit are respectively arranged on two opposite sides of an insulating layer, and the logic circuit and the silicon optical circuit are connected through a connecting structure. In the first aspect, the three-dimensional integration of the logic circuit and the silicon photoelectric circuit can be realized, which is beneficial to reducing the area of the semiconductor device; in the second aspect, the logic circuit and the silicon optical circuit are compatible in manufacturing process, thereby being beneficial to simplifying the process flow and reducing the manufacturing cost; in the third aspect, the three-dimensional integration of the logic circuit and the silicon optical circuit is beneficial to improving the integration density and the electrical performance of the photoelectric device and realizing functional diversity.

In the description of the embodiments of the present application, the descriptions of the terms "one embodiment," "an example," "a particular example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representations of the above terms are not necessarily for the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the various embodiments or examples described in the present application and the features of the various embodiments or examples may be combined by those skilled in the art without contradiction.

The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A method of manufacturing a semiconductor device, comprising:

2. The method of manufacturing according to claim 1, characterized in that the method of manufacturing further comprises:

3. The method of manufacturing of claim 2, wherein the substrate further comprises a sacrificial substrate layer and an epitaxial layer, the epitaxial layer being located between the sacrificial substrate layer and the second substrate layer; the preparation method further comprises the following steps:

4. A method of manufacturing according to claim 3, wherein said removing the sacrificial substrate layer and the epitaxial layer comprises:

And etching the epitaxial layer until the second substrate layer is exposed.

5. A method of manufacturing as claimed in claim 3 wherein the material of the sacrificial substrate layer comprises silicon and the material of the epitaxial layer comprises silicon germanium.

6. A semiconductor device, comprising:

7. The semiconductor device of claim 6, wherein the front projection of the silicon optical circuit and the front projection of the logic circuit at least partially overlap.

8. The semiconductor device according to claim 6, wherein the semiconductor device further comprises:

9. The semiconductor device of claim 8, wherein the connection structure extends through the substrate layer and into the first and second dielectric layers, respectively.

10. The semiconductor device of claim 6, wherein the silicon photo-circuit comprises at least one of a laser, an optical modulator, an optical amplifier, and a photodetector.