CN117995693A

CN117995693A - Heterogeneous bonding structure, preparation method thereof and electronic equipment

Info

Publication number: CN117995693A
Application number: CN202211369218.5A
Authority: CN
Inventors: 王玉西; 殷祥; 左致远; 赵佳; 康汝燕; 李洵
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-11-03
Filing date: 2022-11-03
Publication date: 2024-05-07
Also published as: WO2024093982A1

Abstract

The application discloses a hetero-bonding structure, a preparation method thereof and electronic equipment, and belongs to the technical field of semiconductors. The heterobonding structure comprises: a first substrate, a second substrate, a first intercalation formed on the first substrate, a second intercalation formed on the second substrate; the first and second interposers are bonded, one of the first and second interposers having a slot-like symmetrical pattern configured to relieve at least one of lattice stress and thermal stress. The groove-shaped symmetrical patterns can relieve lattice mismatch and/or thermal mismatch between the first substrate and the second substrate, relieve lattice stress and/or thermal stress of an interface, inhibit dislocation extension and migration of the interface, and improve reliability and stability of the heterogeneous bonding structure. In addition, volatile substances generated during bonding annealing can be effectively discharged, interface cavities are reduced, and bonding yield is effectively improved.

Description

Heterogeneous bonding structure, preparation method thereof and electronic equipment

Technical Field

The disclosure relates to the technical field of semiconductors, in particular to a heterojunction bonding structure, a preparation method thereof and electronic equipment.

Background

Currently, heterogeneous bonding processes are generally used for integration of different types of semiconductor materials, and common heterogeneous bonding processes include a plasma activated bonding process, a wet activated bonding process, a BCB (Benzocyclobutene) bonding process, and the like.

However, the heterojunction bonding process has the problem of large interface stress, and the problems of dislocation extension, migration and the like are easy to occur.

BRIEF SUMMARY OF THE PRESENT DISCLOSURE

In view of the above, the present disclosure provides a heterobonding structure, a preparation method thereof, and an electronic device, which can solve the above technical problems.

Specifically, the method comprises the following technical scheme:

In one aspect, embodiments of the present disclosure provide a heterobonding structure comprising: a first substrate, a second substrate, a first intercalation formed on the first substrate, a second intercalation formed on the second substrate;

The first and second interposers are bonded, one of the first and second interposers having a slot-like symmetrical pattern configured to relieve at least one of lattice stress and thermal stress.

According to the heterogeneous bonding structure provided by the embodiment of the disclosure, the groove-shaped symmetrical patterns are arranged on the first intercalation or the second intercalation, and comprise a plurality of symmetrical features which are periodically and repeatedly arranged, and the plurality of symmetrical features are utilized to correspond to the lattice features and/or the thermal expansion features of the first substrate or the second substrate, so that the groove-shaped symmetrical patterns can relieve lattice mismatch and/or thermal mismatch between the first substrate and the second substrate, strengthen release and balance of lattice stress and/or thermal stress, relieve lattice stress and/or thermal stress of an interface, avoid localization and long-term accumulation of the lattice stress and/or thermal stress, inhibit dislocation extension and migration of the interface, and improve reliability and stability of the heterogeneous bonding structure. In addition, the groove-shaped symmetrical patterns are arranged on the first intercalation or the second intercalation, so that volatile substances generated during bonding annealing can be effectively discharged, interface cavities are reduced, and bonding yield is effectively improved.

In some possible implementations, the first interposer and the first substrate have a first degree of mismatch therebetween, the second interposer and the second substrate have a second degree of mismatch therebetween, and the first degree of mismatch and the second degree of mismatch each include: at least one of lattice mismatch degree and thermal expansion coefficient mismatch degree;

when the first mismatch degree is larger than the second mismatch degree, the groove-shaped symmetrical pattern is positioned in the first intercalation;

when the second mismatch degree is larger than the first mismatch degree, the groove-shaped symmetrical pattern is positioned in the second intercalation;

And when the first mismatch degree is equal to the second mismatch degree, the groove-shaped symmetrical pattern is positioned in one of the first intercalation and the second intercalation.

In some possible implementations, the slot-like symmetrical pattern has at least one of a first symmetrical structure and a second symmetrical structure;

the first symmetrical structure corresponds to the lattice characteristics of the corresponding substrate so as to relieve lattice stress;

the second symmetrical structure corresponds to thermal expansion characteristics of the respective substrate to relieve thermal stresses.

When the slot-like symmetrical pattern includes both the first symmetrical structure and the second symmetrical structure, the following two cases may be included: first, first symmetrical structure and second symmetrical structure can be the same and keep overlapping, at this moment, can consider that the slot-like symmetrical pattern has first symmetrical structure and second symmetrical structure concurrently, and then can alleviate lattice stress and thermal stress simultaneously. And secondly, the first symmetrical structure and the second symmetrical structure are different and are mutually communicated through crossed arrangement, the first symmetrical structure is used for relieving lattice stress, and the second symmetrical structure is used for relieving thermal stress.

In some possible implementations, when the respective substrate has a symmetric lattice structure, the symmetry of the plurality of symmetric features included in the first symmetric structure is consistent with the lattice structure symmetry of the respective substrate;

When the respective substrate is an amorphous structure, the first symmetrical structure exhibits isotropy, including but not limited to a circle, ring, or other geometric figure having isotropic characteristics.

In some possible implementations, when the thermal expansion feature of the corresponding substrate has directionality, a distribution direction of the plurality of symmetrical features included in the second symmetrical structure coincides with the thermal expansion direction of the corresponding substrate;

the second symmetrical structure exhibits isotropy when the thermal expansion characteristics of the respective substrate are not directional, including but not limited to circular, annular, or other geometric shapes having isotropic characteristics.

In some possible implementations, the pattern shape of the slot-like symmetrical pattern includes at least one of a one-dimensional grating shape, a multiple symmetric dot slot shape, a multiple symmetric slot shape, an isotropic geometry.

For a multiple symmetrical spot-slot shape, it comprises a plurality of periodically arranged spot slots, which may be circular through slots, for example.

For a multiple symmetrical slot shape, it includes a plurality of periodically arranged slots, which may be rectangular through slots, for example.

In some possible implementations, the ratio of the area of the slot-like symmetrical pattern to the area of the interposed layer is 5% -80%.

In some possible implementations, the materials of the first substrate and the second substrate are selected from silicon carbide, silicon oxide, indium phosphide, gallium arsenide, gallium phosphide, gallium nitride or aluminum nitride.

In some possible implementations, the first intercalation and the second intercalation are made of the same material, and are each selected from silicon dioxide, silicon nitride, silicon carbide or aluminum oxide.

In another aspect, an embodiment of the present disclosure provides a method for preparing a heterobonding structure, where the heterobonding structure is any one of the foregoing, and the method for preparing a heterobonding structure includes:

forming a first interlayer on a first substrate, and forming a second interlayer on a second substrate;

Preparing a groove-like symmetrical pattern on one of the first and second interposers according to a first degree of mismatch between the first substrate and the first interposer and a second degree of mismatch between the second substrate and the second interposer, the groove-like symmetrical pattern configured to relieve at least one of lattice stress and thermal stress;

and bonding the first intercalation and the second intercalation to obtain the heterogeneous bonding structure.

In some possible implementations, the first intercalation is formed on the first substrate and the second intercalation is formed on the second substrate by a deposition process or a sputtering process.

According to the intercalation material and the specific bonding requirement, the deposition processes such as low-pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer epitaxy and the like can be selected adaptively, or the ion beam sputtering process or the plasma sputtering process and the like can be selected adaptively.

In some possible implementations, the trough-like symmetrical pattern is prepared by a photolithographic process in combination with an etching process.

In some possible implementations, the bonding the first intercalation and the second intercalation to obtain the heterobonding structure includes:

performing surface treatment on the first intercalation and the second intercalation;

Attaching the treatment surface of the first intercalation to the treatment surface of the second intercalation and pre-bonding to obtain an intermediate material;

And annealing the intermediate material to obtain the heterojunction bonding structure.

In some possible implementations, the surface treating the first intercalation and the second intercalation includes: and carrying out surface polishing, surface cleaning and surface activation on the first intercalation and the second intercalation in sequence.

In some possible implementations, the pre-bonding has a bonding pressure of 10N to 200N and a bonding temperature of 150 ℃ to 300 ℃.

In some possible implementations, the temperature of the annealing treatment is 175-950 ℃ and the time of the annealing treatment is 15 minutes-50 hours.

The preparation method of the heterojunction bonding structure has the advantages of being easy to operate in technical route, low in manufacturing cost, high in manufacturability, high in applicability, high in compatibility with the existing manufacturing process and the like, and therefore large-scale mass production of the heterojunction bonding structure is facilitated.

In yet another aspect, an embodiment of the present disclosure provides an electronic device including any one of the heterojunction structure described above.

Illustratively, the electronic device includes, but is not limited to: computers, cell phones, printers, cameras, medical devices, fitness devices, etc.

Drawings

Fig. 1 is a schematic structural diagram of an exemplary heterobonding structure provided in embodiment 1 of the present disclosure before bonding;

fig. 2 is a schematic structural diagram of an exemplary heterobonding structure provided in embodiment 1 of the present disclosure after bonding;

FIG. 3 is a first exemplary structural schematic diagram of a slot-like symmetrical pattern provided on a first interposer according to an embodiment of the present disclosure;

FIG. 4 is a second exemplary structural schematic diagram of a slot-like symmetrical pattern provided on a first interposer according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a third exemplary configuration of a slot-like symmetrical pattern provided on a first interposer according to an embodiment of the present disclosure;

FIG. 6 is a fourth exemplary structural schematic diagram of a slot-like symmetrical pattern provided on a first interposer according to an embodiment of the present disclosure;

FIG. 7 is a fifth exemplary structural schematic diagram of a slot-like symmetrical pattern provided on a first interposer according to an embodiment of the present disclosure;

FIG. 8 is a sixth exemplary structural schematic diagram of a slot-like symmetrical pattern provided on a first interposer according to an embodiment of the present disclosure;

FIG. 9 is a seventh exemplary structural schematic diagram of a slot-like symmetrical pattern provided on a first interposer according to an embodiment of the present disclosure;

FIG. 10 is a schematic view of an eighth exemplary configuration of a slot-like symmetrical pattern provided on a first interposer according to an embodiment of the present disclosure;

FIG. 11 is a ninth exemplary architecture diagram of a slot-like symmetrical pattern provided on a first interposer according to an embodiment of the present disclosure;

FIG. 12 is a tenth exemplary structural schematic of a slot-like symmetrical pattern provided on a first interposer according to an embodiment of the present disclosure;

FIG. 13 is a schematic view of an eleventh exemplary configuration of a slot-like symmetrical pattern provided on a first interposer according to an embodiment of the present disclosure;

FIG. 14 is a twelfth exemplary architecture diagram of a slot-like symmetrical pattern provided on a first interposer according to an embodiment of the present disclosure;

fig. 15 is a schematic structural diagram of a heterobonding structure provided in embodiment 2 of the present disclosure;

FIG. 16 is a schematic view of an exemplary structure of a slot-like symmetrical pattern provided on a second interposer provided in embodiment 2 of the present disclosure;

fig. 17 is a schematic structural diagram of a heterobonding structure provided in embodiment 3 of the present disclosure;

Fig. 18 is a schematic structural diagram of a heterobonding structure provided in embodiment 4 of the present disclosure;

FIG. 19 is a schematic view of an exemplary structure of a slot-like symmetrical pattern provided on a first interposer provided in embodiment 4 of the present disclosure;

fig. 20 is a schematic structural diagram of a heterobonding structure provided in embodiment 5 of the present disclosure;

fig. 21 is a schematic structural diagram of a heterobonding structure provided in embodiment 6 of the present disclosure.

Reference numerals denote:

11. A first substrate; 12. a second substrate; 21. a first intercalation; 22. a second intercalation;

20. A slot-like symmetrical pattern; 201. a first symmetrical structure; 202. and a second symmetrical structure.

Detailed Description

In order to make the technical scheme and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in further detail below with reference to the accompanying drawings.

Heterobonding can integrate different kinds of semiconductor materials, for example, different chips, different wafers, or chips and wafers, and is widely used in the field of semiconductor manufacturing. With the continuous increase of the demands of integrated circuits for power, integration, etc., higher demands are being put on the bonding process and its effects.

However, for the common heterogeneous bonding processes such as a plasma activated bonding process, a wet activated bonding process, a BCB bonding process and the like, the interfaces of the heterogeneous bonding processes have larger stress, which comprises lattice stress and thermal stress, so that the interfaces are easy to have the problems of dislocation extension, migration and the like, and the reliability of the heterogeneous bonding structure is reduced.

Aiming at the technical problems in the related art, the embodiments of the present disclosure provide a heterobonding structure, as shown in fig. 1 and fig. 2, where the heterobonding structure includes: a first substrate 11, a second substrate 12, a first intercalation 21 formed on the first substrate 11, a second intercalation 22 formed on the second substrate 12; wherein the first and second interposers 21 and 22 are bonded, one of the first and second interposers 21 and 22 having a groove-like symmetrical pattern 20, the groove-like symmetrical pattern 20 being configured to relieve at least one of lattice stress and thermal stress.

According to the heterojunction structure provided by the embodiment of the disclosure, the groove-shaped symmetrical patterns 20 are arranged on the first intercalation 21 or the second intercalation 22, and the groove-shaped symmetrical patterns 20 comprise a plurality of symmetrical features which are periodically and repeatedly arranged, so that the groove-shaped symmetrical patterns 20 can relieve lattice mismatch and/or thermal mismatch between the first substrate 11 and the second substrate 12, strengthen release and balance of lattice stress and/or thermal stress, relieve lattice stress and/or thermal stress of an interface, avoid localization and long-term accumulation of the lattice stress and/or thermal stress, inhibit dislocation extension and migration of the interface, and improve reliability and stability of the heterojunction structure. In addition, the groove-shaped symmetrical patterns 20 are arranged on the first intercalation 21 or the second intercalation 22, so that volatile substances generated during bonding annealing can be effectively discharged, interface cavities are reduced, and bonding yield is effectively improved.

In the embodiment of the present disclosure, the mismatch condition between the first interposer 21 and the first substrate 11 is defined as having a first mismatch degree between the first interposer 21 and the first substrate 11, and the mismatch condition between the second interposer 22 and the second substrate 12 is defined as having a second mismatch degree between the second interposer 22 and the second substrate 12, and both the first mismatch degree and the second mismatch degree include: at least one of lattice mismatch degree and thermal expansion coefficient mismatch degree. When the first mismatch degree is greater than the second mismatch degree, the slot-shaped symmetrical pattern 20 is positioned on the first intercalation 21; when the second mismatch is greater than the first mismatch, the slot-like symmetrical pattern 20 is located in the second interposer 22; the slot-like symmetrical pattern 20 is located in one of the first 21 and second 22 interposers when the first degree of mismatch is equal to the second degree of mismatch.

When the mismatch conditions at two sides of the bonding interface are inconsistent, the groove-shaped symmetrical patterns 20 are arranged on an intercalation with larger lattice mismatch degree and/or thermal expansion coefficient mismatch degree between the groove-shaped symmetrical patterns and the corresponding substrate; the groove-like symmetrical pattern 20 may be provided in one of the first interposer 21 and the second interposer 22 when the mismatch conditions on both sides of the bonding interface are substantially identical.

In some examples, if lattice mismatch is not considered, the position and shape of the slot-like symmetrical pattern 20 need only be determined in accordance with the thermal mismatch condition.

In the presently disclosed embodiment, referring to fig. 13 or 14, the slot-like symmetrical pattern 20 has at least one of a first symmetrical structure 201 and a second symmetrical structure 202, the first symmetrical structure 201 corresponding to a lattice feature of a corresponding substrate to relieve lattice stress; the second symmetrical structure 202 corresponds to the thermal expansion characteristics of the respective substrate to relieve thermal stresses.

When the slot-like symmetrical pattern 20 includes both the first symmetrical structure 201 and the second symmetrical structure 202, the following two cases may be included: first, the first symmetrical structure 201 and the second symmetrical structure 202 may be identical and overlap, and at this time, the groove-shaped symmetrical pattern 20 may be considered to have both the first symmetrical structure 201 and the second symmetrical structure 202, and thus, the lattice stress and the thermal stress may be relieved at the same time. Second, the first symmetrical structure 201 and the second symmetrical structure 202 are different, and are arranged in a crossing manner so as to be communicated with each other, the first symmetrical structure 201 is used for relieving lattice stress, and the second symmetrical structure 202 is used for relieving thermal stress.

The "corresponding substrate" referred to above refers to the first substrate 11 for the first interposer 21, and the "corresponding substrate" referred to above refers to the second substrate 12 for the second interposer 22.

The above-mentioned "the first symmetrical structure 201 corresponds to the lattice feature of the corresponding substrate" may be considered that the first symmetrical structure 201 needs to be matched with the lattice structure of the corresponding substrate, and the first symmetrical structure 201 can perform stress regulation in a specific lattice direction in-plane, so as to alleviate the problem of lattice stress concentration caused by lattice mismatch.

The above-mentioned "the second symmetrical structure 202 corresponds to the thermal expansion characteristic of the corresponding substrate" may be considered that the second symmetrical structure 202 needs to be matched to the thermal expansion direction of the corresponding substrate, and further, if the corresponding substrate has thermal expansion in a plurality of directions, the second symmetrical structure 202 needs to be matched to the direction in which the thermal expansion coefficient of the corresponding substrate is larger. In this way, the second symmetrical structure 202 is capable of stress modulation in the thermal expansion direction, thereby alleviating the problem of thermal stress concentration due to thermal mismatch.

In some examples, where the respective substrate referred to above has a symmetrical lattice structure, the symmetry of the plurality of symmetrical features comprised by the first symmetrical structure 201 is consistent with the lattice structure symmetry of the respective substrate. The plurality of symmetrical features included in the first symmetrical structure 201 are periodically and repeatedly arranged, and the symmetrical features are all in a through groove shape, and the distribution direction of the plurality of symmetrical features is consistent with the lattice arrangement direction of the corresponding substrate.

Where the respective substrate referred to above is an amorphous structure, the first symmetric structure 201 may exhibit isotropy, e.g., for a first symmetric structure 201 exhibiting isotropy, this includes, but is not limited to, circular, annular, or other geometric shapes having isotropic characteristics.

In some examples, where the thermal expansion characteristics of the respective substrates referred to above are directional, the second symmetrical structure 202 includes a plurality of symmetrical features that are distributed in a direction that coincides with the thermal expansion direction of the respective substrates. The plurality of symmetrical features included in the second symmetrical structure 202 are periodically and repeatedly arranged, and the symmetrical features are all through grooves, if the substrate has thermal expansion in multiple directions, the distribution direction of the plurality of symmetrical features of the second symmetrical structure 202 is consistent with the direction with larger thermal expansion coefficient.

The second symmetrical structure 202 exhibits isotropy when the thermal expansion characteristics of the respective substrates referred to above are not directional. For example, for a second symmetrical structure 202 that exhibits isotropy, this includes, but is not limited to, a circle, a torus, or other geometric figure having isotropic characteristics.

In some examples, the pattern shape of the slot-like symmetric pattern 20 includes at least one of a one-dimensional grating shape, a multiple symmetric dot slot shape, a multiple symmetric slot shape, an isotropic geometry. That is, the pattern shape of the groove-like symmetrical pattern 20 may be a single one-dimensional grating shape, a plurality of symmetrical dot groove shapes, a plurality of symmetrical line groove shapes, or an isotropic geometric shape or different combinations thereof, or may be a combination of any two or three of a one-dimensional grating shape, a plurality of symmetrical dot groove shapes, a plurality of symmetrical line groove shapes, and an isotropic geometric shape, for example, combining an isotropic geometric shape with a plurality of symmetrical dot groove shapes or a plurality of symmetrical line groove shapes.

Wherein reference herein to "multiple symmetry" refers to the presence of symmetry in multiple directions, i.e., multiple directions, equal in number to the number of directions in which symmetry is present.

For example, fig. 3 and 4 respectively illustrate that the groove-like symmetrical pattern 20 provided on the first interposer 21 is a one-dimensional grating shape (wherein fig. 3 is the first interposer 21 in the form of a wafer, fig. 4 is the first interposer 21 in the form of a chip), fig. 5 illustrates that the groove-like symmetrical pattern 20 provided on the first interposer 21 is a twice symmetrical groove shape, fig. 6 illustrates that the groove-like symmetrical pattern 20 provided on the first interposer 21 is a four-time symmetrical dot groove shape, fig. 7 and 8 respectively illustrate that the groove-like symmetrical pattern 20 provided on the first interposer 21 is a four-time symmetrical groove shape (wherein fig. 7 is the first interposer 21 in the form of a chip, fig. 8 is the first interposer 21 in the form of a wafer), fig. 9 illustrates that the groove-like symmetrical pattern 20 provided on the first interposer 21 is a six-time symmetrical dot groove shape, fig. 10 illustrates that the groove-like symmetrical pattern 20 provided on the first interposer 21 is a six-time symmetrical groove shape, fig. 11 illustrates that the groove-like symmetrical pattern 20 provided on the first interposer 21 is a twelve-time symmetrical dot groove shape, fig. 12 illustrates that the groove-like symmetrical pattern 20 provided on the first interposer 21 is an isotropic concentric annular ring shape, fig. 13 illustrates that the groove-like symmetrical pattern 20 provided on the first interposer 21 is a combination of an isotropic concentric annular ring shape and a four-time symmetrical groove shape, and fig. 14 illustrates that the groove-like symmetrical pattern 20 provided on the first interposer 21 is a combination of one type of four-time symmetrical groove shape and another type of four-time symmetrical groove shape, wherein the one type of four-time symmetrical groove shape is a concentric rectangular annular groove, and the other type of four-time symmetrical groove shape is two straight groove shapes arranged perpendicularly to intersect.

In some examples, for the groove-like symmetrical pattern 20 disposed on the first interposer 21 or the second interposer 22, the first symmetrical structure 201 and the second symmetrical structure 202 thereon overlap (see fig. 6-11), that is, the groove-like symmetrical pattern 20 has both effects of relieving lattice stress and relieving thermal stress.

In some examples, for the groove-like symmetrical pattern 20 disposed on the first interposer 21 or the second interposer 22, the first symmetrical structure 201 and the second symmetrical structure 202 thereon are not coincident and different (see fig. 13-14), i.e., the first symmetrical structure 201 and the second symmetrical structure 202 serve to relieve lattice stress and relieve the effect of thermal stress, respectively.

For the side where the lattice mismatch and thermal mismatch between the substrate and the intercalation are larger, only the lattice structures of the a-axis and b-axis crystal directions (in-plane) of the substrate are considered, the first symmetrical structure 201 of the groove-like symmetrical pattern 20 may be designed to satisfy that the symmetry axis of the first symmetrical structure 201 coincides with the a-axis or b-axis crystal direction.

For example, if the crystal lattice of the substrate is a tetragonal crystal lattice, the first symmetrical structure 201 of the groove-like symmetrical pattern 20 may be designed as a point groove shape of a quartic symmetry or a groove shape of a quartic symmetry, and the symmetry axis of the first symmetrical structure 201 coincides with the a-axis or b-axis crystal direction.

If the crystal lattice of the substrate is a hexagonal crystal lattice, the first symmetrical structure 201 of the groove-like symmetrical pattern 20 may be designed as a dot groove shape of six-order symmetry or a groove shape of six-order symmetry, and the symmetry axis of the first symmetrical structure 201 coincides with the a-axis or b-axis crystal direction.

If the lattice of the substrate is orthorhombic, the thermal mismatch may be directly considered without considering the lattice mismatch.

For the side with larger lattice mismatch and thermal mismatch between the substrate and the intercalation layer, if the specific crystal orientation thermal expansion coefficient of the substrate is far higher than that of other crystal orientations, the plurality of symmetrical features included in the second symmetrical structure 202 can be periodically arranged in the plane, and the distribution direction of the plurality of symmetrical features is consistent with the direction with larger thermal expansion coefficient, for example, the second symmetrical structure 202 is a one-dimensional grating structure, so as to reduce thermal stress accumulation.

In the embodiment of the present disclosure, the thicknesses of the first intercalation layer 21 and the second intercalation layer 22 may be the same or different. In some examples, the thickness of each of the first and second intercalating layers 21, 22 ranges from 2nm to 1000nm, such as 10nm, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1000nm, etc.

The thicknesses of the first intercalation layer 21 and the second intercalation layer 22 are designed to be thinner, so that the first intercalation layer 21 and the second intercalation layer 22 are easier to deposit into films, and the influence on the performance of the first substrate 11 and the second substrate 12 is further reduced, and thus, the integration of heterogeneous materials with high strength, low thermal resistance and low stress can be realized by using the thinner intercalation layers.

In some examples, the ratio of the area of the slot-like symmetric pattern 20 to the area of the intervening layer is 5% -80%, that is, the duty cycle of the slot-like symmetric pattern 20 is 5% -80%, including, for example, but not limited to: 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, 80%, etc.

The duty ratio of the groove-shaped symmetrical patterns 20 in the intercalation is determined according to the lattice mismatch and/or thermal expansion mismatch between the first substrate 11 and the second substrate 12, when the mismatch degree is larger, the duty ratio of the groove-shaped symmetrical patterns 20 is correspondingly increased, otherwise, when the mismatch degree is smaller, the duty ratio of the groove-shaped symmetrical patterns 20 is correspondingly reduced, so that the effect of effectively relieving lattice stress and/or thermal stress is achieved.

The slot-like symmetrical pattern 20 includes a plurality of through slots arranged periodically, the through slots penetrating through the interposer where they are located, one end of each through slot extending to another interposer, and the other end of each through slot extending to the substrate corresponding to the current interposer.

The through grooves can be linear grooves or dot grooves. In some examples, the width of the line grooves is 20nm-20 μm and the diameter of the dot grooves is 20nm-20 μm, including, for example, but not limited to ：50nm、100nm、500nm、1000nm、2000nm、5000nm、7000nm、9000nm、10000nm、11000nm、12000nm、15000nm、18000nm、20000nm, etc.

When the duty ratio of the groove-like symmetrical pattern 20 is relatively large, it can be understood that the width or diameter of the through groove is correspondingly increased, and when the duty ratio of the groove-like symmetrical pattern 20 is relatively small, it can be understood that the width or diameter of the through groove is correspondingly reduced.

In some examples, the first substrate 11 and the second substrate 12 may each be in wafer form or chip form, e.g., the first substrate 11 is a wafer and the second substrate 12 is a chip; the first substrate 11 is a chip and the second substrate 12 is a wafer; the first substrate 11 and the second substrate 12 are both wafers; the first substrate 11 and the second substrate 12 are both chips.

Some suitable materials for the first substrate 11 and the second substrate 12 include, but are not limited to: silicon carbide (SiC), silicon (Si), silicon oxide (SiO or SiO ₂), indium phosphide (InP), gallium arsenide (GaAs), gallium phosphide (GaP), gallium nitride (GaN), aluminum nitride (AlN), and the like.

For example, the first substrate 11 is indium phosphide and the second substrate 12 is silicon carbide; or the first substrate 11 is silicon and the second substrate 12 is indium phosphide; or the first substrate 11 is silicon and the second substrate 12 is gallium nitride.

In the embodiment of the disclosure, the first interposer 21 and the second interposer 22 are made of the same material, so as to ensure that the bonding strength of the bonding interface is sufficiently high and avoid bonding defects as much as possible. Suitable materials for the first substrate 11 and the second substrate 12 of the above types, some suitable materials for the first intercalation layer 21 and the second intercalation layer 22 include, but are not limited to, silicon dioxide (SiO ₂), silicon nitride (SiC), silicon (Si), or aluminum oxide (Al ₂O₃).

The materials of the first interposer 21 and the second interposer 22 may be selected according to practical application scenarios, for example, for photoelectric heterogeneous integration, it is desirable that the interposers have optical windows corresponding to the substrate, such as SiO ₂ or Si ₃N₄, which can be used as interposers to obtain extremely low insertion loss; for heterogeneous integration of ultra-high thermal conductivity packages, it is desirable that the intercalation has a relatively high thermal conductivity to achieve smooth bonding, e.g., siC may be used as intercalation in this case; for vertical structure hetero-integration, it is desirable that the integrated structure has good conductivity, for example Si may act as an intercalation in this case.

Furthermore, the material of the intercalation can be determined according to the adhesiveness, wettability, stability and other factors of the intercalation on the surface of the substrate, so as to obtain good bonding effect.

As can be seen from the above, when the first substrate 11 and the second substrate 12 made of different materials are faced, due to lattice mismatch and/or thermal mismatch between the first substrate 11 and the second substrate 12, the embodiment of the disclosure sets the groove-shaped symmetrical pattern 20 on the first interposer 21 or the second interposer 22, so that lattice stress and/or thermal stress are conducted to the first interposer 21 and the second interposer 22, and the groove-shaped symmetrical pattern 20 is utilized to release the lattice stress and/or thermal stress, thereby improving bonding power and bonding yield, and improving reliability, structural stability and service life of the hetero-bonding structure.

Only one of the intercalation layers on the side with larger lattice mismatch and thermal mismatch is subjected to graphical design, and on the premise of ensuring that lattice stress and/or thermal stress are effectively relieved, the first intercalation layer 21 and the second intercalation layer 22 can be firmly bonded, so that the reliability and the structural stability of the hetero-bonding structure are enhanced. If the first interposer 21 and the second interposer 22 are patterned, it is extremely difficult to achieve alignment by considering whether the patterns of both are completely aligned, and if not, the adhesion strength is lowered.

The heterogeneous bonding structure provided by the embodiment of the disclosure can be applied to various scenes, some common application scenes are wafer heterogeneous integration, photoelectric device heterogeneous integration and the like, and further, the heterogeneous bonding structure provided by the embodiment of the disclosure can also be used for scenes such as bonding a III-V light source with a SiC wafer, bonding a III-V light source or a modulator with a silicon-based wafer, bonding a lithium niobate modulator with a silicon-based passive structure or a III-V device and the like, so that high-density integration of different materials is realized, and efficient geothermal management is realized.

On the other hand, the embodiment of the disclosure also provides a preparation method of the heterojunction bonding structure, wherein the heterojunction bonding structure is as described in any one of the above.

The preparation method of the hetero-bonding structure comprises the following steps:

step S1, forming a first intercalation on a first substrate, and forming a second intercalation on a second substrate.

And S2, preparing a groove-shaped symmetrical pattern on one of the first intercalation and the second intercalation according to the first mismatch degree between the first substrate and the first intercalation and the second mismatch degree between the second substrate and the second intercalation, wherein the groove-shaped symmetrical pattern is configured for relieving at least one of lattice stress and thermal stress.

And step S3, bonding the first intercalation and the second intercalation to obtain a heterogeneous bonding structure.

When preparing the hetero-bonding structure, the first mismatch degree and the second mismatch degree need to be confirmed, and when the first mismatch degree is larger than the second mismatch degree, a groove-shaped symmetrical pattern is prepared on the first intercalation; when the first mismatch degree is smaller than the second mismatch degree, preparing a groove-shaped symmetrical graph on the second intercalation; a groove-like symmetrical pattern is optionally prepared on one of the first intercalation and the second intercalation when the first degree of mismatch is the same or substantially identical to the second degree of mismatch.

For step S1, a first intercalation layer may be formed on a first substrate and a second intercalation layer may be formed on a second substrate by a deposition process or a sputtering process.

The deposition process or the sputtering process can smoothly form the intercalation on the substrate and obtain an accurate intercalation thickness. For example, for CMOS (Complementary Metal-oxide-semiconductor), deposition processes such as low pressure chemical Vapor Deposition (LPCVD, low Pressure Chemical Vapor Deposition), plasma enhanced chemical Vapor Deposition (PECVD, plasma Enhanced Chemical Vapor Deposition), atomic layer epitaxy (ALD, atomic Layer Deposition), or ion beam sputtering processes or plasma sputtering processes may be adaptively selected according to the intercalation material and specific bonding requirements.

For the intercalation formed by the deposition process or the sputtering process, if the surface of the intercalation has bonding risk points such as roughness, coulomb surface state and the like, the surface risk points can be treated by means of passivation, annealing and the like, so that the intercalation obtains a flat and smooth surface.

Further, the first substrate and the second substrate may also be surface treated prior to preparing the first intercalation on the first substrate and prior to preparing the second intercalation on the second substrate, including but not limited to at least one of:

(1) Depending on the surface roughness of the first and second substrates, polishing is selectively performed so that the surfaces of the substrates are smooth, and the polishing may be mechanical polishing or chemical polishing, for example, mechanical polishing may be wheel polishing, and the chemical polishing may be performed based on a polishing liquid, which may be ordinary DI water (deionized water).

(2) And cleaning the surfaces of the first substrate and the second substrate to remove surface impurities of the substrates.

(3) The surfaces of the first substrate and the second substrate are subjected to an activation treatment, which may be, for example, a plasma surface treatment, so as to improve the bonding strength between the substrates and the intercalation.

For step S2, a groove-like symmetrical pattern may be prepared by a photolithography process in combination with an etching process. For example, a groove-shaped symmetrical pattern is obtained by etching through photoetching and/or wet-dry etching processes suitable for CMOS processes, so that the interface lattice mismatch and/or thermal mismatch problems of the hetero-bonding structure are effectively relieved, lattice stress and/or thermal stress are inhibited, and bonding power and bonding yield are further improved.

For step S3, bonding the first interposer and the second interposer includes: carrying out surface treatment on the first intercalation and the second intercalation; attaching the treatment surface of the first intercalation to the treatment surface of the second intercalation and pre-bonding to obtain an intermediate material; and annealing the intermediate material.

The first intercalation and the second intercalation are subjected to surface treatment, pre-bonding and annealing in sequence, so that direct bonding between the first intercalation and the second intercalation is realized, and an excellent bonding effect is obtained.

In some examples, surface treating the first intercalation and the second intercalation includes: and carrying out surface polishing, surface cleaning and surface activation on the first intercalation and the second intercalation in sequence.

The surface polishing may be mechanical polishing or chemical polishing, for example, mechanical polishing may be grinding wheel polishing, and chemical polishing may be performed based on a polishing liquid, which may be common DI water (deionized water), so that the surface of the intercalation is completely smooth. For example, the surface of the intercalation is rinsed with DI water for 20 seconds to 5 minutes.

The surface cleaning may be performed by using ultrasonic water or a solvent to remove impurities from the surface of the intercalation, for example, a suitable solvent may be a dilute hydrochloric acid solution, an ethanol solution, an acetone solution, a polishing solution, etc., wherein the polishing solution includes but is not limited to DI water, SPM (sulfuric acid/hydrogen peroxide) solution, which has a high cleaning efficiency for organic impurities.

For example, embodiments of the present disclosure may clean the surface of the intercalation layer according to the following cleaning steps: DI water rinse 5 min-acetone rinse 20 min-DI water rinse 5 min-ethanol rinse 20 min-DI water rinse 5 min.

In the embodiment of the disclosure, the surface of the intercalation after surface cleaning is subjected to surface activation, and processes such as hydrophilic activation, hydrophobic activation, wet activation, dry activation and the like can be adopted.

For hydrophilic activation, it is possible to achieve bonding at lower temperatures, but with lower strength. For hydrophobic activation, higher bonding strength can be obtained, but the activation temperature is more than or equal to 600 ℃, and the hydrophobic activation can not be used for bonding epitaxial wafers with device structures, chips and the like. Therefore, whether hydrophilic activation or hydrophobic activation is selected at the time of intercalation activation may be determined according to the high temperature resistant characteristics of the substrate and intercalation, the operating scene of the hetero-integrated structure, and the like.

For wet activation, which can be used for both hydrophilic and hydrophobic activation pathways, the activation solution for wet activation may be selected according to the characteristics of the substrate and intercalation, for example, some common activation solutions include, but are not limited to: HF solution, SPM (sulfuric acid/hydrogen peroxide) solution, APM solution (including ammonium hydroxide, hydrogen peroxide and water), HPM solution (including hydrochloric acid, hydrogen peroxide and water).

For example, wet activation techniques that may be employed by embodiments of the present disclosure may be RCA solution activation or HF solution activation, wherein RCA solution activation may include APM solution activation and HPM solution activation performed sequentially, and the activation time of RCA solution activation may be 2 minutes to 30 minutes.

For dry activation, which includes but is not limited to plasma activation, good activation effect is obtained by adjusting parameters such as the type of plasma, radio frequency power, bombardment time and the like.

As mentioned above, the intermediate material is obtained by bonding and pre-bonding the treated surface of the first intercalation with the treated surface of the second intercalation.

For the pre-bonding process, the bonding pressure may be 10N-200N, for example, 10N, 20N, 50N, 70N, 90N, 100N, 110N, 120N, 130N, 140N, 150N, 160N, 170N, 180N, 190N, 200N, etc.

The bonding temperature is 150-300 ℃, for example 150 ℃, 160 ℃, 170 ℃, 180 ℃, 190 ℃, 200 ℃, 210 ℃, 220 ℃, 230 ℃, 240 ℃, 250 ℃, 260 ℃, 270 ℃, 280 ℃, 290 ℃, 300 ℃, etc.

The bonding pressure and bonding temperature are determined according to the bonding effect, and for example, the bonding pressure and bonding temperature are selected to obtain strong bonding energy between layers, so that the layers are reliably adhered, and the layers are not damaged due to compression.

In the embodiment of the disclosure, the intermediate material can be annealed in an inert atmosphere such as air, argon or nitrogen, so as to improve the internal stress phenomenon of the bonding interface.

In order to improve the annealing effect, the annealing temperature is 175-950 ℃, for example 200 ℃, 300 ℃, 400 ℃, 500 ℃, 600 ℃, 700 ℃, 800 ℃, 900 ℃, and the like. The annealing treatment time is 15 minutes to 50 hours, further 30 minutes to 20 hours, for example, 5 hours, 10 hours, 15 hours, 20 hours, and the like.

As can be seen from the above, the preparation method of the heterojunction bonding structure according to the embodiment of the present disclosure has the advantages of easy operation of the technical route and low manufacturing cost, so that the heterojunction bonding structure has stronger manufacturability, and the preparation method also has the advantages of strong applicability, high compatibility with the existing manufacturing process, and the like, thereby facilitating large-scale mass production of the heterojunction bonding structure.

The electronic device provided by the embodiment of the disclosure has all the advantages of the heterojunction structure provided by the embodiment of the disclosure.

The present disclosure will be further described by way of more specific examples, although a few specific implementations are described below, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the examples set forth herein. The specific techniques or conditions not identified in the examples, the techniques or conditions described in the literature in this field or the instructions for the product, and the reagents or apparatus used, not identified to the manufacturer, may be conventional products available commercially.

On the one hand, regarding the hetero-bonding structures according to the following embodiments 1 to 6, there is no excessive attention to the materials of the first substrate, the second substrate, the first interposer and the second interposer, and there is more attention to the structure of the groove-like symmetrical pattern provided on the first interposer or the second interposer, and how the groove-like symmetrical pattern achieves relief, even elimination, of lattice stress and/or thermal stress of the hetero-bonding structure.

For example, in embodiments 1 to 6, the first substrate and the second substrate are made of different materials, and both may be selected from silicon carbide, silicon oxide, indium phosphide, gallium arsenide, gallium phosphide, gallium nitride, or aluminum nitride. The first intercalation and the second intercalation are the same material, and can be selected from silicon dioxide, silicon nitride, silicon or silicon carbide.

And, the integrated form of the first substrate and the second substrate may be any of the following integrated forms: the chip is integrated with the chip, the wafer is integrated with the wafer, the chip is integrated with the wafer, and the wafer is integrated with the chip.

The thickness of the first intercalation and the second intercalation can be selected between 10nm and 1000nm, and the thickness can be selected according to the specific materials of the intercalation and the substrate and the actual application scene of the heterogeneous bonding structure.

The area duty ratio of the groove-shaped symmetrical patterns in the intercalation can be selected between 5% and 80%, and the area duty ratio is selected according to specific lattice mismatch and/or thermal expansion mismatch conditions between the first substrate and the second substrate.

The width of the linear through grooves included in the groove-shaped symmetrical patterns or the diameter of the dot-shaped through grooves can be selected between 20nm and 20 mu m, and the width or the diameter of the dot-shaped through grooves can be selected according to specific lattice mismatch and/or thermal expansion mismatch conditions between the first substrate and the second substrate.

On the other hand, for the hetero-bonding structures of the following examples 1 to 6, the preparation method thereof may employ a general preparation scheme, which includes: step 1, forming a first intercalation on a first substrate, and forming a second intercalation on a second substrate. And 2, preparing a groove-shaped symmetrical pattern on one of the first intercalation and the second intercalation according to the first mismatch degree between the first substrate and the first intercalation and the second mismatch degree between the second substrate and the second intercalation. And step 3, bonding the first intercalation and the second intercalation to obtain a heterogeneous bonding structure. This includes: sequentially performing surface polishing, surface cleaning and surface activation on the first intercalation and the second intercalation; attaching the treatment surface of the first intercalation to the treatment surface of the second intercalation and pre-bonding to obtain an intermediate material; and annealing the intermediate material to obtain the hetero-bonding structure.

The hetero-bonding structures according to examples 1-6 may be different from each other in the preparation process by specific preparation parameters, and the specific preparation parameters may be adaptively determined according to the composition of the specific hetero-bonding structure, and are illustrated below:

For the step 1, low-pressure chemical vapor deposition, plasma enhanced chemical vapor deposition or atomic layer epitaxy can be adopted to form corresponding intercalation on a specific substrate, and the intercalation is selected according to actual requirements.

For step 2, a standard photolithography process suitable for CMOS processes may be used in combination with a wet and dry etching process to form a trench-like symmetrical pattern on the interposer. The specific lithographic and etch parameters may be determined based on the configuration of the specific slot-like symmetry pattern.

For step 3, the surface polishing may be performed by washing the surface of the intercalation with Dl water for 20 seconds to 5 minutes, the specific washing time being selected according to the specific roughness of the surface of the intercalation. The surface cleaning may be as follows: DI water rinse 5 min-acetone rinse 20 min-DI water rinse 5 min-ethanol rinse 20 min-DI water rinse 5 min. The surface activation can be RCA solution activation, which comprises APM solution activation and HPM solution activation which are sequentially carried out, the specific activation time can be 2 minutes to 30 minutes, and each embodiment can be selected according to the specific material of the intercalation.

For the pre-bonding process, the bonding pressure is selected within the range of 10N-200N, the annealing temperature is selected within the range of 175-950 ℃, and each embodiment is selected according to the specific material of the intercalation.

For the annealing treatment, the annealing temperature is 175-950 ℃ and the annealing time is 30 minutes-20 hours, and each embodiment is selected according to the specific material of the intercalation.

Example 1

Embodiment 1 provides a heterobonding structure, see fig. 1, comprising a first substrate 11, a first interposer 21, a second interposer 22, and a second substrate 12 stacked in this order. Wherein the first intercalation layer 21 and the second intercalation layer 22 are combined by bonding, and the first intercalation layer 21 has a groove-shaped symmetrical pattern 20.

The first substrate 11 and the second substrate 12 are both tetragonal lattice structures, and since the lattice mismatch degree and the thermal mismatch degree of the first substrate 11 and the first interlayer 21 are both larger than those of the second substrate 12 and the second interlayer 22, the groove-shaped symmetrical pattern 20 is provided on the first interlayer 21, and the second interlayer 22 is a smooth and uniform film shape.

Referring to fig. 7 or 8, the slot-like symmetrical pattern 20 is a four-time symmetrical slot structure. The first interposer 21 shown in fig. 7 corresponds to the first substrate 11 in the form of a chip, and the second interposer 22 shown in fig. 8 corresponds to the first substrate 11 in the form of a wafer. The structure of the groove-like symmetrical pattern 20 provided on the first interposer 21 will be described with reference to fig. 7, which includes a plurality of line-type through grooves perpendicularly intersecting each other, the plurality of line-type through grooves forming an orthogonal grid, thereby dividing the first interposer 21 into a plurality of square-shaped interposer columns spaced apart from each other. Thus, the groove-like symmetrical pattern 20 exhibits four-time symmetry as a whole, that is, can exhibit symmetry in four directions.

In the groove-shaped symmetrical pattern 20, the first symmetrical structure 201 and the second symmetrical structure 202 are identical and coincide, and are all the four-time symmetrical groove structures, so that the four-time symmetrical groove structures simultaneously correspond to lattice mismatch and thermal mismatch, and the purpose of simultaneously relieving lattice stress and thermal stress is achieved.

The groove-shaped symmetrical pattern 20 arranged on the first intercalation 21 is confirmed to be capable of effectively improving lattice mismatch and thermal mismatch existing between the first substrate 11 and the second substrate 12 with tetragonal lattice structures, so that interface stress is effectively relieved, dislocation extension and migration are inhibited, and particularly the stress relieving effect on the first substrate 11 is more obvious.

Example 2

Embodiment 2 provides a heterobonding structure, see fig. 15, comprising a first substrate 11, a first interposer 21, a second interposer 22, and a second substrate 12 stacked in this order. Wherein the first intercalation layer 21 and the second intercalation layer 22 are bonded, and the second intercalation layer 22 has a groove-like symmetrical pattern 20.

The first substrate 11 and the second substrate 12 are both amorphous structures (i.e., the lattice features have no symmetry and the thermal expansion features have no directionality), and the lattice and thermal mismatch of the second substrate 12 and the second interposer 22 is greater than the lattice and thermal mismatch of the first substrate 11 and the first interposer 21. Therefore, the groove-like symmetrical pattern 20 is provided on the second interlayer 22, and the first interlayer 21 has a smooth and uniform film shape.

Referring to fig. 16, the slot-like symmetrical pattern 20 exhibits an isotropic concentric annular structure including a plurality of annular through slots concentrically arranged to divide the second intercalation 22 into a plurality of spaced-apart annular intercalation columns.

In the groove-shaped symmetrical pattern 20, the first symmetrical structure 201 and the second symmetrical structure 202 are identical and coincide, and are concentric ring structures, so that the concentric ring structures simultaneously correspond to lattice mismatch and thermal mismatch, and the purpose of simultaneously relieving lattice stress and thermal stress is achieved.

The groove-shaped symmetrical pattern 20 arranged on the second intercalation 22 is confirmed to be capable of effectively improving lattice mismatch and thermal mismatch existing between the first substrate 11 and the second substrate 12 with amorphous structures, so that interface stress is effectively relieved, dislocation extension and migration are inhibited, and particularly the stress relieving effect on the second substrate 12 is more obvious.

Example 3

Embodiment 3 provides a heterobonding structure, see fig. 17, comprising a first substrate 11, a first interposer 21, a second interposer 22, and a second substrate 12 stacked in this order. Wherein the first intercalation layer 21 and the second intercalation layer 22 are combined by bonding, and the first intercalation layer 21 has a groove-shaped symmetrical pattern 20.

The first substrate 11 is an amorphous structure, the second substrate 12 is a tetragonal lattice structure, and the lattice mismatch degree and the thermal mismatch degree of the first substrate 11 and the first intercalation 21 are larger than those of the second substrate 12 and the second intercalation 22. Therefore, the first interlayer 21 is provided with the groove-like symmetrical pattern 20, and the second interlayer 22 is formed in a smooth and uniform film shape.

Referring to fig. 13, the slot-like symmetrical pattern 20 is a combination of a four-time symmetrical slot structure and an isotropic concentric ring structure, wherein the four-time symmetrical slot structure includes four linear through slots, exhibiting four-time symmetry; the concentric ring structure comprises a plurality of concentrically arranged ring-shaped through grooves, and is isotropic. The four linear through grooves are symmetrically arranged, the included angle between any two adjacent through grooves is 90 degrees, and each linear through groove simultaneously penetrates through all the circular through grooves so as to divide the concentric circular structure into four equal parts in an orthogonal mode.

In the groove-like symmetrical pattern 20, an isotropic concentric ring structure is used as a first symmetrical structure 201 to mitigate lattice mismatch, and a four-time symmetrical groove structure is used as a second symmetrical structure 202 to mitigate thermal mismatch.

The groove-shaped symmetrical pattern 20 provided on the first interlayer 21 is confirmed to be capable of effectively improving lattice mismatch and thermal mismatch existing between the first substrate 11 with an amorphous structure and the second substrate 12 with a tetragonal lattice structure, effectively relieving interface stress, inhibiting dislocation extension and migration, and particularly has a more obvious effect of relieving stress on the first substrate 11.

Example 4

Embodiment 4 provides a heterobonding structure, see fig. 18, comprising a first substrate 11, a first interposer 21, a second interposer 22, and a second substrate 12 stacked in this order. Wherein the first intercalation layer 21 and the second intercalation layer 22 are combined by bonding, and the first intercalation layer 21 has a groove-shaped symmetrical pattern 20.

The first substrate 11 has a hexagonal lattice structure, the second substrate 12 has a tetragonal lattice structure, and the lattice mismatch degree and the thermal mismatch degree of the first substrate 11 and the first intercalation 21 are larger than those of the second substrate 12 and the second intercalation 22. Therefore, the first interlayer 21 is provided with the groove-like symmetrical pattern 20, and the second interlayer 22 is formed in a smooth and uniform film shape.

Referring to fig. 19, the slot-like symmetrical pattern 20 presents a six-time symmetrical slot structure, which includes a plurality of regular hexagonal annular through slots, each of which surrounds one of the intercalation columns, so that the slot-like symmetrical pattern 20 presents six-time symmetry as a whole.

In the groove-shaped symmetrical pattern 20, the first symmetrical structure 201 and the second symmetrical structure 202 are identical and coincide, and are all six-time symmetrical groove structures, so that the six-time symmetrical groove structures simultaneously relieve lattice mismatch and thermal mismatch.

It was confirmed that, in the case where the first substrate 11 is a hexagonal lattice structure and the second substrate 12 is a tetragonal lattice structure, lattice characteristics of both have periodicity and the thermal expansion coefficient has directionality. Therefore, the slot structure with six symmetrical slot patterns is arranged on the first intercalation 21 as the slot-shaped symmetrical pattern 20, so that the lattice mismatch and thermal mismatch problems existing between the first substrate 11 and the second substrate 12 are effectively improved, the interface stress is effectively relieved, dislocation extension and migration are inhibited, and the stress relieving effect of the first substrate 11 is more obvious.

Example 5

Embodiment 5 provides a heterobonding structure, see fig. 20, comprising a first substrate 11, a first interposer 21, a second interposer 22, and a second substrate 12 stacked in this order. Wherein the first intercalation layer 21 and the second intercalation layer 22 are combined by bonding, and the first intercalation layer 21 has a groove-shaped symmetrical pattern 20.

The first substrate 11 has an orthorhombic lattice structure, the second substrate 12 has a hexagonal lattice structure, and the lattice mismatch degree and the thermal mismatch degree of the first substrate 11 and the first intercalation 21 are larger than those of the second substrate 12 and the second intercalation 22. Therefore, the first interlayer 21 is provided with the groove-like symmetrical pattern 20, and the second interlayer 22 is formed in a smooth and uniform film shape.

Referring to fig. 4, the groove-shaped symmetrical pattern 20 presents a one-dimensional grating structure, which includes a plurality of equally-wide linear through grooves distributed at equal intervals along the a direction, and the linear through grooves and the intercalation columns are alternately distributed in sequence.

Since lattice mismatch is not considered, the groove-shaped symmetrical pattern 20 does not have the first symmetrical structure 201, and the groove-shaped symmetrical pattern 20, that is, the one-dimensional grating structure is used as the second symmetrical structure 202, so as to alleviate thermal mismatch, and the distribution direction of the plurality of linear through grooves in the one-dimensional grating structure is consistent with the thermal expansion direction a.

It was confirmed that, in the case where the first substrate 11 is of an orthorhombic lattice structure and the second substrate 12 is of a hexagonal lattice structure, the thermal expansion coefficient has directionality irrespective of the lattice mismatch problem, and therefore, the one-dimensional grating structure is provided as the groove-like symmetrical pattern 20 on the first interlayer 21, which can effectively improve the thermal mismatch problem existing between the first substrate 11 and the second substrate 12, effectively relieve the interface stress, and suppress dislocation extension and migration, and particularly, the stress relieving effect on the first substrate 11 is more remarkable.

Example 6

Embodiment 6 provides a heterobonding structure, see fig. 21, comprising a first substrate 11, a first interposer 21, a second interposer 22, and a second substrate 12 stacked in this order. Wherein the first intercalation layer 21 and the second intercalation layer 22 are combined by bonding, and the first intercalation layer 21 has a groove-shaped symmetrical pattern 20.

The first substrate 11 is in an orthogonal lattice structure, the second substrate 12 is in an amorphous structure, the lattice mismatch degree and the thermal mismatch degree of the first substrate 11 and the first intercalation 21, and the lattice mismatch degree and the thermal mismatch degree of the second substrate 12 and the second intercalation 22 are relatively large and are basically flat, an included angle between the thermal mismatch directions of the first substrate 11 and the second substrate 12 is 45 degrees, a groove-shaped symmetrical pattern 20 is arranged on the first intercalation 21, and the second intercalation 22 is in a smooth and uniform film shape.

Referring to fig. 14, the slot-like symmetrical pattern 20 is shown as two four symmetrical slot structures having 45 ° included angles, wherein the first four symmetrical slot structure includes a plurality of rectangular annular through slots arranged concentrically, the second four symmetrical slot structure includes two perpendicular linear through slots, one linear through slot simultaneously penetrates the plurality of rectangular annular through slots along one diagonal direction, and the other linear through slot simultaneously penetrates the plurality of rectangular annular through slots along the other diagonal direction, so that the slot-like symmetrical pattern 20 is shown as four times symmetrical as a whole.

The first symmetrical structure 201 in the groove-shaped symmetrical pattern 20 is a four-time symmetrical wire groove structure formed by concentric rectangular ring structures, the second symmetrical structure 202 is a four-time symmetrical wire groove structure formed by two perpendicular linear through grooves, and an included angle between the first symmetrical structure 201 and the second symmetrical structure 202 is 45 degrees so as to respectively relieve lattice mismatch and thermal mismatch.

It is confirmed that, when the first substrate 11 is of an orthogonal lattice structure and the second substrate 12 is of an amorphous structure and the thermal expansion directions of the two structures form a certain included angle, by providing two four symmetrical slot structures forming a 45 ° included angle on the first interposer 21 as the slot-like symmetrical pattern 20, the lattice mismatch and thermal mismatch problems existing between the first substrate 11 and the second substrate 12 can be effectively improved, interface stress can be effectively relieved, dislocation extension and migration can be suppressed, and particularly, the stress relieving effect on the first substrate 11 is more obvious.

As can be seen from the foregoing, the heterojunction bonding structure and the preparation method thereof provided in the embodiments of the present disclosure, with respect to the problem of excessive residual stress and thermal stress of the heterojunction bonding interface in the related art, design a slot-like symmetrical pattern by using the patterned intercalation, so as to effectively relax and regulate lattice mismatch and thermal expansion coefficient mismatch between substrates, which not only can significantly reduce stress concentration problem of the bonding interface, but also uses a thinner intercalation as a hinge to realize a push-pull structure with stress strain at two sides, thereby effectively isolating transmission of dislocation at the bonding interface, and significantly improving bonding strength and stability (e.g., high temperature tolerance) of heterojunction bonding.

The term "and/or" in the embodiments of the present disclosure is merely an association relationship describing an association object, and indicates that three relationships may exist, for example, a and/or B may indicate: a exists alone, A and B exist together, and B exists alone.

The foregoing is merely for facilitating understanding of the technical solutions of the present disclosure by those skilled in the art, and is not intended to limit the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A heterobonding structure, the heterobonding structure comprising: a first substrate, a second substrate, a first intercalation formed on the first substrate, a second intercalation formed on the second substrate;

2. The heterobonding structure of claim 1, wherein a first degree of mismatch is present between the first interposer and the first substrate, and a second degree of mismatch is present between the second interposer and the second substrate, the first degree of mismatch and the second degree of mismatch each comprising: at least one of lattice mismatch degree and thermal expansion coefficient mismatch degree;

3. The heterobonding structure of claim 1, wherein the slot-like symmetric pattern has at least one of a first symmetric structure and a second symmetric structure;

4. The heterobonding structure of claim 3, wherein when the respective substrate has a symmetric lattice structure, the symmetry of the plurality of symmetric features included in the first symmetric structure is consistent with the lattice structure symmetry of the respective substrate;

When the respective substrate is an amorphous structure, the first symmetrical structure exhibits isotropy.

5. The heterobonding structure of claim 3, wherein the second symmetric structure comprises a plurality of symmetric features having a distribution direction that coincides with a thermal expansion direction of the respective substrate when the thermal expansion feature of the respective substrate has directionality;

The second symmetrical structure exhibits isotropy when the thermal expansion characteristics of the respective substrate are not directional.

6. The heterobonding structure of claim 3, wherein the pattern shape of the slot-like symmetric pattern comprises at least one of a one-dimensional grating shape, a multi-symmetric dot slot shape, a multi-symmetric slot shape, an isotropic geometry.

7. The heterobonding structure of any one of claims 1-6, wherein the ratio of the area of the slot-like symmetric pattern to the area of the intervening layer is 5% -80%.

8. The heterobonding structure of any one of claims 1-7, wherein the first and second substrates are each selected from silicon carbide, silicon oxide, indium phosphide, gallium arsenide, gallium phosphide, gallium nitride, or aluminum nitride.

9. The heterobonding structure of claim 8, wherein the first and second intercalation materials are the same and are selected from silicon dioxide, silicon nitride, silicon carbide, or aluminum oxide.

10. A method for preparing a heterobonding structure according to any one of claims 1 to 9, comprising:

11. The method of manufacturing a heterobonded structure according to claim 10, wherein the first intercalation is formed on the first substrate and the second intercalation is formed on the second substrate by a deposition process or a sputtering process.

12. The method of fabricating a heterobonded structure according to claim 10, wherein the trench-like symmetric pattern is fabricated by a photolithographic process in combination with an etching process.

13. The method for preparing a heterobonding structure according to claim 10, wherein the bonding the first intercalation and the second intercalation to obtain the heterobonding structure comprises:

14. The method of preparing a heterobonding structure according to claim 13, wherein the surface treating the first and second intercalation layers comprises: and carrying out surface polishing, surface cleaning and surface activation on the first intercalation and the second intercalation in sequence.

15. The method of preparing a heterobonded structure according to claim 13, wherein the bonding pressure of the pre-bonding is 10N-200N and the bonding temperature is 150 ℃ -300 ℃.

16. The method of claim 13, wherein the annealing is performed at a temperature of 175 ℃ to 950 ℃ for a time of 15 minutes to 50 hours.

17. An electronic device comprising the heterobonding structure of any one of claims 1-9.