CN117995554A

CN117995554A - Ceramic electronic component and method for manufacturing the same

Info

Publication number: CN117995554A
Application number: CN202311444747.1A
Authority: CN
Inventors: 田仁浩; 尹硕晛; 金珍友; 尹秉吉; 具本亨; 张玟祯; 金美良
Original assignee: Samsung Electro Mechanics Co Ltd
Current assignee: Samsung Electro Mechanics Co Ltd
Priority date: 2022-11-04
Filing date: 2023-11-01
Publication date: 2024-05-07

Abstract

The present disclosure provides a ceramic electronic component and a method of manufacturing the same. The ceramic electronic component includes: a body including a dielectric layer and internal electrodes alternately arranged with the dielectric layer; and an external electrode disposed on the body, wherein the dielectric layer includes a first region and a second region other than the first region, the first region being a region extending from an interface surface between the dielectric layer and the internal electrode to 50nm within the dielectric layer, and wherein the first region includes In and Sn, in which an average content of In based on all elements other than oxygen is 0.5at% or more and 2.0at% or less, and an average content of Sn based on all elements other than oxygen is 0.5at% or more and 1.75at% or less.

Description

Ceramic electronic component and method for manufacturing the same

The present application claims the benefit of priority from korean patent application No. 10-2022-0187735 filed at the korean intellectual property office at 12 months of 2022 and korean patent application No. 10-2022-0146266 filed at the korean intellectual property office at 4 months of 2022, the disclosures of which are incorporated herein by reference in their entirety.

Technical Field

The present disclosure relates to a ceramic electronic component and a method of manufacturing the same.

Background

A multilayer ceramic capacitor (MLCC, a ceramic electronic component) may be a chip capacitor that is mounted on a printed circuit board of various electronic products, such as imaging devices, such as Liquid Crystal Displays (LCDs) and Plasma Display Panels (PDPs), computers, smart phones, and mobile phones, and can be charged or discharged.

Such a multilayer ceramic capacitor is useful as a component of various electronic devices due to its relatively small size, high capacity, and ease of installation. As various electronic devices such as computers and mobile devices have been designed to be miniaturized and to have high output, the demand for miniaturized and high-capacity multilayer ceramic capacitors has increased.

Recently, technologies of electric vehicles (EVs (ELECTRIC VEHICLE, pure electric vehicles), HEVs (Hybrid ELECTRIC VEHICLE), PHEVs (Plug in Hybrid ELECTRIC VEHICLE), etc.) are gradually improved, and occupancy increases, and thus, demands for semiconductors and passive electronic devices are rapidly increasing. Unlike passive electronic devices for IT (information technology), passive electronic devices for electric vehicles may need to operate without error in a high temperature/high pressure/high humidity environment. Therefore, it may be desirable to develop materials that can achieve ultra-high reliability at high voltages.

Disclosure of Invention

Example embodiments of the present disclosure are directed to improving the room temperature dielectric constant of a dielectric layer.

Example embodiments of the present disclosure are directed to reducing the Dissipation Factor (DF) of dielectric layers of ceramic electronic components.

An example embodiment of the present disclosure is directed to improving a Temperature Coefficient of Capacitance (TCC) of a ceramic electronic component.

Example embodiments of the present disclosure are directed to improving the high temperature insulation resistance of ceramic electronic components.

Example embodiments of the present disclosure are directed to improving the Mean Time To Failure (MTTF) of ceramic electronic components.

According to an example embodiment of the present disclosure, a ceramic electronic component includes: a body including a dielectric layer and internal electrodes alternately arranged with the dielectric layer; and an external electrode disposed on the body, wherein the dielectric layer includes a first region and a second region other than the first region, the first region being a region extending from an interface surface between the dielectric layer and the internal electrode to 50nm within the dielectric layer, and wherein the first region includes In and Sn, in which an average content of In based on all elements other than oxygen is 0.5at% or more and 2.0at% or less, and an average content of Sn based on all elements other than oxygen is 0.5at% or more and 1.75at% or less.

According to an example embodiment of the present disclosure, a method of manufacturing a ceramic electronic component includes: preparing a dielectric composition including a dielectric powder as a main component, and including 0.9mol or more and 1.8mol or less of Sn and 0.05mol or more and 0.1mol or less of In based on 100mol of the main component; forming a ceramic green sheet using the dielectric composition; forming a laminate by printing and laminating a conductive paste for internal electrodes on the ceramic green sheet; forming a body including a dielectric layer and an internal electrode by firing the laminate; and forming an external electrode on the body.

According to an example embodiment of the present disclosure, a method of manufacturing a ceramic electronic component includes: preparing a dielectric composition including In, sn, and dielectric powder as a main component; forming a ceramic green sheet using the dielectric composition; forming a laminate by printing and laminating a conductive paste for internal electrodes on the ceramic green sheet; and forming a body including the dielectric layer and the internal electrode by firing the laminate in an atmosphere having a hydrogen concentration of 0.2vol% to 0.4 vol%.

According to an example embodiment of the present disclosure, a ceramic electronic component includes: a body including a dielectric layer and internal electrodes alternately arranged with the dielectric layer; and an external electrode disposed on the main body, wherein the dielectric layer includes In, sn, and a first subcomponent element including V, wherein the dielectric layer includes a first region and a second region other than the first region, the first region being a region extending from an interface surface between the dielectric layer and the internal electrode to 50nm within the dielectric layer, and wherein, in the first region, an average content of In based on all elements other than oxygen is 0.5at% or more and 2.0at% or less, and an average content of Sn based on all elements other than oxygen is 0.5at% or more and 1.75at% or less.

Drawings

The foregoing and other aspects, features, and advantages of the disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:

fig. 1 is a perspective view illustrating a ceramic electronic component according to an example embodiment of the present disclosure;

FIG. 2 is a cross-sectional view taken along line I-I' in FIG. 1;

FIG. 3 is a cross-sectional view taken along line II-II' in FIG. 1;

Fig. 4 is an exploded perspective view illustrating a main body according to an example embodiment of the present disclosure;

Fig. 5 is an enlarged view showing a region a in fig. 2;

Fig. 6 is a graph showing the result of line profile analysis of measuring Ni, in, and Sn element contents along regions corresponding to the p region, q region, and r region In fig. 5 using STEM-EDS In a ceramic electronic component according to a comparative example of the present disclosure;

FIG. 7 is a graph showing the results of a line profile analysis of Ni, in, and Sn element contents In the p-region and the r-region In FIG. 5 measured using STEM-EDS In a ceramic electronic component according to an example embodiment of the present disclosure;

FIG. 8 is a graph showing the results of a line profile analysis of In and Sn element contents In the q region In FIG. 5 measured using STEM-EDS In a ceramic electronic component according to an example embodiment of the present disclosure; and

Fig. 9 is a flowchart illustrating a process of a method of sequentially manufacturing ceramic electronic components according to an example embodiment of the present disclosure.

Detailed Description

Hereinafter, example embodiments of the present disclosure will be described below with reference to the accompanying drawings.

The following detailed description is provided to assist the reader in obtaining a thorough understanding of the methods, apparatus, and/or systems described herein. However, various alterations, modifications and equivalents of the methods, devices and/or systems described herein will be readily appreciated after an understanding of the present disclosure.

In the drawings, like elements will be denoted by like reference numerals. Furthermore, redundant descriptions and detailed descriptions of known functions and elements that may unnecessarily obscure the gist of the present disclosure will not be provided. In the drawings, some elements may be exaggerated, omitted, or briefly shown, and the sizes of the elements do not necessarily reflect the actual sizes of the elements. The terms "comprises," "comprising," "including," "includes," "including," "having" and the like in the specification are intended to specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, and does not exclude the possibility of combining or adding one or more other features, amounts, steps, operations, elements, parts or combinations thereof.

In the drawings, a first direction may be defined as a lamination direction or a thickness (T) direction, a second direction may be defined as a length (L) direction, and a third direction may be defined as a width (W) direction.

Ceramic electronic component

Fig. 1 is a perspective view illustrating a ceramic electronic component according to an example embodiment.

Fig. 2 is a sectional view taken along line I-I' in fig. 1.

Fig. 3 is a sectional view taken along line II-II' in fig. 1.

Fig. 4 is an exploded perspective view illustrating a main body according to an example embodiment.

Fig. 5 is an enlarged view showing the region a in fig. 2.

Fig. 6 is a graph showing the result of line profile analysis of Ni, in, and Sn element contents measured along regions corresponding to the p region, q region, and r region In fig. 5 using STEM-EDS In a ceramic electronic component according to a comparative example.

Fig. 7 is a graph showing the result of line profile analysis of Ni, in, and Sn element contents In the p region and the r region In fig. 5 measured using STEM-EDS In a ceramic electronic component according to an example embodiment.

Fig. 8 is a graph showing the result of line profile analysis of In and Sn element contents In the q region In fig. 5 measured using STEM-EDS In a ceramic electronic component according to an example embodiment.

Hereinafter, with reference to fig. 1 to 8, a ceramic electronic component 100 according to an example embodiment will be described in detail. A multilayer ceramic capacitor will be described as an example of a ceramic electronic component, but example embodiments are also applicable to various electronic products (such as an inductor, a piezoelectric element, a varistor, or a thermistor) using a dielectric composition.

The ceramic electronic component 100 in an example embodiment may include: a body 110 including a dielectric layer 111 and internal electrodes 121 and 122 alternately disposed with the dielectric layer; and external electrodes 131 and 132 disposed on the body, wherein the dielectric layer includes a first region and a second region other than the first region, the first region extending from an interface surface between the dielectric layer and the internal electrode into the dielectric layer by 50nm (for example, the first region is a region extending from the interface surface between the dielectric layer and the internal electrode into the dielectric layer by 50nm In a thickness direction), and wherein the first region includes In and Sn, in the first region, an average content of In based on all elements other than oxygen is 0.5at% or more and 2.0at% or less, and an average content of Sn based on all elements other than oxygen is 0.5at% or more and 1.75at% or less.

The body 110 may include internal electrodes alternately arranged with the dielectric layers 111.

The shape of the body 110 may not be limited to any particular shape, but as shown, the body 110 may have a hexahedral shape or a shape similar to a hexahedral shape. The body 110 may not have a precisely hexahedral shape formed of linear edges due to shrinkage of the ceramic powder included in the body 110 during the firing process, but may have a substantially hexahedral shape.

The body 110 may have first and second surfaces 1 and 2 opposite to each other in a first direction, third and fourth surfaces 3 and 4 connected to the first and second surfaces 1 and 2 and opposite in a second direction, and fifth and sixth surfaces 5 and 6 connected to the first and second surfaces 1 and 2 and the third and fourth surfaces 3 and 4 and opposite to each other in the third direction. The plurality of dielectric layers 111 forming the body 110 may be in a fired state, and adjacent dielectric layers 111 may be integrated with each other such that boundaries between adjacent dielectric layers 111 may not be easily distinguished without using a Scanning Electron Microscope (SEM).

In the example embodiment, the raw material for forming the dielectric layer 111 is not limited to any particular example as long as a sufficient capacitance can be obtained. For example, barium titanate-based materials, lead composite perovskite-based materials, or strontium titanate-based materials may be used. The barium titanate-based material may include BaTiO ₃ -based ceramic powder, and examples of the BaTiO ₃ -based ceramic powder may include BaTiO ₃ or (Ba_1-xCa_x)TiO₃(0<x<1)、Ba(Ti_1-yCa_y)O₃(0<y<1)、(Ba_1-xCa_x)(Ti_1-yZr_y)O₃(0<x<1、0<y<1) or Ba (Ti _1-yZr_y)O₃ (0 < y < 1). That is, the dielectric layer 111 may include an oxide containing Ba and Ti in which Ca (calcium), zr (zirconium) is partially solid-dissolved in BaTiO ₃.

Further, in example embodiments, various ceramic additives, organic solvents, binders, dispersants, and the like may be added to raw material powder such as barium titanate (BaTiO ₃) for forming the dielectric layer 111, and In example embodiments, the dielectric layer 111 may include Sn and In. The method of including Sn and In the dielectric layer 111 is not limited to any particular example, but the dielectric layer 111 may include Sn and In by including a material containing Sn and In a dielectric composition described later.

In an example embodiment, by configuring the dielectric layer 111 to include Sn and In and also adjusting their concentration and distribution, the capacitance characteristics (such as a temperature coefficient of capacitance) and high temperature reliability of the ceramic electronic component 100 may be improved.

The average thickness td of the dielectric layer 111 is not limited to any particular example.

For example, the average thickness td of the dielectric layer 111 may be 10 μm or less. Further, the average thickness td of the dielectric layer 111 may be arbitrarily determined according to desired characteristics or uses. For example, in the case of an electronic component for a high-voltage electric vehicle, the average thickness td of the dielectric layer 111 may be 2.8 μm or less, and in the case of a small IT electronic component, the average thickness td of the dielectric layer 111 may be 0.35 μm or less to achieve miniaturization and high capacitance, but example embodiments thereof are not limited thereto.

When the average thickness td of the dielectric layer 111 is too thick, it may be difficult to improve the capacitance of the ceramic electronic component 100, and when the average thickness td of the dielectric layer 111 is too thin, it may be not easy to control the distribution of Sn and In at a predetermined concentration In the first region R1 of the dielectric layer 111 as In the example embodiment.

In the example embodiment, by adjusting the average thickness td of the dielectric layer 111 to be 1.8 μm or more and 2.8 μm or less, the effect of improving the capacitance characteristics (such as the temperature coefficient of capacitance) and the high-temperature reliability of the ceramic electronic component can be improved.

The average thickness td of the dielectric layer 111 may refer to an average size of the dielectric layer 111 disposed between the first and second internal electrodes 121 and 122 in the first direction. When the body 110 includes a plurality of dielectric layers 111, the average thickness td of the dielectric layers 111 may refer to an average thickness of at least one of the plurality of dielectric layers 111.

The average thickness of the dielectric layer 111 may be measured by scanning a cross section of the body 110 in the length and thickness directions (L-T directions) at a magnification of 10000 using a Scanning Electron Microscope (SEM). More specifically, the average value can be measured by scanning the thickness of the dielectric layer 111 at 30 points in the image that are equally spaced apart in the length direction. The capacitance forming portion Ac can specify 30 points at equal distances. Further, when the average value is measured by extending the measurement of the average value to ten dielectric layers 111, the average thickness of the dielectric layers 111 in the first direction can be further generalized. Other methods and/or tools as would be understood by one of ordinary skill in the art may be used, even if not described in the present disclosure.

The body 110 may include: a capacitance forming part Ac disposed in the body 110 and forming a capacitance, the capacitance forming part Ac including first and second internal electrodes 121 and 122 alternately disposed with the dielectric layer 111 interposed between the first and second internal electrodes 121 and 122; and cover portions 112 and 113 formed on upper and lower portions of the capacitance forming portion Ac in the first direction.

The capacitance forming portion Ac may contribute to the capacitance formation of the capacitor, and may be formed by repeatedly stacking a plurality of first internal electrodes 121 and a plurality of second internal electrodes 122 with the dielectric layer 111 interposed between the first internal electrodes 121 and the second internal electrodes 122.

The cover portions 112 and 113 may be disposed on one surface and the other surface of the capacitance forming portion Ac in the first direction.

The cover parts 112 and 113 may include an upper cover part 112 disposed above the capacitance forming part Ac in the first direction and a lower cover part 113 disposed below the capacitance forming part Ac in the first direction.

The upper and lower cover parts 112 and 113 may be formed by stacking a single dielectric layer or two or more dielectric layers on the upper and lower surfaces of the capacitance forming part Ac in the thickness direction, respectively, and damage to the internal electrode caused by physical stress or chemical stress may be prevented.

The upper and lower cover parts 112 and 113 do not include the inner electrode, and may include the same material as that of the dielectric layer 111.

That is, the upper and lower cover parts 112 and 113 may include a ceramic material, for example, a barium titanate (BaTiO ₃) -based ceramic material.

The average thickness tc of the cover portions 112 and 113 is not limited to any particular example. For miniaturization and high capacitance of the ceramic electronic component, the average thickness tc of the covering portions 112 and 113 may be 100 μm or less, 30 μm or less, or 20 μm or less. Here, the average thickness tc of the cover portions 112 and 113 may refer to an average thickness of each of the upper cover portion 112 and the lower cover portion 113.

The average thickness tc of the cover portions 112 and 113 may refer to a dimension in the first direction, and may be an average of the dimensions of the cover portions 112 and 113 in the first direction measured at five points where the upper or lower portions of the capacitance forming portion Ac have equal distances in the second direction. Even if not described in this disclosure, the average thickness tc of the covers 112 and 113 may be measured by SEM or any other method and/or tool as understood by one of ordinary skill in the art.

Further, edge portions 114 and 115 may be provided on one surface and the other surface of the capacitance forming portion Ac.

The edge portions 114 and 115 may include a first edge portion 114 provided on one side surface of the capacitance forming portion Ac in the width direction and a second edge portion 115 provided on the other side surface of the capacitance forming portion Ac in the width direction. That is, the edge portions 114 and 115 may be provided on both side surfaces of the capacitance forming portion Ac in the width direction.

As shown in fig. 3, edge portions 114 and 115 may refer to: in a cross section of the body 110 taken in a width-thickness (W-T) direction, regions between both ends of the first and second internal electrodes 121 and 122 and an outer surface of the body 110.

The edge portions 114 and 115 may prevent damage to the internal electrode caused by physical stress or chemical stress.

The edge portions 114 and 115 may be formed by forming an internal electrode by applying a conductive paste on regions of the ceramic green sheet other than the regions where the edge portions are formed.

Further, in order to suppress the step difference caused by the internal electrodes 121 and 122, after lamination, dicing may be performed such that the internal electrodes are exposed to both side surfaces of the capacitance forming portion Ac in the third direction (width direction), and a single dielectric layer or two or more dielectric layers may be laminated on both side surfaces of the capacitance forming portion Ac in the third direction (width direction), thereby forming the edge portions 114 and 115.

The average width of the edge portions 114 and 115 is not limited to any particular example. However, for miniaturization and high capacitance of the ceramic electronic component, the average width of the edge portions 114 and 115 may be 100 μm or less, 20 μm or less, or 15 μm or less.

The average width of the edge portions 114 and 115 may refer to an average size of a region where the inner electrode is spaced apart from the fifth surface in the third direction and an average size of a region where the inner electrode is spaced apart from the sixth surface in the third direction, and may be an average of sizes of the edge portions 114 and 115 measured at five points having equal distances in the first direction on the side surface of the capacitance forming portion Ac in the third direction.

The internal electrodes 121 and 122 may include a first internal electrode 121 and a second internal electrode 122. The first and second internal electrodes 121 and 122 may be alternately disposed opposite to each other with the dielectric layer 111 interposed between the first and second internal electrodes 121 and 122, and the first and second internal electrodes 121 and 122 may be exposed to the third and fourth surfaces 3 and 4 of the body 110, respectively.

The first internal electrode 121 may be spaced apart from the fourth surface 4 and may be exposed through the third surface 3, and the second internal electrode 122 may be spaced apart from the third surface 3 and may be exposed through the fourth surface 4. The first external electrode 131 may be disposed on the third surface 3 of the body and may be connected to the first internal electrode 121, and the second external electrode 132 may be disposed on the fourth surface 4 of the body and may be connected to the second internal electrode 122.

That is, the first inner electrode 121 may not be connected to the second outer electrode 132 and may be connected to the first outer electrode 131, and the second inner electrode 122 may not be connected to the first outer electrode 131 and may be connected to the second outer electrode 132. Accordingly, the first inner electrode 121 may be spaced apart from the fourth surface 4 by a predetermined distance, and the second inner electrode 122 may be spaced apart from the third surface 3 by a predetermined distance. Further, the first and second internal electrodes 121 and 122 may be spaced apart from the fifth and sixth surfaces of the body 110.

In this case, the first and second internal electrodes 121 and 122 may be electrically separated from each other by the dielectric layer 111 disposed therebetween.

The body 110 may be formed by alternately stacking ceramic green sheets on which conductive paste for the first internal electrodes 121 is printed and ceramic green sheets on which conductive paste for the second internal electrodes 122 is printed and firing.

The material forming the internal electrodes 121 and 122 is not limited to any particular example, and a material having excellent conductivity may be used. For example, the internal electrodes 121 and 122 may include one or more of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tungsten (W), titanium (Ti), aluminum (Al), and alloys thereof. However, the method of manufacturing the ceramic electronic component 100 according to the example embodiment may include predetermined concentrations of Sn and In the dielectric composition, and since Sn and In are intensively distributed In the first region R1 of the dielectric layer 111, the internal electrodes 121 and 122 may preferably not include Sn and In.

Further, the internal electrodes 121 and 122 may be formed by printing a conductive paste for internal electrodes including one or more of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tungsten (W), titanium (Ti), aluminum (Al), and alloys thereof on a ceramic green sheet. As a method of printing the conductive paste for the internal electrode, a screen printing method or a gravure printing method may be used, but example embodiments thereof are not limited thereto.

The average thickness te of the inner electrodes 121 and 122 is not limited to any particular example, and may be, for example, 3 μm or less. Further, the average thickness te of the inner electrodes 121 and 122 may be arbitrarily determined according to desired characteristics or uses. For example, in the case of an electronic component for a high-voltage electric vehicle, the average thickness te of the inner electrodes 121 and 122 may be less than 1 μm, and in the case of an electronic component for a small IT, the average thickness te of the inner electrodes 121 and 122 may be less than or equal to 0.35 μm to achieve miniaturization and high capacitance, but example embodiments thereof are not limited thereto.

The average thickness te of at least one of the plurality of internal electrodes 121 and 122 may refer to an average size of the internal electrodes 121 and 122 in the first direction.

The average thickness of the inner electrodes 121 and 122 may be measured by scanning a section of the body 110 in the length and thickness directions (L-T directions) at a magnification of 10000 using a Scanning Electron Microscope (SEM). More specifically, the average value may be measured by scanning the thickness of the internal electrodes at 30 points spaced apart by equal distances in the second direction in the image. The capacitance forming portion Ac can specify 30 points at equal distances. Further, when the average value is measured by extending the measurement of the average value to ten internal electrodes, the average thickness of the internal electrodes can be further generalized. Other methods and/or tools as would be understood by one of ordinary skill in the art may be used, even if not described in the present disclosure.

External electrodes 131 and 132 may be disposed on the body 110. Specifically, the external electrodes 131 and 132 may be disposed on the third surface 3 and the fourth surface 4 of the body 110.

The external electrodes 131 and 132 may include first and second external electrodes 131 and 132, respectively, disposed on the third and fourth surfaces 3 and 4 of the body 110 and connected to the first and second internal electrodes 121 and 122, respectively.

In the exemplary embodiment, the ceramic electronic component 100 is described as having the structure of two external electrodes 131 and 132, but the number of external electrodes 131 and 132 and the shape thereof may vary according to the shape of the internal electrodes 121 and 122 and other purposes.

The external electrodes 131 and 132 may be formed using any material such as metal as long as the material has conductivity, and specific materials may be determined in consideration of electrical characteristics, structural stability, and the external electrodes 131 and 132 may also have a multi-layered structure.

For example, the external electrodes 131 and 132 may include an electrode layer disposed on the body 110 and a plating layer formed on the electrode layer.

As a more specific example of the electrode layer, the electrode layer may be a fired electrode including a conductive metal and glass or a resin-based electrode including a conductive metal and a resin.

In addition, in the electrode layer, a firing electrode and a resin-based electrode may be sequentially formed on the body. Further, the electrode layer may be formed by transferring a sheet including a conductive metal onto the body or by transferring a sheet including a conductive metal onto the firing electrode.

A material having excellent conductivity may be used as the conductive metal included in the electrode layer, and is not limited to any particular example. For example, the conductive metal may be one or more of nickel (Ni), copper (Cu), and alloys thereof.

The plating layer can improve the mounting characteristics. The type of plating layer is not limited to any particular example, and may be a plating layer including at least one of Ni, sn, pd, and an alloy thereof, and may be formed of a plurality of layers.

As a more specific example of the plating layer, the plating layer may be a Ni plating layer or a Sn plating layer, or may have a form in which a Ni plating layer and a Sn plating layer are sequentially formed on the electrode layer, or may be a form in which a Sn plating layer, a Ni plating layer, and a Sn plating layer are sequentially formed. Further, the plating layer may include a plurality of Ni plating layers and/or a plurality of Sn plating layers.

The dimensions of the ceramic electronic component 100 are not limited to any particular example. In example embodiments described later, samples of ceramic electronic components having dimensions of 3.2mm×1.6mm were manufactured, but example embodiments and various example embodiments may be similarly applied to ceramic electronic components having dimensions greater than or less than the above examples.

The dielectric layer 111 of the ceramic electronic component 100 according to example embodiments may include a first region R1 and a second region R2, the first region R1 being a region from an interface surface IF between the dielectric layer 111 and the internal electrodes 121 and 122 to 50nm within the dielectric layer 111, the second region R2 being a region other than the first region R1, and In the first region, an average content of In based on all elements other than oxygen may be equal to or greater than 0.5at% and equal to or less than 2.0at%, and an average content of Sn based on all elements other than oxygen may be equal to or greater than 0.5at% and equal to or less than 1.75at%.

In general, as a method of improving reliability and capacitance characteristics of ceramic electronic components, rare earth or transition metal may be added to the dielectric layer, and volatile metal element may be added to the Ni inner electrode. However, this method may have limitations in simultaneously securing desired capacitance characteristics (such as a capacitance temperature coefficient) and high-temperature reliability due to various variables such as adjustment of the type, content, firing atmosphere, and microstructure after firing of the additive elements.

Thus, in example embodiments, by adding In and Sn as main additives to the dielectric layer and adjusting to have a predetermined distribution on the boundary surface with the internal electrode, at least one of the capacitance characteristics such as a Temperature Coefficient of Capacitance (TCC) and high temperature reliability of the ceramic electronic component may be improved.

In an example embodiment, the room temperature dielectric constant and Dissipation Factor (DF) value of the dielectric layer 111 may be characteristics related to capacitance, and the high temperature insulation resistance and Mean Time To Failure (MTTF) value may be characteristics related to high temperature reliability.

Referring to fig. 5, in the ceramic electronic component 100 according to the example embodiment, the dielectric layer 111 may include a first region R1 and a second region R2, the first region R1 being a region from an interface surface IF between the dielectric layer 111 and the internal electrodes 121 and 122 to 50nm inside the dielectric layer 111, the second region R2 being a region other than the first region.

The dielectric layer 111 and the internal electrodes 121 and 122 may be formed by: a ceramic green sheet (described later) is formed, a conductive paste for internal electrodes is printed on the ceramic green sheet, laminated to form a laminate, fired, and an interface surface is formed. The interface surface IF between the internal electrodes 121 and 122 and the dielectric layer 111 may be defined as a point where the content of the element included in the dielectric layer 111 and the internal electrodes 121 and 122 rapidly changes. Specifically, in the example embodiment, a region where the Ni content is equal to or greater than 90at% based on all elements other than oxygen may be regarded as the internal electrodes 121 and 122, and a region where the Ni content starts to decrease to less than 90at% based on all elements other than oxygen may be defined as the interface surface IF between the dielectric layer 111 and the internal electrodes 121 and 122. However, there may be a region between the dielectric layer 111 and the internal electrodes 121 and 122 in which Ni content based on all elements except oxygen continuously decreases and is less than 90 at%. Thus, the first region R1 of the dielectric layer 111 defined in the example embodiment may be a region in which Ni content based on all elements except oxygen may continuously decrease from the interface surface and less than 90at%, and may be a region from the interface surface IF to 50nm within the dielectric layer 111.

The comparative example according to fig. 6 may be an example of a ceramic electronic component In which Indium Tin Oxide (ITO) is not added to the dielectric composition, and may correspond to an example In which the dielectric layer substantially does not include In and Sn. That is, the content of In and Sn based on all elements except oxygen detected In the dielectric layer of the ceramic electronic component according to the comparative example may be less than 0.5at%, which may be an example In which the dielectric layer does not substantially include In and Sn.

In an example embodiment, in the graph showing the line profile analysis result according to fig. 7, the average content of Sn and In included In the first region R1 may be measured by calculating an average value of In and Sn content In a region from the interface surface IF (horizontal axis value=0) between the dielectric layer 111 and the internal electrodes 121 and 122 to 50nm (horizontal axis value=50) within the dielectric layer.

Line profile analysis according to fig. 7 can be performed in the p-region, q-region and r-region shown in fig. 5. Specifically, the p-region and the r-region may be determined as regions near the interface surface between the internal electrodes 121 and 122 and the dielectric layer 111, and the q-region may be determined as a central region of the dielectric layer. In this case, the p region and the r region may be determined as regions of width×length=250 nm×250nm, and the q region may be determined as regions of width×height=300 nm×300 nm. The p region, the q region, and the r region may not necessarily be disposed on a straight line in the second direction.

Further, a graph showing the line profile analysis result according to fig. 7 may represent the content ratio of Ni, in, and Sn among the elements detected by STEM-EDS based on the content of all elements except oxygen (O). Even if not described In the present disclosure, the contents and ratios of Ni, in and Sn may be measured by methods and/or tools understood by those of ordinary skill In the art. All elements may include In, sn, ni, and unavoidable impurities.

Further, the average value of the In and Sn contents can be further generalized by determining a plurality of p regions and a plurality of r regions, performing line profile analysis, and obtaining an average value. Specifically, the ceramic electronic component 100 may be ground to the center of the third direction to expose the cross sections In the first direction and the second direction, a plurality of p regions and a plurality of r regions may be determined In the regions of the dielectric layer 111 and the internal electrodes 121 and 122 disposed In the central portion of the capacitance forming portion Ac, and an average value of the contents of Ni, in, and Sn calculated by STEM-EDS line profile analysis may be obtained.

Furthermore, in example embodiments, the average value of the In and Sn content based on all elements except oxygen may be further generalized by: the average content of each element in the upper and lower portions formed by dividing the capacitance forming portion Ac into three regions (upper portion, central portion, lower portion) in the first direction and the region of the dielectric layer 111 and the internal electrodes 121 and 122 provided in the central portion of the capacitance forming portion Ac was measured.

Since the components included In the dielectric composition forming the dielectric layer 111 may be In the form of oxides In a state of the dielectric composition, oxygen (O) element may be detected In addition to metal elements such as In and Sn In the dielectric layer 111 after firing. In the internal electrodes 121 and 122, in addition to metal elements such as Ni, rare earth elements, and additive elements, oxygen (O) elements may be detected, oxygen contained in the dielectric layer 111 may diffuse to the side of the internal electrodes, or these elements may be components of oxide type added before firing the internal electrodes. The contents (at%) of In, sn, and various additive elements described In the example embodiments were determined as element contents (at%) based on all elements except oxygen.

Referring to fig. 6, in the comparative example, it may be designated that the Ni content starts to decrease to a point of less than 90at% based on all elements except oxygen. However, the In content based on all elements except oxygen and the Sn content based on all elements except oxygen (which may be measured In a region from a point at which the Ni content based on all elements except oxygen starts to decrease to less than 90 at%) to 50nm within the dielectric layer) may be less than 0.5at%, which is measured as an impurity level.

Referring to fig. 7, in the first region R1 from the interface surface between the dielectric layer 111 and the internal electrodes 121 and 122 to 50nm within the dielectric layer, the average content of In based on all elements except oxygen is 0.5at% or more and 2.0at% or less, and the average content of Sn based on all elements except oxygen is 0.5at% or more and 1.75at% or less.

Further, the content of In and Sn included In the first region R1 is greater than that of In and Sn included In the second region R2 or the internal electrodes 121 and 122, and the first region R1 is a region from the interface surface between the dielectric layer 111 and the internal electrodes 121 and 122 to 50nm within the dielectric layer. That is, in and Sn may be intensively distributed In the first region R1 In an example embodiment.

When In and Sn elements are intensively distributed near the interface surface between the dielectric layer 111 and the internal electrodes 121 and 122, the reliability of the ceramic electronic component 100 can be improved. However, when In and Sn elements are excessively diffused into the internal electrode or excessively diffused into the dielectric layer 111, the capacitance characteristics may be deteriorated or the capacitance temperature coefficient and the high temperature reliability may be deteriorated. Accordingly, in example embodiments, by including In and Sn near the interface surface between the dielectric layer 111 and the internal electrodes 121 and 122, an effect of improving high temperature reliability may be obtained, and by preventing In and Sn from excessively diffusing into the internal electrodes 121 and 122 or inside the dielectric layer 111, one or more of capacitance characteristics (such as a capacitance temperature coefficient) may be improved.

As In the example embodiment, when the average content of In based on all elements except oxygen is adjusted to 0.5at% or more and 2.0at% or less and the average content of Sn based on all elements except oxygen is adjusted to 0.5at% or more and 1.75at% or less In the first region R1, in and Sn may be concentrated toward the dielectric layer 111 on the interface surface between the dielectric layer 111 and the internal electrodes 121 and 122, so that deterioration of capacitance caused by In and Sn diffused into the internal electrodes may be prevented. Further, by concentrating In and Sn on the first region R1 (the first region R1 is a region from the interface surface between the dielectric layer 111 and the internal electrodes 121 and 122 to 50nm inside the dielectric layer), excessive diffusion of In and Sn into the dielectric layer 111 (such as the second region R2 of the dielectric layer 111) can also be prevented.

That is, as In the example embodiment, when the average content of In based on all elements other than oxygen is 0.5at% or more and 2.0at% or less and the average content of Sn based on all elements other than oxygen is 0.5at% or more and 1.75at% or less In the first region R1, the high temperature reliability of the ceramic electronic component 100, such as the Mean Time To Failure (MTTF) and the high temperature Insulation Resistance (IR), may be improved, and at least one of the capacitance characteristics, such as the capacitance and the capacitance temperature coefficient (TCC) at room temperature, may be improved.

More specifically, in the example embodiment, in the ceramic electronic component 100, the average content of In based on all elements except oxygen In the first region R1 may be adjusted to 0.5at% or more and 2.0at% or less, and the average content of Sn based on all elements except oxygen may be adjusted to 0.5at% or more and 1.75at% or less, so that one or more of the following characteristics may be satisfied: a dielectric constant of 2500 or more, an MTTF of 200 hours or more, a high temperature IR value of 1.0e+07 Ω or more, and a capacitance change rate of 22% or more and 22% or less in a temperature range of-55 ℃ to 125 ℃, and more preferably, all of the following characteristics can be satisfied: a dielectric constant of 2500 or more, an MTTF of 200 hours or more, a high-temperature IR value of 1.0E+07. OMEGA or more, and a capacitance change rate of 22% or more and 22% or less in a temperature range of-55 ℃ to 125 ℃.

The manufacturing method realizing an example In which the average content of In based on all elements except oxygen In the first region R1 is 0.5at% or more and 2.0at% or less, and the average content of Sn based on all elements except oxygen In the first region R1 is 0.5at% or more and 1.75at% or less is not limited to any particular example, and the composition and content of In and Sn In the first region are determined by adjusting one or more of the content of In and Sn added to the dielectric layer, the addition type of In and Sn, the firing temperature, the firing atmosphere, and the type and content of subcomponent elements of the dielectric composition. In example embodiments and various example embodiments thereof, the distribution may be determined as in a method of manufacturing a ceramic electronic component.

In example embodiments, when the average content of In based on all elements except oxygen In the first region R1 is defined as I1, the average content of In based on all elements except oxygen In the second region R2 is defined as I2, the average content of Sn based on all elements except oxygen In the first region is defined as S1, and the average content of Sn based on all elements except oxygen In the second region is defined as S2, I1> I2 and S1> S2 may be satisfied. Therefore, by adjusting the content of Sn and In included In the first region R1 of the dielectric layer 111 to be higher than the content of Sn and In the second region R2 of the dielectric layer 111, excellent capacitance characteristics (such as a capacitance temperature coefficient) and high-temperature reliability can be ensured.

In example embodiments, when the average content of In based on all elements of the inner electrode other than oxygen is defined as I3 and the average content of Sn based on all elements of the inner electrode other than oxygen is defined as S3, I1> I2> I3 and S1> S2> S3 may be satisfied. Therefore, by more intensively disposing In and Sn In the first region R1 of the dielectric layer 111, excellent high temperature reliability and capacitance temperature coefficient can be ensured, and by diffusing In and Sn into the internal electrodes 121 and 122 or the second region R2, capacitance deterioration or insulation resistance deterioration can be prevented.

In this case, the absolute numbers of I1 to I3 and S1 to S3 may be adjusted by adjusting one or more of the following: the size of the ceramic electronic component 100, the contents of Sn and In added to the dielectric composition forming the dielectric layer 111, the forms of adding In and Sn, the firing temperature, the firing atmosphere, and the types and contents of subcomponent elements In the dielectric composition.

Referring to fig. 8, when line profile analysis of the q region In fig. 5 is performed by STEM-EDS, the average content of In based on all elements except oxygen and the average content of Sn based on all elements except oxygen may be 1.0at% or less. When line profile analysis is repeatedly performed in an arbitrary q region and an average value of each element content is obtained, I2 may be 1.0at% or less, and S2 may be 1.0at% or less.

Referring to fig. 7, the average content of In and Sn of the inner electrode may be less than the average content of In and Sn of the first region and/or the second region, and each of the average content of In based on all elements except oxygen and the average content of Sn based on all elements except oxygen of the inner electrode may be less than 0.5at%. That is, in an example embodiment, I3 may be less than 0.5at%, and S3 may be less than 0.5at%. Here, since a value of "less than 0.5at%" may refer to a value corresponding to an impurity level In a result measured by STEM-EDS, it may mean that Sn and In are substantially not included In the internal electrode.

The average content I3 of In based on all elements except oxygen and the average content S3 of Sn based on all elements except oxygen of the inner electrode can be measured by line profile analysis using STEM-EDS for any region In the inner electrode that does not exceed the interface surface IF between the dielectric layer 111 and the inner electrodes 121 and 122. The average content I3 of In based on all elements except oxygen and the average content S3 of Sn based on all elements except oxygen of the internal electrodes can be further generalized by obtaining an average value after measurement In a plurality of regions of the plurality of internal electrodes. Specifically, the cross sections In the first direction and the second direction may be exposed by grinding to the center of the third direction of the ceramic electronic component 100, the capacitance forming portion Ac may be divided into three portions (upper portion, central portion, and lower portion) In the first direction, and an average value of the Sn content based on all elements except oxygen and the In content based on all elements except oxygen may be obtained.

Peaks (In which the Sn content based on all elements except oxygen and the In content based on all elements except oxygen have the maximum value) may exist In the inner electrodes 121 and 122, the dielectric layer 111, the interface surfaces between the inner electrodes 121 and 122 and the dielectric layer 111, and the first and second regions of the dielectric layer 111. When there is a peak In the first region (In which the content of In and the content of Sn based on all elements other than oxygen have the maximum value), it can be expressed that In and Sn are concentrated In the first region. In terms of ensuring excellent high temperature reliability and capacitance temperature coefficient and preventing deterioration of capacitance, in the first region, a peak value based on In content of all elements except oxygen may be 1.2at% or more, and a peak value based on Sn content of all elements except oxygen may be 1.0at% or more, but example embodiments thereof are not limited thereto.

As described above, the dielectric layer 111 may be formed of a dielectric composition including barium titanate (BaTiO ₃) as a main component. Thus, the dielectric layer 111 in a fired state may include Ba and Ti as main constituent elements. According to example embodiments, sn and In may be added. However, when firing of the dielectric layer 111 is performed in a reducing atmosphere as described later, it may be necessary to provide appropriate reduction resistance, and since various characteristics of the ceramic electronic component 100 (such as withstand voltage and high temperature reliability) need to be improved, the dielectric layer 111 may include various subcomponent elements in addition to the main component element.

In example embodiments, the dielectric layer may include one or more of Mn, V, cr, fe, ni, co, cu and Zn as the first subcomponent element, and the content of the first subcomponent element may be greater than 0at% and equal to or less than 0.6at% based on the entire elements except oxygen.

The first subcomponent element as the variable valence acceptor element can reduce the firing temperature of the dielectric layer 111 and can improve high temperature reliability. In this case, when the content of the first subcomponent element based on all elements except oxygen is 0at%, the effect of improving the dielectric constant may not be obtained, and when the content of the first subcomponent element based on all elements except oxygen exceeds 0.6at%, the high temperature reliability and the capacitance temperature coefficient of the ceramic electronic component 100 may deteriorate. Accordingly, by adjusting the content of the first subcomponent element included in the dielectric layer 111 to be more than 0at% and less than 0.6at% based on the total elements other than oxygen to improve the dielectric constant, the capacitance of the ceramic electronic component 100 can be improved, and excellent high temperature reliability and capacitance temperature coefficient can be ensured.

In an example embodiment, the dielectric layer may include Mg as a second subcomponent element, and the content of the second subcomponent element may be 0.3at% or more and 0.6at% or less based on all elements except oxygen.

The second subcomponent element can suppress growth of dielectric crystal grains included in the dielectric layer 111, and can provide appropriate reduction resistance when firing is performed in a reducing atmosphere during a firing process. Therefore, by including the second subcomponent element in the dielectric layer 111, the high temperature reliability and the temperature coefficient of capacitance of the ceramic electronic component can be improved.

However, when the content of the second subcomponent element based on all elements except oxygen is less than 0.3at%, high temperature reliability and capacitance temperature coefficient may not be sufficiently improved due to excessive grain growth of the dielectric layer 111, and when the content of the second subcomponent element based on all elements except oxygen exceeds 0.6at%, the dielectric constant may be lowered because grain growth of the dielectric layer 111 is excessively suppressed. Therefore, by adjusting the content of the second subcomponent element to 0.3at% or more and 0.6at% or less based on all elements other than oxygen, the capacitance of the ceramic electronic component 100 can be improved, and excellent high temperature reliability and capacitance temperature coefficient can be ensured.

In an example embodiment, the dielectric layer may include one or more of Y, dy, ho, er, gd, ce, nd, sm, tb, tm, la, gd and Yb as a third subcomponent element, and the content of the third subcomponent element based on all elements except oxygen is 0.6at% or more and 1.8at% or less. Therefore, the capacitance of the ceramic electronic component 100 can be improved, and excellent high-temperature reliability and capacitance temperature coefficient can be ensured.

The third subcomponent element may be a rare earth element (RE), and may improve HALT reliability and dielectric constant. However, when the dielectric layer 111 includes two or more elements (instead of including only one element) of the third subcomponent elements, the effect in the example embodiment may be more remarkable, and in particular, the dielectric layer 111 may include both Dy and Tb.

In example embodiments, the dielectric layer may include Si as a fourth subcomponent element, and the content of the fourth subcomponent element may be 1.0at% or more and 2.0at% or less based on all elements except oxygen.

The fourth subcomponent element may control the extent of diffusion of the first subcomponent element to the third subcomponent element. When the content of the fourth subcomponent element based on all elements except oxygen is less than 1.0at%, the third subcomponent greatly affecting reliability may not be properly diffused, so that it may be difficult to obtain the effect in the example embodiment. Further, when the content of the fourth subcomponent element based on all elements except oxygen exceeds 2.0at%, it may be difficult to secure a sufficient dielectric constant and MTTF.

Therefore, by adjusting the content of the fourth subcomponent element to 1.0at% or more and 2.0at% or less based on all elements other than oxygen, the capacitance of the ceramic electronic component 100 can be improved, and excellent high temperature reliability and capacitance temperature coefficient can be obtained.

Further, the quantitative content of each element included in the first to fourth sub-components included in the dielectric layer 111 may be measured using a destructive method. In particular, the measurement method using the destructive method may include: grinding the ceramic electronic component, removing the internal electrode, selecting a dielectric composition, and quantitatively analyzing the selected dielectric composition using a device such as an inductively coupled plasma-optical spectrometer (ICP-OES) and an inductively coupled plasma-mass spectrometer (ICP-MS). Other methods and/or tools as would be understood by one of ordinary skill in the art may be used, even if not described in the present disclosure.

When the quantitative contents of the elements included in the first to fourth sub-components of the dielectric layer 111 are analyzed, the oxygen (O) element may have low sensitivity, so that it may be difficult to analyze the inductively coupled plasma. Thus, in the example embodiment, the contents (at%) of the elements included in the first to fourth sub-components included in the dielectric layer 111 are determined as the contents (at%) of the respective elements based on all the elements except oxygen.

Method for manufacturing ceramic electronic component

Fig. 9 is a flowchart illustrating a process of a method of sequentially manufacturing ceramic electronic components according to an example embodiment.

As shown in fig. 9, a method of manufacturing a ceramic electronic component according to an example embodiment may include: preparing a dielectric composition (P1) including a dielectric powder as a main component, and including 0.9mol or more and 1.8mol or less of Sn and 0.05mol or more and 0.1mol or less of In based on 100mol of the main component; forming a ceramic green sheet (P2) using the dielectric composition; forming a laminate (P3) by printing and laminating a conductive paste for internal electrodes on a ceramic green sheet; forming a body (P4) including a dielectric layer and an internal electrode by firing the laminate; and forming an external electrode (P5) on the body.

(P1: preparation of dielectric composition)

In process P1 for preparing a dielectric composition, such a dielectric composition may be prepared: comprises a dielectric powder as a main component, comprises 0.9mol or more and 1.8mol or less of Sn based on 100mol of the main component, and comprises 0.05mol or more and 0.1mol or less of In.

The dielectric composition may include dielectric powder as a main component. For example, the dielectric composition may include BaTiO ₃ -based dielectric powder as a main component.

As the dielectric powder, baTiO ₃ ceramic powder or (Ba_1-xCa_x)TiO₃(0<x<1)、Ba(Ti_1-yCa_y)O₃(0<y<1)、(Ba_1-xCa_x)(Ti_1-yZr_y)O₃(0<x<1、0<y<1) or Ba (Ti _1-yZr_y)O₃ (0 < y < 1)) in which calcium (Ca), zirconium (Zr) are partially solid-dissolved in BaTiO ₃ can be used.

In addition to the above-described main component, the dielectric composition may preferably include 0.9mol or more and 1.8mol or less of Sn and 0.05mol or more and 0.1mol or less of In based on 100mol of the main component.

The content of Sn and In included In the dielectric composition may be a variable controlling the distribution of Sn and In the dielectric layer 111 of the ceramic electronic component 100. When the content of Sn and In exceeds the above range, the MTTF value of the ceramic electronic component 100 may be reduced or the X7S characteristic may not be satisfied, and it may be difficult to control the average content of In included In the first region R1 of the dielectric layer 111 In the example embodiment to 0.5at% or more and 2.0at% or less, and it may be difficult to control the average content of Sn included In the first region R1 of the dielectric layer 111 In the example embodiment to 0.5at% or more and 1.75at% or less.

The addition form of Sn and In included In the dielectric composition is not limited to any particular example. For example, sn oxide and In oxide may be mixed In a predetermined ratio, and may be added to the dielectric composition. However, when Sn and In are added to the dielectric composition In the form of Indium Tin Oxide (ITO), the reliability improvement effect of the ceramic electronic component 100 In the example embodiment may be improved.

Indium Tin Oxide (ITO) may be a material In which indium oxide (In ₂O₃) and tin oxide (SnO ₂) are mixed In a predetermined ratio. In the example embodiment, indium tin oxide (indium tin oxide includes In:74wt%, O:18wt%, and Sn:8 wt%) is added to the dielectric composition, but example embodiments thereof are not limited thereto, and even when indium tin oxide having different compositions is added, the concentrations of Sn and In the dielectric composition may be adjusted by adjusting their amounts.

When indium tin oxide (indium tin oxide includes In:74wt%, O:18wt%, and Sn:8 wt%) is added to the dielectric composition according to example embodiments, the content of indium tin oxide included In the dielectric composition may be 0.5mol or more and 1.0mol or less based on 100mol of the main component, which may be advantageous for improving the reliability of the ceramic electronic component 100.

In example embodiments, the dielectric composition may include a first subcomponent, which may include one or more of an oxide and a carbonate of a variable valence acceptor element.

The element included in the first subcomponent may reduce the firing temperature of the dielectric layer 111 and may improve high temperature reliability. In this case, the variable valence acceptor element may refer to one or more of Mn, V, cr, fe, ni, co, cu and Zn.

When the content of the first sub-component is less than 0.1mol based on 100mol of the main component, it may be difficult to improve the dielectric constant of the dielectric layer 111, and when the content of the first sub-component exceeds 0.3mol based on 100mol of the main component, the high temperature reliability and the capacitance temperature coefficient of the ceramic electronic component 100 may deteriorate.

Therefore, when the dielectric composition includes the first subcomponent in an amount of 0.1mol or more and 0.3mol or less based on 100mol of the main component, the capacitance of the ceramic electronic component 100 can be improved, and excellent high temperature reliability and capacitance temperature coefficient can be ensured.

After firing, in the ceramic electronic component 100, the content of the first subcomponent element included in the dielectric layer 111 based on the entire element other than oxygen may be more than 0at% and equal to or less than 0.6at%.

In example embodiments, the dielectric composition may include a second subcomponent, which may include one or more of an oxide and a carbonate of Mg.

The element included in the second subcomponent can suppress growth of dielectric crystal grains included in the dielectric layer 111, and when firing is performed in a reducing atmosphere during the firing process, the element included in the second subcomponent can provide appropriate reduction resistance.

When the content of the second subcomponent is less than 0.3mol based on 100mol of the main component, high temperature reliability and capacitance temperature coefficient may not be sufficiently improved due to excessive grain growth of the dielectric layer 111, and when the content of the second subcomponent exceeds 0.9mol based on 100mol of the main component, dielectric constant may be lowered because grain growth in the dielectric layer 111 is excessively suppressed.

Therefore, when the second sub-component is included in the dielectric composition in a content of 0.3mol or more and 0.9mol or less based on 100mol of the main component, the capacitance of the ceramic electronic component 100 can be improved, and excellent high-temperature reliability and capacitance temperature coefficient can be ensured.

After firing, in the ceramic electronic component 100, the content of the second subcomponent element included in the dielectric layer 111 based on the entire element other than oxygen may be 0.3at% or more and 0.6at% or less.

In example embodiments, the dielectric composition may include a third subcomponent, which may include one or more of an oxide and a carbonate of a rare earth element.

The third subcomponent can improve high temperature reliability and dielectric constant of the dielectric layer. In this case, the rare earth element may be one or more of Y, dy, ho, er, gd, ce, nd, sm, tb, tm, la, gd and Yb.

In example embodiments, when the third sub-component is included in the dielectric composition in a content of 0.3mol or more and 0.9mol or less based on 100mol of the main component, the capacitance of the ceramic electronic component 100 may be improved, and excellent high temperature reliability and capacitance temperature coefficient may be obtained.

After firing, in the ceramic electronic component 100, the content of all elements based on oxygen of the third subcomponent element included in the dielectric layer 111 may be 0.6at% or more and 1.8at% or less.

When the dielectric layer 111 includes an oxide or carbonate of two or more (instead of including only one) of rare earth elements including the third subcomponent element, the reliability of the ceramic electronic component 100 can be improved.

For example, by adding both Tb ₄O₇ and Dy ₂O₃ instead of only Tb ₄O₇ or only Dy ₂O₃ as the third subcomponent, the capacitance of the ceramic electronic component 100 can be improved by the improved dielectric constant, and the high-temperature reliability and the temperature coefficient of capacitance can be improved.

More specifically, when Tb ₄O₇ alone is added as a third subcomponent to the dielectric composition in a content of 0.6mol or more based on 100mol of the main component, the high temperature insulation resistance and MTTF value may decrease. Further, when Dy ₂O₃ alone is added as a third sub-component to the dielectric composition at a content of 0.6mol or more based on 100mol of the main component, characteristics such as a temperature coefficient of capacitance and high-temperature reliability may be improved, but the dielectric constant may be lowered.

Therefore, when the dielectric composition includes both Tb ₄O₇ and Dy ₂O₃ as the third sub-component, the content of Tb ₄O₇ may be 0.1mol or more and 0.4mol or less based on 100mol of the main component, and the content of Dy ₂O₃ may be 0.2mol or more and 0.5mol or less based on 100mol of the main component.

In example embodiments, the dielectric composition may include a fourth subcomponent, which may include one or more of an oxide of Si, a carbonate of Si, and a Si-containing glass.

The elements included in the fourth subcomponent may control the extent of diffusion of the first to third subcomponent elements in the dielectric layer 111.

When the content of the fourth sub-component is less than 1.0mol based on 100mol of the main component, it may be difficult to obtain the effect in the example embodiment because the third sub-component (which may greatly affect reliability) may not be properly diffused, and when the content of the fourth sub-component exceeds 2.0mol based on 100mol of the main component, it may be difficult to secure a sufficient dielectric constant and MTTF.

Therefore, by including 1.0mol or more and 2.0mol or less of the fourth subcomponent based on 100mol of the main component in the dielectric composition, the capacitance of the ceramic electronic component 100 can be improved, and excellent high temperature reliability and capacitance temperature coefficient can be ensured.

(P2: formation of ceramic Green sheet)

The dielectric composition may be used to form ceramic green sheets.

The dielectric composition may be prepared as a slurry by mixing with a binder and grinding prior to forming the ceramic green sheet. The slurry prepared as above may be formed into a ceramic green sheet using a molding apparatus for producing a sheet.

For the ceramic green sheet, a ceramic green sheet for the capacitance forming portion Ac and a ceramic green sheet for the covering portions 112 and 113 may be separately prepared. The composition of the ceramic green sheet for the capacitance forming portion Ac and the ceramic green sheet for the covering portions 112 and 113 may be substantially the same, but the composition may be different in order to obtain the respective functions of the covering portions 112 and 113 and the capacitance forming portion Ac.

(P3: forming a laminate)

Thereafter, a conductive paste for the internal electrode may be printed on the ceramic green sheet.

The conductive paste for the internal electrode may be a paste including one or more of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), indium (In), aluminum (Al), and alloys thereof.

The conductive paste for the internal electrode may be formed on the ceramic green sheet and may be spaced apart by a predetermined distance. That is, the conductive paste for the inner electrode may be in the form of a bar.

Subsequently, a laminate may be formed by laminating a plurality of ceramic green sheets on which a conductive paste for internal electrodes is printed.

In forming the laminate, a plurality of ceramic green sheets printed with a conductive paste for internal electrodes may be pressed and laminated to form a pressed bar (bar), and the pressed bar may be cut to an appropriate size using a cutting device, thereby preparing the laminate.

(P4: forming a body)

Thereafter, the prepared laminate may be fired to form the body 110 including the dielectric layer 111 and the internal electrodes 121 and 122.

In an example embodiment, the laminate may be subjected to a calcination process before firing, and after calcination, the laminate may be maintained at a temperature of 1150 ℃ to 1200 ℃ in a reducing atmosphere of 0.1% h ₂/99.9％N₂-0.5％H₂/99.5％N₂ for 2 hours, and firing may be performed.

In an exemplary embodiment, after firing, a step of reoxidizing in an atmosphere of N ₂ at 1040 ℃ for 3 hours may be further included.

In the process of firing the body 110, the dielectric layer 111 may also be fired. In this case, the concentration distribution of Sn and In included In the dielectric layer 111 may vary according to the firing atmosphere. That is, the firing atmosphere of the body 110 may be another variable that controls the distribution of Sn and In the dielectric layer 111.

In the firing atmosphere In which the hydrogen concentration is reduced, the dielectric constant and DF level of the dielectric layer 111 may be improved due to the dispersion of In and Sn included In the dielectric composition, but it may be difficult to improve the temperature coefficient of capacitance and high temperature reliability due to uneven grain growth.

Thus, in example embodiments, by firing in an EMF (electromotive force) atmosphere of 730mV or more and 760mV or less, the capacitive characteristics (such as the capacitive temperature coefficient) and high temperature reliability of the ceramic electronic component 100 may be improved. In this case, when the EMF in the above range is converted to a hydrogen concentration, firing may be performed in an atmosphere having a hydrogen concentration of 0.2vol% or more and 0.4vol% or less. The EMF value may vary depending on the hydrogen concentration and the temperature of the measuring sensor, and the EMF value in the example embodiment may correspond to a value measured at a sensor temperature of 850 ℃.

(P5: forming an external electrode)

Thereafter, external electrodes 131 and 132 may be formed on the body 110 formed by firing the laminate.

The external electrodes 131 and 132 may be formed by coating a conductive paste for the external electrodes on the fired body 110, and the fired body 110 may undergo a capping process and a firing process. In addition to the method of using the conductive paste for the external electrode, the external electrode may be formed by a wet plating method (such as electrolytic plating or electroless plating) or a dry plating method (such as sputtering).

Hereinafter, effects of the ceramic electronic component and a method of manufacturing the ceramic electronic component according to example embodiments will be described with reference to various example embodiments.

Samples of the ceramic electronic components used in each of the example embodiments were prepared as follows, and the contents of ITO and the first to fourth subcomponents in tables 1, 3 and 5 are listed in mole numbers of the corresponding components based on 100 moles of the main component. Further, as the ITO added in each of the example embodiments, indium tin oxide including the following components was used: in:74wt%, O:18wt% and Sn:8wt%.

(Sample of ceramic electronic component)

BaTiO ₃ powder having an average particle size of 100nm was used as a dielectric main component base material. Using zirconia beads as a mixing/dispersing medium, a raw material powder including indium tin oxide (ITO, in:74wt%, O:18wt% and Sn:8 wt%), sub-component and main component BaTiO ₃ powders corresponding to the components specified In tables 1,3 and 5 below were mixed with an ethanol/toluene solvent and a dispersing agent, ground for 10 hours, added with a binder, and further ground for 10 hours. The prepared slurry was used to prepare a ceramic green sheet for the covering portion and the capacitance forming portion having a thickness of 5.0 μm using a sheet molding apparatus. Ni inner electrodes are printed on a ceramic green sheet used for a capacitor forming part. The upper and lower cover parts are manufactured by laminating 25 layers of ceramic green sheets for the cover parts, and the bar block is manufactured by laminating 20 layers of printed ceramic green sheets for the capacitor forming parts simultaneously. The bar was cut into stacks of 3.2mm and 1.6mm in size using a cutting device. The completed laminate was calcined, held at a temperature of 1150 ℃ to 1200 ℃ in a reducing atmosphere of 0.1% h ₂/99.9％N₂-0.5％H₂/99.5％N₂(H₂/N₂ atmosphere) for 2 hours of firing, and oxidized in an N ₂ atmosphere at 1040 ℃ for 3 hours again, thereby forming the body 110. Here, in the oxygen partial pressure meter, the hydrogen concentration of 0.1% corresponds to an electromotive force of 680mV, and the hydrogen concentration of 0.5% corresponds to a condition of an electromotive force of 760 mV. For the fired body 110, a capping process was performed using Cu paste, and electrode firing was performed, thereby manufacturing external electrodes 131 and 132. Thus, after firing, samples of ceramic electronic components were fabricated with dielectric layers having a thickness of about 2.2 μm or less and a number of dielectric layers of 20 layers having dimensions of 3.2mm by 1.6 mm.

Further, in each example embodiment, the firing atmospheres varied according to the hydrogen concentration, and the EMF value in each firing atmosphere was a value measured at a sensor temperature of 850 ℃ using a thermoelectric-type hydrogen sensor.

As to whether ITO is detected, as a result of line profile analysis by STEM-EDS on regions (first region and second region) adjacent to the internal electrodes 121 and 122 In the first direction In the dielectric layer 111 of the ceramic electronic component, samples In which the In content based on all elements other than oxygen and the Sn content based on all elements other than oxygen are equal to or greater than 0.5at% are marked as o, and samples In which the In content based on all elements other than oxygen and the Sn content based on all elements other than oxygen are lower than 0.5at% are marked as X In the entire region of the dielectric layer 111.

For the room temperature dielectric constant, the capacitance of the sample was measured at 1kHz, AC (alternating current) 0.5V/μm using an LCR meter, the relative dielectric constant of the dielectric layer was measured by the thickness of the dielectric layer, the area of the internal electrode and the number of stacks, and the results were listed, and a value of 2500 or more was determined as a target characteristic.

The loss factor (DF) value was also measured at 1kHz, AC0.5V/. Mu.m using an LCR meter, and a value of 10% or less was determined as the target property.

The change in capacitance with temperature (capacitance temperature coefficient, TCC) was measured by applying 0.1Vrms in a temperature range of-55 ℃ to 125 ℃, and a sample having a capacitance change of-22% or more and 22% or less (hereinafter, referred to as "X7S characteristic") in a temperature range of-55 ℃ to 125 ℃ was determined as a target characteristic.

For the high temperature IR value, an average value was obtained by measuring an Insulation Resistance (IR) value after charging 10 samples for 60 seconds at a temperature of 150 ℃ with a DC10V/μm voltage applied, and a value of 1.0e+07 Ω or more was determined as a target characteristic.

The MTTF (mean time to failure) value is calculated by: a voltage corresponding to an electric field of 40V/μm was applied to 40 samples at 150 ℃, the time at which failure occurred was measured, and the average time was calculated, and a value of 200 hours or more was determined as a target characteristic.

Example 1

Test numbers 1-1 to 1-4, test numbers 2-1 to 2-4, and test numbers 3-1 to 3-4 in table 1 are various experimental conditions prepared by changing firing atmosphere and content of ITO added to the dielectric composition.

The characteristics of the samples of ceramic electronic components manufactured according to each test number in table 1 are listed in table 2.

TABLE 1

TABLE 2

Referring to tables 1 and 2, test numbers 1-4, 2-4, and 3-1 to 3 have dielectric constants of 2500 or more and DF values of 10% or less, but do not satisfy the X7S characteristic due to uneven grain growth.

In test numbers 2-1 to 2-4 and test numbers 3-1 to 3-4, the MTTF values were below 200 hours.

In test numbers 1 to 2 and 1 to 3, all of an MTTF value of 200 hours or more, a dielectric constant of 2500 or more, a high temperature IR value of 1.0e+07 Ω or more, and an X7S characteristic were satisfied. In test nos. 1-2 and 1-3, the amounts of ITO added were 0.5mol and 1.0mol, respectively, based on 100mol of the main component, the firing atmosphere was In the range of 730mV to 760mV (hydrogen concentration 0.2vol% to 0.4 vol%) of EMF, and after the sample was manufactured, the average content of In based on all elements other than oxygen was 0.5at% or more and 2.0at% or less, and the average content of Sn based on all elements other than oxygen was 0.5at% or more and 1.75at% or less In the first region R1 from the interface surface between the dielectric layer 111 and the internal electrodes 121 and 122 to 50nm inside the dielectric layer 111.

In test numbers 1 to 4, when the ITO content was increased to 1.5mol (based on 100mol of the main component), the average content of In based on all elements except oxygen and the average content of Sn based on all elements except oxygen In the first region R1 after the sample was manufactured were detected to be more than 2at%, and the MTTF value was reduced to less than 200 hours and the X7S characteristic was not satisfied.

In test No. 2-2, test No. 2-3, test No. 2-4, test No. 3-2, test No. 3-3, and test No. 3-4, in content based on all elements except oxygen and Sn content based on all elements except oxygen are detected to be 0.5at% or more In the entire region of the dielectric layer 111, and dielectric constant of 2500 or more and DF of 10% or less are satisfied, but test No. 2-4, test No. 3-2, and test No. 3-3 do not satisfy the X7S characteristic. Test number 2-2, test number 2-3, test number 2-4, test number 3-2, test number 3-3, and test number 3-4 have MTTF of not more than 200 hours.

In test numbers 2-4, 3-2 and 3-3, it appears that the X7S characteristic is not satisfied due to the non-uniform grain growth of the dielectric layer as a result of analyzing the dielectric layer of the sample, and In test numbers 2-2, 2-3, 2-4, 3-2, 3-3 and 3-4, in and Sn are not intensively distributed In the first region of the dielectric layer and distributed In the entire region of the dielectric layer as a result of analyzing the dielectric layer of the sample, so that In the first region, the condition In which the average content of In based on all elements other than oxygen is 0.5at% or more and 2.0at% or less and the average content of Sn based on all elements other than oxygen is 0.5at% or more and 1.75at% or less is not satisfied.

In test numbers 1-2 and 1-3 satisfying all target characteristics, in a first region R1 from the interface surface between the dielectric layer 111 and the internal electrodes 121 and 122 to 50nm inside the dielectric layer 111, the average content of In based on all elements except oxygen is 0.5at% or more and 2.0at% or less, and the average content of Sn based on all elements except oxygen is 0.5at% or more and 1.75at% or less. That is, in order to satisfy all of the MTTF value of 200 hours or more, the dielectric constant of 2500 or more, the high temperature IR value of 1.0e+07 Ω or more, and the X7S characteristic, it is preferable that In the first region R1 from the interface surface between the dielectric layer 111 and the internal electrodes 121 and 122 to 50nm inside the dielectric layer 111, the average content of In based on all elements other than oxygen may be 0.5at% or more and 2.0at% or less, and the average content of Sn based on all elements other than oxygen may be 0.5at% or more and 1.75at% or less.

The firing atmosphere may be in the EMF (sensor temperature 850 ℃) region of 730mV to 760mV (hydrogen concentration 0.2vol% to 0.4 vol%), and the content of ITO added to the dielectric composition may be 0.5mol or more and 1.0mol or less based on 100mol of the main component.

Example 2

Test numbers 4-1 through 4-3, test numbers 5-1 through 5-3, test numbers 6-1 through 6-4, and test numbers 7-1 through 7-4 in Table 3 list various experimental conditions including different amounts of the first subcomponent or different amounts of the second subcomponent in the dielectric composition.

The characteristics of the samples of ceramic electronic components manufactured according to each test number in table 3 are listed in table 4.

TABLE 3

TABLE 4

Referring to tables 3 and 4, in test No. 4-1 and test No. 5-1 (the content of MnO ₂ in the first subcomponent was 0mol based on 100mol of the main component, and the content of V ₂O₅ in the first subcomponent was 0.3mol based on 100mol of the main component), it was confirmed that the dielectric constant at room temperature was less than 2500.

In test No. 4-3 and test No. 5-3 (the content of MnO ₂ is 0.3mol based on 100mol of the main component, and the content of V ₂O₅ is 0mol based on 100mol of the main component), it was confirmed that the X7S characteristic was not satisfied, and the MTTF was less than 200 hours.

Accordingly, the content of the first subcomponent included in the dielectric composition may preferably be 0.1mol or more and 0.3mol or less based on 100mol of the main component, and in the dielectric layer 111 of the ceramic electronic component 100, the first subcomponent element may preferably be included in an amount of 0at% or more and 0.6at% or less.

Referring to test numbers 6-1 to 6-4 and test numbers 7-1 to 7-4, it was confirmed that when MgCO ₃ was included as a second subcomponent in the dielectric composition, TCC characteristics were improved and high temperature IR was improved. However, in test No. 6-4 and test No. 7-4 (in which the content of MgCO ₃ is 1.2mol based on 100mol of the main component), the room temperature dielectric constant was reduced to less than 2500 due to excessive grain growth inhibition, and the X7S characteristic was not satisfied.

Accordingly, the content of the second subcomponent included in the dielectric composition may be preferably equal to or more than 0.3mol and equal to or less than 0.9mol based on 100mol of the main component, and the content of the second subcomponent element based on all elements except oxygen may be preferably equal to or more than 0.3at% and equal to or less than 0.6at% in the dielectric layer 111 of the ceramic electronic component 100.

Example 3

Test No. 8-1 to test No. 8-4, test No. 9-1 to test No. 9-4, test No. 10-1 to test No. 10-3, and test No. 11-1 to test No. 11-3 in table 5 list various experimental conditions including different amounts of the third subcomponent or different amounts of the fourth subcomponent in the dielectric composition.

The characteristics of the samples of ceramic electronic components manufactured according to each test number in table 5 are listed in table 6.

TABLE 5

TABLE 6

In tables 5 and 6, referring to test numbers 8-1 to 8-4 and test numbers 9-1 to 9-4, it can be shown that when the third subcomponent (rare earth oxide including both Dy ₂O₃ and Tb ₄O₇) is added to the dielectric composition, the MTTF value increases and the room temperature dielectric constant increases. In test No. 8-1 and test No. 9-1 (wherein only 0.6mol of Tb ₄O₇ was added based on 100mol of the main component), the high temperature IR and MTTF values were lowered. In addition, in test numbers 8-4 and 9-4 (in which only 0.6mol of Dy ₂O₃ was added based on 100mol of the main component), the dielectric constant at room temperature was lowered.

Therefore, the content of the third subcomponent included in the dielectric composition may be preferably 0.3mol or more and 0.9mol or less based on 100mol of the main component. In particular, instead of including only one of Tb ₄O₇ and Dy ₂O₃ as the third sub-ingredient, a mixture of Tb ₄O₇ and Dy ₂O₃ may be mixed and included in an appropriate amount, and preferably, the content of Tb ₄O₇ may be 0.1mol or more and 0.4mol or less based on 100mol of the main ingredient, and the content of Dy ₂O₃ may be 0.2mol or more and 0.5mol or less based on 100mol of the main ingredient. In this case, preferably, in the dielectric layer 111 of the ceramic electronic component 100, the content of the third subcomponent element may be 0.6at% or more and 1.8at% or less based on all elements other than oxygen.

In test numbers 10-1 to 10-3 and test numbers 11-1 to 11-3, siO ₂ was included as a fourth subcomponent of the dielectric composition. In test No. 10-1 and test No. 11-1 (the content of SiO ₂ is 0.65mol based on 100mol of the main component), excessively fast grain growth was caused and diffusion of ITO and the third subcomponent was suppressed, it was confirmed that the X7S characteristic was not satisfied and the MTTF was less than 200 hours.

In test No. 10-3 and test No. 11-3 (SiO ₂ content of 2.15mol based on 100mol of the main component), it was confirmed that the dielectric constant at room temperature was less than 2500 and the MTTF was less than 200 hours.

Accordingly, the content of the fourth subcomponent included in the dielectric composition may be preferably 1.0mol or more and 2.0mol or less based on 100mol of the main component, and in the dielectric layer 111 of the ceramic electronic component 100, the content of the fourth subcomponent element may be preferably 1.0at% or more and 2.0at% or less based on all elements except oxygen.

According to the foregoing example embodiments, the room temperature dielectric constant of the dielectric layer of the ceramic electronic component may be improved.

In addition, the Dissipation Factor (DF) of the dielectric layer of the ceramic electronic component may be reduced.

In addition, the Temperature Coefficient of Capacitance (TCC) of the ceramic electronic component can be improved.

In addition, the high temperature insulation resistance of the ceramic electronic component can be improved.

In addition, the Mean Time To Failure (MTTF) of the ceramic electronic component can be improved.

Although example embodiments have been shown and described above, it will be readily appreciated by those skilled in the art that modifications and variations may be made without departing from the scope of the disclosure as defined by the appended claims.

Claims

1. A ceramic electronic component comprising:

A body including a dielectric layer and internal electrodes alternately arranged with the dielectric layer; and

An external electrode disposed on the main body,

Wherein the dielectric layer includes a first region and a second region other than the first region, the first region being a region extending from an interface surface between the dielectric layer and the internal electrode to 50nm within the dielectric layer, and

Wherein the first region includes In and Sn, in which an average content of In based on all elements other than oxygen is 0.5at% or more and 2.0at% or less, and an average content of Sn based on all elements other than oxygen is 0.5at% or more and 1.75at% or less.

2. The ceramic electronic component according to claim 1, wherein an average content of In based on all elements except oxygen In the first region is defined as I1, an average content of In based on all elements except oxygen In the second region is defined as I2, an average content of Sn based on all elements except oxygen In the first region is defined as S1, and an average content of Sn based on all elements except oxygen In the second region is defined as S2, satisfying I1> I2 and S1> S2.

3. The ceramic electronic component according to claim 2, wherein In the internal electrode, an average content of In based on all elements other than oxygen is defined as I3, and an average content of Sn based on all elements other than oxygen is defined as S3, satisfying I1> I2> I3 and S1> S2> S3.

4. A ceramic electronic component according to claim 3, wherein I2 is equal to or less than 1.0at% and S2 is equal to or less than 1.0at%.

5. The ceramic electronic component of claim 4, wherein I3 is less than 0.5at% and S3 is less than 0.5at%.

6. The ceramic electronic component according to claim 1, wherein In the first region, a peak value based on an In content of all elements other than oxygen is 1.2at% or more, and a peak value based on an Sn content of all elements other than oxygen is 1.0at% or more.

7. The ceramic electronic component according to claim 1, wherein the internal electrode includes Ni, in which Ni content is 90at% or more based on all elements other than oxygen, and the interface surface is a region where Ni content starts to decrease to less than 90at% based on all elements other than oxygen.

8. The ceramic electronic component of claim 1, wherein the dielectric layer has an average thickness of 1.8 μm or more and 2.8 μm or less.

9. The ceramic electronic component according to claim 1, wherein the dielectric layer includes Ba and Ti as main constituent elements.

10. The ceramic electronic component of claim 9, wherein the dielectric layer further comprises a first subcomponent element including one or more of Mn, V, cr, fe, ni, co, cu and Zn, the content of the first subcomponent element being greater than 0at% and equal to or less than 0.6at% based on all elements except oxygen.

11. The ceramic electronic component according to claim 9, wherein the dielectric layer further comprises Mg as a second subcomponent element, and the content of the second subcomponent element is 0.3at% or more and 0.6at% or less based on the whole elements except oxygen.

12. The ceramic electronic component of claim 9, wherein the dielectric layer further comprises one or more of Y, dy, ho, er, gd, ce, nd, sm, tb, tm, la, gd and Yb as a third subcomponent element, and the content of the third subcomponent element is 0.6at% or more and 1.8at% or less based on the entire elements except oxygen.

13. The ceramic electronic component according to claim 9, wherein the dielectric layer further comprises Si as a fourth subcomponent element, and a content of the fourth subcomponent element is 1.0at% or more and 2.0at% or less based on all elements except oxygen.

14. The ceramic electronic component of claim 1, wherein the ceramic electronic component meets one or more of the following characteristics: a dielectric constant of 2500 or more, an average failure time of 200 hours or more, a high-temperature insulation resistance value of 1.0E+07 Ω or more, and a capacitance change rate of 22% or more and 22% or less in a temperature range of-55 ℃ to 125 ℃.

15. A method of manufacturing a ceramic electronic component, the method comprising:

preparing a dielectric composition including a dielectric powder as a main component, and including 0.9mol or more and 1.8mol or less of Sn and 0.05mol or more and 0.1mol or less of In based on 100mol of the main component;

forming a ceramic green sheet using the dielectric composition;

Forming a laminate by printing and laminating a conductive paste for internal electrodes on the ceramic green sheet;

Forming a body including a dielectric layer and an internal electrode by firing the laminate; and

An external electrode is formed on the body.

16. The method according to claim 15, wherein In and Sn are added to the dielectric composition In the form of indium tin oxide, and the dielectric composition includes 0.5mol or more and 1.0mol or less of indium tin oxide based on 100mol of the main component.

17. The method of claim 15, wherein the dielectric powder is BaTiO ₃ powder.

18. The method according to claim 17,

Wherein the dielectric composition further comprises a first subcomponent including at least one of an oxide and a carbonate of a variable valence acceptor element, the content of the first subcomponent being 0.1mol or more and 0.3mol or less based on 100mol of the main component, and

Wherein the variable valence acceptor element is one or more of Mn, V, cr, fe, ni, co, cu and Zn.

19. The method of claim 17, wherein the dielectric composition further comprises a second subcomponent including at least one of an oxide and a carbonate of Mg, the content of the second subcomponent being 0.3mol or more and 0.9mol or less based on 100mol of the main component.

20. The method according to claim 17,

Wherein the dielectric composition further comprises a third subcomponent including at least one of an oxide and a carbonate of a rare earth element, the content of the third subcomponent being 0.3mol or more and 0.9mol or less based on 100mol of the main component, and

Wherein the rare earth element is one or more of Y, dy, ho, er, gd, ce, nd, sm, tb, tm, la, gd and Yb.

21. The method of claim 17, wherein the dielectric composition further comprises a fourth subcomponent including at least one of Si oxide, si carbonate and Si-containing glass, the fourth subcomponent being contained in an amount of 1.0mol or more and 2.0mol or less based on 100mol of the main component.