CN117995534A - Isolation transformer and semiconductor device - Google Patents
Isolation transformer and semiconductor device Download PDFInfo
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- CN117995534A CN117995534A CN202211333545.5A CN202211333545A CN117995534A CN 117995534 A CN117995534 A CN 117995534A CN 202211333545 A CN202211333545 A CN 202211333545A CN 117995534 A CN117995534 A CN 117995534A
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- 238000002955 isolation Methods 0.000 title claims abstract description 84
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 71
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 71
- 239000010703 silicon Substances 0.000 claims abstract description 71
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 28
- 238000002161 passivation Methods 0.000 claims description 15
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 14
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- 229910052757 nitrogen Inorganic materials 0.000 claims description 7
- 238000005137 deposition process Methods 0.000 claims description 4
- 239000012495 reaction gas Substances 0.000 claims description 3
- 230000002035 prolonged effect Effects 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 description 27
- 239000000463 material Substances 0.000 description 26
- 229910052751 metal Inorganic materials 0.000 description 25
- 239000002184 metal Substances 0.000 description 25
- 239000012212 insulator Substances 0.000 description 15
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 9
- 235000012239 silicon dioxide Nutrition 0.000 description 9
- 239000000377 silicon dioxide Substances 0.000 description 9
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 6
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 229910004286 SiNxOy Inorganic materials 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F19/00—Fixed transformers or mutual inductances of the signal type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/28—Coils; Windings; Conductive connections
- H01F27/32—Insulating of coils, windings, or parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention relates to an isolation transformer and a semiconductor device, the isolation transformer comprises: a lower coil; a main dielectric layer covering the lower coil; the silicon oxynitride layer is positioned on the main dielectric layer; and the upper coil is positioned on the silicon oxynitride layer. According to the invention, the silicon oxynitride layer is arranged between the main dielectric layer and the upper coil, so that the influence of a high-voltage area on a low-voltage area can be reduced while the withstand voltage of the device is ensured, and the service life of the device is prolonged.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to an isolation transformer and a semiconductor device.
Background
In a semiconductor integration process, an exemplary isolation transformer employs silicon dioxide as an isolation medium between upper and lower coils. By increasing the thickness of the silicon dioxide, the withstand voltage of the upper and lower coils can be improved. However, when the upper coil is etched, many defects (defects) are formed on the surface of the etched material, so that dielectric breakdown is likely to occur in the high electric field region at the upper coil position, thereby affecting the withstand voltage of the whole transformer.
In the scheme of capacitance isolation, the voltage withstand of the isolation transformer can be improved by adding a layer of silicon nitride between the main dielectric layer and the upper coil as a buffer layer. However, because the energy gap of the silicon nitride is smaller, for devices integrated with a high-voltage device region and a low-voltage device region, the surface of the high-voltage device and the surface of the low-voltage device are easy to move, and the service life of the low-voltage device is lower over time, so that the overall reliability of the device is affected.
Disclosure of Invention
Based on this, it is necessary to provide an isolation transformer which has a high withstand voltage and can optimize the lifetime of the low-voltage device.
An isolation transformer, comprising: a lower coil; a main dielectric layer covering the lower coil; the silicon oxynitride layer is positioned on the main dielectric layer; and the upper coil is positioned on the silicon oxynitride layer.
According to the isolation transformer, the silicon oxynitride layer is arranged between the main dielectric layer and the upper coil, so that the influence of a high-voltage area on a low-voltage area can be reduced while the voltage resistance of the isolation transformer is ensured, and the service life of the whole device is prolonged.
In one embodiment, the molar ratio of silicon element to nitrogen element in the silicon oxynitride layer is between 0.5 and 1.5.
In one embodiment, the molar ratio of silicon element to nitrogen element in the silicon oxynitride layer is controlled and adjusted to be between 0.5 and 1.5 by controlling the flow ratio of SiH 4 and N 2 O in the reaction gas of the deposition process to be between 1:3 and 2:1 and/or controlling the power of the deposition process to be between 100W and 200W.
In one embodiment, the silicon oxynitride layer has a thickness greater than 300nm.
In one embodiment, the thickness of the silicon oxynitride layer is less than the thickness of the main dielectric layer.
In one embodiment, the main dielectric layer comprises a silicon oxide layer.
In one embodiment, the thickness of the main dielectric layer is greater than 4 microns.
In one embodiment, the isolation transformer further comprises a passivation layer covering at least a portion of the upper coil.
In one embodiment, the upper and lower coils are metal coils or alloy coils.
In one embodiment, the upper and lower coils are comprised of copper and aluminum.
In one embodiment, the silicon oxynitride layer comprises a coil region, and the orthographic projection of the upper coil on the upper surface of the silicon oxynitride layer is positioned in the coil region; the isolation transformer further comprises an isolation region, wherein the isolation region is made of silicon oxide, and the isolation region surrounds the coil region.
In one embodiment, the isolation region is in a ring shape surrounding the coil region, and the silicon oxynitride layer includes an outer region located outside the isolation region in addition to the coil region located inside the isolation region.
In one embodiment, the isolation region and the passivation layer are made of the same material.
In one embodiment, the distance between the isolation region and the upper coil is greater than 0.5 times the thickness of the main dielectric layer.
It is also necessary to provide a semiconductor device.
A semiconductor device comprising a transformer region and a low voltage region, the low voltage region comprising a low voltage device, the transformer region comprising an isolation transformer according to any of the preceding embodiments.
According to the semiconductor device, the silicon oxynitride layer is arranged between the main dielectric layer and the upper coil, so that the influence of the transformer area on the low-voltage area can be reduced while the voltage resistance of the isolation transformer is ensured, and the service life of the whole semiconductor device is prolonged.
Drawings
For a better description and illustration of embodiments and/or examples of those inventions disclosed herein, reference may be made to one or more of the accompanying drawings. Additional details or examples used to describe the drawings should not be construed as limiting the scope of the disclosed invention, the presently described embodiments and/or examples, and any of the presently understood modes of carrying out the invention.
FIG. 1 is a schematic diagram of a isolating transformer in accordance with an embodiment of the present application;
FIG. 2 is a schematic diagram of the shape of the upper and lower coils in one embodiment;
FIG. 3 is a schematic diagram of a isolating transformer according to another embodiment of the present application;
Fig. 4 is a schematic diagram of a isolating transformer according to another embodiment of the present application.
Detailed Description
In order that the invention may be readily understood, a more complete description of the invention will be rendered by reference to the appended drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. In this way, variations from the illustrated shape due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
The application provides an isolation transformer, which adopts silicon oxynitride as a buffer layer between a main dielectric layer and an upper coil, and ensures that the service life of a device is not influenced while improving the withstand voltage of the device.
Fig. 1 is a schematic cross-sectional view of a isolation transformer according to an embodiment of the present application. The isolation transformer 100 (i.e., the area outlined by the dashed line in fig. 1) is integrated in a semiconductor device and includes a lower coil 104, a main dielectric layer 105, a silicon oxynitride layer 103, and an upper coil 101. A main dielectric layer 105 covers the lower coil 104. The silicon oxynitride layer 103 is located on the main dielectric layer 105, and the upper coil 101 is located on the silicon oxynitride layer 103, i.e., the silicon oxynitride layer 103 is located between the main dielectric layer 105 and the upper coil 101. In operation, the isolation transformer 100 forms a mutual inductance between the upper coil 101 and the lower coil 104. In one embodiment of the present application, the material of the main dielectric layer 105 comprises silicon oxide, such as silicon dioxide. In the embodiment shown in fig. 1, the device further comprises a low voltage region 106 for providing a low voltage device (not shown in fig. 1).
In the isolation transformer 100, a silicon oxynitride layer 103 is provided between a main dielectric layer 105 and an upper coil 101. Because silicon oxynitride has a higher withstand voltage than the conventional main dielectric layer material (silicon dioxide), and is less likely to cause charge movement between the high-voltage device (i.e., the isolation transformer 100) and the surface of the low-voltage region 106 than the silicon nitride material, the influence of the high-voltage region on the low-voltage region 106 can be reduced while ensuring the withstand voltage of the isolation transformer 100, and the overall life of the semiconductor device (i.e., the semiconductor device integrated with the isolation transformer 100 and the low-voltage device) can be improved.
Fig. 2 is a schematic diagram of the shape of the upper coil 101 and the lower coil 104 in one embodiment. In the embodiment shown in fig. 1 and 2, the upper coil 101 and the lower coil 104 are identical in shape. Specifically, the shape of the lower coil 104 is the orthographic projection of the upper coil 101 on the surface of the lower coil 104, so as to improve the mutual coupling coefficient of the inductance. In the embodiment shown in fig. 1 and 2, the upper coil 101 and the lower coil 104 are square spirals; in other embodiments, the upper coil 101 and the lower coil 104 may be other inductor coil shapes as is conventional in the art. In one embodiment of the present application, the upper coil 101 and the lower coil 104 are metal coils or alloy coils, and the main material is typically a mixture of Al and Cu. In one embodiment of the present application, the upper coil 101 and the lower coil 104 are made of the same material.
In one embodiment of the application, the isolation transformer 100 further comprises a passivation layer 102, the passivation layer 102 covering at least part of the upper coil 101, a dielectric layer for protecting the devices and circuits.
In the embodiment shown in fig. 1 and 2, the isolation transformer 100 further includes a Pad (Pad) portion 107 on the silicon oxynitride layer 103, and the Pad portion 107 is electrically connected to the upper coil 101. The passivation layer 102 exposes the pad portion 107, and the pad portion 107 is used to connect the upper coil 101 to a peripheral circuit.
By adjusting the ratio of Si to N in the medium of the silicon oxynitride layer 103, the refractive index of the medium can be changed accordingly. In one embodiment of the present application, the molar ratio of silicon element to nitrogen element in the silicon oxynitride layer 103 is preferably between 0.5 and 1.5 (which can be adjusted by the reaction gas ratio (SiH 4/N2 O) =1:3 to 2:1 or the reaction power (150 w±50W)). That is, the SiNxOy material of the silicon oxynitride layer 103 has an X value of 2/3 to 2, and the voltage resistance between the upper coil 101 and the lower coil 104 is improved obviously, and the influence on the service life of the device is small. In one embodiment of the present application, the thickness of the silicon oxynitride layer 103 is greater than 300nm. In one embodiment of the present application, the thickness of silicon oxynitride layer 103 is less than the thickness of main dielectric layer 105. I.e., the thickness of the silicon oxynitride layer 103 may be greater than 300nm and less than the thickness of the main dielectric layer 105.
In one embodiment of the application, the thickness of the main dielectric layer 105 is greater than 4 microns.
In the embodiment shown in fig. 1, the device further comprises a substrate 112. In one embodiment of the application, the upper coil 101 and the lower coil 104 are the top metal (top metal) and middle metal layer (INTER METAL) of the device, respectively. The substrate 112 is a semiconductor substrate, and may be made of undoped single crystal silicon, impurity-doped single crystal silicon, silicon On Insulator (SOI), silicon on insulator (SSOI), silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), germanium on insulator (GeOI), or the like, or at least one of the following materials: si, ge, siGe, siC, siGeC, inAs, gaAs, inP or other III/V compound semiconductors. In one embodiment of the present application, substrate 112 is comprised of single crystal silicon. Devices, such as transistors, e.g., NMOS and/or PMOS, may be formed on substrate 112, these structures being omitted from fig. 1. Also, a conductive member may be formed in the substrate 112 (and on the substrate 112), and the conductive member may be a gate, a source, or a drain of a transistor, a metal interconnection structure electrically connected to the transistor, or the like. In the embodiment shown in fig. 1, shallow Trench Isolation (STI) structures 114 are also formed in the substrate 112.
In the embodiment shown in fig. 1, the device further comprises a contact hole 115 and a plurality of layers of metal interconnect lines 116. The contact hole 115 is filled with a conductive material, such as a tungsten plug, and is electrically connected to the corresponding metal interconnect 116 to lead out the device structures, such as the active region, in the substrate 112.
Fig. 3 is a schematic cross-sectional view of a isolation transformer according to another embodiment of the present application. The isolation transformer 100 (i.e., the area outlined by the dashed line in fig. 3) is integrated in a semiconductor device and includes a lower coil 104, a main dielectric layer 105, a silicon oxynitride layer 103, an upper coil 101, and an isolation region 108. A main dielectric layer 105 covers the lower coil 104. Silicon oxynitride layer 103 is located on main dielectric layer 105. The upper coil 101 is located on the coil region in the silicon oxynitride layer 103, and the isolation region 108 surrounds the coil region of the silicon oxynitride layer 103. In the embodiment shown in fig. 3, the isolation region 108 is a ring-shaped structure surrounding the coil region of the silicon oxynitride layer 103, and may specifically be a square frame structure, a circle structure, an elliptical ring structure, or the like. In one embodiment of the application, the isolation region 108 is a closed loop. In other embodiments of the application, the isolation region 108 may also be a non-closed loop with a notch. In one embodiment of the present application, the isolation region 108 comprises a silicon oxide, such as silicon dioxide. In one embodiment of the present application, the material of the main dielectric layer 105 comprises silicon oxide, such as silicon dioxide. In the embodiment shown in fig. 3, the device further comprises a low voltage region 106 for providing a low voltage device.
In the isolation transformer 100, a silicon oxynitride layer 103 is provided between a main dielectric layer 105 and an upper coil 101. Because silicon oxynitride has a higher withstand voltage than the conventional main dielectric layer material, and is less likely to cause charge movement between the high-voltage device and the surface of the low-voltage region 106 than the silicon nitride material, the influence of the high-voltage region on the low-voltage region 106 can be reduced while ensuring the withstand voltage of the isolation transformer 100, and the overall life of the semiconductor device can be improved. Further, by providing the isolation region 108 surrounding the coil region of the silicon oxynitride layer 103, the influence of the coil region of the silicon oxynitride layer 103 on the low-voltage region 106 can be further reduced, and the reliability of the semiconductor device can be further improved.
Referring to fig. 2, in the embodiment shown in fig. 3 and 2, the upper coil 101 and the lower coil 104 have the same shape. Specifically, the shape of the lower coil 104 is the orthographic projection of the upper coil 101 on the surface of the lower coil 104, so as to improve the mutual coupling coefficient of the inductance. In the embodiment shown in fig. 3 and 2, the upper coil 101 and the lower coil 104 are square spirals; in other embodiments, the upper coil 101 and the lower coil 104 may be other inductor coil shapes as is conventional in the art. In one embodiment of the present application, the upper coil 101 and the lower coil 104 are metal coils or alloy coils, and the main material is typically a mixture of Al and Cu. In one embodiment of the present application, the upper coil 101 and the lower coil 104 are made of the same material.
In one embodiment of the application, the isolation transformer 100 further comprises a passivation layer 102, the passivation layer 102 covering at least part of the upper coil 101, a dielectric layer for protecting the devices and circuits. In one embodiment of the application, isolation region 108 is a passivation layer material that fills in the corresponding location of the fracture when passivation layer 102 is deposited. In one embodiment of the application, the passivation layer material is silicon oxide, such as silicon dioxide.
In the embodiment shown in fig. 3 and 2, the isolation transformer 100 further includes a pad portion 107 on the silicon oxynitride layer 103, and the pad portion 107 is electrically connected to the upper coil 101. The passivation layer 102 exposes the pad portion 107, and the pad portion 107 is used to connect the upper coil 101 to a peripheral circuit.
In one embodiment of the present application, the molar ratio of silicon element to nitrogen element in the silicon oxynitride layer 103 is preferably between 0.5 and 1.5. That is, the SiNxOy material of the silicon oxynitride layer 103 has an X value of 2/3 to 2, and the voltage resistance between the upper coil 101 and the lower coil 104 is improved obviously, and the influence on the service life of the device is small.
In one embodiment of the application, the thickness of the main dielectric layer 105 is greater than 4 microns.
In one embodiment of the application, the spacing a of the isolation region 108 from the upper coil 101 is greater than 0.5 times the thickness of the main dielectric layer 105, i.e., the nearest distance of the isolation region 108 from the upper coil 101 is also greater than 0.5 times the thickness of the main dielectric layer 105. Since the thickness of the main dielectric layer 105 is greater than 4 micrometers, the pitch a is greater than 2 micrometers.
In the embodiment shown in fig. 3, the device further comprises a substrate 112. In one embodiment of the application, the upper coil 101 and the lower coil 104 are the top metal (top metal) and middle metal layer (INTER METAL) of the device, respectively. The substrate 112 is a semiconductor substrate, and may be made of undoped single crystal silicon, impurity-doped single crystal silicon, silicon On Insulator (SOI), silicon on insulator (SSOI), silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), germanium on insulator (GeOI), or the like, or at least one of the following materials: si, ge, siGe, siC, siGeC, inAs, gaAs, inP or other III/V compound semiconductors. In one embodiment of the present application, substrate 112 is comprised of single crystal silicon. Devices, such as transistors, e.g., NMOS and/or PMOS, may be formed on substrate 112, these structures being omitted from fig. 3. Also, a conductive member may be formed in the substrate 112 (and on the substrate 112), and the conductive member may be a gate, a source, or a drain of a transistor, a metal interconnection structure electrically connected to the transistor, or the like. In the embodiment shown in fig. 3, shallow trench isolation structures 114 are also formed in the substrate 112.
In the embodiment shown in fig. 3, the device further comprises a contact hole 115 and a plurality of layers of metal interconnect lines 116. The contact hole 115 is filled with a conductive material, such as a tungsten plug, and is electrically connected to the corresponding metal interconnect 116 to lead out the device structures, such as the active region, in the substrate 112.
Fig. 4 is a schematic cross-sectional view of a isolating transformer according to still another embodiment of the present application. The isolation transformer 100 (i.e., the area outlined by the dashed line in fig. 4) is integrated in a semiconductor device and includes a lower coil 104, a main dielectric layer 105, a silicon oxynitride layer 103, an upper coil 101, and an isolation region 108. A main dielectric layer 105 covers the lower coil 104. Silicon oxynitride layer 103 is located on main dielectric layer 105. In the embodiment shown in fig. 4, the silicon oxynitride layer 103 is disposed only under and around the upper coil 101 (i.e., the coil region), and the isolation region 108 is disposed outside the silicon oxynitride layer 103. The isolation region 108 comprises a silicon oxide, such as silicon dioxide. In one embodiment of the present application, the material of the main dielectric layer 105 comprises silicon oxide, such as silicon dioxide. In the embodiment shown in fig. 4, the device further comprises a low voltage region 106 for providing a low voltage device.
In the isolation transformer 100, a silicon oxynitride layer 103 is provided between a main dielectric layer 105 and an upper coil 101. Because silicon oxynitride has a higher withstand voltage than the conventional main dielectric layer material, and is less likely to cause charge movement between the high-voltage device (i.e., the isolation transformer 100) and the surface of the low-voltage region 106 than the silicon nitride material, the influence of the high-voltage region on the low-voltage region 106 can be reduced while ensuring the withstand voltage of the isolation transformer 100, and the overall life of the semiconductor device can be improved. And only the silicon oxynitride layer 103 is provided under and around the upper coil 101, the influence of the silicon oxynitride layer 103 on the low-voltage region 106 can be further reduced, and the reliability of the semiconductor device can be further improved.
Referring to fig. 2, in the embodiment shown in fig. 4 and 2, the upper coil 101 and the lower coil 104 have the same shape. Specifically, the shape of the lower coil 104 is the orthographic projection of the upper coil 101 on the surface of the lower coil 104, so as to improve the mutual coupling coefficient of the inductance. In the embodiment shown in fig. 4 and 2, the upper coil 101 and the lower coil 104 are square spirals; in other embodiments, the upper coil 101 and the lower coil 104 may be other inductor coil shapes as is conventional in the art. In one embodiment of the present application, the upper coil 101 and the lower coil 104 are metal coils or alloy coils, and the main material is typically a mixture of Al and Cu. In one embodiment of the present application, the upper coil 101 and the lower coil 104 are made of the same material.
In one embodiment of the application, the isolation transformer 100 further comprises a passivation layer 102, the passivation layer 102 covering at least part of the upper coil 101, a dielectric layer for protecting the devices and circuits.
In the embodiment shown in fig. 4 and 2, the isolation transformer 100 further includes a pad portion 107 on the silicon oxynitride layer 103, and the pad portion 107 is electrically connected to the upper coil 101. The passivation layer 102 exposes the pad portion 107, and the pad portion 107 is used to connect the upper coil 101 to a peripheral circuit.
In one embodiment of the present application, the molar ratio of silicon element to nitrogen element in the silicon oxynitride layer 103 is preferably between 0.5 and 1.5. That is, the SiNxOy material of the silicon oxynitride layer 103 has an X value of 2/3 to 2, and the voltage resistance between the upper coil 101 and the lower coil 104 is improved obviously, and the influence on the service life of the device is small.
In one embodiment of the application, the thickness of the main dielectric layer 105 is greater than 4 microns.
In one embodiment of the application, the spacing b of the isolation region 108 from the upper coil 101 is greater than 0.5 times the thickness of the main dielectric layer 105, i.e., the nearest distance of the isolation region 108 from the upper coil 101 is also greater than 0.5 times the thickness of the main dielectric layer 105. Since the thickness of the main dielectric layer 105 is greater than 4 micrometers, the pitch b is greater than 2 micrometers.
In the embodiment shown in fig. 4, the device further comprises a substrate 112. In one embodiment of the application, the upper coil 101 and the lower coil 104 are the top metal (top metal) and middle metal layer (INTER METAL) of the device, respectively. The substrate 112 is a semiconductor substrate, and may be made of undoped single crystal silicon, impurity-doped single crystal silicon, silicon On Insulator (SOI), silicon on insulator (SSOI), silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), germanium on insulator (GeOI), or the like, or at least one of the following materials: si, ge, siGe, siC, siGeC, inAs, gaAs, inP or other III/V compound semiconductors. In one embodiment of the present application, substrate 112 is comprised of single crystal silicon. Devices, such as transistors, e.g., NMOS and/or PMOS, may be formed on substrate 112, these structures being omitted from fig. 4. Also, a conductive member may be formed in the substrate 112 (and on the substrate 112), and the conductive member may be a gate, a source, or a drain of a transistor, a metal interconnection structure electrically connected to the transistor, or the like. In the embodiment shown in fig. 4, shallow trench isolation structures 114 are also formed in the substrate 112.
In the embodiment shown in fig. 4, the device further comprises a contact hole 115 and a plurality of layers of metal interconnect lines 116. The contact hole 115 is filled with a conductive material, such as a tungsten plug, and is electrically connected to the corresponding metal interconnect 116 to lead out the device structures, such as the active region, in the substrate 112.
The present application accordingly provides a semiconductor device comprising a transformer region and a low voltage region 106, the low voltage region 106 having a low voltage device disposed therein, the transformer region comprising an isolation transformer 100 according to any of the preceding embodiments.
In the description of the present specification, reference to the terms "some embodiments," "other embodiments," "desired embodiments," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (10)
1. An isolation transformer, comprising:
A lower coil;
A main dielectric layer covering the lower coil;
the silicon oxynitride layer is positioned on the main dielectric layer;
and the upper coil is positioned on the silicon oxynitride layer.
2. The isolation transformer of claim 1, wherein the molar ratio of elemental silicon to elemental nitrogen in the silicon oxynitride layer is between 0.5 and 1.5.
3. The isolation transformer according to claim 2, wherein the molar ratio of silicon element to nitrogen element in the silicon oxynitride layer is controlled and adjusted to be between 0.5 and 1.5 by controlling the flow ratio of SiH 4 and N 2 O in the reaction gas of the deposition process to be between 1:3 and 2:1 and/or controlling the power of the deposition process to be between 100W and 200W.
4. An isolation transformer according to claim 3, wherein the main dielectric layer comprises a silicon oxide layer.
5. The isolation transformer of claim 1 or 4, wherein the thickness of the main dielectric layer is greater than 4 microns.
6. The isolation transformer of claim 1, further comprising a passivation layer covering at least a portion of the upper coil.
7. The isolation transformer of claim 1, wherein the silicon oxynitride layer comprises a coil region within which an orthographic projection of the upper coil on an upper surface of the silicon oxynitride layer is located;
The isolation transformer further comprises an isolation region, wherein the isolation region is made of silicon oxide, and the isolation region surrounds the coil region.
8. The isolation transformer of claim 7, wherein the isolation region is in the shape of a coil surrounding the coil region; the silicon oxynitride layer includes an outer region outside the isolation region in addition to the coil region inside the isolation region.
9. An isolation transformer according to claim 7 or 8, wherein the isolation region is spaced from the upper coil by more than 0.5 times the thickness of the main dielectric layer.
10. A semiconductor device comprising a transformer region and a low voltage region, the low voltage region comprising a low voltage device, wherein the transformer region comprises an isolation transformer as claimed in any one of claims 1-9.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211333545.5A CN117995534A (en) | 2022-10-28 | 2022-10-28 | Isolation transformer and semiconductor device |
| PCT/CN2023/111553 WO2024087792A1 (en) | 2022-10-28 | 2023-08-07 | Isolation transformer and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211333545.5A CN117995534A (en) | 2022-10-28 | 2022-10-28 | Isolation transformer and semiconductor device |
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| Publication Number | Publication Date |
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| CN117995534A true CN117995534A (en) | 2024-05-07 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202211333545.5A Pending CN117995534A (en) | 2022-10-28 | 2022-10-28 | Isolation transformer and semiconductor device |
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| CN (1) | CN117995534A (en) |
| WO (1) | WO2024087792A1 (en) |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8860544B2 (en) * | 2007-06-26 | 2014-10-14 | Mediatek Inc. | Integrated inductor |
| CN103022000B (en) * | 2011-09-27 | 2015-04-29 | 中芯国际集成电路制造(上海)有限公司 | Planar inductor and manufacturing method thereof, and semiconductor device and manufacturing method thereof |
| US20140273825A1 (en) * | 2013-03-15 | 2014-09-18 | Infineon Technologies Ag | Semiconductor Chip Configuration with a Coupler |
| CN108022913B (en) * | 2016-11-01 | 2019-11-01 | 中芯国际集成电路制造(上海)有限公司 | Transformer |
| US11348884B1 (en) * | 2020-11-13 | 2022-05-31 | Taiwan Semiconductor Manufacturing Company Limited | Organic interposer including a dual-layer inductor structure and methods of forming the same |
| US11532693B2 (en) * | 2021-01-19 | 2022-12-20 | Texas Instruments Incorporated | Passive components with improved characteristics |
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- 2022-10-28 CN CN202211333545.5A patent/CN117995534A/en active Pending
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| WO2024087792A1 (en) | 2024-05-02 |
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