CN117995256A

CN117995256A - Memory testing method and device

Info

Publication number: CN117995256A
Application number: CN202211332501.0A
Authority: CN
Inventors: 庄勇
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-10-28
Filing date: 2022-10-28
Publication date: 2024-05-07

Abstract

The disclosure provides a method and device for testing a memory, comprising the following steps: sequentially writing data into a plurality of memory chips in a memory; sequentially reading data from the plurality of memory chips after waiting for the target time period; and determining whether the storage unit has a fault according to the data written into the storage unit and the data read from the storage unit. The method and the device write data into one memory chip in the reserved time after the writing of the other memory chip is completed, so that the reserved time of the previous memory chip is fully utilized, and the test time is saved. The target time length is determined according to the difference between the reserved time length and the total writing time length of the plurality of memory chips, so that the reserved time length can be fully utilized as far as possible, the actual waiting time length between writing data and reading data of each memory unit is ensured to be consistent with the reserved time length, and the testing accuracy of data reservation faults is improved.

Description

Memory testing method and device

Technical Field

The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a method and equipment for testing a memory.

Background

A memory is a data storage device that provides data access functions, and typically stores data in binary form. The memory may include a large number of memory cells, each of which may store one bit of binary data 0 or 1. For example, a DRAM (dynamic random access memory ) is a commonly used memory, and a memory cell of the DRAM includes a storage capacitor and a transistor for controlling writing of data into the storage capacitor or controlling reading of data from the storage capacitor.

In the prior art, in order to detect whether a faulty unit exists in a memory, the memory may be tested, and the testing process of the memory includes the testing process of all the memory units. In the testing process of each storage unit, data is written into each storage unit first, and after waiting for a preset retention time, the data is read from the storage unit. Wherein the retention period is varied by parameters such as PVT (process, voltage, temperature, process, voltage, temperature), called variable retention period (variable retention time, VRT). When the read data and the write data corresponding to the memory cell are inconsistent, it can be determined that the memory cell has a fault due to the power failure of the memory cell. When the read data and the written data corresponding to the storage unit are consistent, it can be determined that the storage unit has no fault.

However, the existing test schemes with reserved time periods have the problem of waste of test time.

Disclosure of Invention

The embodiment of the disclosure provides a method and equipment for testing a memory, so as to fully utilize test time.

In a first aspect, an embodiment of the present disclosure provides a method for testing a memory, the method including:

Sequentially writing data into a plurality of memory chips in the memory;

After waiting for a target time length, sequentially reading data from the plurality of memory chips, wherein the target time length is determined according to a difference between a preset retention time length and a total writing time length of the plurality of memory chips, and the retention time length is a waiting time length between writing data and reading data when testing data retention faults of each memory unit;

For a memory cell in the memory chip, determining whether the memory cell has a failure according to data written to the memory cell and data read from the memory cell.

In some embodiments, the writing data sequentially to the plurality of memory chips in the memory includes:

Determining the maximum number of writable chips in a reserved time according to the preset reserved time and the writing time of a single memory chip;

and sequentially writing data into the memory chips with the maximum chip number in the memory.

In some embodiments, the determining, according to a preset reserved time period and a writing time period of a single memory chip, a maximum number of writable chips in the reserved time period includes:

and taking an integer part of the ratio between the reserved time length and the writing time length of the single memory chip as the maximum chip number.

In some embodiments, the method further comprises:

and dividing the reserved time length by the writing time length of the single memory chip to obtain a remainder as the target time length.

after writing data to each memory chip, counting the total writing time length of one or more memory chips with written data;

If the sum of the total writing time length and the writing time length of the single memory chip is smaller than or equal to the reserved time length, continuing to write data into the next memory chip;

And if the sum of the total writing time length and the writing time length of the single memory chip is greater than the reserved time length, stopping writing data to the next memory chip.

In some embodiments, the writing data process of each of the memory chips includes:

and writing data into the rows in sequence according to the address sequence of each row in the memory chip.

In some embodiments, the writing data to the row includes:

Activating a word line of the row;

sequentially writing data into each storage unit in the row;

the bit lines of the row are precharged.

In some embodiments, the process of reading data from each of the memory chips includes:

and reading data from the rows in sequence according to the address sequence of each row in the memory chip, wherein the reading sequence of each memory cell in the memory is consistent with the writing sequence of each memory cell in the memory.

In some embodiments, the reading data for the row includes:

Activating a word line of the row;

Sequentially reading data from each memory cell in the row;

the bit lines of the row are precharged.

In some embodiments, after the sequentially reading the data from the plurality of memory chips, the method further includes:

Performing a reverse operation on the plurality of memory chips in sequence, wherein the reverse operation of each memory chip comprises: sequentially re-writing and re-reading each storage unit in the storage chip, wherein the re-written data and the last written data are different for the same storage unit;

For each of the memory cells, determining whether the memory cell has a failure based on the data re-written to the memory cell and the data re-read from the memory cell.

In some implementations, the memory is a high bandwidth memory.

In some embodiments, the plurality of memory chips includes stacked first and second memory chips, the first and second memory chips being alternately written, and the first and second memory chips being alternately read.

In some embodiments, the first memory chip is a plurality, a plurality of the first memory chips are written in parallel, and a plurality of the first memory chips are read in parallel;

the second memory chips are plural, plural second memory chips are written in parallel, and plural second memory chips are read in parallel.

In a second aspect, an embodiment of the present disclosure provides a test apparatus for a memory, including:

The writing data module is used for sequentially writing data into a plurality of memory chips in the memory;

The data reading module is used for sequentially reading data from the plurality of memory chips after waiting for a target duration, wherein the target duration is determined according to a difference value between a preset reserved duration and a total writing duration of the plurality of memory chips, and the reserved duration is the waiting duration between writing data and reading data when the data of each memory unit is tested to be reserved and failed;

And the first fault determining module is used for determining whether the storage unit has faults according to the data written into the storage unit and the data read from the storage unit for the storage unit in the storage chip.

In some embodiments, the write data module is further to:

In some embodiments, the apparatus further comprises:

And the target duration determining module is used for dividing the reserved duration by the writing duration of the single memory chip to obtain a remainder serving as the target duration.

In some embodiments, the write data module is further to:

And in the process of writing data into each memory chip, writing data into the rows in sequence according to the address sequence of each row in the memory chip.

In some embodiments, the write data module is further to:

Activating a word line of the row;

sequentially writing data into each storage unit in the row;

the bit lines of the row are precharged.

In some embodiments, the read data module is further to:

And in the process of reading data of each memory chip, reading the data of each row in sequence according to the address sequence of each row in the memory chip, wherein the reading sequence of each memory cell in the memory is consistent with the writing sequence of each memory cell in the memory.

In some embodiments, the read data module is further to:

Activating a word line of the row;

Sequentially reading data from each memory cell in the row;

the bit lines of the row are precharged.

In some embodiments, the apparatus further comprises:

The inverse operation module is used for sequentially performing inverse operation on the memory chips after sequentially reading data from the memory chips, and the inverse operation of each memory chip comprises the following steps: sequentially re-writing and re-reading each storage unit in the storage chip, wherein the re-written data and the last written data are different for the same storage unit;

and the second fault determining module is used for determining whether the storage unit has faults according to the data which is written into the storage unit again and the data which is read from the storage unit again for each storage unit.

In some implementations, the memory is a high bandwidth memory.

In a third aspect, embodiments of the present disclosure further provide a computer readable storage medium, on which a computer program is stored, which when executed by a processor, implements the method for testing a memory of the first aspect.

In a fourth aspect, an embodiment of the present disclosure further provides an electronic device, including:

A processor; and

A memory for storing executable instructions of the processor;

Wherein the processor is configured to perform the method of testing the memory of the first aspect via execution of the executable instructions.

In a fifth aspect, embodiments of the present disclosure also provide a computer program product for performing the method of the first aspect.

The method and the device for testing the memory provided by the embodiment of the disclosure comprise the following steps: sequentially writing data into a plurality of memory chips in a memory; after waiting for a target time length, sequentially reading data from a plurality of memory chips, wherein the target time length is determined according to a difference value between a preset retention time length and a total writing time length of the plurality of memory chips, and the retention time length is a waiting time length between writing data and reading data when testing data retention faults of each memory unit; for memory cells in a memory chip, it is determined whether the memory cells have a failure based on data written to the memory cells and data read from the memory cells. When the memory includes at least two memory chips, the embodiments of the present disclosure may sequentially write data to a plurality of memory chips of the at least two memory chips, and sequentially read data to the plurality of memory chips after waiting for a target period of time. That is, data is written into one memory chip within the retention time after the writing of the other memory chip is completed, so that the retention time of the previous memory chip is fully utilized, and the test time can be saved. The target time length is determined according to the difference between the preset reserved time length and the total writing time length of the plurality of memory chips, so that the reserved time length can be fully utilized as far as possible, the actual waiting time length between writing data and reading data of each memory unit is ensured to be consistent with the reserved time length, and the testing accuracy of data reservation faults is improved.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the embodiments of the disclosure.

FIG. 1 is a schematic diagram of a memory array in a memory according to an embodiment of the disclosure;

FIG. 2 is a flow chart of steps of a method for testing a memory according to an embodiment of the present disclosure;

FIG. 3 is a detailed flow diagram of a conventional testing process provided by embodiments of the present disclosure;

FIG. 4 is a detailed flow diagram of a first write process provided by an embodiment of the present disclosure;

FIG. 5 is a detailed flow diagram of a first read process provided by an embodiment of the present disclosure;

FIG. 6 is a detailed flow chart of a re-read/write process provided by an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of a testing device for a memory according to an embodiment of the disclosure.

Specific embodiments thereof have been shown by way of example in the drawings and will herein be described in more detail. These drawings and the written description are not intended to limit the scope of the disclosed embodiment concepts in any way, but rather to illustrate the disclosed embodiment concepts to those skilled in the art by reference to the specific embodiments.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the embodiments of the present disclosure. Rather, they are merely examples of apparatus and methods consistent with aspects of embodiments of the present disclosure as detailed in the accompanying claims.

Embodiments of the present disclosure may be used in a memory that may include one or more memory arrays, each of which may include a plurality of memory cells. Thus, embodiments of the present disclosure may detect a failed storage unit (which may be referred to as a failed unit) in a memory. Fig. 1 is a schematic structural diagram of a memory array in a memory according to an embodiment of the disclosure. Referring to fig. 1, the memory array 100 includes 9 rows and 9 columns of memory cells 101, each of which may be used to store one bit of binary data, so that the memory array 100 of fig. 1 may store a maximum of 81 bits of binary data. Of course, the embodiment of the present disclosure does not limit the number of memory arrays and memory cells included in the memory arrays, and the above-described 9 rows and 9 columns of memory cells 101 are only memory cells in a small area of the memory array.

In some embodiments, for each storage unit in the memory, data may be written into the storage unit first, then the data is read from the storage unit after waiting for a preset retention period, finally whether the read data and the written data are consistent is judged, if so, it is determined that no abnormality exists in the storage unit, otherwise, it is determined that an abnormality exists in the storage unit.

It can be seen that each memory cell needs to wait for a predetermined retention period in the above-mentioned test process, and the waiting process may result in wasting test time.

In order to solve the above-mentioned problem, when the memory includes at least two memory chips, the embodiments of the present disclosure may sequentially write data to the memory cells in the plurality of memory chips of the at least two memory chips, and sequentially read data to the memory cells in the plurality of memory chips after waiting for the target period. That is, data is written into one memory chip within the retention time after the writing of the other memory chip is completed, so that the retention time of the previous memory chip is fully utilized, and the test time can be saved.

It should be noted that the target waiting time period is determined according to a difference between the preset reserved time period and the total writing time period of the plurality of memory chips. On the one hand, data can be written into as many memory chips as possible within a preset retention time period, so that the retention time period is fully utilized as much as possible. On the other hand, the actual waiting time between the writing data and the reading data of each storage unit is consistent with the reserved time, and the testing accuracy of the data reserved faults is guaranteed.

The method for testing the Memory provided by the embodiment of the disclosure belongs to an MBIST (Memory Build-In Self-Test) method, and the MBIST method is a Self-Test method In which a Test circuit is arranged inside the Memory.

Fig. 2 is a flowchart of steps of a method for testing a memory according to an embodiment of the present disclosure. Referring to fig. 2, the method for testing the memory includes:

S201: data is written to a plurality of memory chips in the memory sequentially.

Wherein a plurality of memory chips may be disposed in a memory in any manner, embodiments of the present disclosure may be applied to any memory having a plurality of memory chips. In a common example, the memory may be a high bandwidth memory (High Bandwidth Memory, HBM) that encapsulates multiple memory chips together in a stacked manner, thereby featuring a large storage capacity. Rather than being physically integrated with a CPU (central processing unit ) or GPU (graphics processing unit, graphics processing unit), the HBM has a compact and fast connection through an interposer, with higher read and write speeds and higher bandwidths. The HBM of an embodiment of the present disclosure may be HBM3.

In the embodiment of the present disclosure, a plurality of memory chips may be divided into a stacked first memory chip and second memory chip. The first memory chip and the second memory chip are alternately written, and the first memory chip and the second memory chip are alternately read.

It is understood that the first memory chip and the second memory chip are read and written in a time-sharing manner. For example, writing may be performed in the following order: first memory chip-second memory chip. Of course, the first memory chip and the second memory chip may be alternately read in the above order.

The first memory chip and the second memory chip may be understood as two kinds of memory chips, each of which may have at least one. For example, the first memory chip may be one or more, and the second memory chip may be one or more. When the first memory chips are plural, the plural first memory chips are written in parallel, and the plural first memory chips are read in parallel. When the second memory chips are plural, the plural second memory chips are written in parallel, and the plural second memory chips are read in parallel. For example, when the first memory chip is the stacked chip stack SID0 and the second memory chip is the stacked chip stack SID1, the writing order may be: parallel writing to each memory chip in the stacked chip stack SID 0-parallel writing to each memory chip in the stacked chip stack SID1, the reading order may be: parallel read for each memory chip in stacked die stack SID 0-parallel read for each memory chip in stacked die stack SID 1.

The parallel writing means that there is an overlap in writing time, and data is written at the same time in an ideal case. Similarly, parallel reading refers to the existence of overlapping read times, and ideally, the data is read simultaneously. The above-mentioned alternate writing means that there is no overlap in writing time, and alternate reading means that there is no overlap in reading time.

When the plurality of memory chips are used for writing data, two write strategies can be adopted according to different determination methods of the number of the memory chips to be written. In the first write strategy, the number of memory chips to be written continuously is predetermined to write data to the memory chips according to the number of memory chips to be written continuously. In the second write strategy, the total write time length is counted after writing one memory chip at a time, and then it is determined whether writing is continued or not. The implementation of the two write strategies described above is described in detail below.

In a first write strategy, firstly, determining the maximum number of writable chips in a preset reserved time according to the preset reserved time and the write time of a single memory chip; then, data is written sequentially to the memory chips of the maximum number of chips in the memory. It can be seen that, in the embodiment of the present disclosure, the maximum number of chips that can be written in the reserved time period may be predetermined, so that the total write time period is smaller than the reserved time period and as close to the reserved time period as possible, and the reserved time period may be fully utilized, so as to save the test time. In addition, the determination of the maximum chip number is performed before the data is written into the plurality of memory chips, so that the calculation amount in the process of writing the data into the plurality of memory chips can be reduced as much as possible, the time consumed by writing the data can be saved, and the efficiency of writing the data can be improved.

The writing time of the single memory chip can be determined through a history writing process. When the actual duration of writing data to one memory cell is T1, it can be taken as the writing duration of a single memory chip. In order to improve the accuracy of the writing time length of a single memory cell, the average writing time length of a plurality of memory cells may also be calculated as the writing time length of the single memory cell, for example, when the total time length of historical writing into N memory cells is T1, then the value obtained by T1/N may be used as the writing time length of a single memory chip, and the N memory cells may be all or part of the memory cells in one or more memory chips.

The write time length of the single memory chip may also be determined by a standard write process of the single memory chip, for example, when the standard write process includes a plurality of sub-processes, each sub-process has a standard time length, so that the standard time lengths of the plurality of sub-processes may be added to obtain the write time length of the single memory chip.

After the write-in time length of the single memory chip is obtained, an integer part of the ratio between the reserved time length and the write-in time length of the single memory chip may be taken as a maximum chip number, and the maximum chip number may be understood as a value obtained by downrounding the ratio between the reserved time length and the write-in time length of the single memory chip. For example, when the ratio between the retention period and the write-time period of a single memory chip is 2.3, the maximum chip number may be set to 2.

It can be seen that in practical applications, the ratio between the reserved time length and the write time length of a single memory chip may be a non-integer, and then the reserved time length is not reached after writing data according to the maximum number of chips. At this time, it is also necessary to wait for the target time period to reach the reserved time period. Thus, the remainder obtained by dividing the reserved period by the write period of the single memory chip can be taken as the target period, that is, the target period=the reserved period% of the write period of the single memory chip. Therefore, the sum of the total duration and the target duration of the data written into the memory chips with the maximum chip number is the preset reserved duration, the real waiting duration is ensured to be consistent with the preset reserved duration for each memory chip, and the testing accuracy can be improved. For example, when the reserved period is 32ms (millisecond), the writing period of a single memory chip is 15ms, and then the value 2ms obtained by 32%15 can be taken as the target period of waiting.

It should be noted that, when the ratio between the preset retention period and the write-in period of the single memory chip is a positive number, the target period is 0. That is, when writing data to the memory chip of the maximum chip number is ended, the retention period is reached, and at this time, data reading can be performed without waiting.

In the second write strategy, first, after writing data to each memory chip, the total write time length of one or more memory chips to which data has been written is counted; then, calculating the sum of the total writing time and the writing time of the single memory chip; finally, determining the size relation between the sum of the total writing time length and the writing time length of the single memory chip and the reserved time length, and if the sum of the total writing time length and the writing time length of the single memory chip is smaller than or equal to the reserved time length, continuing to write data into the next memory chip; and if the sum of the total writing time length and the writing time length of the single memory chip is greater than the reserved time length, stopping writing data to the next memory chip. It can be seen that the total writing time length is the actual total writing time length, whether the data is written continuously is determined according to the actual total writing time length, so that the actual waiting time length corresponding to each storage unit can be better ensured to be consistent with the preset reserved time length, and the testing accuracy is further improved.

There may be two strategies for the statistical process of the total write duration.

In a first statistical strategy of total write duration, the total write duration is initialized to 0 before writing data to the first memory chip. After data is written into one memory chip at a time, the writing time length of the memory chip can be obtained, and the sum of the writing time length of the memory chip and the total writing time length before updating is calculated to obtain the updated total writing time length.

In a second statistical strategy of total write time length, the start time is recorded when writing data to the first memory chip is started. After each writing of data to one memory chip, the difference between the current time and the start time may be calculated as the total writing duration.

When the sum of the total writing time length and the writing time length of the single memory chip is smaller than the reserved time length, the remaining time of the reserved time length is enough to be rewritten into one memory chip, and then the data can be written into the next memory chip continuously, and the reserved time length is still remained. When the sum of the total writing time length and the writing time length of the single memory chip is equal to the reserved time length, the remaining time of the reserved time length is just enough to be rewritten into one memory chip, and then the data can be written into the next memory chip continuously, and at the moment, the reserved time length is not remained. When the sum of the total writing time length and the writing time length of the single memory chip is larger than the reserved time length, the reserved time length is insufficient to write data into one memory chip, and the next memory chip needs to be stopped from continuing to write data.

For example, assume that the preset reservation period is 32ms and the write period of a single memory chip is 15ms. The total write time length at the end of writing data to the first memory chip is 14ms. It should be noted that, if the writing duration of a single memory chip is determined according to the history writing process, the total writing duration at the end of writing data into the first memory chip may be understood as the current real writing duration of one memory chip, where there may be a small difference between the current real writing duration and the writing duration of the single memory chip determined by the history writing process. Since the sum 29ms of the total write time length 14ms and the write time length 15ms of the single memory chip is smaller than the reserved time length 32ms, writing of data to the second memory chip can be continued. The total writing time length at the end of writing data to the second memory chip is 31ms, and the sum of the total writing time length 31ms and the writing time length 15ms of the single memory chip is 46ms and is larger than the reserved time length 32ms, so that the writing of data to the second memory chip is stopped.

In the embodiment of the present disclosure, a plurality of memory chips in a memory are sequentially written, that is, writing times of different memory chips are different. The data writing process of each memory chip can be to write data to the rows in sequence according to the address sequence of each row in the memory chip. The address sequence among the rows can be flexibly set, and the sequence comprises the sequence from large to small of the addresses of the rows and the sequence from small to large of the addresses of the rows. For example, if the rows in the memory chip are respectively denoted as R1 to Rn together with n rows whose addresses are arranged in order from small to large, data can be written in the following order: r1, R2, …, rn, or write data in the following order: rn, rn-1, …, R1. Because each memory cell in a row corresponds to one word line, all memory cells in the row can be continuously written after the word line is activated, so that the activation time of the word line can be saved, and further, the writing time and the testing time can be saved.

In some implementations, the following procedure of writing data needs to be performed for each row in the memory chip: first, the word line of the row is activated; then, sequentially writing data into each storage unit in the row; finally, the bit lines of the row are precharged.

Wherein each storage unit comprises a storage capacitor and a transistor. The storage capacitor is used for storing data, and the transistor is used for performing read-write control on the storage capacitor. The data in the storage capacitor can be read and written when the transistor is turned on, and the data in the storage capacitor cannot be read and written when the transistor is turned off. The word line is used for controlling the on or off of the transistor, and the transistor can be turned on by activating the word line, so that the memory cell can be read and written.

The transistors herein may be PMOS (positive CHANNEL METAL oxide semiconductor, P-channel metal oxide semiconductor) or NMOS (NEGATIVE CHANNEL METAL oxide semiconductor, N-channel metal oxide semiconductor). The NMOS has a gate-source voltage larger than a threshold voltage, and is suitable for a scene when the source is grounded. The grid source voltage of the PMOS is smaller than the threshold voltage, and the PMOS can be conducted, so that the PMOS is suitable for a scene that the source is connected with the power supply voltage. NMOS is generally used in practical applications because of the large on-resistance of PMOS.

After writing the data, the bit lines of the row may be precharged, and the corresponding command for the precharge may be used to: the activated word line is turned off and the bit line voltage is charged to VDD/2 in preparation for the next operation. Wherein VDD is the supply voltage.

S202: after waiting for a target time length, sequentially reading data from the plurality of memory chips, wherein the target time length is determined according to a difference value between a preset retention time length and a total writing time length of the plurality of memory chips, and the retention time length is a waiting time length between writing data and reading data when testing data retention faults of each memory unit.

Wherein the target time length is close to a difference between the reserved time length and a total writing time length of the plurality of memory chips, so that a time difference between writing data and reading data of each memory cell is close to the reserved time length. In an ideal case, the target period is equal to a difference between the reserved period and a total writing period of the plurality of memory chips, so that a time difference between writing data and reading data of each memory cell is equal to the reserved period.

In some embodiments, the process of reading data for each memory chip includes: and reading data from the rows in sequence according to the address sequence of each row in the memory chip. The reading sequence of each storage unit in the memory is consistent with the writing sequence of each storage unit in the memory. That is, the read order and the write order between different memory chips in the memory are identical, and the read order and the write order between different rows in the same memory chip are identical, and the read order and the write order between different memory cells in the same row are identical. Therefore, the time difference between the written data and the read data of each storage unit in the memory can be guaranteed to be uniform, and the testing accuracy can be improved. The time difference is infinitely close to the preset retention period, and ideally the time difference is equal to the retention period.

Similarly, since each memory cell in a row corresponds to one word line, all memory cells in the row can be read continuously after the word line is activated, so that the activation time of the word line can be saved, and further the reading time and the testing time can be saved.

In some embodiments, the process of reading data from the row includes: first, the word lines of the row are activated; then, sequentially reading data from each storage unit in the row; finally, the bit lines of the row are precharged. The process of activating the word line and the precharge process when reading data may refer to the foregoing process of activating the word line and precharge process when writing data, and will not be described herein.

S203: for memory cells in a memory chip, it is determined whether the memory cells have a failure based on data written to the memory cells and data read from the memory cells.

Specifically, for each memory cell, if the data written to the memory cell and the data read from the memory cell agree, it is determined that the memory cell has no failure. If the data written to the memory cell and the data read from the memory cell are inconsistent, then a failure of the memory cell is determined. In this way, it is possible to determine whether or not all the memory cells in all the memory chips in the memory have a failure in such a manner that the failed memory cells are called failed cells for repair.

The repair may be to repair the failed cell with a redundant cell in the redundant array. Specifically, a redundancy unit may be allocated to a failure unit to establish a correspondence between the redundancy unit and the failure unit, so that the failure unit may be replaced with the redundancy unit, data may be stored in the redundancy unit, and data may be read from the redundancy unit.

In some embodiments, after sequentially reading data from the plurality of memory chips, the plurality of memory chips may be further sequentially subjected to a reverse operation, where the reverse operation of each memory chip includes: sequentially re-writing and re-reading each memory cell in the memory chip, wherein the re-written data and the last written data are different for the same memory cell; then, for each of the memory cells, it is determined whether the memory cell has a failure based on the data written again to the memory cell and the data read again from the memory cell.

The re-write and re-read processes described above may include: first, for each row of memory cells in each memory chip, activating a word line of the row; then, writing and reading each memory cell again according to the sequence of the memory cells in the row; finally, the bit lines of the row are precharged.

It can be seen that when the memory is re-written and re-read, the re-writing and re-reading is continuous for the same memory cell in the memory. The embodiment of the disclosure can combine the twice writing and the twice reading to realize the twice detection of faults, namely the march 4n algorithm, and can detect more fault units by combining the march 4n algorithm, thereby further improving the test coverage rate. The re-written data is different from the data written in S201, so that the re-writing can be referred to as anti-writing, a test process of writing different data twice is implemented, whether the storage unit has a fault under the condition of different data can be tested, and further improvement of test coverage rate is facilitated.

A general test procedure and a test procedure of embodiments of the present disclosure are given below by way of example.

In a conventional test procedure, each memory cell of each memory chip in the memory needs to wait for a predetermined retention period after writing data, and then read the data. Fig. 3 is a detailed flow chart of a conventional testing process according to an embodiment of the present disclosure. Referring to fig. 3, the detailed flow of the above-described general test procedure may include steps S301 to S313.

S301: and selecting one memory chip as the current memory chip, and setting the number of the tested chips to be 0.

S302: it is determined whether the number of tested chips is less than the number of memory chips in the memory. If yes, S303 is entered, and if not, S313 is entered.

S303: the current line number is set to 1.

S304: it is determined whether the current line number is less than or equal to the maximum line number. If yes, S305 is entered, otherwise S312 is entered.

S305: and activating a word line corresponding to the current line number in the current memory chip.

S306: the current column number is set to 1.

S307: it is determined whether the current column number is less than or equal to the maximum column number. If yes, S308 is entered, otherwise S311 is entered.

S308: and writing data into the storage units corresponding to the current row number and the current column number in the current storage chip, and reading the data after waiting for the retention time.

S309: and writing back data to the storage units corresponding to the current row number and the current column number in the current storage chip, and reading the data again.

S310: the current column number is added to 1 and the process proceeds to S307.

S311: after the bit line corresponding to the current row number in the current memory chip is precharged, the current row number is added with 1, and S304 is entered.

S312: the next memory chip is taken as the current memory chip, and the number of tested chips is increased by 1 to proceed to S302.

S313: ending the test process.

It should be noted that the order between S301 to S313 may be flexibly adjusted on the basis of no mutual dependency, and the embodiment of the present disclosure does not limit the order.

From the above-mentioned common test process, the test duration of the memory is the sum of the test durations of all the memory chips, the test duration of each memory chip is the sum of the test durations of all the rows in one memory chip, and the test duration of each row is the sum of the following durations: the length of time required to activate a word line for the row, the length of time required to test each memory cell in the row, and the length of time required to perform a precharge for the row. Wherein the test duration of each memory cell comprises the sum of the following durations: the time required for writing data for the first time, the waiting reservation time, the time required for reading data for the first time, the time required for writing data again (back writing), the time required for reading data again, namely the sum of the time required for writing data for the second time, the time required for reading data for the second time and the reservation time corresponding to the storage unit. Thus, the above-described test period T1 can be calculated by the following formula:

Where Nc is the number of memory chips included in the memory, rmax is the number of rows included in each memory chip, and Cmax is the number of columns included in each memory chip. Ta is a time period required to perform one activation of a word line, tp is a time period required to perform one precharge, tw is a time period required to perform one reading of one memory cell, tr is a time period required to perform one writing of one memory cell, tt is a retention time period corresponding to each memory cell.

R is any row, and c is any column. In the embodiment of the disclosure, the testing processes of different rows are the same, so that the testing duration is the same. And, the testing process of the memory cells of different columns in the same row is also the same, so that the testing time length of the memory cells of different columns is also the same.

In the test method provided by the embodiment of the disclosure, after a plurality of memory chips are continuously written and a target period of time is waited, the plurality of memory chips are continuously read. Fig. 4 to 6 are detailed flowcharts of a testing process according to an embodiment of the present disclosure. The detailed flow of the memory test process includes the detailed flow of the first write process shown in fig. 4, the detailed flow of the first read process shown in fig. 5, and the detailed flow of the re-read process shown in fig. 6.

As shown with reference to fig. 4, the detailed flow of the first writing process described above may include steps S401 to S412.

S401: and selecting one memory chip as the current memory chip.

S402: it is determined whether the current memory chip belongs to a plurality of memory chips that are sequentially written. If yes, the process proceeds to S403, and if not, the process proceeds to S412.

Specifically, it can be determined in two ways whether or not the current memory chip belongs to a plurality of memory chips that are successively written.

In the first mode, the number of memory chips to which data has been written is initialized to 0, and the number of memory chips to which data has been written is increased by 1 between S411 and S402. If the number of memory chips of the written data is smaller than the maximum number of chips determined in the aforementioned S201, it may be determined that the current memory chip belongs to a plurality of memory chips which are sequentially written. If the number of memory chips of the written data is greater than or equal to the maximum number of chips determined in S201 described above, it may be determined that the current memory chip does not belong to the plurality of memory chips that are continuously written.

In a second approach, the total write-time length of one or more memory chips to which data has been written is counted. If the sum of the total write time length and the write time length of the single memory chip is less than or equal to the preset reserved time length, the current memory chip can be determined to belong to a plurality of memory chips which are continuously written. If the sum of the total write time length and the write time length of the single memory chip is greater than the preset reserved time length, it may be determined that the current memory chip does not belong to the plurality of memory chips for continuous writing.

S403: the current line number is set to 1.

S404: it is determined whether the current line number is less than or equal to the maximum line number. If yes, the process proceeds to S405, otherwise, the process proceeds to S411.

S405: and activating a word line corresponding to the current line number in the current memory chip.

S406: the current column number is set to 1.

S407: it is determined whether the current column number is less than or equal to the maximum column number. If yes, go to S408, otherwise go to S410.

S408: and writing data into the storage units corresponding to the current row number and the current column number in the current storage chip.

S409: the current column number is added to 1 and the process proceeds to S407.

S410: after the bit lines of the row corresponding to the current row number in the current memory chip are precharged, the current row number is added with 1, and S404 is entered.

S411: the next memory chip is taken as the current memory chip, and S402 is entered.

S412: waiting for a target duration.

After S412 is performed, the plurality of memory chips have a writing sequence, which may be used as a reference sequence for subsequent reading and writing. Thereafter, S413 may be performed to enter the first read process, and the detailed flow of the first write process described above with reference to fig. 5 may include steps S413 to S424.

S413: and selecting the first memory chip in the reference sequence as the current memory chip.

S414: it is determined whether a current memory chip is present. If yes, the process proceeds to S415, and if not, the process proceeds to S424.

S415: the current line number is set to 1.

S416: it is determined whether the current line number is less than or equal to the maximum line number. If yes, S417 is entered, otherwise S423 is entered.

S417: and activating a word line corresponding to the current line number in the current memory chip.

S418: the current column number is set to 1.

S419: it is determined whether the current column number is less than or equal to the maximum column number. If so, S420 is entered, otherwise S422 is entered.

S420: and reading data from the storage units corresponding to the current row number and the current column number in the current storage chip.

S421: the current column number is added to 1 and S419 is entered.

S422: after the bit line corresponding to the current row number in the current memory chip is precharged, the current row number is added with 1, and S416 is entered.

S423: the next memory chip in the above-described reference sequence is taken as the current memory chip, and the process proceeds to S414.

S424: the first write process is ended.

It can be seen that S425 may be performed after S424 to enter the re-read-write process, and the detailed flow of the re-read-write process described above with reference to fig. 6 may include steps S425 to S436.

S425: and selecting the first memory chip for writing data in the reference sequence as the current memory chip.

S426: it is determined whether a current memory chip is present. If yes, the process advances to S427, and if not, the process advances to S436.

S427: the current line number is set to 1.

S428: it is determined whether the current line number is less than or equal to the maximum line number. If so, S429 is entered, otherwise S435 is entered.

S429: and activating a word line corresponding to the current line number in the current memory chip.

S430: the current column number is set to 1.

S431: it is determined whether the current column number is less than or equal to the maximum column number. If yes, S432 is entered, otherwise S434 is entered.

S432: and after the data is reversely written into the memory cells corresponding to the current row number and the current column number in the current memory chip, the data is read again.

S433: the current column number is added to 1 and the process proceeds to S431.

S434: after the bit lines of the row corresponding to the current row number in the current memory chip are precharged, the current row number is added by 1, and S428 is entered.

S435: the next memory chip in the above-described reference sequence is taken as the current memory chip, and the process proceeds to S426.

S436: and ending the read-write process again.

It should be noted that the order between S401 to S436 may be flexibly adjusted on the basis of no mutual dependency, and the embodiment of the present disclosure does not limit the order.

The test duration of the memory can be analyzed from the common test process, and the test duration is the sum of the following durations: the method comprises the steps of adding up time periods for writing data into a plurality of memory chips in a memory for the first time, waiting target time periods, adding up time periods for reading data from the plurality of memory chips for the first time, and adding up time periods for reading data from and writing data into the plurality of memory chips again.

The time length of the first data writing of each memory chip is the sum of the time lengths of the data writing of all rows of the memory chip. The time length of each row of written data is the sum of the following time lengths: the length of time required to activate a word line for the row, the sum of the lengths of time to write data to each memory cell in the row, the length of time required to perform precharge for the row.

The time period for reading data for the first time for each memory chip is the sum of the time periods for reading data for all rows of the memory chip. The time length of each row of read data is the sum of the following time lengths: the length of time required to activate a word line for the row, the sum of the lengths of time required to read data for each memory cell in the row, and the length of time required to perform precharge for the row.

The time length for re-reading and writing data for each memory chip is the sum of the time lengths for re-reading and writing data for all rows of the memory chip. The time length of each row of read-write data is the sum of the following time lengths: the length of time required to activate a word line for the row, the sum of the lengths of time required to read and write data to each memory cell in the row, and the length of time required to perform precharge for the row. The time length for reading and writing data to each storage unit is the sum of the time length for writing data to one storage unit and the time length for reading data to the storage unit.

As can be seen from the above-described procedure, there is only one procedure of waiting for the target period in the test methods shown in fig. 4 to 6. For each row of each memory chip, there are the following three activated word lines: an active word line when data is written for the first time, an active word line when data is read for the first time, and an active word line when data is read and written again. Likewise, the row has the following three activated precharging times: precharge at the time of first writing data, precharge at the time of first reading data, precharge at the time of reading and writing data again. The number of writes per memory cell in the row includes two times: write data for the first time, write data again (write-back). The number of reads per memory cell in the row includes two times: the data is read for the first time and read again. Thus, for the test method of the embodiments of the present disclosure, the test duration T2 may be calculated by the following formula:

Where Ts is the target duration in S202 described above.

In some embodiments, a third test procedure may be provided that has a test duration that is between the test procedures shown in fig. 3 and fig. 4-6. In the third test flow, the first data reading process corresponding to S413 to S423 and the re-reading and writing process corresponding to S424 to S435 in the test flow shown in fig. 4 to 6 described above may be combined. Specifically, S424 to S431, and S433 are deleted, and S432 is moved between S420 and S421. This third test procedure can also be understood as: for each memory chip in the memory, the waiting reservation time in the common test flow shown in fig. 3 is shifted from between the first writing and the first reading of each memory cell to the end of the first writing of data to the memory chip, and the data needs to be written again and read again to the memory chip. At this time, the corresponding test duration may be calculated by the following formula:

As can be seen by comparing the formulas (1), (2) and (3), the retention period Tt in the formula (1) is accumulated with the rows and the columns, resulting in a larger test period T1. The reserved period Tt in the formula (3) is not accumulated with the rows and the columns, and the target period Ts in the formula (2) is not accumulated with the rows and the columns. According to experience, the retention time Tt is much longer than Ta and Tp, so that even though Ta and Tp are accumulated along with more rows, the retention time can be shortened without accumulation, and the test time of the formula (2) and the formula (3) is shorter than that of the formula (1). And the waiting time of the formula (2) is the target time Ts, and the target time Ts cannot be accumulated along with the memory chip, so that the test time of the formula (2) is shorter than the test time of the formula (3).

In some embodiments, ta=tp=12.5 ns (nanoseconds), tw=tr=2.5 ns, and the reserved period is 32ms. Further, when the memory has two memory chips and Nc is 2 as described above, and the number of rows Rmax included in each memory chip is 128×1024, and the number of columns Cmax included in each memory chip is 32, the test period T1 of the memory constituted by two memory chips is 161ms according to the formula (1), the test period T2 of the memory constituted by two memory chips is 108ms according to the formula (2), and the test period T2 is shortened by 33% than T1.

Fig. 7 is a schematic structural diagram of a testing device for a memory according to an embodiment of the disclosure. Referring to fig. 7, the memory testing apparatus 500 includes:

The write data module 501 is configured to sequentially write data to a plurality of memory chips in the memory.

The data reading module 502 is configured to sequentially read data from the plurality of memory chips after waiting for a target duration, where the target duration is determined according to a difference between a preset retention duration and a total write duration of the plurality of memory chips, and the retention duration is a waiting duration between writing data and reading data when testing a data retention failure of each memory cell.

A first failure determining module 503, configured to determine, for a memory cell in the memory chip, whether the memory cell has a failure according to data written to the memory cell and data read from the memory cell.

In some embodiments, the write data module 501 is further configured to:

And determining the maximum number of the chips which can be written in the reserved time according to the preset reserved time and the writing time of the single memory chip.

In some embodiments, the write data module 501 is further configured to:

In some embodiments, the apparatus further comprises:

In some embodiments, the write data module 501 is further configured to:

After writing data to each of the memory chips, the total write-time length of one or more memory chips to which data has been written is counted.

And if the sum of the total writing time length and the writing time length of the single memory chip is smaller than or equal to the reserved time length, continuing to write data into the next memory chip.

In some embodiments, the write data module 501 is further configured to:

The word lines of the row are activated.

And writing data into each storage unit in the row in turn.

The bit lines of the row are precharged.

In some embodiments, the read data module 502 is further configured to:

The word lines of the row are activated.

And reading data from each storage unit in the row in turn.

The bit lines of the row are precharged.

In some embodiments, the apparatus further comprises:

The inverse operation module is used for sequentially performing inverse operation on the memory chips after sequentially reading data from the memory chips, and the inverse operation of each memory chip comprises the following steps: and sequentially re-writing and re-reading each storage unit in the storage chip, wherein the re-written data is different from the last written data for the same storage unit.

In some implementations, the memory is a high bandwidth memory.

In some embodiments, the first memory chip is a plurality, a plurality of the first memory chips are written in parallel, and a plurality of the first memory chips are read in parallel; the second memory chips are plural, plural second memory chips are written in parallel, and plural second memory chips are read in parallel.

The above-described apparatus embodiments are embodiments corresponding to the foregoing method embodiments, and have the same technical effects as the method embodiments. The detailed description of the embodiment of the apparatus may refer to the detailed description of the embodiment of the method described above, and will not be repeated here.

The disclosed embodiments also provide an electronic device including a memory and at least one processor.

Wherein the memory is for storing executable instructions of the processor.

The at least one processor is configured to perform a test method implementing the aforementioned memory via execution of the executable instructions.

The embodiment of the disclosure also provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor, implements the method for testing a memory.

The embodiment of the disclosure also provides a computer program product for executing the method for testing the memory.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments.

The foregoing is only the preferred embodiments of the present disclosure, and not the patent scope of the embodiments of the present disclosure, and all equivalent structures or equivalent flow changes made by the descriptions of the embodiments of the present disclosure and the accompanying drawings, or direct or indirect application in other related technical fields, are included in the scope of the embodiments of the present disclosure.

Claims

1. A method for testing a memory, the method comprising:

Sequentially writing data into a plurality of memory chips in the memory;

2. The method of claim 1, wherein sequentially writing data to the plurality of memory chips in the memory comprises:

3. The method according to claim 2, wherein the determining the maximum number of chips writable in the reserved time period according to the preset reserved time period and the writing time period of the single memory chip includes:

4. A method according to claim 3, characterized in that the method further comprises:

5. The method of claim 1, wherein sequentially writing data to the plurality of memory chips in the memory comprises:

6. The method of any one of claims 1 to 5, wherein the process of writing data to each of the memory chips comprises:

7. The method of claim 6, wherein the writing data to the row comprises:

Activating a word line of the row;

sequentially writing data into each storage unit in the row;

the bit lines of the row are precharged.

8. The method of claim 7, wherein the process of reading data from each of the memory chips comprises:

9. The method of claim 8, wherein the reading data for the row comprises:

Activating a word line of the row;

Sequentially reading data from each memory cell in the row;

the bit lines of the row are precharged.

10. The method of claim 9, wherein after sequentially reading data from the plurality of memory chips, further comprising:

11. The method according to any one of claims 1 to 10, wherein the memory is a high bandwidth memory.

12. The method of claim 11, wherein the plurality of memory chips comprises stacked first and second memory chips, the first and second memory chips being alternately written to, and the first and second memory chips being alternately read from.

13. The method of claim 12, wherein the first memory chips are a plurality, the plurality of first memory chips are written in parallel, and the plurality of first memory chips are read in parallel;

14. A memory testing apparatus, comprising:

15. A computer readable storage medium having stored thereon a computer program, characterized in that the computer program, when executed by a processor, implements the method of testing a memory according to any of claims 1 to 13.

16. An electronic device, comprising:

A processor; and

A memory for storing executable instructions of the processor;

Wherein the processor is configured to perform the method of testing the memory of any one of claims 1 to 13 via execution of the executable instructions.