CN117995252A

CN117995252A - Circuit testing method and device

Info

Publication number: CN117995252A
Application number: CN202211349628.3A
Authority: CN
Inventors: 史腾
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-10-31
Filing date: 2022-10-31
Publication date: 2024-05-07

Abstract

The disclosure provides a circuit testing method and device, which relate to the technical field of semiconductors and comprise the following steps: accessing a plurality of first row addresses preselected in a memory for multiple times, and recording the Bank information and the first row addresses accessed each time; wherein the probabilities of the first row addresses being accessed are different; monitoring row hammering refreshing operation of the RHR circuit, and recording the Bank information and the first row address corresponding to each row hammering refreshing operation; based on the recorded information, the access times and row hammering refreshing times of each first row address in each Bank are counted, so that whether the RHR circuit can accurately capture each row address which is repeatedly accessed by high frequency can be determined, the working efficiency of the RHR circuit is further determined, and a basis is provided for improving the RHR circuit.

Description

Circuit testing method and device

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a circuit testing method and apparatus.

Background

As the density of memories increases, the data lines in their memory cells become physically closer, thereby causing the capacitive coupling between adjacent data lines to increase gradually. When a Row (Row) address is repeatedly accessed at a high frequency, data on a data line near the Row address is likely to be abnormal, and this phenomenon is commonly called Row Hammer (Row Hammer).

In order to solve the above problems, some conventional semiconductor memory devices add a Row hammer refresh (Row HAMMER REFRESH, RHR) circuit for additionally refreshing data lines near a Row address that is repeatedly accessed at a high frequency, so as to protect data.

The working efficiency of the RHR circuit determines whether the RHR circuit can accurately capture the row address repeatedly accessed by high frequency, so how to test the working efficiency of the RHR circuit is a technical problem that needs to be solved at present.

Disclosure of Invention

The present disclosure provides a circuit testing method and apparatus, which can effectively detect the working efficiency of an RHR circuit.

In a first aspect, an embodiment of the present disclosure provides a circuit testing method applied to a memory, where the memory is provided with an RHR circuit, the method including:

Accessing a plurality of first row addresses preselected in the memory for a plurality of times, and recording the Bank information and the first row addresses accessed each time; wherein the probabilities of each first row address being accessed are different;

monitoring row hammering refreshing operation of the RHR circuit, and recording the Bank information and the first row address corresponding to each row hammering refreshing operation;

counting the access times and row hammering refreshing times of each first row address in each Bank based on recorded Bank information and first row addresses of each access and Bank information and first row addresses corresponding to each row hammering refreshing operation;

And determining the working efficiency of the RHR circuit according to the access times and the row hammering refreshing times of each first row address in each Bank.

In a possible embodiment, the method further includes:

Every n tREFI, executing n preset refreshing operations on the memory; wherein n is more than or equal to 1 and less than or equal to 9.

In a possible implementation manner, the n is equal to or less than 2 and equal to or less than 9, and the performing n preset refresh operations on the memory every n tREFI includes:

and continuously executing n preset refreshing operations on the memory every n tREFI.

In one possible implementation, the preset refresh operation is a full memory bank refresh operation.

In a possible implementation, before the accessing the preselected first row addresses in the memory multiple times, the method further includes:

And randomly selecting a plurality of row addresses from the memory as the first row addresses.

In a possible embodiment, the accessing the preselected first row addresses in the memory a plurality of times includes:

Accessing each of the first row addresses in the memory, and after each access to one of the first row addresses, randomly accessing a second row address in the memory other than the first row address.

In a possible implementation manner, the determining the working efficiency of the RHR circuit according to the access times and the row hammering refresh times of each first row address in each Bank includes:

Taking the access times and the row hammering refreshing times of the same first row address in the same Bank as a judging array, and determining whether each judging array meets preset conditions or not; the preset condition is that the access times of the same first row address in the same Bank are larger than a preset first time threshold value, and the row hammering refresh times in the same Bank are preset values or smaller than a preset second time threshold value;

Determining the working efficiency of the RHR circuit according to the number of the judgment arrays meeting the preset conditions; the working efficiency of the RHR circuit is inversely proportional to the number of the judgment arrays meeting the preset condition.

In a second aspect, embodiments of the present disclosure provide a circuit testing apparatus for use with a memory provided with RHR circuitry, the apparatus comprising:

the access module is used for accessing a plurality of first row addresses preselected in the memory for a plurality of times and recording the Bank information and the first row addresses accessed each time; wherein the probabilities of each first row address being accessed are different;

the monitoring module is used for monitoring row hammering refreshing operation of the RHR circuit and recording the corresponding Bank information and the first row address of each row hammering refreshing operation;

The statistics module is used for counting the access times and the row hammering refreshing times of each first row address in each Bank based on recorded Bank information and first row addresses accessed each time and Bank information and first row addresses corresponding to each row hammering refreshing operation;

and the processing module is used for determining the working efficiency of the RHR circuit according to the access times and the row hammering refreshing times of each first row address in each Bank.

In a possible implementation manner, the device further comprises a refresh module, configured to:

In a possible implementation manner, n is equal to or less than 2 and equal to or less than 9, and the refreshing module is specifically configured to:

In a possible implementation manner, the method further comprises a selection module for:

In a possible embodiment, the access module is specifically configured to:

In a possible embodiment, the processing module is specifically configured to:

In a third aspect, an embodiment of the present disclosure provides an electronic device, including: at least one processor and memory;

The memory stores computer-executable instructions;

The at least one processor executes computer-executable instructions stored by the memory, causing the at least one processor to perform the circuit testing method as provided in the first aspect.

In a fourth aspect, embodiments of the present disclosure provide a computer-readable storage medium having stored therein computer-executable instructions that, when executed by a computer, implement a circuit testing method as provided in the first aspect.

In a fifth aspect, embodiments of the present disclosure provide a computer program product comprising a computer program which, when executed by a computer, implements a circuit testing method as provided in the first aspect.

The circuit testing method and device provided by the embodiment of the disclosure comprise the following steps: accessing a plurality of first row addresses preselected in a memory for multiple times, and recording the Bank information and the first row addresses which are accessed each time and the Bank information and the first row addresses which correspond to each row hammering refreshing operation of the RHR circuit; based on the recorded information, the access times and the row hammering refreshing times of each first row address in each Bank are counted, and according to the access times and the row hammering refreshing times of each first row address in each Bank, whether the RHR circuit can accurately capture each row address repeatedly accessed by high frequency can be determined, so that the working efficiency of the RHR circuit is determined, and a basis is provided for improving the RHR circuit.

Drawings

FIG. 1 is a schematic layout diagram of a memory according to an embodiment of the disclosure;

fig. 2 is a schematic structural diagram of a memory cell of a memory according to an embodiment of the disclosure;

FIG. 3 is a flowchart illustrating a circuit testing method according to an embodiment of the present disclosure;

FIG. 4 is a second flowchart illustrating a circuit testing method according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a program module of a circuit testing apparatus according to an embodiment of the disclosure;

fig. 6 is a schematic hardware structure of an electronic device according to an embodiment of the disclosure.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are some embodiments of the present disclosure, but not all embodiments. Based on the embodiments in this disclosure, all other embodiments that a person of ordinary skill in the art would obtain without making any inventive effort are within the scope of protection of this disclosure. Furthermore, while the disclosure has been presented by way of example only, it should be appreciated that various aspects of the disclosure may be separately implemented in a complete embodiment.

It should be noted that the brief description of the terms in the present disclosure is only for convenience in understanding the embodiments described below, and is not intended to limit the embodiments of the present disclosure. Unless otherwise indicated, these terms should be construed in their ordinary and customary meaning.

The terms first, second and the like in the description and in the claims and in the above-described figures are used for distinguishing between similar or similar objects or entities and not necessarily for describing a particular sequential or chronological order, unless otherwise indicated. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the disclosure are, for example, capable of operation in sequences other than those illustrated or otherwise described herein.

Furthermore, the terms "comprise" and "have," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a product or apparatus that comprises a list of elements is not necessarily limited to those elements expressly listed, but may include other elements not expressly listed or inherent to such product or apparatus.

The term "module" as used in the embodiments of the present disclosure refers to any known or later developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware or/and software code that is capable of performing the function associated with that element.

The embodiment of the disclosure relates to the technical field of semiconductor memories, and can be applied to chip design of dynamic random access memories (Dynamic Random Access Memory, DRAM) by way of example, and comprises the steps of detecting the working efficiency of an RHR circuit and providing a basis for upgrading and improving the RHR circuit.

In some embodiments, the memory includes a plurality of Bit Lines (BL), a plurality of Word Lines (WL), and a plurality of memory cells, wherein each memory cell is connected to a corresponding one of the WL's and one of the BL's.

In some embodiments, taking DRAM as an example, to increase the capacity, the existing DRAM is internally composed of a plurality of banks, and each Bank is placed in a memory according to a certain order. The memory controller of the CPU accesses each Bank inside the DRAM with the ID of the Bank as address information.

Referring to fig. 1, fig. 1 is a schematic layout diagram of a memory according to an embodiment of the disclosure.

Taking one Bank in DRAM as an example, the plurality of bit lines may be divided into 128 bit line groups, each having 8 bit lines therein, and the bit lines in each bit line group are designated as BL0, BL1, BL2 … … BL7 for convenience of description below. The plurality of word lines may be divided into 8192 word line groups, each having 8 word lines therein, and the bit lines in each of the bit line groups are designated WL0, WL1, WL2 … … WL7 for convenience of description below.

The plurality of memory cells P11-P88 are distributed in a matrix, wherein the memory cells in the first column are all connected with a word line WL0, the memory cells in the second column are all connected with a word line WL1, and the memory cells in the eighth column are all connected with a word line WL7 by analogy; the memory cells of the first row are all connected to bit line BL0, the memory cells of the second row are all connected to bit line BL1, and so on, the memory cells of the eighth row are all connected to bit line BL7, so that each memory cell is connected to one WL and one BL.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a memory cell of a memory according to an embodiment of the disclosure.

In some embodiments, each memory cell 10 includes a transistor 12 and a capacitor 11, where the gate of the transistor 12 is connected to WL, the source of the transistor 12 is connected to BL, the drain of the transistor 12 is connected to the capacitor 11, and it should be noted that the source of the transistor 12 may also be connected to the capacitor 11, and accordingly, the drain of the transistor 12 is connected to BL.

In some embodiments, BL may write a high signal "1" to storage capacitor C when the signal on WL turns on switching transistor T, and the charge on storage capacitor C slowly leaks over time after the signal on WL turns off switching transistor T. The time between the leakage of the storage capacitor C from the high level signal '1' to the low level signal '0' is the data storage time of the storage capacitor C. The data storage time of the storage capacitor C needs to be longer than a preset time to realize the dynamic storage function of the dynamic random access memory.

As the density of memory increases, the word lines in its memory cells are physically closer, thereby causing the capacitive coupling between adjacent WLs to increase gradually. When a Row (Row) address is repeatedly accessed at high frequency, data on a data line near the Row address is likely to be abnormal, which is often called Row hammering, and this is often used as a system attack means.

In order to protect data stored in the memory, some existing memories are added with RHR circuits for additionally refreshing data lines near row addresses repeatedly accessed at high frequency, so as to achieve the purpose of protecting the data.

The RHR circuit can continuously capture the accessed row address, randomly store some row addresses with higher occurrence frequency in a certain register, and calculate the nearby data line address according to the row address (or called as a seed address) stored in the register when the row hammering refreshing time (the memory automatically performs row hammering refreshing after refreshing for a certain times) arrives, so as to perform refreshing action.

The RHR circuit aims at resisting potential risks caused by high-frequency access to the same row address, and the mode for eliminating the risks is to accurately find the row address accessed by high frequency and refresh the peripheral data lines, so that the row address accessed by high frequency can be positioned faster, and the higher the working efficiency of the RHR circuit is.

At present, a plurality of test schemes and methods for preventing the memory from being attacked are provided at the system level, but a method for testing and evaluating the RHR circuit in the circuit design process is lacking, so that a test method is needed to detect whether the RHR circuit can accurately capture the row address repeatedly accessed by high frequency under the condition that the number of simulation samples is enough, and the working efficiency of the RHR circuit can be evaluated based on the detection result, thereby providing a basis for updating and changing the RHR circuit.

In view of the above technical problems, an embodiment of the present disclosure provides a circuit testing method, which accesses a plurality of first row addresses preselected in a memory for a plurality of times, and records Bank information and the first row addresses accessed each time, and Bank information and the first row addresses corresponding to each row hammering refresh operation of an RHR circuit; based on the recorded information, the access times and row hammering refreshing times of each first row address in each Bank are counted, so that whether the RHR circuit can accurately capture each row address which is repeatedly accessed by high frequency can be determined, the working efficiency of the RHR circuit is further determined, and a basis is provided for improving the RHR circuit. Reference is made to the following examples for details.

Referring to fig. 3, fig. 3 is a schematic step flow diagram of a circuit testing method according to an embodiment of the disclosure. In some embodiments of the present disclosure, the above-described circuit testing method is applied to a memory provided with an RHR circuit, including:

S301, accessing a plurality of first row addresses preselected in a memory for multiple times, and recording the Bank information and the first row addresses accessed each time; wherein the probabilities of the respective first row addresses being accessed are not the same.

In a possible implementation manner, a plurality of row addresses may be randomly selected in the memory in advance as the first row addresses to be attacked, and the total number of times each first row address is accessed in the whole test process is different by configuring different access probabilities for each first row address.

For example, 10 row addresses may be pre-selected as the first row addresses that are attacked, and different access probabilities may be configured for each first row address.

In some embodiments, the above-described number of first row addresses may be repeatedly accessed a number of times over a period of time, with the probability that each first row address is accessed, and with the likelihood that each first row address is captured by the RHR circuit.

For example, assuming that the RHR circuit captures a row address having a number of accesses exceeding m times within a period of time t as a "seed address", when the access probability of the first row address having the smallest access probability among the plurality of first row addresses is 5%, the total number of accesses to the plurality of first row addresses within the period of time t needs to be greater than m/5%.

In one possible embodiment, each time an access operation is performed, the Bank information and the first row address of the current access are recorded. For example, the Bank information and the first row address of each access may be added in a specified file.

S302, monitoring row hammering refreshing operation of the RHR circuit, and recording the Bank information and the first row address corresponding to each row hammering refreshing operation.

In a possible implementation manner, the row hammering refresh operation of the RHR circuit may be monitored in real time, and when the RHR circuit performs the row hammering refresh operation each time, the Bank information corresponding to the current row hammering refresh operation and the first row address are recorded. For example, the Bank information corresponding to each row hammer refresh operation and the first row address (seed address) may be added in the specified file.

S303, counting the access times and the row hammering refresh times of each first row address in each Bank based on the recorded Bank information and the first row address of each access and the Bank information and the first row address corresponding to each row hammering refresh operation.

In a possible implementation manner, the specified file may be scanned line by line, an item conforming to the format of < Row address+bank information+rhr/ACTIVE > is searched for by a format matching function of the scripting language, and is stored as a specific element in the hash table, and if the element is matched again in the scanning process, the element is accumulated, after the specified file is traversed, all the elements in the hash table are output according to a fixed format, a table file is generated, and based on the table file, the access times of each first Row address in each Bank and the Row hammering refresh times can be obtained.

Wherein ACTIVE indicates that the row address is accessed.

For example, referring to table 1, table 1 is a schematic table of the number of accesses of each first row address at each Bank and the number of row hammer refresh times.

Table 1: access times and row hammering refresh times of each row address in each Bank are shown schematically

In table 1, the first column represents 5 first row addresses selected in advance, bank ACT represents the number of times a row address is accessed at Bank, and Bank RHR represents the number of times a row address is accessed at Bank. For example, in table 1, the number of accesses and row hammer refresh times of the row address "RowAddr fff" in Bank0 are 4917 times and 12 times, respectively, and the number of accesses and row hammer refresh times of the row address "RowAddr fff" in Bank1 are 4970 times and 17 times, respectively.

Wherein, since the probability that each first row address is accessed is different, the number of accesses of each first row address in each Bank is also different.

S304, according to the access times and the row hammering refreshing times of each first row address in each Bank, the working efficiency of the RHR circuit is determined.

In one possible implementation, the operating efficiency of the RHR circuit may be determined according to whether the access times and row hammer refresh times of each first row address at each Bank meet the row hammer refresh expectations.

For example, suppose a row hammer refresh is expected to be: when the number of accesses to the same row address exceeds 800 in a period of time, at least one row hammering refresh is required to be performed on the data lines near the row address. Referring to table 1, since the access frequency of the row address "RowAddr" in Bank0 is 974 times and the row hammering refresh frequency is 0 times, the access frequency of the row address "RowAddr" in Bank2 is 937 times and the row hammering refresh frequency is 0 times, it can be determined that the RHR circuit cannot accurately capture the row address which is repeatedly accessed at high frequency, and the working efficiency of the RHR circuit needs to be improved.

According to the circuit testing method provided by the embodiment of the disclosure, a plurality of first row addresses preselected in a memory are accessed for a plurality of times, and the Bank information and the first row addresses which are accessed each time and the Bank information and the first row addresses which correspond to each row hammering refreshing operation of the RHR circuit are recorded; based on the recorded information, the access times and the row hammering refreshing times of each first row address in each Bank are counted, and according to the access times and the row hammering refreshing times of each first row address in each Bank, whether the RHR circuit can accurately capture each row address repeatedly accessed by high frequency can be determined, so that the working efficiency of the RHR circuit is determined, and a basis is provided for improving the RHR circuit.

Based on the descriptions in the above embodiments, referring to fig. 4, fig. 4 is a second schematic step flow diagram of a circuit testing method according to an embodiment of the disclosure. In some embodiments of the present disclosure, the circuit testing method includes:

S401, randomly selecting a plurality of row addresses in a memory as first row addresses.

S402, accessing each first row address for a plurality of times, and after each first row address is accessed, randomly accessing a second row address except the first row addresses in a memory; and when each access to the first row address, recording the Bank information and the first row address of each access.

Wherein the probabilities of each of the first row addresses being accessed are different.

In some embodiments, each time according to the probability that each first row address is accessed, a first row address is accessed randomly, and then a second row address except the first row addresses is accessed randomly, so that the cycle is performed, the discreteness of address access can be increased, the testing pressure of the RHR circuit can be increased, and the testing accuracy can be improved.

It can be understood that for the memory, the more row addresses are attacked in the same time period, the more the accesses are scattered, the more pressure is applied to the RHR circuit, so that different access probabilities are allocated to a plurality of selected first row addresses, the plurality of first row addresses only occupy half of the access amount, and the other half of the access amount randomly accesses other remaining effective row addresses, thereby disturbing the efficiency of the RHR circuit for acquiring the attacked row addresses and testing the compression resistance of the RHR circuit.

In some embodiments, in the process of accessing the row address in the memory, n preset refresh operations may be performed on the memory every n refresh interval durations tREFI; wherein n is more than or equal to 1 and less than or equal to 9.

In the example of DRAM, the DRAM is a volatile memory, and the charge of the capacitor in the memory cell is gradually lost, so in order to maintain the integrity of data, the DRAM needs to refresh the row address of one Bank or a plurality of banks at intervals. The DRAM has a plurality of Refresh modes, the most basic is Refresh command of All banks, at this time, the ACT pin is in high level to pressurize All banks, activate All row addresses in the banks, and simultaneously has SELF REFRESH states, activate the row addresses in a single Bank, if a certain row address in the Bank is in an active state (in work), then the column address is activated to read out and write back, thus completing the Refresh task.

Where tRFC (Row REFRESH CYCLE TIME) is the Row address refresh period, defining the period time required to refresh all Bank Row addresses. Higher tRFC values can enhance memory stability, but higher tRFC values can affect memory read and write performance to a small extent, significantly affect memory latency, and longer refresh cycles can cause read and write tasks to be shifted backwards, thus resulting in increased memory latency.

TREFI is the memory refresh interval, i.e., the interval between the completion of tRFC and the next refresh cycle. Compared with tRFC, tREFI affects read-write performance more significantly, but tREFI affects memory stability more significantly, and too high or too low can easily cause memory data loss.

In some embodiments, the memory generally has two refresh strategies as follows:

One of the most common None-postponed modes, i.e. refresh every tREFI, during which normal operation can be performed, the other mode, postponed mode, allows refresh operations for the longest 9 tREFI intervals, but requires 9 consecutive refreshes.

Alternatively, when n=2, 1 preset refresh operation may be performed on the memory every 1 tREFI; when 2.ltoreq.n.ltoreq.9, the preset refresh operation may be consecutively performed on the memory n times every n tREFI, for example, every 9 tREFI times.

Alternatively, the preset refresh operation may be an all bank refresh (all bank refresh) operation.

S403, monitoring row hammering refreshing operation of the RHR circuit, and recording the Bank information and the first row address corresponding to each row hammering refreshing operation.

S404, based on the recorded Bank information and first row addresses of each access and the Bank information and first row addresses corresponding to each row hammering refreshing operation, the access times and row hammering refreshing times of each first row address in each Bank are counted.

S405, according to the access times and the row hammering refreshing times of each first row address in each Bank, the working efficiency of the RHR circuit is determined.

In some embodiments, the number of accesses and the number of row hammering refreshes of the same first row address in the same Bank are used as a judgment array, and whether each judgment array meets a preset condition is determined; determining the working efficiency of the RHR circuit according to the number of the judgment arrays meeting the preset conditions; the working efficiency of the RHR circuit is inversely proportional to the number of the judgment arrays meeting the preset conditions. The preset condition is that the access times of the same first row address in the same Bank are larger than a preset first time threshold value, and the row hammering refresh times in the same Bank are preset values or smaller than a preset second time threshold value.

For example, if the number of accesses of the same row address in the same Bank is greater than 800 and the number of row hammering refreshes in the same Bank is 0, the judgment array corresponding to the row address may be considered to be (800,0), and the judgment array satisfies the above preset condition.

According to the circuit testing method provided by the embodiment of the disclosure, a plurality of first row addresses preselected in a memory are accessed for a plurality of times, and the Bank information and the first row addresses which are accessed each time and the Bank information and the first row addresses which correspond to each row hammering refreshing operation of the RHR circuit are recorded; based on the recorded information, the access times and row hammering refreshing times of each first row address in each Bank are counted, and based on the access times and the row hammering refreshing times, whether the RHR circuit can accurately capture each row address which is repeatedly accessed by high frequency can be determined, so that the working efficiency of the RHR circuit is determined, and a basis is provided for improving the RHR circuit.

Based on what is described in the above embodiments, a circuit testing device is also provided in the embodiments of the disclosure. Referring to fig. 5, fig. 5 is a schematic diagram of a program module of a circuit testing apparatus provided in an embodiment of the disclosure, and the circuit testing apparatus 50 includes:

An access module 501, configured to access a plurality of first row addresses preselected in the memory for multiple times, and record the Bank information and the first row addresses accessed each time; wherein the probabilities of each of the first row addresses being accessed are different.

The monitoring module 502 is configured to monitor a row hammering refresh operation of the RHR circuit, and record Bank information and a first row address corresponding to each row hammering refresh operation.

A statistics module 503, configured to count the number of accesses and the number of row hammering refreshes of each first row address in each Bank based on the recorded Bank information and the first row address for each access, and the Bank information and the first row address corresponding to each row hammering refresh operation.

And a processing module 504, configured to determine the working efficiency of the RHR circuit according to the access times and the row hammering refresh times of each Bank of each first row address.

According to the circuit testing device provided by the embodiment of the disclosure, a plurality of first row addresses preselected in a memory are accessed for a plurality of times, and the Bank information and the first row addresses which are accessed each time and the Bank information and the first row addresses which correspond to each row hammering refreshing operation of the RHR circuit are recorded; based on the recorded information, the access times and the row hammering refreshing times of each first row address in each Bank are counted, and according to the access times and the row hammering refreshing times of each first row address in each Bank, whether the RHR circuit can accurately capture each row address repeatedly accessed by high frequency can be determined, so that the working efficiency of the RHR circuit is determined, and a basis is provided for improving the RHR circuit.

In one possible implementation, the access module 501 is specifically configured to:

In one possible implementation, the processing module 504 is specifically configured to:

It should be noted that, in the embodiment of the disclosure, the specific execution of the access module 501, the monitoring module 502, the statistics module 503, and the processing module 504 may refer to the relevant content in the embodiment shown in fig. 3 to 4, which is not described herein.

Further, based on what is described in the foregoing embodiments, there is also provided in an embodiment of the disclosure an electronic device including at least one processor and a memory; wherein the memory stores computer-executable instructions; the at least one processor executes computer-executable instructions stored in the memory to implement the steps in the circuit testing method as described in the above embodiment, which is not described herein.

For a better understanding of the embodiments of the present disclosure, referring to fig. 6, fig. 6 is a schematic hardware structure of an electronic device according to an embodiment of the present disclosure.

As shown in fig. 6, the electronic device 60 of the present embodiment includes: a processor 601 and a memory 602; wherein:

a memory 602 for storing computer-executable instructions;

The processor 601 is configured to execute computer-executable instructions stored in the memory to implement the steps of the circuit testing method described in the foregoing embodiments, and specific reference may be made to the description of the foregoing method embodiments.

In some embodiments, the memory 602 may be separate or integrated with the processor 601.

When the memory 602 is provided separately, the device further comprises a bus 603 for connecting the memory 602 and the processor 601.

Further, based on the descriptions in the foregoing embodiments, a computer-readable storage medium is further provided in the embodiments of the present disclosure, where computer-executable instructions are stored in the computer-readable storage medium, and when the processor executes the computer-executable instructions, the steps in the circuit testing method described in the foregoing embodiments are implemented, which is not described herein again.

Further, based on the descriptions in the foregoing embodiments, a computer program product is further provided in the embodiments of the present disclosure, where the computer program is executed by a processor to implement each step in the circuit testing method as described in the foregoing embodiments, and this embodiment is not described herein again.

In the several embodiments provided in the present disclosure, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the above-described division of modules is merely a logical function division, and there may be other manners of division in actual implementation, for example, multiple modules may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or modules, which may be in electrical, mechanical, or other forms.

The modules described above as separate components may or may not be physically separate, and components shown as modules may or may not be physical units, may be located in one place, or may be distributed over multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional module in the embodiments of the present disclosure may be integrated in one processing unit, or each module may exist alone physically, or two or more modules may be integrated in one unit. The integrated units of the modules can be realized in a form of hardware or a form of hardware and software functional units.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present disclosure, and not for limiting the same; although the present disclosure has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A circuit testing method, characterized by being applied to a memory provided with a row hammer refresh RHR circuit, the method comprising:

Accessing a plurality of first row addresses preselected in the memory for a plurality of times, and recording the Bank information and the first row addresses of the memory accessed each time; wherein the probabilities of each first row address being accessed are different;

2. The circuit testing method of claim 1, further comprising:

Executing n preset refreshing operations on the memory every n refreshing interval time tREFI; wherein n is more than or equal to 1 and less than or equal to 9.

3. The circuit testing method of claim 2, wherein 2 n is equal to or less than 9, and wherein the performing n preset refresh operations on the memory every n tREFI comprises:

4. The circuit testing method of claim 3, wherein the preset refresh operation is a full memory bank refresh operation.

5. The circuit testing method of claim 1, wherein prior to said accessing a preselected number of first row addresses in said memory a plurality of times, further comprising:

6. The circuit testing method of any one of claims 1 to 5, wherein said accessing a preselected number of first row addresses in said memory a plurality of times comprises:

7. The circuit testing method according to claim 1, wherein determining the operating efficiency of the RHR circuit according to the access times and the row hammer refresh times of each first row address in each Bank comprises:

8. A circuit testing device for use with a memory, the memory being provided with RHR circuitry, the device comprising:

9. The circuit testing device of claim 8, further comprising a refresh module to:

10. The circuit testing device of claim 9, wherein 2 n is less than or equal to 9, and wherein the refresh module is specifically configured to:

11. The circuit testing device of claim 10, wherein the preset refresh operation is a full memory bank refresh operation.

12. The circuit testing device of claim 8, further comprising a selection module configured to:

13. Circuit testing device according to any of claims 8 to 12, wherein said access module is specifically configured to:

14. The circuit testing device of claim 8, wherein the processing module is specifically configured to:

15. An electronic device, comprising: at least one processor and memory;

The memory stores computer-executable instructions;

The at least one processor executing computer-executable instructions stored in the memory causes the at least one processor to perform the circuit testing method of any one of claims 1 to 7.

16. A computer-readable storage medium having stored therein computer-executable instructions that, when executed by a computer, implement the circuit testing method of any one of claims 1 to 7.

17. A computer program product comprising a computer program, characterized in that the computer program, when executed by a computer, implements the circuit testing method of any of claims 1 to 7.