CN117995081A - Clock signal supply circuit and display device - Google Patents
Clock signal supply circuit and display device Download PDFInfo
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- CN117995081A CN117995081A CN202211323890.0A CN202211323890A CN117995081A CN 117995081 A CN117995081 A CN 117995081A CN 202211323890 A CN202211323890 A CN 202211323890A CN 117995081 A CN117995081 A CN 117995081A
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Abstract
The invention provides a clock signal providing circuit and a display device. The clock signal providing circuit comprises an inductance circuit, a voltage clamping circuit and a clock signal output end for providing an output clock signal; the first end of the inductance circuit is electrically connected with a clock signal source for providing an input clock signal, and the second end of the inductance circuit is electrically connected with the clock signal output end; the voltage clamping circuit is electrically connected with the clamping end and is used for clamping the potential of the clamping end so that the potential of the clamping end is smaller than or equal to a voltage value threshold; the clamping end is electrically connected with the second end of the inductance circuit or the clock signal output end. The voltage clamping circuit is used for clamping the potential of the clamping end, so that the potential of the clamping end is smaller than or equal to the voltage value threshold, the potential of the output clock signal is not too high, and the threshold voltage characteristic of the output transistor in the corresponding driving circuit is not too fast caused.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a clock signal providing circuit and a display device.
Background
In the related art, TV (television) products tend to have high resolution, high refresh rate. However, as the size of the display product becomes larger, the resolution becomes higher, and the charging rate is required to be higher. The larger the Panel size is, the higher the source and drain loads of the transistors in the pixel circuit are, the higher the voltage of the required Gate driving signal is, the higher the voltage rising speed and the voltage falling speed are, in order to increase the rising time Tr and the falling time Tf of the Gate driving signal, the inductors can be connected in series before the clock signal enters the Panel, and the characteristics that the energy storage of the inductors is far away and the voltage cannot be suddenly changed are utilized, so that the potential of the clock signal generates overcharge voltage when rising and falling, thereby increasing the rising time and the falling time of the driving signal output by a GOA (Gate On Array) circuit, and increasing the charging rate. However, too high an overcharge voltage of the clock signal tends to cause the characteristics of the output transistors in the GOA circuit to drift too fast, resulting in a shortened display product lifetime.
Disclosure of Invention
The invention mainly aims to provide a clock signal providing circuit and a display device, which solve the problem that the threshold voltage characteristics of output transistors in corresponding driving circuits drift too fast due to the fact that the overcharge voltage exists when the potential of a clock signal rises in the prior art.
The embodiment of the invention provides a clock signal providing circuit, which comprises an inductance circuit, a voltage clamping circuit and a clock signal output end for providing an output clock signal;
The first end of the inductance circuit is electrically connected with a clock signal source for providing an input clock signal, and the second end of the inductance circuit is electrically connected with the clock signal output end;
The voltage clamping circuit is electrically connected with the clamping end and is used for clamping the potential of the clamping end so that the potential of the clamping end is smaller than or equal to a voltage value threshold;
The clamping end is electrically connected with the second end of the inductance circuit or the clock signal output end.
Optionally, the clock signal providing circuit according to at least one embodiment of the present invention further includes a resistor circuit;
The second end of the inductance circuit is electrically connected with the clock signal output end through the resistance circuit.
Optionally, the clock signal providing circuit according to at least one embodiment of the present invention further includes a resistor circuit;
the first end of the inductance circuit is electrically connected with the clock signal source through the resistance circuit.
Optionally, the voltage clamping circuit includes a varistor;
The first end of the piezoresistor is electrically connected with the clamping end, and the second end of the piezoresistor is electrically connected with the first voltage end.
Optionally, the voltage-sensitive voltage of the piezoresistor and the breakdown voltage of the piezoresistor are greater than the voltage value threshold;
A voltage difference between the voltage-sensitive voltage and the voltage value threshold is greater than or equal to 1V and less than or equal to 3V, and a voltage difference between the breakdown voltage and the voltage value threshold is greater than or equal to 4V and less than or equal to 6V;
The first voltage terminal is a ground terminal.
Optionally, the voltage clamping circuit includes a TVS diode;
the anode of the TVS diode is electrically connected with the clamping end, and the cathode of the TVS diode is electrically connected with the first voltage end.
Optionally, the voltage clamp circuit includes an ESD resistor;
the first end of the ESD resistor is electrically connected with the clamping end, and the second end of the ESD resistor is electrically connected with the first voltage end.
Optionally, the first voltage terminal is a dc voltage terminal.
The embodiment of the invention also provides a display device which comprises the clock signal providing circuit.
Optionally, the display device according to at least one embodiment of the present invention further includes a clock signal source and a driving circuit;
The clock signal source is used for providing an input clock signal to the clock signal providing circuit;
The driving circuit is electrically connected with a clock signal output end included in the clock signal providing circuit and is used for receiving an output clock signal and generating a driving signal according to the output clock signal.
Optionally, the display device according to at least one embodiment of the present invention further includes a circuit board;
the clock signal providing circuit is arranged on the circuit board.
Optionally, the clock signal source includes a timing controller and a level shifter;
The timing controller is used for providing a reference clock signal for the level converter;
the level shifter is used for carrying out level conversion on the reference clock signal to obtain an input clock signal;
The time schedule controller and the level shifter are arranged on the circuit board.
According to the embodiment of the invention, the voltage clamping circuit is used for clamping the potential of the clamping end, so that the potential of the clamping end is smaller than or equal to the voltage value threshold, the potential of the output clock signal provided by the clock signal output end through the clock signal providing circuit is not too high, the threshold voltage characteristic of the output transistor in the corresponding driving circuit is not too fast, the overcharging voltage of the rising edge of the output clock signal is reduced, stress of the output clock signal to the output transistor in the driving circuit is reduced, and the service life of a display product is prolonged.
Drawings
Fig. 1 is a block diagram of a clock signal supply circuit according to an embodiment of the present invention;
FIG. 2 is a block diagram of a clock signal providing circuit according to at least one embodiment of the present invention;
FIG. 3 is a block diagram of a clock signal providing circuit according to at least one embodiment of the present invention;
FIG. 4 is a block diagram of a clock signal providing circuit according to at least one embodiment of the present invention;
FIG. 5 is a circuit diagram of a clock signal providing circuit according to at least one embodiment of the present invention;
FIG. 6A is a waveform diagram of an output clock signal provided by the clock signal output CLK_OUT of at least one embodiment of the clock signal providing circuit shown in FIG. 5;
FIG. 6B is a waveform diagram of the output clock signal provided by the clock signal output CLK_OUT when at least one embodiment of the clock signal providing circuit shown in FIG. 5 does not employ a varistor R01;
FIG. 7 is a circuit diagram of a clock signal providing circuit according to at least one embodiment of the present disclosure;
FIG. 8 is a circuit diagram of a clock signal providing circuit according to at least one embodiment of the present disclosure;
FIG. 9 is a block diagram of a display device according to at least one embodiment of the present invention;
fig. 10 is a block diagram of a display device according to at least one embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices having the same characteristics. In the embodiment of the invention, in order to distinguish the two poles of the transistor except the grid electrode, one pole is called a first pole, and the other pole is called a second pole.
In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or the first pole may be a source and the second pole may be a drain.
The clock signal providing circuit comprises an inductance circuit, a voltage clamping circuit and a clock signal output end for providing an output clock signal;
The first end of the inductance circuit is electrically connected with a clock signal source for providing an input clock signal, and the second end of the inductance circuit is electrically connected with the clock signal output end;
The voltage clamping circuit is electrically connected with the clamping end and is used for clamping the potential of the clamping end so that the potential of the clamping end is smaller than or equal to a voltage value threshold;
The clamping end is electrically connected with the second end of the inductance circuit or the clock signal output end.
According to the embodiment of the invention, the voltage clamping circuit is used for clamping the potential of the clamping end, so that the potential of the clamping end is smaller than or equal to the voltage value threshold, the potential of the output clock signal provided by the clock signal output end through the clock signal providing circuit is not too high, the threshold voltage characteristic of the output transistor in the corresponding driving circuit is not too fast, the overcharging voltage of the rising edge of the output clock signal is reduced, stress of the output clock signal to the output transistor in the driving circuit is reduced, and the service life of a display product is prolonged.
As shown in fig. 1, the clock signal providing circuit according to the embodiment of the present invention includes an inductance circuit 11, a voltage clamping circuit 12, and a clock signal output terminal clk_out for providing an output clock signal;
The first terminal of the inductor 11 is electrically connected to a clock signal input clk_in which is electrically connected to a clock signal source for providing an input clock signal;
A second end of the inductance circuit 11 is electrically connected with the clock signal output end CLK_OUT;
the voltage clamping circuit 12 is electrically connected with a clamping end and is used for clamping the potential of the clamping end so that the potential of the clamping end is smaller than or equal to a voltage value threshold;
the clamping terminal is electrically connected to the clock signal output terminal clk_out.
In at least one embodiment of the present invention, the voltage threshold may be selected according to actual situations; in a specific implementation, the voltage threshold may be selected according to a parameter of an output transistor in the driving circuit, but is not limited thereto.
In the related art, the large-size high-resolution high-refresh rate display product also has the problem of PLG (PLG is a Panel peripheral wiring) corner heating, and along with the improvement of the size, resolution and refresh rate, the problem is increasingly prominent, and the use experience of the display product is influenced. In order to reduce the PLG temperature, a resistor with a certain resistance value can be connected in series after an inductor connected in series with the clock signal output end to reduce the overcharge voltage of the clock signal, reduce the current flowing through the clock signal output end and reduce the PLG temperature.
According to one embodiment, the clock signal providing circuit according to at least one embodiment of the present invention further includes a resistor circuit;
The second end of the inductance circuit is electrically connected with the clock signal output end through the resistance circuit.
According to another embodiment, the clock signal providing circuit according to at least one embodiment of the present invention further includes a resistor circuit;
the first end of the inductance circuit is electrically connected with the clock signal source through the resistance circuit.
As shown in fig. 2, on the basis of at least one embodiment of the clock signal providing circuit shown in fig. 1, the clock signal providing circuit according to at least one embodiment of the present invention may further include a resistor circuit 21;
The second end of the inductance circuit 11 is electrically connected with the clock signal output end CLK_OUT through the resistance circuit 21;
The clamping terminal is electrically connected to the second terminal of the inductive circuit 11.
As shown in fig. 3, on the basis of at least one embodiment of the clock signal providing circuit shown in fig. 1, the clock signal providing circuit according to at least one embodiment of the present invention may further include a resistor circuit 21;
The second end of the inductance circuit 11 is electrically connected with the clock signal output end CLK_OUT through the resistance circuit 21;
the clamping terminal is electrically connected to the clock signal output terminal clk_out.
As shown in fig. 4, on the basis of at least one embodiment of the clock signal providing circuit shown in fig. 1, the clock signal providing circuit according to at least one embodiment of the present invention may further include a resistor circuit 21;
the first end of the inductance circuit 11 is electrically connected with the clock signal input terminal clk_in through the resistance circuit 21;
the second terminal of the inductance circuit 11 is directly electrically connected to the clock signal output terminal clk_out, and the clamp terminal is electrically connected to the clock signal output terminal clk_out.
In at least one embodiment of the present invention, the voltage clamping circuit includes a varistor;
The first end of the piezoresistor is electrically connected with the clamping end, and the second end of the piezoresistor is electrically connected with the first voltage end.
The varistor is a voltage limiting type protection device with nonlinear volt-ampere characteristics, and by utilizing the nonlinear characteristics of the varistor, when a overvoltage occurs between two ends of the varistor, the varistor can clamp the voltages at the two ends of the varistor to a relatively fixed voltage value and absorb redundant current, so that the protection of a rear-stage circuit is realized.
According to at least one embodiment of the invention, the voltage dependent resistor is adopted to clamp the potential of the clamping end, when the potential of the output clock signal exceeds the voltage-sensitive voltage of the voltage dependent resistor at the rising edge of the output clock signal, the resistance value of the voltage dependent resistor is reduced, the potential of the output clock signal is clamped to a relatively fixed voltage value, the overcharging voltage of the rising edge of the output clock signal is reduced, thereby reducing stress of the output clock signal to an output transistor in a driving circuit, prolonging the service life of a display product, reducing the current flowing through the output end of the clock signal and the PLG temperature, and solving the problem that the black spot of the current 8K display product is caused by the fact that the PLG temperature is too high at high temperature to cause liquid crystal to reach a clearing point. Because the GOA design at present has the precharge time to the drive signal output, and the characteristics of piezo-resistor only can reduce the electric potential of output clock signal at the rising edge of output clock signal, does not influence the electric potential of the falling edge of output clock signal, consequently after increasing piezo-resistor, can not influence display panel's charging rate, can guarantee that the picture quality is not influenced.
Optionally, the voltage-sensitive voltage of the piezoresistor and the breakdown voltage of the piezoresistor are greater than the voltage value threshold;
A voltage difference between the voltage-sensitive voltage and the voltage value threshold is greater than or equal to 1V and less than or equal to 3V, and a voltage difference between the breakdown voltage and the voltage value threshold is greater than or equal to 4V and less than or equal to 6V;
The first voltage end is a ground end;
But is not limited thereto.
In the implementation, the voltage-sensitive voltage of the piezoresistor can be set to be about 2V higher than the voltage value threshold value, and the breakdown voltage of the piezoresistor can be set to be about 5V higher than the voltage value threshold value, so that the output end of the clock signal can be ensured to output normal voltage, and meanwhile, the output clock signal can be limited to be excessively high in rising edge, and optionally, the voltage-sensitive voltage of the piezoresistor can be set to be about 5V higher than the effective level of the clock signal, for example, about 2V higher than the high level. Referring to fig. 6B, the waveform of the clock signal includes an overcharged bump waveform of a high level and a downcharged bump waveform of a low level, and since there is an overcharged bump waveform, the long-time overcharging affects the lifetime of the output transistor of the gate driving circuit, the output transistor is a transistor connected to the clock signal, the pull-up node of the gate driving circuit and the gate line, and the overcharging also causes PLG problem to be too high, so that the voltage dependent resistor is further provided in this case, the rising edge signal overcharging voltage of the CLK can be reduced, and referring to fig. 6A, the waveform of the clock signal includes a bump reduction of the overcharged bump waveform of a high level, and the specific reduced height is not limited, alternatively, the reduced amplitude may be 20% -100% of the depressed height of the downcharged waveform, including the end value. The design can ensure that the CLK can output normal voltage, and can limit the CLK from being excessively charged at the rising edge.
As shown in fig. 5, in at least one embodiment of the clock signal providing circuit shown in fig. 2, the inductance circuit 11 includes an inductance L0, the resistance circuit 21 includes a resistance R0, and the voltage clamping circuit 12 includes a varistor R01;
the first end of the inductor L0 is electrically connected with the clock signal input end CLK_IN, the second end of the inductor L0 is electrically connected with the first end of the resistor R0, and the second end of the resistor R0 is electrically connected with the clock signal output end CLK_OUT;
The first end of the piezoresistor R01 is electrically connected with the second end of the inductor L0, and the second end of the piezoresistor R01 is electrically connected with the ground end GND.
FIG. 6A is a waveform diagram of an output clock signal provided by the clock signal output CLK_OUT of at least one embodiment of the clock signal providing circuit shown in FIG. 5;
FIG. 6B is a waveform diagram of the output clock signal provided by the clock signal output CLK_OUT when at least one embodiment of the clock signal providing circuit shown in FIG. 5 does not employ a varistor R01.
As shown in fig. 7, in at least one embodiment of the clock signal providing circuit shown in fig. 3, the inductance circuit 11 includes an inductance L0, the resistance circuit 21 includes a resistance R0, and the voltage clamping circuit 12 includes a varistor R01;
the first end of the inductor L0 is electrically connected with the clock signal input end CLK_IN, the second end of the inductor L0 is electrically connected with the first end of the resistor R0, and the second end of the resistor R0 is electrically connected with the clock signal output end CLK_OUT;
the first terminal of the varistor R01 is electrically connected to the clock signal output terminal clk_out, and the second terminal of the varistor R01 is electrically connected to the ground terminal GND.
As shown in fig. 8, in at least one embodiment of the clock signal providing circuit shown in fig. 4, the inductance circuit 11 includes an inductance L0, the resistance circuit 21 includes a resistance R0, and the voltage clamping circuit 12 includes a varistor R01;
the first end of the resistor R0 is electrically connected with the clock signal input end CLK_IN, the second end of the resistor R0 is electrically connected with the first end of the inductor L0, and the second end of the inductor L0 is electrically connected with the clock signal output end CLK_OUT;
the first terminal of the varistor R01 is electrically connected to the clock signal output terminal clk_out, and the second terminal of the varistor R01 is electrically connected to the ground terminal GND.
In particular implementations, the voltage clamp circuit may include a TVS (TRANSIENT VOLTAGE SUPPRESSION ) diode;
the anode of the TVS diode is electrically connected with the clamping end, and the cathode of the TVS diode is electrically connected with the first voltage end.
Optionally, the voltage clamp circuit includes an ESD (Electro-STATIC DISCHARGE, electrostatic discharge) resistor;
the first end of the ESD resistor is electrically connected with the clamping end, and the second end of the ESD resistor is electrically connected with the first voltage end.
In at least one embodiment of the present invention, the voltage clamping circuit is not limited to include a varistor, a TVS diode and an ESD resistor, and any circuit structure capable of clamping a voltage is within the scope of the present invention.
In at least one embodiment of the present invention, the first voltage terminal may be a dc voltage terminal; for example, the first voltage terminal may be a ground terminal, but is not limited thereto.
The display device according to the embodiment of the invention comprises the clock signal providing circuit.
The display device according to at least one embodiment of the present invention further includes a clock signal source and a driving circuit;
The clock signal source is used for providing an input clock signal to the clock signal providing circuit;
The driving circuit is electrically connected with a clock signal output end included in the clock signal providing circuit and is used for receiving an output clock signal and generating a driving signal according to the output clock signal.
In an implementation, the display device may further include a clock signal source for providing an input clock signal, and a driving circuit receiving the output clock signal provided by the clock signal providing circuit and generating the driving signal according to the output clock signal.
In at least one embodiment of the present invention, the display device further includes a circuit board;
the clock signal providing circuit is arranged on the circuit board.
In an implementation, the circuit board may be a PCB (Printed Circuit Board ) circuit board, but is not limited thereto.
Optionally, the clock signal source includes a timing controller and a level shifter;
The timing controller is used for providing a reference clock signal for the level converter;
the level shifter is used for carrying out level conversion on the reference clock signal to obtain an input clock signal;
The time schedule controller and the level shifter are arranged on the circuit board.
In a specific implementation, the clock signal source may include a timing controller and a level shifter, where the timing controller provides a reference clock signal to the level shifter, and the level shifter performs level conversion on the reference clock signal to obtain an input clock signal, and the timing controller and the level shifter may be disposed on a circuit board.
As shown in fig. 9, the timing controller Tc supplies a reference clock signal to the level shifter LS, the level shifter LS level-converts the reference clock signal to obtain m input clock signals, and supplies the m input clock signals to the clock signal supply circuit;
The clock signal providing circuit comprises a first resistor R1, a first inductor L1, a first piezoresistor R11, a second resistor R2, a second inductor L2, a second piezoresistor R12, a third resistor R3, a third inductor L3, a third piezoresistor R13, an m-1 resistor Rm-1, an m-1 inductor Lm-1, an m-1 piezoresistor R1m-1, an m-resistance Rm, an m-inductance Lm and an m-1 piezoresistor R1m; m is an integer greater than 4;
The first end of R1 is electrically connected with the first clock signal input end and receives a first input clock signal from the level converter LS;
The second end of R1 is electrically connected with the first end of L1, and the second end of L1 is electrically connected with the first clock signal line CLK 1;
The first end of R11 is electrically connected with the second end of L1, and the second end of R11 is electrically connected with the ground;
The first end of R2 is electrically connected with the second clock signal input end and receives a second input clock signal from the level converter LS;
The second end of R2 is electrically connected with the first end of L2, and the second end of L2 is electrically connected with the second clock signal line CLK 2;
The first end of R12 is electrically connected with the second end of L2, and the second end of R12 is electrically connected with the ground;
the first end of R3 is electrically connected with the third clock signal input end and receives a third input clock signal from the level converter LS;
the second end of R3 is electrically connected with the first end of L3, and the second end of L3 is electrically connected with the third clock signal line CLK 3;
The first end of R13 is electrically connected with the second end of L3, and the second end of R13 is electrically connected with the ground;
the first end of Rm-1 is electrically connected with the m-1 clock signal input end and receives the m-1 input clock signal from the level converter LS;
The second end of Rm-1 is electrically connected with the first end of Lm-1, and the second end of Lm-1 is electrically connected with the m-1 clock signal line CLKm-1;
The first end of R1m-1 is electrically connected with the second end of Lm-1, and the second end of R1m-1 is electrically connected with the ground;
the first end of Rm is electrically connected with the m-th clock signal input end and receives the m-th input clock signal from the level converter LS;
the second end of Rm is electrically connected with the first end of Lm, and the second end of Lm is electrically connected with an mth clock signal line CLKm;
The first end of R1m is electrically connected with the second end of Lm, and the second end of R1m is electrically connected with the ground.
In fig. 9, a first driving circuit denoted by GOA1, a second driving circuit denoted by GOA2, a third driving circuit denoted by GOA3, an n-1 driving circuit denoted by GOAn-1, and an n-driving circuit denoted by GOAn; a driving signal output terminal of the first driving circuit denoted by Gout1, a driving signal output terminal of the second driving circuit denoted by Gout2, a driving signal output terminal of the third driving circuit denoted by Gout3, a driving signal output terminal of the n-1 driving circuit denoted by Goutn-1, and a driving signal output terminal of the n-driving circuit denoted by Goutn;
n is a positive integer.
In at least one embodiment shown in FIG. 9, CLK1, CLK2, CLK3, CLKm-1, CLkm, GOA1, GOA2, GOA3, GOAm-1, and GOAm are all disposed in a peripheral region of the display panel.
In at least one embodiment of the present invention, the clock signal providing circuit may be disposed on a circuit board, for example, but not limited to, a printed circuit board PCB or a flexible circuit board FPC. In actual operation, the clock signal supply circuit may also be disposed on the display panel, for example, in a non-display area of the display panel.
In fig. 10, reference numeral 200 denotes a display panel, reference numeral 201 denotes a display region, reference numeral 202 denotes a peripheral region, and reference numeral 100 denotes a driving circuit region; a driving circuit and a clock signal line may be provided in the driving circuit region 100;
the reference numeral 250 is a PCB circuit board;
The timing controller, the level shifter LS, and the clock signal supply circuit CP are disposed on the PCB circuit board 250.
The display device provided by the embodiment of the invention can be any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that various modifications and adaptations can be made without departing from the principles of the present invention, and such modifications and adaptations are intended to be comprehended within the scope of the present invention.
Claims (12)
1. A clock signal providing circuit, characterized by comprising an inductance circuit, a voltage clamping circuit and a clock signal output terminal for providing an output clock signal;
The first end of the inductance circuit is electrically connected with a clock signal source for providing an input clock signal, and the second end of the inductance circuit is electrically connected with the clock signal output end;
The voltage clamping circuit is electrically connected with the clamping end and is used for clamping the potential of the clamping end so that the potential of the clamping end is smaller than or equal to a voltage value threshold;
The clamping end is electrically connected with the second end of the inductance circuit or the clock signal output end.
2. The clock signal providing circuit of claim 1, further comprising a resistive circuit;
The second end of the inductance circuit is electrically connected with the clock signal output end through the resistance circuit.
3. The clock signal providing circuit of claim 1, further comprising a resistive circuit;
the first end of the inductance circuit is electrically connected with the clock signal source through the resistance circuit.
4. The clock signal providing circuit of claim 1, wherein the voltage clamping circuit comprises a varistor;
The first end of the piezoresistor is electrically connected with the clamping end, and the second end of the piezoresistor is electrically connected with the first voltage end.
5. The clock signal providing circuit of claim 4, wherein a voltage dependent voltage of the varistor and a breakdown voltage of the varistor are greater than the voltage value threshold;
A voltage difference between the voltage-sensitive voltage and the voltage value threshold is greater than or equal to 1V and less than or equal to 3V, and a voltage difference between the breakdown voltage and the voltage value threshold is greater than or equal to 4V and less than or equal to 6V;
The first voltage terminal is a ground terminal.
6. The clock signal providing circuit of claim 1, wherein the voltage clamp circuit comprises a TVS diode;
the anode of the TVS diode is electrically connected with the clamping end, and the cathode of the TVS diode is electrically connected with the first voltage end.
7. The clock signal supply circuit of claim 1, wherein the voltage clamp circuit comprises an ESD resistor;
the first end of the ESD resistor is electrically connected with the clamping end, and the second end of the ESD resistor is electrically connected with the first voltage end.
8. The clock signal providing circuit of claim 4, 6 or 7, wherein the first voltage terminal is a dc voltage terminal.
9. A display device comprising the clock signal supply circuit according to any one of claims 1 to 8.
10. The display device of claim 9, further comprising a clock signal source and a drive circuit;
The clock signal source is used for providing an input clock signal to the clock signal providing circuit;
The driving circuit is electrically connected with a clock signal output end included in the clock signal providing circuit and is used for receiving an output clock signal and generating a driving signal according to the output clock signal.
11. The display device according to claim 9 or 10, further comprising a circuit board;
the clock signal providing circuit is arranged on the circuit board.
12. The display device of claim 10, wherein the clock signal source comprises a timing controller and a level shifter;
The timing controller is used for providing a reference clock signal for the level converter;
the level shifter is used for carrying out level conversion on the reference clock signal to obtain an input clock signal;
The time schedule controller and the level shifter are arranged on the circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211323890.0A CN117995081A (en) | 2022-10-27 | 2022-10-27 | Clock signal supply circuit and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211323890.0A CN117995081A (en) | 2022-10-27 | 2022-10-27 | Clock signal supply circuit and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117995081A true CN117995081A (en) | 2024-05-07 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211323890.0A Pending CN117995081A (en) | 2022-10-27 | 2022-10-27 | Clock signal supply circuit and display device |
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| Country | Link |
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| CN (1) | CN117995081A (en) |
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2022
- 2022-10-27 CN CN202211323890.0A patent/CN117995081A/en active Pending
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