CN117981245A

CN117981245A - Method and apparatus for carrying Constant Bit Rate (CBR) client signals

Info

Publication number: CN117981245A
Application number: CN202280059834.2A
Authority: CN
Inventors: S·穆玛; W·莫克; S·S·戈尔什
Original assignee: Microchip Technology Inc
Current assignee: Microchip Technology Inc
Priority date: 2021-11-23
Filing date: 2022-08-22
Publication date: 2024-05-03

Abstract

A method and apparatus in which a data stream generated by a previous network node, an accumulated phase offset report (CPOR), and a Client Rate Report (CRR) are received. The counter that accumulates the PHY-scaled stream clocks (IPSCk) is sampled at a nominal sampling period (Tps) to obtain an accumulated PHY-scaled count (CPSC). A PHY-scaled stream phase offset (PSPO) is calculated, the PSPO indicating a phase difference between a PHY-scaled stream nominal bit count (LPSD) and an incoming PHY-scaled count delta (IPSD), wherein the IPSD indicates CPSC increment between consecutive CPSC samples. The data stream is demultiplexed to obtain a CBR carrier stream that includes the previous network node CPOR (CPOR-P) and the previous network node CPO (CPO-P). CPO is calculated as a function of the CPO-P and the PSPO. Replacing the CPO-P with the calculated CPO. The CBR carrier stream is multiplexed into an intermediate network node data stream that is transmitted from the intermediate network node.

Description

Method and apparatus for carrying Constant Bit Rate (CBR) client signals

Cross Reference to Related Applications

The present application claims priority from U.S. provisional patent application Ser. No. 63/282,292, filed 11/23, 2021, and U.S. non-provisional patent application Ser. No. 17/885,194, filed 8/10, 2022, each of which is incorporated herein by reference in its entirety.

Background

There are three main categories of methods for transmitting Constant Bit Rate (CBR) clients over a cell/packet transmission network. The first type of approach is fully adaptive, in which the sink node monitors the arrival rate of cells/packets carrying CBR clients and adjusts its transmit phase locked loop (TxPLL) accordingly to accelerate or decelerate. Sink nodes often implement FIFO buffers to hold CBR clients and use their depth to control the transmit phase locked loop. This scheme is susceptible to delay variations encountered by CBR clients in the transport network. For example, the reduction in delay will appear to the sink node as a faster arrival rate, and thus the transmit phase locked loop may be falsely accelerated.

In a second class of methods, the source node inserts a timestamp based on the arrival time of certain key bits of the CBR client. The time stamp and CBR client data are bundled into a carrier stream. The bit rate of the CBR client is calculated by dividing the number of CBR client bits between consecutive time stamps by the change in the time stamp value. This approach is exemplified by IETF RFC 4553 SAToP, which requires that the source node and sink node share a common clock reference. However, the need for a common clock reference at the source node and sink node increases the deployment cost of the transport network. Furthermore, adding a common clock reference is not feasible in some cases.

A third class of methods, illustrated by the International Telecommunications Union (ITU) universal mapping procedure (GMP), introduces low jitter and drift into CBR clients and does not require a common reference clock. It involves periodically inserting client speed reports (such as GMP overhead) into the carrier stream of CBR clients at the source node. At the input of the intermediate switching node, the rate reports are processed to recover the bit rate of each CBR client. At the output of the intermediate node, the bit rate of the respective one of the CBR clients is re-encoded into a new rate report related to the bit rate of the outgoing carrier stream of the intermediate node. When the number of CBR clients at the intermediate node is very large, such a scheme may be expensive and complex to implement because the respective one of the CBR clients requires its own rate reporting Digital Signal Processor (DSP) engine.

Thus, there is a need for methods and apparatus that will allow for communication of CBR client signals without the need to process and regenerate new rate reports for respective ones of the CBR clients at the intermediate node. In addition, there is a need for methods and apparatus that do not require the source node and sink node to share a common reference clock.

Disclosure of Invention

A method is disclosed that includes receiving, at a respective intermediate network node of a plurality of intermediate network nodes, a respective data stream generated by a previous network node. The respective data streams include Constant Bit Rate (CBR) carrier streams corresponding to Constant Bit Rate (CBR) signals received at the source nodes. The counter accumulating the PHY-scaled stream clocks (IPSCk) is sampled with a nominal sampling period (Tps) of the local reference clock of the intermediate network node to obtain an accumulated PHY-scaled count (CPSC) of the received respective data stream. IPSCk are generated by scaling the clock recovered from the received respective data stream to a predetermined nominal frequency (Fipsck _nom). The method includes calculating a PHY-scaled stream phase offset (PSPO), the PSPO indicating a phase difference between a PHY-scaled stream nominal bit count (LPSD) and an incoming PHY-scaled count delta (IPSD), wherein the IPSD represents an increment between consecutive CPSCs.

The received respective data streams are demultiplexed to obtain CBR carrier streams. The respective ones of the CBR carrier streams include a previous network node accumulated phase offset report (CPOR-P) indicating a previous network node accumulated phase offset (CPO-P) and a Client Rate Report (CRR) indicating a measured bit count of the respective CBR client at the source node. A Cumulative Phase Offset (CPO) of a respective one of the CBR carrier streams is calculated. The calculated CPO is a function of the CPO-P of the corresponding CBR carrier stream and the calculated PSPO. The CPO-P in a respective one of the CBR carrier streams is replaced with the calculated CPO of the respective CBR carrier stream or a function of the calculated CPO of the respective CBR carrier stream to generate an updated Cumulative Phase Offset Report (CPOR) to replace CPOR-P in the respective CBR carrier stream. The corresponding CBR carrier streams are multiplexed into the intermediate network node data stream. The intermediate network node data stream is then sent from the particular intermediate network node.

An Integrated Circuit (IC) device includes a PHY link input to receive a data stream generated by a previous network node, the data stream including a plurality of CBR carrier streams, respective ones of the CBR carrier streams including CPOR-P indicative of CPO-P and CRR indicative of a measured bit count of the respective CBR client at a source node. A clock offset circuit is coupled to the PHY link input to sample the accumulated IPSCk counter with Tps of a local reference clock of the intermediate network node to obtain CPSCs of the received respective data stream, the IPSCk being generated by scaling a clock recovered from the received respective data stream to Fipsck _nom; and to calculate PSPO indicating a phase difference between the LPSD and the IPSD indicating the CPSC delta between consecutive CPSC samples. A demultiplexer is coupled to the PHY link input to demultiplex the received data streams to obtain the plurality of CBR carrier streams. Accumulated phase offset report (CPOR) update logic is coupled to the demultiplexer and the clock offset circuit to calculate CPOs of respective ones of the CBR carrier streams, wherein the calculated CPOs are a function of the CPO-P and the calculated PSPO; and to replace the CPO-P with the calculated CPO of the respective CBR carrier stream or with a function of the calculated CPO of the respective CBR carrier stream; and to generate updated CPOR of the respective CBR carrier stream in place of CPOR-P in the respective CBR carrier stream. A multiplexer is coupled to the demultiplexer and the CPOR update logic to multiplex the CBR carrier stream into a plurality of intermediate network node data streams. An encoder is coupled to the multiplexer to encode the plurality of intermediate network node data streams. The PHY link output is coupled to the encoder to transmit the plurality of intermediate network node data streams from the IC device.

A network comprising a source node, the source node comprising: an input for receiving a plurality of CBR signals; CPOR a generating circuit, the CPOR generating circuit for generating CPOR indicative of an initial CPO; a CRR generating circuit for generating a CRR indicative of the measured bit rate of the respective CBR client; a CBR mapper coupled to the input to generate a corresponding CBR carrier stream for a respective one of the CBR signals and to insert CRR and CBR client data into the respective CBR carrier stream; and source output processing circuitry for inserting CPOR into the respective CBR carrier streams and multiplexing the CBR carrier streams to generate a plurality of source data streams.

The network includes a plurality of intermediate network nodes coupled to the source node, respective ones of the intermediate network nodes including an IC device comprising: a PHY link input for receiving a data stream generated by a previous network node, the data stream comprising a plurality of CBR carrier streams, respective ones of the CBR carrier streams comprising CRR and CPOR-P indicating CPO-P.

The intermediate network nodes include a clock offset circuit coupled to the PHY link input to: sampling the accumulated IPSCk counter with Tps of the local reference clock of the intermediate network node to obtain the CPSC of the received respective data stream, the IPSCk being generated by scaling the clock recovered from the received respective data stream to Fipsck _nom; and calculates a PHY-scaled stream phase offset (PSPO), the PSPO indicating a phase difference between the LPSD and the IPSD, wherein the IPSD indicates an increment between consecutive CPSCs.

The intermediate network nodes include a demultiplexer coupled to the PHY link input to demultiplex the received data streams to obtain individual CBR carrier streams; and CPOR update logic, the CPOR update logic coupled to the demultiplexer and the clock offset circuit. The CPOR update logic is to calculate a CPO for a corresponding CBR carrier stream of the CBR carrier streams, wherein the calculated CPO is a function of the CPO-P for the particular CBR carrier stream and the calculated PSPO; and the calculated CPO for replacing the CPO-P of the particular CBR carrier stream with the calculated CPO for the corresponding CBR carrier stream to generate updated CPOR for the corresponding CBR carrier stream to replace CPOR-P of the particular CBR carrier stream.

The intermediate network node comprises: a multiplexer coupled to the demultiplexer and CPOR the update logic to multiplex the CBR carrier stream into a plurality of intermediate network node data streams; an encoder coupled to the multiplexer to encode the plurality of intermediate network node data streams; and a PHY link output coupled to the encoder to transmit a plurality of intermediate network node data streams from the IC device.

The network includes an aggregation node coupled to a last one of the intermediate network nodes to receive an intermediate network node data stream from the last one of the intermediate network nodes, recovering a CBR client signal; and outputting, from the sink node, a CBR signal comprising the restored CBR client signal.

The disclosed methods and apparatus allow for communication of CBR client signals without the need to process and regenerate new rate reports for respective ones of the CBR clients at the intermediate network node. In addition, the method and the device do not need the source node and the sink node to share the common reference clock.

Drawings

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The figures illustrate various examples. The drawings referred to in this brief description are not drawn to scale.

Fig. 1 is a diagram illustrating a network including a source node, a sink node, and a plurality of intermediate network nodes.

Fig. 2 is a diagram showing a circuit of a source node.

Fig. 3 is a block diagram illustrating CPOR.

Fig. 4 is a block diagram showing a data flow.

Fig. 5 is a block diagram illustrating an intermediate network node switch of the network of fig. 1.

Fig. 6 is a diagram illustrating an IC device (switch) of the intermediate network node switch shown in fig. 5.

Fig. 7 is a diagram showing an example of CPOR update logic for calculating a CPO by adding CPO-P to the calculated PSPO.

Fig. 8 is a diagram illustrating an example of CPOR update logic to calculate a CPO as a function of all CPOs-P received by an intermediate network node from the last initialization of the intermediate network node and all PSPO calculated by the intermediate network node from the last initialization of the intermediate network node.

Fig. 9 is a diagram showing a circuit of the sink node.

Fig. 10A is a flowchart illustrating a method for coupling CBR signals over a network.

Fig. 10B to 10I are block diagrams showing examples of portions for performing the method of fig. 10A.

Detailed Description

Fig. 1 shows an example of a network 4 comprising a source node 1, a sink node 2 and a plurality of intermediate network nodes 3 (shown in fig. 1 as a first intermediate network node 3a, a second intermediate network node 3b and a last intermediate network node 3 c), these intermediate network nodes 3 logically extending between the source node 1 and the sink node 2 to couple the source node 1 to the sink node 2. The respective intermediate network node may be implemented as a switch. The relative parts per million frequency offset (RPPM) (RPPMpath) between the reference clocks of the source node and sink node may be represented by the following equation:

RPPMpath＝RPPMsw1+RPPMsw2+...RPPMswn+RPPMsk

Where RPPMsw is the RPPM between the reference clocks of the intermediate network node 3a and the source node 1 and measured at the first intermediate network node 3a, RPPMsw2 is the RPPM between the reference clocks of the intermediate network node 3b and the intermediate network node 3a and measured at the second intermediate network node 3b, RPPMswn is the RPPM between the reference clocks of the intermediate network node 3c and its upstream node and measured at the nth intermediate network node 3c, and RPPMsk is the RPPM between the reference clocks of the immediately preceding intermediate network node (e.g., intermediate network node 3 c) and the sink node 2 and measured at the sink node 2.

Fig. 2 shows an exemplary source node 1 comprising a local reference clock 20, a reference clock input 27, a plurality of CBR processing circuits 29a to 29c, a source output processing circuit 22 comprising a transmit PLL 28, a CBR signal input 30 and a PHY link output 7. The respective CBR processing circuits of the CBR processing circuits 29a to 29c include a CRR timer circuit 23, a CRR generation circuit 24, CPOR timer circuits 25, CPOR generation circuit 26, and a CBR mapper 21. The CRR generation circuit 24 may be implemented using a Digital Signal Processor (DSP).

Respective CPOR ones of CPOR processing circuits 29a through 29c are coupled to reference clock input 27, respective CBR signal input 30 for receiving respective CBR signals (e.g., CBR signals 30a, 30b, 30 c), and source output processing circuit 22. The CRR generation circuit 24 is coupled to the CRR timer circuit 23 and the CBR mapper 21.CPOR generation circuit 26 is coupled to CPOR timer circuit 25 and source output processing circuit 22. A respective one of CBR mappers 21 is coupled to a respective CBR signal input (e.g., one of CBR signal inputs 30) and source output processing circuit 22. Source output processing circuit 22 is coupled to PHY link output 7.

The reference clock input 27 is coupled to the local reference clock 20 of the source node 1 to supply a reference clock signal 27a to the CRR timer circuit 23 of the corresponding CBR processing circuit 29, the CPOR timer circuit 25 of the corresponding CBR processing circuit 29 and the transmit phase locked loop 28.

CPOR timer circuit 25 receives reference clock signal 27a on reference clock input 27 and generates timing signal Tcpor. CPOR generation circuit 26 receives timing signal Tcpor and generates CPOR in response to received timing signal Tcpor. CRR timer circuit 23 receives reference clock signal 27a and generates timing signal Tcrr. CRR generation circuit 24 receives respective CBR signals 30 a-30 c at respective CBR signal inputs 30 and uses received CBR signals 30 a-30 c and received timing signals Tcrr to generate CRR indicative of the measured clock rate of the respective CBR clients. The generation periods of CRR (in response to timing signal Tcrr) and CPOR (in response to timing signal Tcpor) may be independent.

Fig. 3 shows an example of CPOR 40 generated by CPOR generation circuit 26 including CPOR header 31 and CPO 5. The term "CPO" as used in the present application is one or more values or words that indicate the accumulated phase offset. In this example, it is a single numerical value indicated in terms of the number of bits, bytes, or words of the phase offset. The term "CPOR" as used in the present application is a sequence of characters that indicates a CPO. The CPO output by CPOR generation circuit 26 may be referred to as an "initial CPO". In this example, the initial CPO is not calculated at the source node, but is set to a predetermined value, e.g., "0", in response to the received timing signal Tcpor.

CBR mapper 21 of fig. 2 receives respective CBR signals 30 a-30 c and CRR from CRR generation circuit 24 and generates a respective CBR carrier stream that is coupled to source output processing circuit 22. CBR mapper 21 formats the CBR client data into a CBR carrier stream using information in the CRR and inserts the CRR and CBR client data into the corresponding CBR carrier stream. The source output processing circuit 22 inserts CPOR into the corresponding CBR carrier stream and multiplexes the CBR carrier streams to generate a plurality of source data streams 7a to 7d, which are output through the PHY link output 7, respectively. A transmit Phase Locked Loop (PLL) 28 receives as input the reference clock signal 27a and generates a timing signal that controls the timing of the output of the source data streams 7a to 7d. PHY link output 7 is phase locked to local reference clock 20 by transmit PLL 28.

Fig. 4 shows an example of a data flow cell or packet 6 including cell/packet overhead 32, carrier overhead 33, CPOR overhead 34, CRR overhead 35, and CBR client payload 36. The CRR overhead 35 is composed of CRRs generated by the CRR generation circuit 24 (e.g., CRRs generated for a specific data stream). When a data stream cell or packet 6 leaves as the source data stream 7 a-7 d of fig. 2, CPOR overhead 34 consists of CPOR 40 generated by CPOR generation circuit 26, such that CRR and CPOR are carried in-band with CBR client payloads in the outgoing source data streams 7 a-7 d. In this example, CRR and CPOR in a data stream cell or packet 6 may be distributed over multiple cells/packets for robust handling of burst errors.

Fig. 5 shows an exemplary intermediate network node 3 comprising an Integrated Circuit (IC) device 10 and a local reference clock 37. IC device 10 is coupled to local reference clock 37 by reference clock input 39 and includes PHY link input 8 and PHY link output 9.IC device 10 may implement a switch and in that example, intermediate network node 3 may be an intermediate network node switch. There is no need to phase lock the local reference clock 37 of the intermediate network node 3 to the local reference clocks of the other intermediate network nodes 3, the local reference clock 20 of the source node 1, or the local reference clock 39a-1 of the sink node.

Fig. 6 shows an example of an IC device 10 (e.g., "switch") that includes a reference clock input 39, a PHY link input 8 for receiving a corresponding data stream, a clock offset circuit 11, a demultiplexer 12, multiplexers 13, CPOR update logic 14, FIFO registers 52 a-52 f, other intermediate network node circuits 53, an encoder 15, and a PHY link output 9. Clock offset circuit 11 is coupled to CPOR update logic 14, reference clock input 39, and PHY link input 8. The demultiplexer 12 is coupled to the PHY link inputs 8 and CPOR update logic 14.CPOR update logic 14 is coupled to first-in-first-out (FIFO) registers 52 a-52 c such that respective ones of the CBR carrier streams are coupled to respective FIFOs of FIFOs 52 a-52 c. More specifically, a first CBR carrier stream 50a is coupled to FIFO 52a, a second CBR carrier stream 50b is coupled to FIFO 52b, and a third CBR carrier stream 50c is coupled to FIFO 52c, it being understood that there may be n CBR carrier streams with n corresponding FIFOs. The multiplexer 13 includes one or more transmit PLLs 16 and is coupled to FIFOs 52a through 52f and encoder 15. Respective ones of the encoders 15 are coupled to respective ones of the PHY link outputs 9. The transmit PLL 16 receives as input a local reference clock signal 39a at a reference clock input 39 and generates a timing signal that controls the timing of the output of the Intermediate Network Node (INN) data streams 9a to 9 d. The clock offset circuit 11 includes a sampling pulse generator 41, an accumulated phase counter circuit 42, a clock recovery circuit 43, a clock scaler circuit 44, a current count register 45, a previous count register 46, a first subtraction logic 48, a second subtraction logic 49, and an LPSD register 47. The sampling pulse generator 41 is coupled to the reference clock input 39 and the accumulated phase counter circuit 42. The clock recovery circuit 43 is coupled to the respective PHY link input 8 and the clock scaler circuit 44. The accumulated phase counter circuit 42 is coupled to a current count register 45 and a clock scaler circuit 44. The current count register 45 is coupled to the previous count register 46. The first subtraction logic 48 is coupled to the current count register 45, the previous count register 46 and the second subtraction logic 49. The second subtraction logic 49 is coupled to the LPSD registers 47 and CPOR update logic 14. The first subtracting logic 48 and the second subtracting logic 49 may be implemented as respective subtracting circuits.

In this example, IC device 10 is formed on a single integrated circuit die and does not include a respective DSP engine for each CBR client. The PHY link input 8, clock offset circuit 11, de-multiplexers 12, CPOR update logic 14, encoder 15, and PHY link output 9 may be provided in a single integrated circuit die.

The circuitry for demultiplexing and updating CPOR of the data stream received at the first PHY link input 8 is shown in fig. 6 as dashed line 54. The other intermediate network node circuits 53 may include the same circuits 54 for demultiplexing and updating CPOR of the data streams 8 b-8 d received at the other PHY link inputs 8 and for coupling other carrier streams with updated CPOR to the respective FIFOs 52 d-52 f.

A respective one of the PHY link inputs 8 (e.g., each PHY link input) receives data streams generated by a previous network node, which are shown as data streams 8 a-8 d (e.g., one of the source data streams 7 a-7 d or INN data streams 9 a-9 d from a previous intermediate network node). The sampling pulse generator 41 receives the local reference clock signal 39a at the reference clock input 39 and uses the local reference clock signal 39a to generate sampling pulses at a sampling period Tps. The nominal period of the sampling pulse is constant over all nodes in the network 4, wherein the actual deviation of the period depends on the actual ppm offset of the corresponding local reference clock signal 39 a. The sampling period (i.e., tps) of the accumulated phase counter circuit 42 is selected to be longer than Tcpor of fig. 2. In one example, tps > 2 tcpor.

The clock recovery circuit 43 receives the data stream 8a from the previous network node at the respective PHY link input 8 and recovers the PHY link clock signal (i.e., the clock of the data stream 8 a). The recovered PHY link clock signal (Rclk) is output to a clock scaler circuit 44. The sequence of data bits in the data stream 8a received at the clock recovery circuit 43 is independent of the operation of the clock offset circuit 11 and can be discarded at the clock offset circuit 11.

Clock scaler circuit 44 scales Rclk to generate a PHY-scaled stream clock (IPSCk). In one example, a nominal clock rate (PHYck-nom) of the PHY link is used to determine the scaling factor. The term "nominal clock rate of the PHY link" as used in the present application is a certain value and may be a value indicating a clock rate (i.e., a bit rate at which the PHY link input 8 is designed to operate) or a value indicating that a PHY link (not shown) coupled to the PHY link input 8 is designed to operate at a rate such as 10 Gbit/s or 25 Gbit/s. In one example, the scaling factor in 44 is set to (PHYck-nom/Fipsck _nom), where Fipsck _nom is the predetermined nominal frequency. Thus, IPSCk rate = Rclk (Fipsck _nom/PHYck-nom). Thus, the nominal clock rate of IPSCk is constant over the entire network 4 (all intermediate network nodes and sink nodes). Fipsck _nom is a constant defined across all nodes in the transport network and is selected to provide a simple scalar ratio between PHY link clock rates in network 4. For example Fipsck _nom in the network 4 may be set to 1.0MHz or 10MHz. In one example Fipsck _nom represents the nominal rate of IPSCk and is the nominal clock frequency of all "PHY-scaled stream clocks" in the network, with clock recovery circuit 43 and clock scaler circuit 44 of each clock offset circuit 11 in network 4 being considered to constitute the "PHY-scaled stream clocks" of the network, but is not limited thereto. In one example, the value 1MHz is used as Fipsck _nom to perform scaling in all intermediate network nodes of the network and in sink nodes. In this example, rclk is divided by a scaling factor at 44 to generate IPSCk. It should be understood that the current use of 1MHz as the nominal Fipsck _nom is only a single example, and that other values may be used.

The counter of the accumulated phase counter circuit 42 of the accumulated IPSCk (i.e., the accumulated phase counter) is sampled by the accumulated phase counter circuit 42 at a period Tps based on the local reference clock signal 39a provided by the local reference clock 37 to obtain the CPSC of the received respective data stream. In one example, the accumulated phase counter circuit 42 accumulates IPSCk edges into a free-running counter to generate the CPSC. Logically, the counter may reach infinity. In this example, the counter of the accumulated phase counter circuit 42 is sampled at each pulse (once per Tps) received from the sampling pulse generator 41 to obtain the CPSC of the corresponding received data stream. In one example, the accumulated phase counter circuit 42 is incremented by 1 at each IPSCk clock edge and the value of the counter in the accumulated phase counter circuit 44 is sampled once per Tps to identify the current bit count that includes the CPSC. The current CPSC output by the accumulated phase counter circuit 42 at Tps is stored in the current count register 45. When a new CPSC is output in response to the next pulse (i.e., after Tps) from the sampling pulse generator 41, the previous CPSC is stored in the previous count register 46 (e.g., by moving the CPSC stored in the current count register 45 to the previous count register 46) before the new CPSC is stored in the current count register 45. Thereby, the current CPSC and the previous CPSC output from the accumulated phase counter circuit 42 are stored in the registers 45 to 46.

In one example, the counter in the accumulated phase counter circuit 42 is not cleared. It samples only with Tps instances. The previous sample value is subtracted from the current sample value to produce an effect similar to the clearing at each Tps, but is insensitive to clearing signals closely aligned with IPSCk, which increment a counter.

In the present example, the CPSC generated by the accumulated phase counter circuit 42 indicates the phase using bits (bit count). Bits (bit counts) are convenient units of measure in which the amount of phase delivered by an upstream node is a monotonically increasing value that reaches infinity in terms of bits, bytes, or radians, without limitation. In alternative implementations, the accumulated phase counter circuit 42 may use bytes, radians, or other measurements to identify the actual delivery of phase relative to Tps as determined by the local reference clock signal 39 a. In alternative examples, a bit rate may be used. However, this may involve one or more division steps and thus may not be as efficient as staying in the count field.

Clock offset circuit 11 calculates PSPO, which PSPO indicates the phase difference between the PHY-scaled stream nominal bit count (LPSD) and the incoming PHY-scaled count delta (IPSD). The term "PHY-scaled stream nominal bit count" (which may also be referred to as "local PHY stream delta" or "LPSD") as used in the present application is a value that indicates a local constant increment of the phase count over a period of time, and may be a function of Tps and Fipsck _bom. LPSD represents an amount based on the expected increment of Fipsck _nom and Tps at the intermediate network node. In this example, the LPSD as a function of Fipsck _nom and Tps is stored in the LPSD register 47. In one example, LPSD is calculated from the product of Fipsck _nom and Tps using the following equation: lpsd= Fipsck _nom×tps. As described above, the LPSD is stored in the LPSD register 47. Logically Tcrr of fig. 2 can be represented in terms of the number of PHY-scaled stream bits (Ncrr) using the relationship ncrr= Tcrr x Fipsck _nom.

First subtraction logic 48 subtracts the previous CPSC in register 46 from the current CPSC in register 45 to obtain the IPSD. Since IPSD represents the CPSC increment between consecutive CPSCs sampled by the accumulated phase counter circuit 42 (i.e., an increment indicating the CPSC count within a Tps period), it indicates the increment of the accumulated phase (bit count) within Tps.

The second subtraction logic 49 subtracts the LPSD from the IPSD to calculate a PHY-scaled stream phase offset (PSPO). Thus PSPO = (IPSD-LPSD) such that PSPO captures a relative Parts Per Million (PPM) offset (RPPM) between a reference clock at an upstream node used to generate data stream 8a and local reference clock 37, the RPPM encoded in phase units. Using phase units is preferred over frequency units because the phase allows easier phase locking of the sink node to the source node. Using frequency units will only allow frequency locking.

In one example, given IPSCk =rclk/10,000 sampled at Tps (1,000,000/10,000,000,000) =rclk/10,000 and lpsd=1,000,000×tps, the PHY link is a 10Gbit/s link such that its clock rate is nominally 10,000,000,000 cycles/second and Fipsck _nom is 1MHz. Thus, the resulting PSPO will capture the difference between the expected content (LPSD) and the calculated/measured content (IPSD) in phase units.

The demultiplexer 12 demultiplexes the received data stream 8a to obtain individual CBR carrier streams 50a to 50c and outputs a first CBR carrier stream 50a at a respective demultiplexer output 50 coupled to CPOR the update logic 14, a second CBR carrier stream 50b at a respective demultiplexer output 50 coupled to CPOR the update logic 14, and so on to the 3 rd CBR carrier stream 50c output at a respective demultiplexer output 50 coupled to CPOR the update logic 14. Although 3 CBR carrier stream outputs are shown, n CBR carrier streams may be output at n respective demultiplexer outputs 50.

The respective ones of CBR carrier streams 50 a-50 c (e.g., each of CBR carrier streams 50 a-50 c) include CRR indicating the measured bit count of the respective CBR client at the source node and CPOR-P indicating CPO-P (i.e., the CPO of the previous node). CPOs of respective ones of the CBR carrier streams (e.g., each of CBR carrier streams 50 a-50 c) are calculated and CPOs-P of respective ones of the CBR carrier streams 50 a-50 c are replaced with the calculated CPOs of the respective CBR carrier streams, wherein the calculated CPOs are a function of the CPOs-P of the particular carrier stream and the calculated PSPO.

In fig. 7, an example of CPOR update logic 14 is shown as CPOR update logic 14a, which CPOR update logic includes CPOR-P registers 55, PSPO registers 95 (e.g., self-cleaning registers), adder circuits 57, CPO replacement logic 58, and outputs 59 coupled to respective ones of FIFOs 52 a-52 c. CPOR-P register 55 is coupled to a demultiplexer output 50, which carries the respective CBR carrier streams. Adder circuit 57 is coupled to CPOR-P register 55 and PSPO register 95.PSPO register 95 is coupled to clock offset circuit 11 (fig. 6) through CPOR update logic input 56, wherein CPOR update logic input 56 is coupled to second subtraction logic 49.CPO replacement logic 58 is coupled to PSPO register 95, to the output of adder circuit 57, and to the output 59 of the corresponding one of FIFOs 52a through 52 c. In one example, CPO replacement logic 58 indicates that the CPO has been replaced with the CPRO _updated signal to trigger PSPO register 95 to clear to value 0.

Continuing with FIG. 7, CPOR-P indicating CPO-P is received at CPOR-P register 55. Adder circuit 57 obtains calculated PSPO from PSPO registers 95 and calculates the CPOs of the respective ones of the CBR carrier streams by adding calculated PSPO to the CPOs-P of the respective CBR carrier streams. CPOR update logic 14a replaces CPO-P in CPOR-P with the calculated CPO of the respective CBR carrier stream to generate updated CPOR of the respective CBR carrier stream, which updated CPOR is output to the corresponding FIFOs 52 a-52 f. When CPOR-P is replaced with the calculated CPO, PSPO register 55 is reset to the value "0". In this example, there is a single PSPO calculated from the PHY link, and the calculated PSPO is shared by all CBR carriers demultiplexed from the particular PHY link. Alternatively, the CPO-P is replaced with a function of the calculated CPO (such as an offset relative to the calculated CPO or a code of the calculated CPO).

In the example shown in fig. 7, source node 1 generates CPOR placeholders and the corresponding one of the intermediate nodes updates CPOR by adding calculated PSPO indicative of the "phase delta" (e.g., relative phase change) of the PHY-scaled logic flow derived from the ingress PHY link to what that node expects to see using its own local reference clock signal 39a (i.e., LPSD). PSPO (e.g., "phase delta") can be positive or negative, such as +3, -7, +6, but is not limited thereto. Whatever the value, the node adds the value to the received CPOR embedded within the corresponding CBR carrier stream by adding the calculated PSPO to the CPO-P and replacing CPOR 40 with the resulting value. If PSPO is negative, this addition will result in the calculated CPO in output CPOR being less than the CPO-P from the previous network node. If the calculated PSPO is positive, this addition will result in the calculated CPO in output CPOR being greater than the CPO-P from the previous network node. In any case, CPOR updates have the effect of accumulating PSPO (e.g., "phase delta") as PSPO traverses the network. CPOR may be lost in transmission. If this happens, the sink will lose a set of phases delta from the intermediate node between the source and sink. The method and apparatus shown in fig. 8 aim to solve this problem.

In an alternative example shown in fig. 8, the calculated CPOs are a function of all CPOs-P received by the intermediate network node 3 from the last initialization of the intermediate network node 3 and a function of all PSPO calculated by the intermediate network node 3 from the last initialization of the intermediate network node 3. In this example, CPOR update logic 14b is shown as including CPOR-P register 55, accumulator 60, previous CPOR-P register 61, subtraction logic 62, accumulator 63, adder logic 64, CPO replacement logic 58, and output 59 coupled to respective ones of FIFOs 52 a-52 c. Subtraction logic 62 may be implemented by a subtraction circuit and adder logic 64 may be implemented by an adder circuit. CPOR-P register 55 is coupled to a demultiplexer output 50 carrying the corresponding CBR carrier stream and to a preceding CPOR-P register 61. Subtraction logic 62 is coupled to CPOR-P register 55, previous CPOR-P register 61, and accumulator 63. Adder logic 64 is coupled to accumulator 63, accumulator 60, and CPO replacement logic 58. Accumulator 60 is coupled to clock offset circuit 11 (fig. 6) through CPOR update logic input 56. CPO replacement logic 58 is coupled to demultiplexer output 50 and to an output 59 of a respective one of FIFOs 52a through 52 c.

CPOR update logic 14b receives CPOR-P from the respective CBR carrier stream at CPOR-P register 55. When the next CPOR-P is received, the previous CPOR-P moves to the previous CPOR-P register 61, becomes "previous CPOR-P", and the received CPOR-P is stored in CPOR-P register 55. Subtracting logic 62 subtracts the CPO-P stored in the previous CPOR-P in previous CPOR-P register 61 from the current CPO-P in CPOR-P register 55 to obtain a delta cumulative phase offset (D-CPO). Accumulator 63 calculates an accumulated delta accumulated phase offset by accumulating all D-CPOs calculated by the particular intermediate network node since the last initialization of the particular intermediate network node (ADCPO). Accumulator 60 calculates the accumulated PSPO (APSPO) by accumulating all calculated PSPO received at input 56 since the last initialization of a particular intermediate network node 3. Adder logic 64 adds ADCPO and APSPO to calculate a CPO, which may also be referred to as an Accumulated CPO (ACPO). The CPO replacement logic 58 receives the CBR carrier streams and replaces the CPO-P in CPOR-P with ACPO to generate updated CPOR of the respective CBR carrier streams, which updated CPOR is output to the respective ones of FIFOs 52a through 52f at output 59.

In applications where the PHY link may experience a high bit error rate, cells and packets carrying CPOR may be discarded due to CRC validation failure. The example shown in fig. 8 tolerates dropped CPOR cells and packets. More specifically, instead of calculating the CPO by adding PSPO to the CPO-P as in the embodiment of FIG. 7, the current incoming CPOR-P and the previous CPOR-P are used to ensure that the calculated CPO is correct. If CPOR is lost, the received CPOR-P is not actually the previous CPOR-P, but the previous CPOR-P of the previous CPOR-P. In the example where CPOR sequences are present, the latest to oldest may be marked as: CPOR5, CPOR, CPOR, CPOR, CPOR1.CPRO1 first reaches the last intermediate network node 3c. CPOR2 is the next arrival and CPOR is the most recent arrival. Accumulator 63 accumulates the differences as reflected by each incoming CPOR. Consider the case of CPOR where 3 is lost due to damage. The previous CPOR-P register 61 in fig. 8 would contain CPOR2 and the current CPOR-P register 55 would contain CPOR. The difference between CPOR and CPOR2 is equal to (CPRO 3-CPOR 2) + (CPOR 4-CPOR 3). Thus, the value in Accumulator (ADCPO) will catch up with the same value as if no CPOR were lost. Thus, the lost CPOR does not continue to fail.

The CBR carrier streams are multiplexed into intermediate network node data streams and these intermediate network node data streams are transmitted from the respective intermediate network nodes. In fig. 6, multiplexer 13 receives the outputs of FIFOs 52a through 52f and multiplexes the outputs of FIFOs 52a through 52f (CBR carrier streams) into intermediate network node data streams that are coupled to respective encoders in encoder 15 that encode the received intermediate network node data streams to output corresponding INN data streams on respective PHY link outputs 9. The clock at the PHY link output is phase locked to a local reference clock signal 39a received at local reference clock input 39 via transmit PLL 16. The respective ones of the intermediate network node data flows comprise CRRs generated by the source node 1 and the intermediate network node 3 is not required to change the content of any of the CRRs. In one example, none of the intermediate network nodes 3 changes the content of any of the CRRs.

Fig. 9 shows a sink node 2. In the following discussion, many of the operations of sink node 2 are performed in the same manner as they were performed at the intermediate network node. To distinguish the calculated and resulting values at the sink node from the calculated and resulting values performed at the intermediate network node, the corresponding values are indicated as "sink" values and the other items are distinguished from those of the intermediate network node by adding "S" to the end of the relevant item, and by adding the phrase "sink node" after the respective item, wherein the numbers of some of the similar elements in the sink node are distinguished from those of fig. 6 by adding "-1" to the respective numbers of the particular elements in fig. 6.

Sink node 2 includes PHY link input 8-1, local reference clock input 39-1 for receiving local reference clock signal 39a-1, clock offset circuit 11-1, demultiplexers 12-1, CPOR update logic 14-1, sink output processing circuit 79, other sink node circuits 70, and outputs 78 a-78 d. The demultiplexer 12-1 is coupled to the PHY link inputs 8-1 and CPOR update logic 14-1. Clock offset circuit 11-1 is coupled to local reference clock input 39-1, PHY link inputs 8-1 and CPOR update logic 14-1. The aggregate output handling circuit 79 is coupled to CPOR the update logic 14-1 and to the output 78. The clock offset circuit 11 includes a sampling pulse generator 41-1, an accumulated phase counter circuit 42-1, a clock recovery circuit 43-1, a clock scaler circuit 44-1, a current count register 45-1, a previous count register 46-1, a first subtraction logic 48-1, a second subtraction logic 49-1, and an LPSD register 47-1. The first subtracting logic 48-1 and the second subtracting logic 49-1 may be implemented as respective subtracting circuits. The sampling pulse generator 41-1 is coupled to the reference clock input 39-1 and the accumulated phase counter circuit 42-1. Clock recovery circuit 43-1 is coupled to a corresponding PHY link input 8-1 and clock scaler circuit 44-1. The accumulated phase counter circuit 42-1 is coupled to the current count register 45-1 and the clock scaler circuit 44-1. The current count register 45-1 is coupled to the previous count register 46-1. The first subtraction logic 48-1 is coupled to the current count register 45-1, the previous count register 46-1, and the second subtraction logic 49-1. The second subtraction logic 49-1 is coupled to the LPSD registers 47-1 and CPOR update logic 14-1.

The aggregate output handling circuit 79 includes CPO extraction logic 71, read modulator 72, CRR extraction logic 73, CBR extraction logic 74, CRR FIFO 75, CBR payload FIFO 76, and transmit PLL 77.CPO extraction logic 71 is coupled to output 59-1 of CPOR update logic 14-1, which outputs CBR carrier stream 50d with updated CPOR and is coupled to read modulator 72.CRR extraction logic 73 and CBR extraction logic 74 are coupled to output 50-1 of demultiplexer 12-1 to receive one of CBR carrier streams 50a through 50 c. The CRR FIFO 75 is coupled to the read modulator 72, the CRR extraction logic 73 and the transmit PLL 77. The transmit PLL 77 is coupled to the local reference clock input 39-1.CBR payload FIFO 76 is coupled to CBR extraction logic 74 and transmit PLL 77. The other sink circuits 70 are coupled to the local reference clock input 39-1, PHY link input 8, and outputs 78 b-78 d.

Intermediate network node data streams 8e to 8h are received at sink node 2. In fig. 9, the sink node 'S clock offset circuit 11-1 receives the INN data stream at PHY link input 8-1, and the clock offset circuit 11-1 measures the bit count of the received INN data stream based on the sink node' S local reference clock signal 39a-1 and calculates PSPO-S of the received intermediate network node data stream. In this example PSPO-S is calculated in the same manner as PSPO is calculated at the intermediate network node and indicates the difference between the CPSC delta and the LPSD in the particular INN data stream received at the sink node.

The following is an example of processing a single INN data stream 8e to obtain a CBR signal with a recovered client signal 78 a. The processing of the other INN data streams 8 f-8 h may be performed in the same manner as the INN data stream 8e, and some or all of the means for processing the INN data streams 8e shown in fig. 9 may be included in the other sink node circuitry 70 for processing the INN data streams 8 f-8 h (e.g., the other sink node circuitry 70 may include the same set of circuitry for processing each of the INN data streams 8 f-8 h). The PHY link input 8-1 of the sink node receives an intermediate network node data stream 8e from the last intermediate network node. The clock offset circuit 11-1 of the sink node is coupled to the PHY link input 8-1 of the sink node to: accumulating the counter of IPSCk at the sink node with Tps of the sink node's local reference clock to obtain the CPSC at the sink node, the IPSCk being generated by scaling the clock recovered from the received intermediate network node data stream of the last intermediate network node 8e to Fipsck; and calculating PSPO (PSPO-S) at the sink node, the PSPO-S indicating a phase difference between the LPSD at the sink node and the IPSD at the sink node, wherein the IPSD at the sink node indicates a CPSC delta between consecutive CPSC samples at the sink node. The sink node's demultiplexer 12-1 is coupled to the sink node's PHY link input 8-1 to demultiplex intermediate network node data streams received from the last intermediate network node 8e to obtain individual CBR carrier streams at the sink nodes 50d to 50 f. The CPOR update logic 14-1 of the sink node is coupled to the clock offset circuit 11-1 to calculate the CPO (CPO-S) at the sink node for the respective one of the CBR carrier streams 50 d-50 f by summing PSPO-S with the CPO-P received at the sink node (i.e., received from the last intermediate network node) for the respective CBR data stream 50 d-50 f. The aggregate output handling circuit 79 is coupled to the aggregate node 'S demultiplexer 12-1 and the aggregate node' S CPOR update logic 14-1 to recover the CBR client signal using the CPO-S and the CRR corresponding to the particular CBR signal. The PHY link output 78 of the sink node is coupled to the sink output processing circuit 78 to output CBR signals from the sink node including the recovered CBR client signals.

In one example, the CPO-S is calculated in the same manner as shown with respect to FIG. 7, where calculating the CPO-S includes adding the calculated PSPO-S to the CPO-P (e.g., CPO-P from the last intermediate network node) received at the sink node for the corresponding CBR data stream. In one example, the intermediate network node data stream 8e includes CPOR-P indicating the CPO-P from the last intermediate network node, which CPOR-P is demultiplexed to obtain individual CBR carrier streams 50d to 50f output at the respective demultiplexer outputs 50-1. CPOR update logic 14-1 calculates the CPO-S of carrier flow 50d that replaces the CPO-P in CBR carrier flow 50d to form a first updated CPOR at sink node 91 a. CPOR update logic 14-1 calculates the CPO-S of carrier flow 50e that replaces the CPO-P in CBR carrier flow 50e to form a second updated CPOR at sink node 91b, and so on to the nth CPO-S91 c of nth CBR carrier flow 50f.

In another example, CPO-S is calculated in the same manner as shown in FIG. 8, with CPOR update logic 14b receiving CPOR-P from the corresponding CBR carrier streams 50 d-50 f at CPOR-P register 55, which CPOR-P is CPOR-P from the last intermediate network node. When the next CPOR-P is received, the previous CPOR-P moves to the previous CPOR-P register 61, becomes the "previous CPOR-P" at the sink node and the received CPOR-P is stored in CPOR-P register 55. Subtracting logic 62 subtracts the CPO-P stored in the previous CPOR-P in previous CPOR-P register 61 from the current CPO-P in CPOR-P register 55 to obtain the delta-cumulative phase offset (D-CPO) at the sink node. Accumulator 63 calculates an aggregate accumulated delta accumulated phase offset by accumulating all D-CPOs calculated by the sink node since the last initialization of the sink node (ADCPO-S). The accumulator 60 calculates an aggregate accumulation PSPO (APSPO-S) by accumulating all calculated PSPO received at the input 56 since the last initialization of the sink node. Adder logic 64 adds ADCPO-S to APSPO-S to calculate CPO-S. The CPO replacement logic 58 receives the CBR carrier streams 50d through 50f and replaces CPOR-P with the calculated CPO-S to generate updated CPOR of the respective CBR carrier streams 50d through 50f, which updated CPOR is output to the CRR extraction logic 71 at output 59.

Optionally, the CPO-P received at the sink node is replaced with the CPO-S of the corresponding CBR carrier stream (e.g., such that the circuitry of CPOR update logic 14 is identical to CPOR update logic 14-1 to simplify design and manufacturing). The converged output processing circuit 79 uses the CPO-S and the CRR corresponding to the particular CBR signal to recover the CBR client signal. PHY link output 78 is coupled to aggregate output processing circuitry 79 to output CBR signal 78a, including the gray-multiplexed CBR client signal, from the aggregate node.

In fig. 9, a single aggregate output handling circuit 79 is shown to illustrate the handling of 91a and CBR carrier flow 50 d. However, in one example, the aggregate output handling circuit 79 includes similar or identical circuits coupled to each output 59 that operate in the same manner as the illustrated aggregate output handling circuit 79 for handling the first update CPOR and the first carrier flow 50d at the aggregate node 91 a.

In one example, CRR extraction logic 73 extracts an incoming CRR from CBR carrier stream 50d and stores it in CRR FIFO 75. CRR FIFO 75 is read nominally at Tcrr as measured by a local reference clock, and the phase value in the CRR is sent to transmit PLL 77 as the reference input phase. In one example, CPOR update logic 14-1 generates a new CPOR at CPOR of the first update at sink node 91 a. The new CPOR is coupled to the CPO extraction logic 71, which extracts the CPO-S and indicates the corresponding CPO-S to the read modulator 72. In the example shown in FIG. 7, CPO-S may be taken directly from CPOR update logic 14-1 and used by read modulator 72 to modulate an instance of the read-out of the CRR from CRR FIFO 75. However, in the example shown in FIG. 8, since CPO is an accumulated value, the previous CPO-S is subtracted from the new CPO-S to identify the CPO-S to be used by the read modulator 72 to modulate an instance of the read-out CRR from the CRR FIFO 75. If the CPO-S indicates that there is a positive ppm offset (RPPMpath is positive) between the reference clock at the source node relative to the sink node, then the CRR FIFO is read more frequently than Tcrr. Conversely, if the CPO-S indicates that there is a negative ppm offset between the reference clock relative to the sink node (if RPPMpath is negative), then the CRR FIFO is read less frequently than Tcrr. CBR extraction logic 74 receives CBR carrier stream 50d and extracts CBR client signals, which are coupled to CBR payload FIFO 76. The transmit PLL 77 is coupled to the local reference clock input 39-1 and receives the reference clock signal 39a-1 and provides the transmit clock signal to the CBR payload FIFO 76 to regenerate a phase-locked copy of the client stream of the source node. An implementation alternative to the modulated CRR FIFO read example is described in U.S. patent 8,542,708 and 9,019,997, the entire contents of which are incorporated herein by reference.

Fig. 10A shows a block of a method 100 in which a data stream (101) generated by a previous network node is received. The received data stream includes a CBR carrier stream corresponding to a CBR signal received at the source node. The accumulated IPSCk counter is sampled (102) with Tps of the local reference clock of the intermediate network node to obtain the CPSC of the received respective data stream, which IPSCk is generated by scaling the clock recovered from the received respective data stream to Fipsck _nom. A calculation (103) indicates PSPO of a phase difference between the LPSD and the IPSD, where the IPSD represents an increment between consecutive CPSCs. In one example, LPSD represents an amount based on the expected delta of Fipck _nom and Tps at the intermediate network node. In one example shown in block 103-1 of FIG. 10B, PSPO is calculated by: calculate IPSD indicating an increase in bit count within Tps (e.g., by subtracting the previous CPSC from the current CPSC); and subtracting the LPSD from the IPSD), wherein PSPO is calculated in phase units and the LPSD is a function of Fipsck _nom and Tps.

The received data streams are demultiplexed (104) to obtain CBR carrier streams, respective ones of which include CPOR-P, which is indicative of CPO-P. In the example shown in block 104-1 of fig. 10C, each of the CBR carrier streams further includes a CRR that indicates the measured bit count of the corresponding CBR client at the source node. In one example, the intermediate network nodes 3 to 3c do not change the content of the CRR. In one example, no intermediate network node is required to terminate any of the CRRs, generate new CRRs, or change the contents of any of the CRRs. In one example, the intermediate network nodes 3 to 3c do not terminate any of the CRRs, do not generate new CRRs, or do not change the content of any of the CRRs.

Calculating (105) a CPO of a respective one of the CBR carrier streams (e.g., each of the CBR carrier streams) and replacing (106) the CPO-P of the respective one of the CBR carrier streams (e.g., each of the CBR carrier streams) with the calculated CPO of the respective CBR carrier stream, wherein the calculated CPO is a function of the CPO-P of the particular carrier stream and the calculated PSPO. In the example shown in block 105-1 of FIG. 10D, the CPO is calculated by adding PSPO of the calculated CPO to the CPO-P. In the example shown in block 105-2 of fig. 10E, the CPO is a function of all CPOs-P received by the intermediate network node since the last initialization of the intermediate network node. In the example shown in block 105-3 of fig. 10F, the CPO is an accumulated PSPO (ACPO) calculated by: calculating a delta cumulative phase offset (D-CPO) by subtracting a previously received CPO-P from the CPO-P; calculating an accumulated D-CPO (ADCPO) by accumulating all D-CPOs calculated by the intermediate network node since the last initialization of the intermediate network node; calculating an accumulated PSPO (APSPO) by accumulating all PSPO calculated by the intermediate network node since the last initialization of the intermediate network node; and adding APSPO to ADCPO).

The CBR carrier streams are multiplexed into intermediate network node data streams (107), and these intermediate network node data streams are transmitted (108) from the respective intermediate network nodes.

Fig. 10G illustrates blocks of the method 100 performed at the sink node. An intermediate network node data stream is received (100-1) from a last intermediate network node at the sink node. The method includes sampling (100-2) a counter accumulating PHY-scaled stream clocks (IP SCk-S) at sink nodes with Tps based on the sink node' S local reference clock to obtain accumulated PHY-scaled counts (CPSC-S) at the sink nodes, the IPSCk-S generated by scaling clocks recovered from the received intermediate network node data stream of the last intermediate network node to Fipsck _nom. The PHY-scaled stream phase offset (PSPO-S) at the sink node is calculated (100-3) by subtracting the LPSD at the sink node from an incoming PHY-scaled count delta (IPSD-S) at the sink node, where the IPSD-S represents an increment between consecutive CPSC-S, which may be referred to as a CPSC-S increment. The received intermediate network node data streams from the last intermediate network node are demultiplexed (100-4) to obtain individual CBR carrier streams.

CPO (CPO-S) at the sink node is calculated (100-5) for respective ones of the CBR carrier flows. In the example shown in block 100-5-1 of fig. 10H, calculating the CPO-S includes adding the calculated PSPO-S to the CPO-P received at the sink node for the corresponding CBR data stream. In the example shown in block 100-5-2 of FIG. 10I, the calculated CPO-S is calculated ACPO by: calculating a delta cumulative phase offset (D-CPO) at the sink node by subtracting a previously received CPO-P received at the sink node from a CPO-P received at the sink node; computing a converged accumulated D-CPO (ADCPO-S) by accumulating all D-CPOs computed by the sink node since the last initialization of the sink node; computing a aggregate accumulation PSPO (APSPO-S) by accumulating all PSPO computed by the sink node since its last initialization; and adding APSPO-S to ADCPO-S.

The calculated CPO-S and the CRR corresponding to the particular CBR signal are used to recover (100-6) the CBR client signal. A CBR signal comprising the restored CBR client signal is output (100-7) from the sink node.

According to the method and apparatus of the present invention, the ppm offset of a respective one of the nodes is represented by CPOR generated by the respective one of the nodes. At the sink node, the received CPOR is generated by the last switching node, and thus only the relative ppm offset between the last switching node and the sink node needs to be biased (RPPMsk). The CRR is generated by the source node and forwarded verbatim to the sink node. The ppm offset of the source node is denoted CRR, which may be ITU GMP based or similar. The sink node uses a relative ppm offset (RPPMpath) between the source node and the sink node to bias the processing of the received CRR.

The method and apparatus of the present invention measures ppm offset between node pairs and then sums the measured ppm offset together to obtain the source to sink ppm offset. In the source node 1, there are actually two ppm offsets to work. One is ppm offset of CBR clients from their nominal value. This is what the CRR encodes. Unfortunately, when this is done, the measurement is contaminated by ppm offset of the local reference clock at the source node 1. This is the second ppm offset. For example, when a CBR client is 10ppm faster than its nominal value, if the local reference clock 20 is fully nominal, the CRR will indicate only such 10ppm value. If the source local reference clock 20 is also 10ppm faster, the CRR will report the nominal value falsely.

The inventive method and apparatus uses CPOR to communicate RPPMpath to the aggregate output handling circuit 79 to avoid the problem of measurement contamination by the reference clock at the source node 1. Because the present methods and apparatus share a common mathematical basis with the ITU GMP scheme, both are expected to have similar jitter and drift performance.

The following is an example in which the network 4 of fig. 1 comprises intermediate network node switches 3a to 3 c. In this example, the PHY-scaled stream phase offset measured at the first intermediate network node switch 3a is indicated by PSPO ₁, the PHY-scaled stream phase offset measured at the second intermediate network node switch 3b is indicated by PSPO ₂, the PHY-scaled stream phase offset measured at the third intermediate network node switch 3c is indicated by PSPO ₃, and the PHY-scaled stream phase offset measured at the sink node switch 2 is indicated by PSPO-S. In this example, the CPO ₀ sent to the first intermediate network node switch 3a will have an initial value of zero. At the output of the intermediate network node switch 3a, the CPO in the intermediate network node data flow will have a calculated CPO (CPO ₁) reflecting the sum of 0 (initial CPO value) and PSPO ₁. At the output of the intermediate network node switch 3b, the CPO in the intermediate network node data flow will have the calculated CPO (CPO ₂) as PSPO ₁+PSPO₂. At the output of the intermediate network node switch 3c, the CPO in the intermediate network node data flow will have the calculated CPO (CPO ₃) as PSPO ₁+PSPO₂+PSPO₃. The corresponding CPO-S calculated at sink node 2 will be PSPO ₁+PSPO₂+PSPO₃ + PSPO-S. Thus, the CPO-S will be the accumulation of all relative PPM offsets in the path and will indicate the relative parts per million (RPPMpath) of the entire path.

In one example, the ppm offset of the local reference clock in the source node is PPMsrc relative to the nominal value. The measured rate of the CBR client at the source node is encoded into the period CRR. The nominal period between CRRs is Tcrr as measured by the local reference clock at source node 1. The CPOR of the carrier stream is nominally generated once every Tcpor cycles, as measured by the local reference clock of the source node 1. CPOR may be initialized to 0 or some other predetermined value.

In this example, a respective one of the intermediate network node switches 3 a-3 c demultiplexes a respective one of the data streams (e.g., each of the data streams) into a set of n CBR carrier streams (each CBR carrier stream for a respective one of the CBR signals) and monitors for the presence of CPOR of the respective ones of the carrier streams. PSPO, which is common to all CBR carriers sharing the same PHY link, is then summed by CPOR update logic 14 into incoming CPOR. Because CPOR is generated more frequently than PSPO (Tps > Tcpor), there are more CPOR values than PSPO values in any given time period. In one example, once PSPO has been summed into CPOR of a CBR carrier, the subsequent CPOR of that CBR carrier will be left unmodified until a new PSPO is available. In another example, once PSPO has been added up into CPOR of a CBR carrier, the subsequent CPOR of that CBR carrier will be updated using the same PSPO until a new PSPO is available.

In one example, the calculated CPO may be positive (when the measured bit count is greater than the PHY-scaled stream nominal bit count value) or negative (when the measured bit count is less than the PHY-scaled stream nominal bit count value). In one example, CPOR update logic 14 calculates the CPO by adding PSPO to the P-CPO when the measured bit count is greater than the PHY-scaled stream nominal bit count value; and when the measured bit count is less than the PHY-scaled stream nominal bit count value, CPOR update logic 14 calculates the CPO by adding the calculated PSPO (negative value) to the CPO-P.

Certain complications and details commonly known to those of ordinary skill in the relevant art have been omitted or discussed in less detail for clarity and brevity, and to avoid unnecessary or unwanted confusion, obscuring, blocking, or occlusion of the features or elements of the examples of the present disclosure. Any such omissions or discussions are not deemed necessary to describe examples of the present disclosure and/or to implement an understanding of the salient features, functions, elements, and/or aspects of the examples of the present disclosure as described herein.

In the description and drawings herein, exemplary implementations are thus described with respect to the claims set forth below. However, the disclosure is not limited to these examples, and the description and drawings herein are therefore intended to inspire an understanding, appreciation, and suggestion of alternatives and equivalents thereof by those of ordinary skill in the art relating to integrated circuits.

Claims

1. A method, the method comprising:

receiving, at an intermediate network node, a data stream generated by a previous network node, wherein the received data stream comprises a Constant Bit Rate (CBR) carrier stream corresponding to a Constant Bit Rate (CBR) signal received at a source node;

Sampling a counter accumulating PHY-scaled stream clocks (IPSCk) with a nominal sampling period (Tps) of a local reference clock of the intermediate network node to obtain accumulated PHY-scaled counts (CPSCs) of the received respective data streams, the IPSCk being generated by scaling clocks recovered from the received respective data streams to a predetermined nominal frequency (Fipsck _nom);

calculating a PHY-scaled stream phase offset (PSPO), the PSPO indicating a phase difference between a PHY-scaled stream nominal bit count (LPSD) and an incoming PHY-scaled count delta (IPSD), wherein the IPSD indicates an increment between consecutive CPSCs;

Demultiplexing the received data streams to obtain the CBR carrier streams, respective ones of the CBR carrier streams comprising a previous network node accumulated phase offset report (CPOR-P) indicating a previous network node accumulated phase offset (CPO-P) and a Client Rate Report (CRR) indicating measured bit counts of respective CBR clients at the source node;

Calculating a Cumulative Phase Offset (CPO) of a respective CBR carrier stream of the CBR carrier streams, the CPO being a function of the CPO-P of the respective CBR carrier stream and the calculated PSPO;

Replacing CPOs-P in a respective one of the CBR carrier streams with calculated CPOs of the respective CBR carrier stream or a function of the calculated CPOs of the respective CBR carrier stream to generate updated CPOR to replace the CPOR-P in the respective CBR carrier stream;

Multiplexing the CBR carrier stream into an intermediate network node data stream; and

The intermediate network node data stream is sent from a particular intermediate network node.

2. The method of claim 1, wherein the LPSD is a function of the Fipsck _nom and the Tps, and wherein the PSPO is in phase, and wherein calculating the PSPO comprises:

calculating the IPSD; and

The LPSD is subtracted from the IPSD.

3. The method of claim 1, wherein the CPO is calculated by adding the calculated PSPO to the CPO-P.

4. The method of claim 1, wherein the calculated CPO is a function of all CPOs-P received by the intermediate network node since a last initialization of the intermediate network node.

5. The method of claim 1, wherein calculating the CPO comprises:

Calculating a delta cumulative phase offset (D-CPO) by subtracting a previously received CPO-P from said CPO-P;

Calculating an accumulated D-CPO (ADCPO) by accumulating all of the D-CPOs calculated by the intermediate network node since the last initialization of the intermediate network node;

Calculating an accumulated PSPO (APSPO) by accumulating all of the PSPO calculated by the intermediate network node since the last initialization of the intermediate network node; and

The APSPO is added to the ADCPO.

6. The method of claim 1, wherein the source node measures bit rates of respective ones of the CBR clients in the CBR signal based on a local reference clock of the source node and encodes the CRR indicative of the measured bit rates of the respective CBR clients into respective ones of the CBR carrier streams, and

Wherein the intermediate network node does not change the content of the corresponding one of the CRRs.

7. The method of claim 1, the method further comprising:

Receiving an intermediate network node data stream from a last intermediate network node at the sink node;

Sampling a counter accumulating PHY-scaled stream clocks (IPSCk-S) at the sink node with Tps based on a local reference clock of the sink node to obtain an accumulated PHY-scaled count (CPSC-S) at the sink node, the IPSCk-S generated by scaling clocks recovered from the received intermediate network node data stream of the last intermediate network node to Fipsck _nom;

Calculating a PHY-scaled stream phase offset (PSPO-S) at the sink node by subtracting the LPSD from an incoming PHY-scaled count delta (IPSD-S) at the sink node, wherein the IPSD-S represents an increment between consecutive CPSC-ss;

Demultiplexing the received intermediate network node data streams from the last intermediate network node to obtain individual CBR carrier streams;

Calculating CPOs (CPOs) at the sink node for respective ones of the CBR carrier streams;

recovering a CBR client signal using the calculated CPO-S and the CRR corresponding to a particular CBR signal; and

And outputting a CBR signal comprising the restored CBR client signal from the sink node.

8. The method of claim 7, wherein calculating the CPO-S comprises adding the calculated PSPO-S to a CPO-P received at the sink node for the respective CBR data stream.

9. The method of claim 7, wherein calculating CPO-S comprises:

calculating a delta cumulative phase offset (D-CPO) at the sink node by subtracting a previously received CPO-P received at the sink node from a CPO-P received at the sink node;

Computing a converged accumulated D-CPO (ADCPO-S) by accumulating all of said D-CPOs computed by said sink node since a last initialization of said sink node;

Calculating a aggregate accumulation PSPO (APSPO-S) by accumulating all of the PSPO calculated by the sink node since a last initialization of the sink node; and

Adding said APSPO-S to said ADCPO-S.

10. An Integrated Circuit (IC) device for an intermediate network node, the IC device comprising:

A PHY link input for receiving a data stream generated by a previous network node, the data stream comprising a plurality of Constant Bit Rate (CBR) carrier streams, respective ones of the CBR carrier streams comprising a previous network node accumulated phase offset report (CPOR-P) indicating a previous network node accumulated phase offset (CPO-P) and a Client Rate Report (CRR) indicating a measured bit count of the respective CBR client at the source node;

A clock shifting circuit coupled to the PHY link input for sampling a counter accumulating PHY-scaled stream clocks (IPSCk) with a nominal sampling period (Tps) of a local reference clock of the intermediate network node to obtain accumulated PHY-scaled counts (CPSCs) of the received respective data streams, the IPSCk being generated by scaling clocks recovered from the received respective data streams to a predetermined nominal frequency (Fipsck _nom); and to calculate a PHY-scaled stream phase offset (PSPO) indicative of a phase difference between a PHY-scaled stream nominal bit count (LPSD) and an incoming PHY-scaled count delta (IPSD), wherein the IPSD is indicative of the delta between consecutive CPSCs;

a demultiplexer coupled to the PHY link input for demultiplexing the received data streams to obtain the plurality of CBR carrier streams;

Accumulated phase offset reporting (CPOR) update logic coupled to the demultiplexer and the clock offset circuit to calculate accumulated phase offsets (CPOs) of respective ones of the CBR carrier streams, wherein the calculated CPOs are a function of the CPO-P and the calculated PSPO; and to replace the CPO-P with the calculated CPO of the respective CBR carrier stream or with a function of the calculated CPO of the respective CBR carrier stream; and to generate updated CPOR of the respective CBR carrier stream to replace the CPOR-P in the respective CBR carrier stream;

A multiplexer coupled to the demultiplexer and the CPOR update logic to multiplex the CBR carrier stream into a plurality of intermediate network node data streams;

An encoder coupled to the multiplexer to encode the plurality of intermediate network node data streams; and

A PHY link output coupled to the encoder to transmit the plurality of intermediate network node data streams from the IC device.

11. The IC device of claim 10, wherein the PHY link input, the clock offset circuit, the demultiplexer, the CPOR update logic, the encoder, and the output circuit are provided in a single integrated circuit die.

12. The IC device of claim 10, wherein the CPOR update logic is to calculate the CPO by adding the calculated PSPO to the CPO-P.

13. The IC device of claim 10, wherein the CPOR update logic calculates the CPO by:

The ADCPO is added to the APSPO.

14. The IC device of claim 10, wherein the clock offset circuit comprises:

a reference clock input for receiving the local reference clock signal;

a sampling pulse generator coupled to the reference clock input to generate sampling pulses at Tps;

a clock recovery circuit coupled to the PHY input to recover a PHY link clock signal;

A clock scaler circuit coupled to the clock recovery circuit and the sampling pulse generator to scale the recovered PHY link clock signal to the Fipsck _nom to obtain the PHY-scaled stream clock;

an accumulated phase counter circuit coupled to an output of the clock scaler circuit and the sampling pulse generator, the accumulated phase counter circuit sampling the counter that accumulates IPSCk at TPs to obtain the CPSC;

A first register coupled to the accumulated phase counter circuit to store the CPSC;

a second register coupled to the first register to store a previous CPSC;

First subtracting logic coupled to the first register and the second register to subtract the previous CPSC from the CPSC to obtain the IPSD;

A third register for storing the LPSD; and

Second subtracting logic coupled to the first subtracting logic to subtract the LPSD from the IPSD to calculate the PSPO.

15. The IC device of claim 10, wherein the intermediate network node does not change the content of a respective one of the CRRs.

16. A network, the network comprising:

a source node, the source node comprising:

An input for receiving a plurality of Constant Bit Rate (CBR) signals,

An accumulated phase offset report (CPOR) generation circuit for generating CPOR indicative of an initial accumulated phase offset (CPO),

A CRR generation circuit for generating a Client Rate Report (CRR) indicating the measured bit rate of the respective CBR client, and

A CBR mapper coupled to the input for generating a corresponding CBR carrier stream for a respective one of the CBR signals, and for inserting the CRR and CBR client data into the respective CBR carrier stream,

Source output processing circuitry for inserting the CPOR into a respective CBR carrier stream and multiplexing the CBR carrier streams to generate a plurality of source data streams;

A plurality of intermediate network nodes coupled to the source node, respective ones of the intermediate network nodes comprising an Integrated Circuit (IC) device comprising:

A PHY link input for receiving a data stream generated by a previous network node, the data stream comprising a plurality of CBR carrier streams, respective ones of the CBR carrier streams comprising the CRR and a previous network node accumulated phase offset report (CPOR-P) indicating a previous network node accumulated phase offset (CPO-P);

a clock offset circuit coupled to the PHY link input to:

Sampling a counter accumulating PHY-scaled stream clocks (IPSCk) with a nominal sampling period (Tps) of a local reference clock of the intermediate network node to obtain an accumulated PHY-scaled count (CPSC) of the received respective data stream, the IPSCk being generated by scaling clocks recovered from the received respective data stream to a predetermined nominal frequency (Fipsck _nom), and

Calculating a PHY-scaled stream phase offset (PSPO), the PSPO indicating a phase difference between a PHY-scaled stream nominal bit count (LPSD) and an incoming PHY-scaled count delta (IPSD), wherein the IPSD indicates the delta between consecutive CPSCs;

a demultiplexer coupled to the PHY link input for demultiplexing the received data stream to obtain the individual CBR carrier streams,

Accumulated phase offset report (CPOR) update logic coupled to the demultiplexer and the clock offset circuit to calculate CPOs for respective ones of the CBR carrier streams, wherein the calculated CPOs are a function of the CPOs-P for the particular CBR carrier stream and the calculated PSPO; and to replace the CPOR-P of the particular CBR carrier stream with the calculated CPO of the particular CBR carrier stream to generate an updated CPOR of the corresponding CBR carrier stream,

A multiplexer coupled to the demultiplexer and the CPOR update logic to multiplex the CBR carrier stream into a plurality of intermediate network node data streams,

An encoder coupled to the multiplexer to encode the plurality of intermediate network node data streams, an

A PHY link output coupled to the encoder to transmit the plurality of intermediate network node data streams from the IC device; and

A sink node coupled to a last one of the intermediate network nodes to receive an intermediate network node data stream from the last one of the intermediate network nodes, recovering a CBR client signal; and outputting, from the sink node, a CBR signal comprising the restored CBR client signal.

17. The network of claim 16, wherein the plurality of intermediate network nodes do not change the content of respective ones of the CRRs.

18. The network of claim 16, wherein the CPOR update logic calculates the CPO by adding the calculated PSPO to the CPO-P.

19. The network of claim 16, wherein the calculated CPOs are a function of all CPOs-P received from a last initialization of the respective intermediate network node and all of the PSPO calculated from the last initialization of the respective intermediate network node.

20. The network of claim 16, wherein the sink node comprises:

The PHY link input of the sink node is configured to receive the intermediate network node data stream from the last intermediate network node;

A clock shifting circuit of the sink node, the clock shifting circuit coupled to the PHY link input of the sink node to:

Sampling a counter accumulating PHY-scaled stream clocks (IPSCk-S) at the sink node with Tps of a local reference clock of the sink node to obtain an accumulated PHY-scaled count (CPSC-S) at the sink node, the IPSCk-S generated by scaling clocks recovered from the received intermediate network node data stream of the last intermediate network node to Fipsck _nom; and

Calculating PSPO (PSPO-S) at the sink node, the PSPO-S indicating a phase difference between LPSD and an incoming PHY-scaled count delta (IPSD-S) at the sink node, wherein the IPSD-S indicates the delta between consecutive CPSC-ss;

A demultiplexer of the sink node coupled to the PHY link input of the sink node for demultiplexing the intermediate network node data stream received from the last intermediate network node to obtain the individual CBR carrier streams at the sink node;

CPOR update logic of the sink node, the CPOR update logic coupled to the clock offset circuit to calculate a CPO (CPO-S) at the sink node for a respective one of the CBR carrier streams by summing the PSPO-S with a CPO-P of the respective CBR data stream received at the sink node;

a converged output processing circuit coupled to the demultiplexer of the sink node and the CPOR update logic of the sink node to recover the CBR client signal using the CPO-S and the CRR corresponding to the particular CBR signal; and

A PHY link output of the sink node, the PHY link output coupled to the sink output processing circuit to output a CBR signal from the sink node comprising the recovered CBR client signal.