CN117979751A

CN117979751A - Display substrate, preparation method thereof and display device

Info

Publication number: CN117979751A
Application number: CN202410205573.1A
Authority: CN
Inventors: 安一; 陈家兴; 尚庭华; 杜丽丽; 李正坤; 牛佐吉; 杨中流
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2024-02-23
Filing date: 2024-02-23
Publication date: 2024-05-03

Abstract

A display substrate, a manufacturing method thereof and a display device. The display substrate comprises a plurality of circuit units, at least one first data connecting wire and at least one second data connecting wire, wherein the circuit units comprise a pixel driving circuit, a data signal wire and at least one constant potential signal wire, the data signal wire is connected with the first data connecting wire, and the first data connecting wire is connected with the second data connecting wire; the circuit unit further comprises a first fracture and a fracture shielding structure, the first fracture is arranged on the first data connecting line, the fracture shielding structure is connected with the constant potential signal line, the first data connecting line is arranged in one conducting layer, and the fracture shielding structure is arranged in any conducting layer or a plurality of conducting layers except the conducting layer where the first data connecting line is arranged; the orthographic projection of the first fracture on the substrate at least partially overlaps the orthographic projection of the fracture shielding structure on the substrate. The display substrate can improve the transmittance, is beneficial to eliminating shadows, and avoids poor appearance of the display substrate.

Description

Display substrate, preparation method thereof and display device

Technical Field

The invention relates to the technical field of display, in particular to a display substrate, a preparation method thereof and a display device.

Background

Organic LIGHT EMITTING Diodes (OLED) and Quantum-dot LIGHT EMITTING Diodes (QLED) are active light emitting display devices, and have advantages of self-luminescence, wide viewing angle, high contrast ratio, low power consumption, extremely high reaction speed, light weight, flexibility, low cost, and the like. With the continuous development of Display technology, a Flexible Display device (Flexible Display) using an OLED or a QLED as a light emitting device and a thin film transistor (Thin Film Transistor, abbreviated as TFT) for signal control has become a mainstream product in the current Display field.

At present, the prior OLED display device has the problems of low transmittance and the like.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

The technical problem to be solved by the present disclosure is to provide a display substrate, a preparation method thereof, and a display device, so as to solve the problem of low transmittance of the existing display device.

In one aspect, the present disclosure provides a display substrate including a plurality of circuit units, at least one first data link line extending along a first direction, and at least one second data link line extending along a second direction in a direction parallel to the display substrate, the first direction and the second direction intersecting; at least one circuit unit includes a pixel driving circuit, a data signal line configured to supply a data signal to the pixel driving circuit, and at least one constant potential signal line configured to supply a constant potential signal to the pixel driving circuit, the data signal line being connected to the first data link line, the first data link line being connected to the second data link line; the at least one circuit unit further comprises at least one first fracture and at least one fracture shielding structure, the first fracture is arranged on the first data connecting line and cuts off the first data connecting line, and the fracture shielding structure is connected with the constant potential signal line; in the direction perpendicular to the display substrate, the display substrate at least comprises a plurality of conductive layers arranged on a base, the first data connecting wire is arranged in one conductive layer, and the fracture shielding structure is arranged in any conductive layer or a plurality of conductive layers except the conductive layer where the first data connecting wire is arranged; the orthographic projection of the first fracture on the substrate at least partially overlaps the orthographic projection of the fracture shielding structure on the substrate.

In an exemplary embodiment, the at least one fracture shielding structure comprises a first fracture shielding block, wherein the orthographic projection of the first fracture on the substrate and the orthographic projection of the first fracture shielding block on the substrate at least partially overlap, and the first fracture shielding block is arranged in a conductive layer of a side, close to the substrate, of the conductive layer where the first data connecting line is located.

In an exemplary embodiment, the plurality of conductive layers includes at least a first conductive layer disposed on the substrate, a second conductive layer disposed on a side of the first conductive layer away from the substrate, a third conductive layer disposed on a side of the second conductive layer away from the substrate, and a fourth conductive layer disposed on a side of the third conductive layer away from the substrate, the first data link line is disposed in the third conductive layer, and the first fracture shielding block is disposed in the first conductive layer and/or the second conductive layer.

In an exemplary embodiment, the at least one constant potential signal line includes a first initial signal line, the pixel driving circuit includes at least a first transistor and a second transistor, a gate electrode of the first transistor is connected to a second scan signal line, a first electrode of the first transistor is connected to the first initial signal line, a gate electrode of the second transistor is connected to a third scan signal line, and a first electrode of the second transistor is connected to a second electrode of the first transistor; in at least one circuit unit, the first initial signal line is disposed between the second scanning signal line and the third scanning signal line, and the first fracture shielding block is connected with the first initial signal line.

In an exemplary embodiment, in at least one circuit unit, the first data link line is disposed between the second scan signal line and the first initial signal line, and the first break shielding block is disposed at a side of the first initial signal line near the second scan signal line.

In an exemplary embodiment, the first transistor includes at least a first active layer, the second transistor includes at least a second active layer, a second region of the first active layer is connected to a first region of the second active layer, and in at least one circuit unit, an orthographic projection of the first break shielding block on the substrate at least partially overlaps an orthographic projection of the second region of the first active layer on the substrate.

In an exemplary embodiment, the at least one constant potential signal line includes a second initial signal line, the pixel driving circuit includes at least a third transistor and a seventh transistor as driving transistors, a gate electrode of the seventh transistor is connected to the first scanning signal line, and a first electrode of the seventh transistor is connected to the second initial signal line; in at least one circuit unit, the second initial signal line is disposed at a side of the first scanning signal line far away from the third transistor, and the first fracture shielding block is connected with the second initial signal line.

In an exemplary embodiment, in at least one circuit unit, the first data link line is disposed between the first scan signal line and the second initial signal line, and the first break shielding block is disposed at a side of the second initial signal line close to the first scan signal line.

In an exemplary embodiment, at least one first break is provided between the first direction adjacent circuit units, and at least one first break blocking piece is provided between the first direction adjacent circuit units.

In an exemplary embodiment, the at least one circuit unit further comprises at least one second break and at least one second break stop, the second break being provided on the second data connection line and cutting off the second data connection line, an orthographic projection of the second break on the substrate overlapping at least partially an orthographic projection of the second break stop on the substrate.

In an exemplary embodiment, the plurality of conductive layers includes at least a first conductive layer disposed on the substrate, a second conductive layer disposed on a side of the first conductive layer remote from the substrate, a third conductive layer disposed on a side of the second conductive layer remote from the substrate, and a fourth conductive layer disposed on a side of the third conductive layer remote from the substrate, the second data connection line being disposed in the fourth conductive layer, the second fracture shielding block being disposed in any one or more of the first, second, and third conductive layers.

In an exemplary embodiment, the at least one constant potential signal line includes a first initial signal line configured to supply a first initial signal to the pixel driving circuit, and the second break blocking block is connected to the first initial signal line in the at least one circuit unit.

In an exemplary embodiment, the at least one constant potential signal line includes a second initial signal line configured to supply a second initial signal to the pixel driving circuit, and the second break stopper is connected to the second initial signal line in the at least one circuit unit.

In an exemplary embodiment, at least one second break is provided between the first direction adjacent circuit units, and at least one second break blocking piece is provided between the first direction adjacent circuit units.

In an exemplary embodiment, the at least one fracture shielding structure comprises a third fracture shielding block, wherein the orthographic projection of the first fracture on the substrate and the orthographic projection of the third fracture shielding block on the substrate are at least partially overlapped, and the third fracture shielding block is arranged in a conductive layer on the side, away from the substrate, of the conductive layer where the first data connecting line is located.

In an exemplary embodiment, the plurality of conductive layers includes at least a first conductive layer disposed on the substrate, a second conductive layer disposed on a side of the first conductive layer away from the substrate, a third conductive layer disposed on a side of the second conductive layer away from the substrate, and a fourth conductive layer disposed on a side of the third conductive layer away from the substrate, the first data link line is disposed in the third conductive layer, and the third fracture shielding block is disposed in the fourth conductive layer.

In an exemplary embodiment, the at least one constant potential signal line includes a first power supply line configured to supply a first power supply signal to the pixel driving circuit; in at least one circuit unit, the third fracture shielding block is connected with the first power line.

In an exemplary embodiment, the at least one potentiostatic signal line includes a second power line configured to provide a second power signal to the light emitting device; in at least one circuit unit, the third fracture shielding block is connected with the second power line.

In an exemplary embodiment, at least one circuit unit further includes a first power supply line configured to supply a first power supply signal to the pixel driving circuit, the first power supply line simultaneously functioning as the break shielding structure and the constant potential signal line; the orthographic projection of the first fracture on the substrate at least partially overlaps with the orthographic projection of the first power line on the substrate, and the first power line is arranged in a conductive layer on one side of the conductive layer where the first data connection line is located, which is far away from the substrate.

In an exemplary embodiment, the pixel driving circuit includes at least a first transistor having a gate electrode connected to a second scan signal line, a first electrode connected to a first initial signal line, a gate electrode connected to a third scan signal line, and a second transistor having a first electrode connected to a second electrode of the first transistor; in at least one circuit unit, the first initial signal line is disposed between the second scan signal line and the third scan signal line, and the first data link line is disposed between the first initial signal line and the third scan signal line.

On the other hand, the disclosure also provides a display device, which comprises the display substrate.

In yet another aspect, the present disclosure also provides a method of manufacturing a display substrate including a plurality of circuit units, at least one first data link line extending along a first direction, and at least one second data link line extending along a second direction, the first direction intersecting the second direction; at least one circuit unit includes a pixel driving circuit, a data signal line configured to supply a data signal to the pixel driving circuit, and at least one constant potential signal line configured to supply a constant potential signal to the pixel driving circuit, the data signal line being connected to the first data link line, the first data link line being connected to the second data link line; the at least one circuit unit further comprises at least one first fracture and at least one fracture shielding structure, the first fracture is arranged on the first data connecting line and cuts off the first data connecting line, and the fracture shielding structure is connected with the constant potential signal line; the preparation method comprises the following steps:

And forming a plurality of conductive layers on a substrate, wherein the first data connecting line is arranged in one conductive layer, the fracture shielding structure is arranged in any conductive layer or layers except the conductive layer where the first data connecting line is arranged, and the orthographic projection of the first fracture on the substrate at least partially overlaps with the orthographic projection of the fracture shielding structure on the substrate.

The utility model provides a display substrate and preparation method, display device thereof, utilize fracture to shelter from the structure and shelter from first fracture, fracture shelter from the structure and be connected with constant potential signal line, not only can improve the transmissivity, be favorable to eliminating the shadow moreover, avoid display substrate's outward appearance bad.

Other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

Drawings

The accompanying drawings are included to provide an understanding of the technical aspects of the present disclosure, and are incorporated in and constitute a part of this specification, illustrate the technical aspects of the present disclosure and together with the embodiments of the disclosure, not to limit the technical aspects of the present disclosure.

FIG. 1 is a schematic diagram of a display device;

FIG. 2 is a schematic diagram of a display substrate;

FIG. 3A is a schematic plan view of a display area of a display substrate;

FIG. 3B is a schematic plan view of a display area of another display substrate;

FIG. 4 is a schematic cross-sectional view of a display area of a display substrate;

fig. 5 is an equivalent circuit diagram of a pixel driving circuit;

Fig. 6 is a schematic structural diagram of a data connection line according to an exemplary embodiment of the present disclosure;

fig. 7 is a schematic structural view of a display substrate according to an exemplary embodiment of the present disclosure;

FIG. 8 is a schematic diagram of an embodiment of the present disclosure after formation of a masking layer pattern;

fig. 9A and 9B are schematic views of a semiconductor layer after patterning according to an embodiment of the present disclosure;

FIGS. 10A and 10B are schematic diagrams of the first conductive layer pattern formed according to the embodiment of the present disclosure;

FIGS. 11A and 11B are schematic diagrams of a second conductive layer pattern formed according to an embodiment of the present disclosure;

FIG. 12 is a schematic diagram of a fourth insulating layer pattern formed according to an embodiment of the present disclosure;

fig. 13A and 13B are schematic views of a third conductive layer pattern formed according to an embodiment of the present disclosure;

FIG. 14 is a schematic diagram of an embodiment of the present disclosure after forming a first planarizing layer pattern;

fig. 15A and 15B are schematic views of a fourth conductive layer pattern formed according to an embodiment of the present disclosure;

Fig. 16, 17A and 17B are schematic structural views of another display substrate according to an embodiment of the present disclosure;

Fig. 18, 19A and 19B are schematic structural views of a display substrate according to still another embodiment of the disclosure;

fig. 20, 21A and 21B are schematic structural views of a display substrate according to still another embodiment of the disclosure;

fig. 22 and 23 are schematic structural views of a display substrate according to still another embodiment of the present disclosure;

FIG. 24 is a schematic view of a display substrate according to another embodiment of the disclosure;

FIGS. 25 and 26 are schematic views illustrating a structure of a display substrate according to still another embodiment of the present disclosure;

FIG. 27 is a schematic view of a display substrate according to another embodiment of the disclosure;

fig. 28 is a schematic structural diagram of a display substrate according to another embodiment of the disclosure.

Reference numerals illustrate:

11—a first active layer; 12-a second active layer; 13-a third active layer;

14-a fourth active layer; 15-a fifth active layer; 16-a sixth active layer;

17-seventh active layer; 18-node active layer; 21-a first scanning signal line;

22-a second scanning signal line; 23-a third scanning signal line; 25-a fifth gate electrode;

26-a sixth gate electrode; 27-a first light-emitting signal line; 28-a second light-emitting signal line;

31-a first plate; 32-a second plate; 33-opening;

34-plate connecting bars; 35-plate electrode connecting electrode; 41-a first initial signal line;

42-a second initial signal line; 43-a first shielding electrode; 44-a second shielding electrode;

51—a first connection electrode; 52-a second connection electrode; 53-a third connection electrode;

54-fourth connection electrode; 55-a fifth connection electrode; 56-a sixth connection electrode;

57-seventh connection electrode; 61-a first fracture masking block; 62-a second fracture stop;

63-a third fracture stop; 71-a first power line; 72-a second power line;

73—a data signal line; 74-anode connection electrode; 80-a data outgoing line;

81—a first data link; 82-a second data connection line; 83—a data connection block;

90-shielding electrode; 91-a first shielding connection strip; 92-a second shielding connection strip;

93-a third shielding connecting strip; 94-fourth shade connecting bar; 95-a first shielding block;

96—a second shutter block; 100—a display area; 101-a substrate;

102-a driving structure layer; 103-a light emitting structure layer; 104-packaging structure layer;

200—binding area; 201-a lead-out area; 202-a kink zone;

300-border area.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail hereinafter with reference to the accompanying drawings. Note that embodiments may be implemented in a number of different forms. One of ordinary skill in the art can readily appreciate the fact that the manner and content may be varied into a wide variety of forms without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure should not be construed as being limited to the following description of the embodiments. Embodiments of the present disclosure and features of embodiments may be combined with each other arbitrarily without conflict.

The scale of the drawings in this disclosure may be referred to in the actual process, but is not limited thereto. For example: the width-to-length ratio of the channel, the thickness and the spacing of each film layer, and the width and the spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the number shown in the drawings, the drawings described in the present disclosure are only schematic structural drawings, and one mode of the present disclosure is not limited to the shapes or values shown in the drawings, etc.

The ordinal numbers of "first", "second", "third", etc. in the present specification are provided to avoid mixing of constituent elements, and are not intended to be limited in number.

In the present specification, for convenience, words such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, which indicate an azimuth or a positional relationship, are used to describe positional relationships of constituent elements with reference to the drawings, only for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or elements referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus are not to be construed as limiting the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which the respective constituent elements are described. Therefore, the present invention is not limited to the words described in the specification, and may be appropriately replaced according to circumstances.

In this specification, the terms "mounted," "connected," and "connected" are to be construed broadly, unless explicitly stated or limited otherwise. For example, it may be a fixed connection, a removable connection, or an integral connection; may be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intermediate members, or may be in communication with the interior of two elements. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art in the specific context.

In this specification, a transistor means an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and a source electrode (a source electrode terminal, a source region, or a source electrode), and a current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, a channel region refers to a region through which current mainly flows.

In this specification, the first electrode may be a drain electrode, the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using a transistor having opposite polarity, or in the case of a change in the direction of current during circuit operation, the functions of the "source electrode" and the "drain electrode" may be interchanged. Therefore, in this specification, "source electrode" and "drain electrode" may be exchanged, and "source terminal" and "drain terminal" may be exchanged.

In this specification, "electrically connected" includes a case where constituent elements are connected together by an element having some electric action. The "element having a certain electric action" is not particularly limited as long as it can transmit and receive an electric signal between the constituent elements connected. Examples of the "element having some electric action" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.

In the present specification, "parallel" means a state in which two straight lines form an angle of-10 ° or more and 10 ° or less, and therefore, a state in which the angle is-5 ° or more and 5 ° or less is also included. The term "perpendicular" refers to a state in which two straight lines form an angle of 80 ° or more and 100 ° or less, and thus includes an angle of 85 ° or more and 95 ° or less.

In this specification, "film" and "layer" may be exchanged with each other. For example, the "conductive layer" may be sometimes replaced with a "conductive film". In the same manner, the "insulating film" may be replaced with the "insulating layer" in some cases.

The triangle, rectangle, trapezoid, pentagon or hexagon, etc. in this specification are not strictly defined, but may be approximated to triangle, rectangle, trapezoid, pentagon or hexagon, etc., and there may be some small deformation due to tolerance, and there may be lead angles, arc edges, deformation, etc. The term "about" in this disclosure refers to values that are not strictly limited to the limits, but are allowed to fall within the limits of the process and measurement errors.

Fig. 1 is a schematic structural diagram of a display device. As shown in fig. 1, the display device may include a timing controller, a data driver, a scan driver, a light emitting driver, and a pixel array, the timing controller being connected to the data driver, the scan driver, and the light emitting driver, respectively, the data driver being connected to a plurality of data signal lines (D1 to Dn), the scan driver being connected to a plurality of scan signal lines (S1 to Sm), respectively, the light emitting driver being connected to a plurality of light emitting signal lines (E1 to Eo), respectively. The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, and at least one sub-pixel Pxij may include a circuit unit and a light emitting unit, the circuit unit may include at least a pixel driving circuit, the pixel driving circuit is respectively connected with a scan signal line, a light emitting signal line, and a data signal line, the light emitting unit may include a light emitting device, and the light emitting device is connected with the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide gray values and control signals suitable for the specification of the data driver to the data driver, may provide a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the scan driver, may provide a clock signal, an emission stop signal, etc. suitable for the specification of the light emitting driver to the light emitting driver. The DATA driver may generate DATA voltages to be supplied to the DATA signal lines DATA1, D2, D3, … …, and Dn using the gray values and control signals received from the timing controller. For example, the DATA driver may sample the gray value with a clock signal and apply a DATA voltage corresponding to the gray value to the DATA signal lines DATA1 to Dn in pixel row units, and n may be a natural number. The scan driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, … …, and Sm by receiving a clock signal, a scan start signal, and the like from the timing controller. For example, the scan driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm. For example, the scan driver may be configured in the form of a shift register, and may sequentially generate the scan signals in such a manner that the scan start signal supplied in the form of an on-level pulse is transmitted to the next stage circuit under the control of the clock signal, and m may be a natural number. The light emitting driver may generate the emission signals to be supplied to the light emitting signal lines EM1, E2, E3, … …, and Eo by receiving a clock signal, an emission stop signal, and the like from the timing controller. For example, the light emitting driver may sequentially supply the emission signal having the off-level pulse to the light emitting signal lines EM1 to Eo. For example, the light emitting driver may be configured in the form of a shift register, and may generate the emission signal in such a manner that the emission stop signal provided in the form of a cut-off level pulse is sequentially transmitted to the next stage circuit under the control of a clock signal, o may be a natural number. In an exemplary embodiment, the pixel array may be disposed on the display substrate.

Fig. 2 is a schematic structural diagram of a display substrate. As shown in fig. 2, the display substrate may include a display area 100, a bonding area 200 at one side of the display area 100, and a bezel area 300 at the other side of the display area 100. In an exemplary embodiment, the display area 100 may be a flat area including a plurality of subpixels Pxij constituting a pixel array, the plurality of subpixels Pxij being configured to display a moving picture or a still image, and the display area 100 may be referred to as an effective area (ACTIVE AREA, abbreviated as AA). In an exemplary embodiment, the display substrate may employ a flexible substrate, and thus the display substrate may be deformable, such as curled, bent, folded, or rolled.

In an exemplary embodiment, the bonding area 200 may include a lead-out area 201, a bent area 202, a driving chip area, and a bonding pin area sequentially disposed in a direction away from the display area, the lead-out area 201 being connected to the display area 100, including at least a data lead-out. The bending region 202 is connected to the lead out region 201 and may include at least a composite insulating layer provided with grooves configured to bend the binding region to the back surface of the display region. The driver chip region may include an integrated circuit (INTEGRATED CIRCUIT, simply referred to as an IC) configured to connect with a plurality of data pinouts. The Bonding Pad region may include a Bonding Pad (Bonding Pad) configured to be bonded to an external flexible circuit board (Flexible Printed Circuit, abbreviated as FPC).

In an exemplary embodiment, the bezel area 300 may include a circuit area, a power line area, a crack dam area, and a cutting area sequentially disposed in a direction away from the display area 100. The circuit region is connected to the display region 100, and may include at least a gate driving circuit connected to the scan signal line and the light emitting signal line in the display region 100. The power line region is connected to the circuit region and may include at least a frame power lead extending in a direction parallel to an edge of the display region to be connected to a cathode in the display region 100. The crack dam region is connected to the power line region and may include at least a plurality of cracks provided on the composite insulating layer. The cutting region is connected to the crack dam region and may include at least cutting grooves provided on the composite insulating layer, the cutting grooves being configured such that the cutting devices cut along the cutting grooves, respectively, after all the film layers of the display substrate are prepared.

In an exemplary embodiment, the outlet region in the bonding region 200 and the power line region in the bezel region 300 may be provided with a barrier, which may extend in a direction parallel to the display region edge, which is an edge of one side of the display region bonding region or the bezel region, forming a ring-shaped structure surrounding the display region 100.

Fig. 3A is a schematic plan view of a display area in a display substrate. As shown in fig. 3A, the display region may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first subpixel P1, a second subpixel P2, a third subpixel P3, and a fourth subpixel P4. Each sub-pixel may include a circuit unit and a light emitting unit, the circuit unit may include at least a pixel driving circuit, the pixel driving circuit is connected to the scan signal line, the light emitting signal line, and the data signal line, respectively, and the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light emitting unit under control of the scan signal line and the light emitting signal line. The light emitting unit may include a light emitting device connected to the pixel driving circuit of the sub-pixel, the light emitting device being configured to emit light of a corresponding brightness in response to a current output from the pixel driving circuit of the sub-pixel.

In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) emitting red light, the second subpixel P2 and the fourth subpixel P4 may be green subpixels (G) emitting green light, and the third subpixel P3 may be blue subpixels (B) emitting blue light. In an exemplary embodiment, the shape of the sub-pixels may be rectangular, diamond, pentagonal, or hexagonal, and the four sub-pixels may be arranged in an RGBG manner.

Fig. 3B is a schematic plan view of a display area of another display substrate. As shown in fig. 3B, the pixel unit P may include three sub-pixels, the first sub-pixel P1 may be a red sub-pixel emitting red light, the second sub-pixel P2 may be a blue sub-pixel emitting blue light, the third sub-pixel P3 may be a green sub-pixel emitting green light, and the three sub-pixels may be arranged in Real RGB.

In other exemplary embodiments, three or four sub-pixels may be arranged in a horizontal or vertical juxtaposition, etc., and the disclosure is not limited thereto.

Fig. 4 is a schematic cross-sectional structure of a display area in a display substrate, illustrating the structure of four sub-pixels in the display area. As shown in fig. 4, on a plane perpendicular to the display substrate, the display region may include a driving structure layer 102 disposed on the base 101, a light emitting structure layer 103 disposed on a side of the driving structure layer 102 away from the base 101, and a package structure layer 104 disposed on a side of the light emitting structure layer 103 away from the base 101. In some possible implementations, the display area may include other film layers, such as a touch structure layer, etc., which are not limited herein.

In an exemplary embodiment, the substrate 101 may be a flexible substrate, or may be a rigid substrate. The driving structure layer 102 may include a plurality of circuit units, and each circuit unit may include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light emitting structure layer 103 may include a plurality of light emitting units, each of which may include a light emitting device, which may include at least an anode connected to the pixel driving circuit, an organic light emitting layer connected to the anode, and a cathode connected to the organic light emitting layer, and the organic light emitting layer emits light of a corresponding color under the driving of the anode and the cathode. The packaging structure layer 104 may include a first packaging layer, a second packaging layer and a third packaging layer, which are stacked, where the first packaging layer and the third packaging layer may be made of inorganic materials, the second packaging layer may be made of organic materials, and the second packaging layer is disposed between the first packaging layer and the third packaging layer, so as to form an inorganic material/organic material/inorganic material stacked structure, which can ensure that external water vapor cannot enter the light emitting structure layer 103.

Fig. 5 is an equivalent circuit diagram of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in fig. 5, the pixel driving circuit may include 7 transistors (first to seventh transistors T1 to T7) and 1 storage capacitor C, and is connected to 9 signal lines (first, second, third, first, second, and second light emitting signal lines S1, S2, S3, EM1, EM2, first, second, and initial signal lines INIT1, INIT2, DATA signal line DATA, and first power supply line VDD), respectively.

In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the second pole of the first transistor, the first pole of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the storage capacitor C, the second node N2 is connected to the first pole of the third transistor T3, the second pole of the fourth transistor T4, and the second pole of the fifth transistor T5, the third node N3 is connected to the second pole of the second transistor T2, the second pole of the third transistor T3, and the first pole of the sixth transistor T6, respectively, and the fourth node N4 is connected to the second pole of the sixth transistor T6 and the second pole of the seventh transistor T7, respectively.

In an exemplary embodiment, a first terminal of the storage capacitor C is connected to the first node N1, and a second terminal of the storage capacitor C is connected to the first power line VDD.

In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor is connected to the first node N1.

In an exemplary embodiment, the gate electrode of the second transistor T2 is connected to the third scan signal line S3, the first electrode first node N1 of the second transistor T2 is connected, and the second electrode of the second transistor T2 is connected to the third node N3.

In an exemplary embodiment, the gate electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3.

In an exemplary embodiment, the gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the DATA signal line DATA, and the second electrode of the fourth transistor T4 is connected to the second node N2.

In an exemplary embodiment, the gate electrode of the fifth transistor T5 is connected to the first light emitting signal line EM1, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2.

In the exemplary embodiment, the gate electrode of the sixth transistor T6 is connected to the second light emitting signal line EM2, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4.

In the exemplary embodiment, the gate electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the fourth node N4.

In the exemplary embodiment, the first pole of the light emitting device EL is connected to the fourth node N4, and the second pole of the light emitting device EL is connected to the second power line VSS. The light emitting device EL may be an OLED including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked, or a QLED including a first electrode (anode), a quantum dot light emitting layer, and a second electrode (cathode) stacked.

In an exemplary embodiment, the first power line VDD is configured to supply a constant first voltage signal to the pixel driving circuit, the second power line VSS is configured to supply a constant second voltage signal to the light emitting device, and the first voltage signal is a high level signal and the second voltage signal is a low level signal. The first and second initial voltage signals may be constant voltage signals, and the disclosure is not limited herein.

In an exemplary embodiment, the first to seventh transistors T1 to T7 in the pixel driving circuit may be P-type transistors or may be N-type transistors. The same type of transistor is adopted in the pixel driving circuit, so that the process flow can be simplified, the process difficulty of the display panel is reduced, and the yield of products is improved. In some possible implementations, the first to seventh transistors T1 to T7 may include a P-type transistor and an N-type transistor.

In an exemplary embodiment, the first to seventh transistors T1 to T7 may employ low temperature polysilicon thin film transistors, or may employ oxide thin film transistors, or may employ low temperature polysilicon thin film transistors and oxide thin film transistors. The active layer of the low-temperature polysilicon thin film transistor adopts low-temperature polysilicon (Low Temperature Poly-Silicon, LTPS for short), and the active layer of the Oxide thin film transistor adopts an Oxide semiconductor (Oxide). The low-temperature polycrystalline silicon thin film transistor has the advantages of high mobility, quick charging and the like, the Oxide thin film transistor has the advantages of low leakage current and the like, the low-temperature polycrystalline silicon thin film transistor and the Oxide thin film transistor are integrated on one display substrate to form a LTPO (Low Temperature Polycrystalline +oxide) display substrate, the advantages of the low-temperature polycrystalline silicon thin film transistor and the Oxide thin film transistor can be utilized, low-frequency driving can be realized, power consumption can be reduced, and display quality can be improved.

With the development of OLED display technology, consumers have higher requirements on display effects and display quality of display products, and narrow frames become a new trend of development of display products, so that narrowing of frames and even borderless design are increasingly emphasized in OLED display product design. In the display substrate, since the data signal of the integrated circuit in the binding area needs to be introduced into the wider display area through the data outgoing line in a Fanout (Fanout) manner, the outgoing line area occupies a larger space, and the width of the lower frame is larger.

In order to reduce the width of the lower frame, exemplary embodiments of the present disclosure provide a display substrate, which adopts a Fanout line in Panel (FIP) structure, a plurality of data connection lines are disposed in a display area, one ends of the plurality of data connection lines are correspondingly connected with a plurality of data signal lines in the display area, and the other ends of the plurality of data connection lines extend to a binding area and are correspondingly connected with an integrated circuit through a plurality of outgoing lines of an outgoing line area. As the outgoing line area does not need to be provided with fan-shaped oblique lines, the width of the outgoing line area is reduced, and the width of the lower frame is reduced.

Exemplary embodiments of the present disclosure provide a display substrate including a plurality of circuit units, at least one first data link line extending along a first direction, and at least one second data link line extending along a second direction in a direction parallel to the display substrate, the first direction and the second direction crossing; at least one circuit unit includes a pixel driving circuit, a data signal line configured to supply a data signal to the pixel driving circuit, and at least one constant potential signal line configured to supply a constant potential signal to the pixel driving circuit, the data signal line being connected to the first data link line, the first data link line being connected to the second data link line; the at least one circuit unit further comprises at least one first fracture and at least one fracture shielding structure, the first fracture is arranged on the first data connecting line and cuts off the first data connecting line, and the fracture shielding structure is connected with the constant potential signal line; in the direction perpendicular to the display substrate, the display substrate at least comprises a plurality of conductive layers arranged on a base, the first data connecting wire is arranged in one conductive layer, and the fracture shielding structure is arranged in any conductive layer or a plurality of conductive layers except the conductive layer where the first data connecting wire is arranged; the orthographic projection of the first fracture on the substrate at least partially overlaps the orthographic projection of the fracture shielding structure on the substrate.

Fig. 6 is a schematic structural diagram of a data connection line according to an exemplary embodiment of the present disclosure, where the data connection line adopts a FIP structure. As shown in fig. 6, the display substrate may include a display area 100, a bonding area 200 at one side of the display area 100, and a bezel area 300 at the other side of the display area 100 in a plane parallel to the display substrate. The driving structure layer of the display area 100 may include a plurality of circuit units constituting a plurality of cell rows and a plurality of cell columns, a plurality of data signal lines 73, a plurality of first data link lines 81, and a plurality of second data link lines 82, and at least one of the circuit units may include a pixel driving circuit configured to output a corresponding current to the connected light emitting device. The light emitting structure layer of the display area 100 may include a plurality of light emitting cells, and at least one of the light emitting cells may include a light emitting device connected to the pixel driving circuit of the corresponding circuit unit, the light emitting device being configured to emit light of a corresponding brightness in response to a current output from the connected pixel driving circuit.

In an exemplary embodiment, the circuit unit referred to in the present disclosure refers to a region divided by a pixel driving circuit, and the light emitting unit referred to in the present disclosure refers to a region divided by a light emitting device. In an exemplary embodiment, the position of the light emitting unit orthographic projection on the substrate and the position of the circuit unit orthographic projection on the substrate may be corresponding, or the position of the light emitting unit orthographic projection on the substrate and the position of the circuit unit orthographic projection on the substrate may not be corresponding.

In an exemplary embodiment, the plurality of circuit cells sequentially arranged along the first direction X may be referred to as a cell row, the plurality of circuit cells sequentially arranged along the second direction Y may be referred to as a cell column, the plurality of cell rows and the plurality of cell columns constitute a circuit cell array arranged in an array, and the first direction X crosses the second direction Y.

In an exemplary embodiment, the second direction Y (vertical direction) may be an extending direction of the data signal line, and the first direction X (horizontal direction) may be perpendicular to the second direction Y.

In an exemplary embodiment, the first data link line 81 may have a linear or folded shape extending along the first direction X, and the data signal line 73 and the second data link line 82 may have a linear or folded shape extending along the second direction Y. The plurality of data signal lines 73 are sequentially arranged at set intervals in the first direction X, at least one data signal line 73 is connected to a plurality of pixel driving circuits in one cell column, and the data signal line 73 is configured to supply a data signal to the connected pixel driving circuits. The first end of at least one first data link line 81 is connected to one data signal line 73, the second end is connected to one end of one second data link line 82, and the other end of the second data link line 82 extends to the bonding area and then is connected to one data outgoing line 80, so that the data signal line 73 in the display area is connected to the data outgoing line 80 in the bonding area 200 through the first data link line 81 and the second data link line 82, forming a FIP structure (also referred to as FIAA structure). In the exemplary embodiment, the first data link line 81 and the second data link line 82 are collectively referred to as a data link line.

In an exemplary embodiment, the bonding region 200 may include a lead-out region 201, a bent region, a driving chip region, and a bonding pin region sequentially disposed in a direction away from the display region, the lead-out region 201 being connected to the display region 100, and the bent region being connected to the lead-out region 201. The lead out area 201 may be provided with a plurality of data lead out lines 80, the plurality of data lead out lines 80 extending in a direction away from the display area, a first end of a portion of the data lead out lines 80 being correspondingly connected to the second data connection lines 82 in the display area 100, a first end of another portion of the data lead out lines 80 being correspondingly connected to the data signal lines 73 in the display area 100, and second ends of all the data lead out lines 80 extending in the second direction Y and then crossing the bending area to be connected to the integrated circuit of the driving chip area, such that the integrated circuit applies the data signal to the data signal lines through the data lead out lines and the data connection lines. Because the first data connection line 81 and the second data connection line 82 are arranged in the display area, the length of the outgoing line area in the second direction Y can be effectively reduced, the width of the lower frame is greatly reduced, the screen occupation ratio is improved, and the full-screen display is facilitated.

In an exemplary embodiment, the number of the data link lines in the display area may be the same as the number of the data signal lines, each of which is connected to one of the outgoing lines through one of the data link lines. Or the number of the data link lines in the display area may be smaller than the number of the data signal lines, a part of the data signal lines in the display area are correspondingly connected with the outgoing lines through the data link lines, and another part of the data signal lines are directly connected with the outgoing lines, which is not limited herein.

Fig. 7 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of circuit units of one circuit row and 2 circuit columns. As shown in fig. 7, in a plane parallel to the display substrate, the driving structure layer may include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, and at least one of the circuit units may include a pixel driving circuit, and the pixel driving circuit may be connected to the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the first light emitting signal line 27, the second light emitting signal line 28, the first initial signal line 41, the second initial signal line 42, the first power supply line 71, and the data signal line 73, respectively. The first to third scan signal lines 21 to 23 are configured to supply first to third scan signals to the pixel driving circuits, respectively, the first and second light emitting signal lines 27 and 28 are configured to supply first and second light emitting control signals to the pixel driving circuits, respectively, the first and second initial signal lines 41 and 42 are configured to supply first and second initial signals to the pixel driving circuits, respectively, the first power supply line 71 is configured to supply the first power supply signal to the pixel driving circuits, and the data signal line 73 is configured to supply the data signal to the pixel driving circuits. Wherein a plurality of signal lines connected to the pixel driving circuits may be located in the circuit unit.

In an exemplary embodiment, the shapes of the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the first light emitting signal line 27, the second light emitting signal line 28, the first preliminary signal line 41, and the second preliminary signal line 42 may be linear or folded, the body portion of which extends along the first direction X, and the shapes of the first power supply line 71 and the data signal line 73 may be linear or folded, the body portion of which extends along the second direction Y.

In the present disclosure, a extending along the B direction means that a may include a main portion and a sub portion connected to the main portion, the main portion being a line, a line segment, or a bar-shaped body, the main portion extending along the B direction, and the main portion extending along the B direction for a length greater than that of the sub portion extending along other directions. The "a extends in the B direction" referred to in the following description means that the main body portion of a extends in the B direction. In an exemplary embodiment, the first direction X may be a cell row direction and the second direction Y may be a cell column direction.

In an exemplary embodiment, the pixel driving circuit may include at least a storage capacitor and a plurality of transistors. The plurality of transistors may include a first transistor T1 as a first reset transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first light emitting control transistor, a sixth transistor T6 as a second light emitting control transistor, and a seventh transistor T7 as a second reset transistor, and the storage capacitor may include stacked first and second plates.

In the exemplary embodiment, the gate electrode of the first transistor T1 is connected to the second scan signal line 22, the first electrode of the first transistor T1 is connected to the first initial signal line 41, and the second electrode of the first transistor T1 is connected to the first electrode and the first plate (also the gate electrode of the third transistor T3) of the second transistor T2, respectively. The gate electrode of the second transistor T2 is connected to the third scan signal line 23, and the second electrode of the second transistor T2 is connected to the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6, respectively. The gate electrode of the fourth transistor T4 is connected to the first scan signal line 21, the first pole of the fourth transistor T4 is connected to the data signal line 73, and the second pole of the fourth transistor T4 is connected to the first pole of the third transistor T3 and the second pole of the fifth transistor T5, respectively. The gate electrode of the fifth transistor T5 is connected to the first light-emitting signal line 27, and the first electrode of the fifth transistor T5 is connected to the first power supply line 71. The gate electrode of the sixth transistor T6 is connected to the second light-emitting signal line 28, and the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7. The gate electrode of the seventh transistor T7 is connected to the first scan signal line 21, and the first electrode of the seventh transistor T7 is connected to the second initial signal line 42.

In an exemplary embodiment, in at least one circuit unit, the third scan signal line 23 may be disposed at a side of the storage capacitance opposite to the second direction Y, the first initial signal line 41 may be disposed at a side of the third scan signal line 23 remote from the storage capacitance, and the second scan signal line 22 may be disposed at a side of the first initial signal line 41 remote from the storage capacitance, that is, the first initial signal line 41 is disposed between the second scan signal line 22 and the third scan signal line 23. The first light emitting signal line 27 may be disposed at a side of the storage capacitor in the second direction Y, the first scan signal line 21 may be disposed at a side of the first light emitting signal line 27 away from the storage capacitor, the second light emitting signal line 28 may be disposed at a side of the first scan signal line 21 away from the storage capacitor, and the second preliminary signal line 42 may be disposed at a side of the second light emitting signal line 28 away from the storage capacitor, i.e., the second preliminary signal line 42 is disposed at a side of the first scan signal line 21 away from the storage capacitor (the third transistor T3).

In an exemplary embodiment, the at least one circuit unit may further include at least one first data link line 81 and at least one second data link line 82, the first data link line 81 may have a shape of a straight line or a folded line extending along the first direction X, and the second data link line 82 may have a shape of a straight line or a folded line extending along the second direction Y. At least one first data link line 81 is connected to the data signal line 73 and the second data link line 82, respectively, to form a structure in which the data link lines are located in the display area.

In an exemplary embodiment, at least one first data link line 81 may be disposed between the second scan signal line 22 and the first initial signal line 41 in the second direction Y. In the first direction X, at least one second data connection line 82 may be disposed between adjacent cell columns, i.e., between adjacent circuit cells in the first direction X.

In an exemplary embodiment, the at least one circuit unit may further include at least one first break K1, the first break K1 being disposed on the first data link line 81 and cutting off the first data link line 81 into a first connection sub-line and a second connection sub-line, the first connection sub-line being located at one side of the first break K1 in the opposite direction of the first direction X, the second connection sub-line being located at one side of the first break K1 in the first direction X, the first connection sub-line being configured to be connected with one data signal line 73, the second connection sub-line being configured as a first dummy line.

In an exemplary embodiment, the at least one circuit unit may further include a first fracture shielding block 61 as a shielding structure, an orthographic projection of the first fracture K1 on the substrate at least partially overlaps with an orthographic projection of the first fracture shielding block 61 on the substrate, and the first fracture shielding block 61 may shield the first fracture K1 from below to improve transmittance.

In an exemplary embodiment, in at least one circuit unit, the first fracture shielding block 61 may have a block shape (e.g., rectangular shape), may be disposed at a side of the first preliminary signal line 41 near the second scanning signal line 22, and is connected to the first preliminary signal line 41 as a constant potential signal line of the present disclosure.

In an exemplary embodiment, the display substrate may include at least a first conductive layer disposed on the base, a second conductive layer disposed on a side of the first conductive layer away from the base, a third conductive layer disposed on a side of the second conductive layer away from the base, and a fourth conductive layer disposed on a side of the third conductive layer away from the base, in a direction perpendicular to the display substrate, the first data link 81 may be disposed in the third conductive layer, and the first fracture shielding block 61 may be disposed in a conductive layer on a side of the third conductive layer close to the base. For example, the first fracture mask 61 may be disposed in the first conductive layer. As another example, the first fracture stop 61 may be disposed in the second conductive layer. For another example, the first fracture stopper 61 may be provided in the first conductive layer and the second conductive layer.

In an exemplary embodiment, the first preliminary signal line 41 and the first fracture shielding block 61 may be disposed in the second conductive layer in the same layer and be an integral structure connected to each other.

In an exemplary embodiment, the first transistor T1 may include at least a first active layer, and the second transistor may include at least a second active layer, and a second region of the first active layer and a first region of the second active layer are connected to each other. In at least one circuit unit, the orthographic projection of the first fracture shielding block 61 on the substrate and the orthographic projection of the second region of the first active layer on the substrate at least partially overlap, so that the first fracture shielding block 61 and the first node N1 of the pixel driving circuit form a node capacitance.

In an exemplary embodiment, the at least one circuit unit may further include at least one second break K2, the second break K2 being disposed on the second data link line 82 and cutting the second data link line 82 into a third connection sub-line and a fourth connection sub-line, the third connection sub-line being located at a second direction Y side of the second break K2, the fourth connection sub-line being located at an opposite direction side of the second break K2 from the second direction Y, the third connection sub-line being connected with the first connection sub-line in the first data link line 81, the fourth connection sub-line being configured as a second dummy line.

In an exemplary embodiment, the at least one circuit unit may further include a second fracture shielding block 62, an orthographic projection of the second fracture K2 on the substrate at least partially overlaps with an orthographic projection of the second fracture shielding block 62 on the substrate, and the second fracture shielding block 62 may shield the second fracture K2 from below to improve transmittance.

In an exemplary embodiment, the second fracture shielding block 62 may have a block shape (e.g., rectangular) in at least one circuit unit. In the first direction X, the second fracture K2 and the second fracture shielding block 62 may be disposed between adjacent circuit units in the first direction X. In the second direction Y, the second fracture shielding block 62 may be disposed at a side of the second preliminary signal line 42 remote from the second scan signal line 22, and connected to the second preliminary signal line 42.

In an exemplary embodiment, the second data link 82 may be disposed in a fourth conductive layer, and the second fracture mask 62 may be disposed in a conductive layer of the fourth conductive layer on a side near the substrate. For example, the second fracture mask 62 may be disposed in the first conductive layer. As another example, a second fracture mask 62 may be disposed in the second conductive layer. For another example, the second fracture stop 62 may be disposed in the third conductive layer.

In an exemplary embodiment, the second initial signal line 42 and the second fracture stop 62 may be co-layer disposed in the second conductive layer and be an integral structure connected to each other.

In an exemplary embodiment, the at least one circuit unit may further include a second power line 72, and the second power line 72 may have a shape of a straight line or a folded line extending along the second direction Y and may be disposed between the first power line 71 and the data signal line 73.

In an exemplary embodiment, in one cell row, the pixel driving circuits in adjacent two circuit cells may be symmetrically disposed with respect to a column center line, which may be a straight line located between adjacent two circuit cells in the first direction X and extending along the second direction Y. For example, the pixel driving circuits of the nth cell column and the n+1th cell column may be symmetrically disposed with respect to the column center line. In an exemplary embodiment, the pixel driving circuits in adjacent cell rows may be substantially the same.

The following is an exemplary description of a preparation process of the display substrate by the present exemplary embodiment. The "patterning process" referred to in this disclosure includes processes for depositing a film layer, coating a photoresist on the film layer, mask exposing, developing, etching, stripping the photoresist, etc., and processes for coating an organic material, mask exposing, developing, etc., for an organic material. The deposition may be any one or more of sputtering, evaporation and chemical vapor deposition, the coating may be any one or more of spraying, spin coating and ink jet printing, and the etching may be any one or more of dry etching and wet etching, which is not limited in this disclosure. "film" refers to a layer of film formed by depositing, coating, or other process a material on a substrate. The "film" may also be referred to as a "layer" if the "film" does not require a patterning process throughout the fabrication process. If the "thin film" requires a patterning process throughout the fabrication process, it is referred to as a "thin film" prior to the patterning process, and as a "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern". The term "a and B are arranged in the same layer" in the present disclosure means that a and B are formed simultaneously by the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of a" or "the orthographic projection of a includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of a or the boundary of the orthographic projection of a overlaps with the boundary of the orthographic projection of B.

In an exemplary embodiment, taking 2 circuit units of one unit row and 2 unit columns as an example, the preparation process of the display substrate of this example may include the following operations.

(11) Forming a shielding layer pattern. In an exemplary embodiment, forming the shielding layer pattern may include: a shadow film is deposited on a substrate, patterned by a patterning process, and a shadow layer pattern is formed on the substrate, as shown in fig. 8. In an exemplary embodiment, the shielding layer may be referred to as an underlying metal (LS) layer.

In an exemplary embodiment, the shielding layer pattern of each circuit unit may include at least a shielding electrode 90, a first shielding connection bar 91, a second shielding connection bar 92, a third shielding connection bar 93, a fourth shielding connection bar 94, a first shielding stopper 95, and a second shielding stopper 96.

In an exemplary embodiment, the shielding electrode 90 may have a rectangular shape, corners of the rectangular shape may be provided with chamfers or grooves, the shielding electrode 90 may be disposed at a middle region of the circuit unit in the first direction X and the second direction Y, and the shielding electrode 90 is configured to shield a channel region of the third transistor T3.

In an exemplary embodiment, the first shielding connection bar 91 may have a bar shape, the first shielding connection bar 91 may be disposed between partially adjacent shielding electrodes 90, a first end of the first shielding connection bar 91 is connected with the shielding electrode 90 in one side circuit unit, and a second end of the first shielding connection bar 91 is connected with the shielding electrode 90 in the other side circuit unit. For example, the first shielding connection bar 91 may be disposed between the shielding electrode 90 in the nth cell column and the shielding electrode 90 in the n+1th cell column.

In an exemplary embodiment, the second shielding connection bar 92 may have a bar shape, the second shielding connection bar 92 may be disposed between the partially adjacent shielding electrodes 90, a first end of the second shielding connection bar 92 is connected to the shielding electrode 90 in the one side circuit unit, and a second end of the second shielding connection bar 92 is connected to the shielding electrode 90 in the other side circuit unit. For example, the second shielding connection bar 92 may be disposed between the shielding electrode 90 in the N-1 th cell column and the shielding electrode 90 in the N-th cell column. As another example, the second shielding connection bar 92 may be disposed between the shielding electrode 90 in the n+1 cell column and the shielding electrode 90 in the n+2 cell column.

In an exemplary embodiment, the extending directions of the first and second shielding connection bars 91 and 92 may be along the first direction X, or may have a set angle with the first direction X, which is not limited herein.

In an exemplary embodiment, the shielding electrode 90, the first shielding connection bar 91, and the second shielding connection bar 92 may be an integral structure connected to each other in at least one cell row.

In an exemplary embodiment, the third shielding connection bar 93 and the fourth shielding connection bar 94 may have a shape of a straight line or a folded line in which a main body portion extends along the second direction Y, the third shielding connection bar 93 may be disposed at one side of the shielding electrode 90 opposite to the second direction Y, the fourth shielding connection bar 94 may be disposed at one side of the shielding electrode 90 opposite to the second direction Y, the first end of the third shielding connection bar 93 in the present cell row is connected to the shielding electrode 90 in the present cell row, the second end of the third shielding connection bar 93 is connected to the second end of the fourth shielding connection bar 94 in the previous cell row, the first end of the fourth shielding connection bar 94 in the present cell row is connected to the shielding electrode 90 in the present cell row, and the second end of the fourth shielding connection bar 94 is connected to the second end of the third shielding connection bar 93 in the next cell row.

In an exemplary embodiment, the extending directions of the third and fourth shielding connection bars 93 and 94 may be along the second direction Y, or may have a set angle with the second direction Y, which is not limited herein.

In an exemplary embodiment, the first blocking piece 95 may have a block shape (e.g., rectangular) and the second blocking piece 96 may have an "L" shape. In the first direction X, the first shielding block 95 may be disposed at a side of the third shielding connection bar 93 opposite to the first direction X, and the second shielding block 96 may be disposed at a side of the third shielding connection bar 93 opposite to the first direction X. In the second direction Y, the second shielding block 96 may be disposed at a side of the shielding electrode 90 opposite to the second direction Y, the first shielding block 95 may be disposed at a side of the second shielding block 96 away from the shielding electrode 90, the first shielding block 95 may be configured to shield the channel region of the first transistor T1, and the second shielding block 96 may be configured to shield the channel region of the second transistor T2.

In an exemplary embodiment, a first end of the first shielding block 95 may be connected with the third shielding connection bar 93, and a second end of the first shielding block 95 may extend in the opposite direction of the first direction X. The first end of the second shielding block 96, which is close to the shielding electrode 90, may be connected to the shielding electrode 90 and the first shielding connection bar 91, the second end of the second shielding block 96, which is close to the third shielding connection bar 93, may be connected to the third shielding connection bar 93, and the third end of the second shielding block 96, which is far from the third shielding connection bar 93, may be connected to the second shielding block 96 of the adjacent circuit unit in the first direction X.

In an exemplary embodiment, the shielding electrode 90, the third shielding connection bar 93, the fourth shielding connection bar 94, the first shielding stopper 95, and the second shielding stopper 96 may be an integral structure connected to each other in at least one cell column.

In an exemplary embodiment, the shielding layers in the plurality of unit rows and the plurality of unit columns may be of an integrated structure connected with each other, so that the shielding layers in the display substrate can be ensured to have the same electric potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

In an exemplary embodiment, the positions and shapes of the shielding layers in two adjacent circuit cells may be symmetrically arranged with respect to the column center line in one cell row. For example, the positions and shapes of the shielding layers in the nth cell column and the n+1th cell column may be symmetrically arranged with respect to the column center line. In an exemplary embodiment, the positions and shapes of the shielding layers in the plurality of circuit cells in one cell column may be substantially the same.

(12) A semiconductor layer pattern is formed. In an exemplary embodiment, forming the semiconductor layer pattern may include: a first insulating film and a semiconductor film are sequentially deposited on the substrate on which the foregoing patterns are formed, the semiconductor film is patterned by a patterning process to form a first insulating layer covering the shielding layer, and a semiconductor layer pattern is disposed on the first insulating layer, as shown in fig. 9A and 9B, and fig. 9B is a schematic plan view of the semiconductor layer in fig. 9A.

In an exemplary embodiment, the semiconductor layer pattern of each circuit unit may include at least the first to seventh active layers 11 to 17 of the first to seventh transistors T1 to T7, and the first to seventh active layers 11 to 17 may be integrally connected to each other.

In an exemplary embodiment, in the second direction Y, the first active layer 11 and the second active layer 12 may be located at one side of the third active layer 13 opposite to the second direction Y, and the fourth active layer 14, the fifth active layer 15, the sixth active layer 16, the seventh active layer 17, and the seventh active layer 17 may be located at one side of the third active layer 13 in the second direction Y.

In an exemplary embodiment, the third active layer 13 may have an arch shape, the first active layer 11 may have an "n" shape, the second and fifth active layers 12 and 15 may have an "L" shape, and the fourth, sixth and seventh active layers 14, 16 and 17 may have an "I" shape.

In some possible embodiments, the shape of the third active layer 13 may be a stripe shape extending along the first direction X.

In an exemplary embodiment, the first to seventh active layers 11 to 17 may each include a first region, a second region, and a channel region between the first region and the second region. In an exemplary embodiment, the second region 11-2 of the first active layer and the first region 12-1 of the second active layer may be connected to each other, and the second region 11-2 of the first active layer may serve as the first region 12-1 of the second active layer. The first region 13-1 of the third active layer, the second region 14-2 of the fourth active layer, and the second region 15-2 of the fifth active layer may be connected to each other, and the first region 13-1 of the third active layer may serve as both the second region 14-2 of the fourth active layer and the second region 15-2 of the fifth active layer. The second region 12-2 of the second active layer, the second region 13-2 of the third active layer, and the first region 16-1 of the sixth active layer may be connected to each other, and the second region 12-2 of the second active layer may serve as both the second region 13-2 of the third active layer and the first region 16-1 of the sixth active layer. The second region 16-2 of the sixth active layer and the second region 17-2 of the seventh active layer may be connected to each other, and the second region 16-2 of the sixth active layer may serve as the second region 17-2 of the seventh active layer. The first region 11-1 of the first active layer, the first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, and the first region 17-1 of the seventh active layer may be separately provided.

In an exemplary embodiment, the semiconductor layer pattern of each circuit unit may further include a node active layer 18. The node active layer 18 may have a block shape (e.g., rectangular shape), may be disposed between the first region 12-1 of the second active layer and the second region 12-2 of the second active layer, and is connected to the second active layer 12.

In an exemplary embodiment, the node active layers 18 in part of adjacent circuit cells may be connected to each other to form an interconnected unitary structure. For example, the node active layer 18 in the nth cell column and the node active layer 18 in the n+1th cell column may be a unitary structure connected to each other.

In the exemplary embodiment, since the first to seventh active layers 11 to 17 in each circuit unit are integrally connected to each other, the second active layer 12 is connected to the node active layer 18, and the node active layers 18 in adjacent circuit units are connected to each other, the semiconductor layers in part of the adjacent circuit units may be integrally connected to each other. For example, the semiconductor layer in the nth cell column and the semiconductor layer in the n+1th cell column may be an integral structure connected to each other.

In an exemplary embodiment, the orthographic projection of the third active layer 13 on the substrate at least partially overlaps with the orthographic projection of the shielding electrode 90 on the substrate, and the shielding electrode 90 may serve as a shielding layer of the third transistor T3, shielding a channel region of the third transistor T3, and ensuring electrical performance of the third transistor T3.

In an exemplary embodiment, the orthographic projection of the channel region of the third active layer 13 on the substrate is within the range of the orthographic projection of the shielding electrode 90 on the substrate.

In an exemplary embodiment, the orthographic projection of the first active layer 11 on the substrate at least partially overlaps with the orthographic projection of the first shielding block 95 on the substrate, and the first shielding block 95 may serve as a shielding layer of the first transistor T1, shielding a channel region of the first transistor T1, and ensuring electrical performance of the first transistor T1.

In an exemplary embodiment, the orthographic projection of the channel region of the first active layer 11 on the substrate is within the range of the orthographic projection of the first barrier block 95 on the substrate.

In an exemplary embodiment, the orthographic projection of the second active layer 12 on the substrate at least partially overlaps with the orthographic projection of the second shielding block 96 on the substrate, and the second shielding block 96 may serve as a shielding layer of the second transistor T2 to shield the channel region of the second transistor T2, so as to ensure the electrical performance of the second transistor T2.

In an exemplary embodiment, the orthographic projection of the channel region of the second active layer 12 on the substrate is within the orthographic projection of the second barrier block 96 on the substrate.

In an exemplary embodiment, the positions and shapes of the semiconductor layers in the adjacent two circuit cells may be symmetrically arranged with respect to the column center line in one cell row. For example, the positions and shapes of the semiconductor layers in the nth cell column and the n+1th cell column may be symmetrically arranged with respect to the column center line. In an exemplary embodiment, the positions and shapes of the shielding layers in the plurality of circuit cells in one cell column may be substantially the same.

In an exemplary embodiment, the semiconductor layer may employ polysilicon (p-Si), i.e., the third to seventh transistors are LTPS transistors. In an exemplary embodiment, patterning the semiconductor thin film through the patterning process may include: an amorphous silicon (a-si) film is formed on a first insulating film, the amorphous silicon film is dehydrogenated, and the dehydrogenated amorphous silicon film is crystallized to form a polysilicon film. Then, the polysilicon film is patterned to form a semiconductor layer pattern.

(13) A first conductive layer pattern is formed. In an exemplary embodiment, forming the first conductive layer pattern may include: a second insulating film and a first conductive film are sequentially deposited on the substrate on which the foregoing patterns are formed, the first conductive film is patterned by a patterning process to form a second insulating layer covering the semiconductor layer, and the first conductive layer is patterned on the second insulating layer, as shown in fig. 10A and 10B, fig. 10B is a schematic plan view of the first conductive layer in fig. 10A. In an exemplary embodiment, the first conductive layer may be referred to as a first GATE metal (GATE 1) layer.

In an exemplary embodiment, the first conductive layer pattern of each circuit unit in the display substrate may include at least a first scan signal line 21, a second scan signal line 22, a third scan signal line 23, a fifth gate electrode 25, a sixth gate electrode 26, and a first plate 31 of a storage capacitor.

In an exemplary embodiment, the first plate 31 of the storage capacitor may have a rectangular shape, corners of the rectangular shape may be provided with chamfers or grooves, an orthographic projection of the first plate 31 on the substrate at least partially overlaps an orthographic projection of the third active layer on the substrate, and the first plate 31 may serve as both a lower plate of the storage capacitor and a gate electrode of the third transistor T3.

In an exemplary embodiment, the orthographic projection of the area where the first electrode plate 31 and the third active layer overlap on the substrate may be within the range of orthographic projection of the shielding electrode 90 on the substrate, and the shielding electrode 90 may shield the channel area of the third transistor T3, so as to ensure the electrical performance of the third transistor T3.

In an exemplary embodiment, the first scan signal line 21 may have a shape of a straight line or a folded line extending along the first direction X, may be disposed at one side of the first plate 31 in the second direction Y, a region where the first scan signal line 21 overlaps with the fourth active layer may be used as the gate electrode of the fourth transistor T4, and a region where the first scan signal line 21 overlaps with the seventh active layer may be used as the gate electrode of the seventh transistor T7.

In an exemplary embodiment, the second scan signal line 22 may have a shape of a straight line or a folded line extending along the first direction X, may be disposed at one side of the first plate 31 in the opposite direction of the second direction Y, and a region where the second scan signal line 22 overlaps the first active layer may serve as a gate electrode of the first transistor T1 of the dual gate structure.

In an exemplary embodiment, the orthographic projection of the area where the second scanning signal line 22 and the first active layer overlap on the substrate may be within the range of the orthographic projection of the first shielding block 95 on the substrate, and the first shielding block 95 may shield the channel area of the first transistor T1, so as to ensure the electrical performance of the first transistor T1.

In an exemplary embodiment, the third scan signal line 23 may have a shape of a straight line or a folded line extending along the first direction X, and may be disposed between the first plate 31 and the second scan signal line 22. The third scan signal line 23 may be provided with a gate block 23-1, and the gate block 23-1 may have a bar shape extending along the second direction Y, a first end of the gate block 23-1 being connected to a side of the third scan signal line 23 adjacent to the second scan signal line 22, and a second end of the gate block 23-1 extending toward the direction adjacent to the second scan signal line 22. The third scan signal line 23 and the region where the gate block 23-1 overlaps the second active layer may serve as a gate electrode of the second transistor T2 of the dual gate structure.

In an exemplary embodiment, the orthographic projection of the third scan signal line 23 and the gate block 23-1 with the second active layer overlapping region on the substrate may be located within the orthographic projection range of the second shielding block 96 on the substrate, and the second shielding block 96 may shield the channel region of the second transistor T2, ensuring the electrical performance of the second transistor T2.

In an exemplary embodiment, the first, second, and third scan signal lines 21, 22, and 23 may be straight lines of non-uniform width, and the widths of the first, second, and third scan signal lines 21, 22, and 23 at the positions where they intersect the semiconductor layer may be greater than those of other positions.

In an exemplary embodiment, the fifth gate electrode 25 may have a bar shape extending along the first direction X, and may be disposed between the first plate 31 and the first scan signal line 21. The region where the fifth gate electrode 25 overlaps with the fifth active layer may serve as a gate electrode of the fifth transistor T5.

In an exemplary embodiment, a fifth gate connection block 25-1 may be disposed on the fifth gate electrode 25. The fifth gate connection block 25-1 may have a block shape (e.g., rectangular shape), may be disposed at a side of the fifth gate electrode 25 adjacent to the sixth gate electrode 26, and is connected to the fifth gate electrode 25, and the fifth gate connection block 25-1 is configured to be connected to a first light emitting signal line formed later.

In an exemplary embodiment, the sixth gate electrode 26 may have a bar shape extending along the first direction X, and may be disposed between the first plate 31 and the first scan signal line 21. The region where the sixth gate electrode 26 overlaps with the sixth active layer may serve as a gate electrode of the sixth transistor T6.

In an exemplary embodiment, a sixth gate connection block 26-1 may be disposed on the sixth gate electrode 26. The sixth gate connection block 26-1 may have a block shape (e.g., rectangular shape), may be disposed at a side of the sixth gate electrode 26 remote from the fifth gate electrode 25, and is connected to the sixth gate electrode 26, and the sixth gate connection block 26-1 is configured to be connected to a second light emitting signal line formed later.

In an exemplary embodiment, the sixth gate connection blocks 26-1 in part of adjacent circuit cells may be connected to each other to form an integral structure connected to each other such that the sixth gate electrodes 26 of two circuit cells share the same sixth gate connection block 26-1. For example, the sixth gate electrode 26 and the sixth gate connection block 26-1 in the nth cell column and the n+1th cell column may be an integral structure connected to each other.

According to the display device, the sixth gate electrodes 26 of the adjacent circuit units are of the integrated structure connected with each other, so that the sixth transistors T6 of the two adjacent pixel driving circuits share the same sixth gate connecting block, the occupied space of the pixel driving circuits can be effectively reduced, and the display resolution can be improved.

In an exemplary embodiment, the positions and shapes of the first conductive layers in the adjacent two circuit cells may be symmetrically disposed with respect to the column center line in one cell row. For example, the positions and shapes of the first conductive layers of the nth cell column and the n+1th cell column may be symmetrically disposed with respect to the column center line. In an exemplary embodiment, the positions and shapes of the first conductive layers in the plurality of circuit cells in one cell column may be substantially the same.

(14) And forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: a third insulating film and a second conductive film are sequentially deposited on the substrate on which the foregoing patterns are formed, the second conductive film is patterned by a patterning process to form a third insulating layer covering the first conductive layer pattern, and the second conductive layer pattern is disposed on the third insulating layer, as shown in fig. 11A and 11B, and fig. 11B is a schematic plan view of the second conductive layer in fig. 11A. In an exemplary embodiment, the second conductive layer may be referred to as a second GATE metal (GATE 2) layer.

In an exemplary embodiment, the second conductive layer pattern of each circuit unit in the display substrate includes at least: a second plate 32 of the storage capacitor, a first initial signal line 41, a second initial signal line 42, a first shielding electrode 43, and a second shielding electrode 44.

In an exemplary embodiment, the second plate 32 of the storage capacitor may have a rectangular shape, corners of the rectangular shape may be provided with chamfers or grooves, a front projection of the second plate 32 on the substrate at least partially overlaps a front projection of the first plate 31 on the substrate, the second plate 32 may serve as an upper plate of the storage capacitor, and the first plate 31 and the second plate 32 constitute the storage capacitor.

In an exemplary embodiment, the second plate 32 is provided with an opening 33, and the opening 33 may have a rectangular shape and may be located in a middle region of the second plate 32 such that the second plate 32 forms a ring shape. The opening 33 exposes the third insulating layer covering the first plate 31, and the orthographic projection of the first plate 31 on the substrate includes the orthographic projection of the opening 33 on the substrate. In an exemplary embodiment, the opening 33 is configured to receive a subsequently formed ninth via, which is located within the opening 33 and exposes the first plate 31, so that a subsequently formed first connection electrode is connected to the first plate 31.

In an exemplary embodiment, the second pole plate 32 may be provided with a pole connection strip 34. The shape of the plate connecting bar 34 may be a straight line or a folded line extending along the first direction X, the plate connecting bar 34 may be disposed at one side of the second plate 32 in the first direction X or at one side opposite to the first direction X, the first end of the plate connecting bar 34 is connected to the second plate 32 in the present circuit unit, and the second end of the plate connecting bar 34 is connected to the second plate 32 in the adjacent circuit unit in the first direction X.

In an exemplary embodiment, the second electrode plates 32 and the electrode plate connecting bars 34 in the adjacent two circuit units in one unit row may be an integral structure connected to each other. For example, the second electrode plate 32 of the nth cell column and the second electrode plate 32 of the n+1th cell column are connected to each other by the plate connecting bar 34 to form an integrally connected structure. The second plates 32 in each circuit unit are connected with the first power lines formed subsequently, and the second plates 32 of the adjacent circuit units form an integrated structure which is connected with each other, so that the second plates of the integrated structure can be multiplexed into the power signal lines, a plurality of second plates in one unit row can be ensured to have the same electric potential, the uniformity of the panel is improved, poor display of the display substrate is avoided, and the display effect of the display substrate is ensured.

In an exemplary embodiment, the second electrode plate 32 may be provided with a plate connection electrode 35. The plate connecting electrode 35 may have a bar shape extending along the second direction Y, and may be disposed at a side of the second plate 32 near the first scanning signal line 21. A first end of the plate connection electrode 35 is connected to a side of the second plate 32 adjacent to the first scan signal line 21, and a second end of the plate connection electrode 35 extends toward a direction adjacent to the first scan signal line 21, and the plate connection electrode 35 is configured to be connected to the first region of the fifth active layer through a third connection electrode formed later.

In an exemplary embodiment, the first preliminary signal line 41 may have a shape of a straight line or a folded line extending along the first direction X, and may be disposed between the second scan signal line 22 and the third scan signal line 23. The first initial signal line 41 may be provided with a first initial connection block 41-1, the first initial connection block 41-1 may have a bar shape extending along the second direction Y, a first end of the first initial connection block 41-1 is connected to a side of the first initial signal line 41 adjacent to the third scan signal line 23, a second end of the first initial connection block 41-1 extends toward a direction adjacent to the third scan signal line 23, and the first initial connection block 41-1 is configured to be connected to the first region of the first active layer through a sixth connection electrode formed later.

In an exemplary embodiment, the second preliminary signal line 42 may have a shape of a straight line or a folded line extending along the first direction X, and may be disposed at a side of the first scan signal line 21 remote from the second electrode plate 32. The second initial signal line 42 may be provided with a second initial connection block 42-1, the second initial connection block 42-1 may have a block shape (e.g., rectangular shape), a first end of the second initial connection block 42-1 is connected to a side of the second initial signal line 42 adjacent to the first scan signal line 21, a second end of the second initial connection block 42-1 extends toward a direction adjacent to the first scan signal line 21, and the second initial connection block 42-1 is configured to be connected to the first region of the seventh active layer through a seventh connection electrode formed later.

In an exemplary embodiment, the first shielding electrode 43 may have a block shape (e.g., rectangular shape) and may be disposed at a side of the first preliminary signal line 41 near the third scanning signal line 23. A first end of the first shielding electrode 43 is connected to a side of the first initial signal line 41 near the third scanning signal line 23, a second end of the first shielding electrode 43 extends toward a direction near the third scanning signal line 23, and an orthographic projection of the first shielding electrode 43 on the substrate and an orthographic projection of the second active layer and the node active layer 18 between two gate electrodes in the second transistor T2 at least partially overlap. In an exemplary embodiment, the first shielding electrode 43 is configured to shield a node between two gate electrodes in the second transistor T2, avoid an influence of a data voltage jump on the second transistor T2, reduce the influence of the data voltage jump on a normal operation of the pixel driving circuit, and improve a display effect.

In an exemplary embodiment, the first preliminary signal line 41, the first preliminary connection block 41-1, and the first shielding electrode 43 may be integrally formed with each other.

In an exemplary embodiment, the first shielding electrodes 43 in part of the adjacent circuit units may be connected to each other to form an integrally connected structure. For example, the first shielding electrode 43 in the nth cell column and the first shielding electrode 43 in the n+1th cell column may be integrally connected to each other.

In an exemplary embodiment, the second shielding electrode 44 may have a block shape (e.g., rectangular shape) and may be disposed at a side of the second preliminary signal line 42 near the first scanning signal line 21. A first end of the second shielding electrode 44 is connected to a side of the second initial signal line 42 close to the first scanning signal line 21, and a second end of the second shielding electrode 44 extends toward a direction close to the first scanning signal line 21, and an orthographic projection of the second shielding electrode 44 on the substrate at least partially overlaps an orthographic projection of the first active layer between two gate electrodes in the first transistor T1 on the substrate. In an exemplary embodiment, the second shielding electrode 44 is configured to shield a node between two gate electrodes in the first transistor T1, avoid an influence of a data voltage jump on the first transistor T1, reduce the influence of the data voltage jump on a normal operation of the pixel driving circuit, and improve a display effect.

In an exemplary embodiment, the second preliminary signal line 42, the second preliminary connection block 42-1, and the second shielding electrode 44 may be integrally formed with each other.

In an exemplary embodiment, the second conductive layer of the at least one circuit unit may further include a first fracture mask 61. The first fracture stopper 61 may have a block shape (e.g., rectangular shape) and may be disposed at a side of the first preliminary signal line 41 near the second scanning signal line 22. The first end of the first fracture shielding block 61 is connected to a side of the first initial signal line 41 near the second scanning signal line 22, the second end of the first fracture shielding block 61 extends toward a direction near the second scanning signal line 22, and the first fracture shielding block 61 is configured to shield a first fracture on a first data connection line formed subsequently from below.

In an exemplary embodiment, the first fracture stopper 61 may be disposed in the circuit unit of the n+1 cell column.

In an exemplary embodiment, the orthographic projection of the first fracture mask 61 onto the substrate at least partially overlaps with the orthographic projection of the second region of the first active layer (also the first region of the second active layer) onto the substrate. Since the second region of the first active layer (also the first region of the second active layer) is connected to the first connection electrode formed later, the first connection electrode serves as the first node N1 of the pixel driving circuit, so that the first break barrier 61 forms a node capacitance with the first node N1, the node capacitance being configured to stabilize the potential of the first node N1.

In an exemplary embodiment, the second conductive layer of the at least one circuit unit may further include a second fracture mask 62. The second fracture shielding block 62 may have a block shape (e.g., rectangular shape) and may be disposed on a side of the second initial signal line 42 away from the second scan signal line 22. The first end of the second fracture shielding block 62 is connected to a side of the second initial signal line 42 away from the second scan signal line 22, and the second end of the second fracture shielding block 62 extends in a direction away from the second scan signal line 22, and the second fracture shielding block 62 is configured to shield a second fracture on a second data connection line formed subsequently from below.

In an exemplary embodiment, the first and second fracture masking blocks 61 and 62 may be provided in the same circuit unit or in two circuit units, respectively, and the disclosure is not limited herein. For example, the first break stop 61 may be disposed in the circuit cells of the M-th cell row, the second break stop 62 may be disposed in the circuit cells of the M-1 th cell row, and M may be a positive integer greater than or equal to 2.

In an exemplary embodiment, the position and shape of the second conductive layer (except for the first and second fracture masking blocks) in two adjacent circuit cells in one cell row may be symmetrically disposed with respect to the column center line. For example, the second conductive layers of the nth cell column and the n+1th cell column may be positioned and shaped to be symmetrical with respect to the column center line. In an exemplary embodiment, the positions and shapes of the second conductive layers in the plurality of circuit cells in one cell column may be substantially the same.

(15) And forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: and depositing a fourth insulating film on the substrate with the patterns, and patterning the fourth insulating film by a patterning process to form a fourth insulating layer covering the second conductive layer, wherein a plurality of through holes are formed on the fourth insulating layer, as shown in fig. 12.

In an exemplary embodiment, the plurality of vias of each circuit unit in the display substrate includes at least: the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, and thirteenth vias V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, and V13.

In an exemplary embodiment, the orthographic projection of the first via V1 on the substrate is within the range of the orthographic projection of the first region of the first active layer on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer within the first via V1 are etched away, exposing the surface of the first region of the first active layer, and the first via V1 is configured such that the subsequently formed sixth connection electrode is connected to the first region of the first active layer through the via.

In an exemplary embodiment, the orthographic projection of the second via V2 on the substrate is located within the range of the orthographic projection of the second region of the first active layer (also the first region of the second active layer) on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer within the second via V2 are etched away, exposing the surface of the second region of the first active layer (also the first region of the second active layer), and the second via V2 is configured such that the subsequently formed first connection electrode is connected to the second region of the first active layer (also the first region of the second active layer) through the via.

In an exemplary embodiment, the orthographic projection of the third via V3 on the substrate is within the orthographic projection of the first region of the fourth active layer on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer within the third via V3 are etched away to expose the surface of the first region of the fourth active layer, and the third via V3 is configured such that the subsequently formed second connection electrode is connected with the first region of the fourth active layer through the via.

In an exemplary embodiment, the orthographic projection of the fourth via V4 on the substrate is within the range of the orthographic projection of the first region of the fifth active layer on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer within the fourth via V4 are etched away to expose the surface of the first region of the fifth active layer, and the fourth via V4 is configured such that the third connection electrode formed later is connected to the first region of the fifth active layer through the via.

In an exemplary embodiment, the orthographic projection of the fifth via V5 on the substrate is within the orthographic projection of the second region of the sixth active layer (also the second region of the seventh active layer) on the substrate, the second insulating layer, the third insulating layer, and the fourth insulating layer within the fifth via V5 are etched away, exposing the surface of the second region of the sixth active layer (also the second region of the seventh active layer), and the fifth via V5 is configured such that the fourth connection electrode formed later is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the via.

In an exemplary embodiment, the orthographic projection of the sixth via V6 on the substrate is within the orthographic projection of the first region of the seventh active layer on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer within the sixth via V6 are etched away to expose the surface of the first region of the seventh active layer, and the sixth via V6 is configured such that the subsequently formed seventh connection electrode is connected to the first region of the seventh active layer through the via.

In an exemplary embodiment, the orthographic projection of the seventh via V7 on the substrate is within the range of the orthographic projection of the fifth gate connection block 25-1 of the fifth gate electrode 25 on the substrate, the third insulating layer and the fourth insulating layer within the seventh via V7 are etched away to expose the surface of the fifth gate connection block 25-1, and the seventh via V7 is configured such that the first light emitting signal line formed later is connected to the fifth gate connection block 25-1 through the via.

In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is within the range of the orthographic projection of the sixth gate connection block 26-1 of the sixth gate electrode 26 on the substrate, the third insulating layer and the fourth insulating layer within the eighth via V8 are etched away to expose the surface of the sixth gate connection block 26-1, and the eighth via V8 is configured such that the subsequently formed second light emitting signal line is connected to the sixth gate connection block 26-1 through the via. In an exemplary embodiment, the eighth via V8 may be referred to as a gate connection via.

In the exemplary embodiment, since the sixth gate electrodes 26 in part of the adjacent circuit units are of an integral structure connected to each other, the sixth gate electrodes 26 of the two circuit units share the same sixth gate connection block 26-1, so that the two circuit units can share the same gate connection via hole, the number of via holes is effectively reduced, the occupied space of the pixel driving circuit can be effectively reduced, and the resolution is improved.

In an exemplary embodiment, the orthographic projection of the ninth via V9 on the substrate is within the range of the orthographic projection of the opening 33 on the substrate, the third insulating layer and the fourth insulating layer within the ninth via V9 are etched away to expose the surface of the first plate 31, and the ninth via V9 is configured to connect the subsequently formed first connection electrode with the first plate 31 therethrough.

In an exemplary embodiment, the orthographic projection of the tenth via V10 on the substrate is within the range of the orthographic projection of the second electrode plate 32 on the substrate, the fourth insulating layer within the tenth via V10 is etched away to expose the surface of the second electrode plate 32, and the tenth via V10 is configured to connect a fifth connection electrode formed later to the second electrode plate 32 therethrough.

In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is within the range of the orthographic projection of the first initial connection block 41-1 of the first initial signal line 41 on the substrate, the fourth insulating layer within the eleventh via hole V11 is etched away to expose the surface of the first initial connection block 41-1, and the eleventh via hole V11 is configured to connect a sixth connection electrode formed later to the first initial connection block 41-1 therethrough.

In an exemplary embodiment, the orthographic projection of the twelfth via V12 on the substrate is within the range of the orthographic projection of the second initial connection block 42-1 of the second initial signal line 42 on the substrate, the fourth insulating layer within the twelfth via V12 is etched away to expose the surface of the second initial connection block 42-1, and the twelfth via V12 is configured to connect the seventh connection electrode formed later to the second initial connection block 42-1 through the via.

In an exemplary embodiment, the front projection of the thirteenth via V13 on the substrate is within the range of the front projection of the plate connecting electrode 35 of the second plate 32 on the substrate, the fourth insulating layer within the thirteenth via V13 is etched away to expose the surface of the plate connecting electrode 35, and the thirteenth via V13 is configured to connect a third connecting electrode formed later with the plate connecting electrode 35 therethrough.

(16) And forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: on the substrate with the patterns, a third conductive film is deposited, and patterned by a patterning process to form a third conductive layer disposed on the fourth insulating layer, as shown in fig. 13A and 13B, fig. 13B is a schematic plan view of the third conductive layer in fig. 13A. In an exemplary embodiment, the third conductive layer may be referred to as a first source drain metal (SD 1) layer.

In an exemplary embodiment, the third conductive layer of each circuit unit includes at least: the first light emitting signal line 27, the second light emitting signal line 28, the first connection electrode 51, the second connection electrode 52, the third connection electrode 53, the fourth connection electrode 54, the fifth connection electrode 55, the sixth connection electrode 56, the seventh connection electrode 57, and the first data link line 81.

In an exemplary embodiment, the first light emitting signal line 27 may have a shape of a straight line or a folded line extending along the first direction X, and may be located between the second electrode plate 32 and the first scan signal line 21, and the first light emitting signal line 27 is connected to the fifth gate connection block 25-1 through the seventh via hole V7. Since the fifth gate connection block 25-1 is connected to the fifth gate electrode 25, connection of the first light emitting signal line 27 to the fifth gate electrode 25 is achieved, and the first light emitting signal line 27 can control on or off of the fifth transistor T5.

In an exemplary embodiment, the second light emitting signal line 28 may have a shape of a straight line or a folded line extending along the first direction X, and may be located between the first light emitting signal line 27 and the second preliminary signal line 42. The second light emitting signal line 28 may be provided with a light emitting connection block 28-1, and the light emitting connection block 28-1 may have a bar shape extending along the second direction Y and may be disposed at a side of the second light emitting signal line 28 near the first light emitting signal line 27. The first end of the light-emitting connection block 28-1 is connected to the side of the second light-emitting signal line 28 close to the first light-emitting signal line 27, and the second end of the light-emitting connection block 28-1 extends in a direction close to the first light-emitting signal line 27 and is then connected to the sixth gate connection block 26-1 through the eighth via hole V8. Since the sixth gate connection block 26-1 is connected to the sixth gate electrode 26, connection of the second light emitting signal line 28 to the sixth gate electrode 26 is achieved, and the second light emitting signal line 28 can control on or off of the sixth transistor T6.

In an exemplary embodiment, the light emitting connection blocks 28-1 in part of the adjacent circuit units may be connected to each other to form an integral structure connected to each other such that the second light emitting signal lines 28 of the two circuit units share the same light emitting connection block 28-1 and are connected to the sixth gate connection block 26-1 through the eighth via hole V8 shared by the two circuit units.

In an exemplary embodiment, the first light-emitting signal line 27 and the second light-emitting signal line 28 are arranged on the first source drain metal (SD 1) layer with larger thickness, so that the resistance of the light-emitting signal line is effectively reduced, the voltage drop of a light-emitting signal is reduced, the quality of light-emitting control can be improved, and the display quality is improved.

In an exemplary embodiment, the first connection electrode 51 may have a bar shape in which a body portion extends along the first direction X, a first end of the first connection electrode 51 is connected to the second region of the first active layer (also the first region of the second active layer) through the second via hole V2, and a second end of the first connection electrode 51 is connected to the first pad 31 through the ninth via hole V9. Since the first plate 31 serves as the gate electrode of the third transistor T3, the first connection electrode 51 enables interconnection between the second pole of the first transistor T1, the first pole of the second transistor T2, the gate electrode of the third transistor T3 and the first plate 31 of the storage capacitor, forming the first node N1 of the pixel driving circuit.

In an exemplary embodiment, the second connection electrode 52 may have a block shape (e.g., rectangular shape), the second connection electrode 52 is connected to the first region of the fourth active layer through the third via hole V3, and the second connection electrode 52 is configured to be connected to a data signal line formed later.

In an exemplary embodiment, the third connection electrode 53 may have a bar shape extending along the first direction X, a first end of the third connection electrode 53 is connected to the first region of the fifth active layer through the fourth via hole V4, and a second end of the third connection electrode 53 is connected to the plate connection electrode 35 through the thirteenth via hole V13. Since the plate electrode connection electrode 35 is connected to the second plate 32, the third connection electrode 53 enables interconnection between the first electrode of the fifth transistor T5 and the second plate 32 of the storage capacitor, the first electrode of the fifth transistor T5 and the second plate 32 of the storage capacitor having the same potential.

In an exemplary embodiment, the fourth connection electrode 54 may have a block shape (e.g., rectangular shape), the fourth connection electrode 54 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the fifth via hole V5, and the fourth connection electrode 54 is configured to be connected to an anode connection electrode formed later.

In an exemplary embodiment, the fifth connection electrode 55 may have a block shape (e.g., rectangular shape), the fifth connection electrode 55 being connected to the second electrode plate 32 through a tenth via hole V10, the fifth connection electrode 55 being configured to be connected to a first power line formed later.

In an exemplary embodiment, the sixth connection electrode 56 may have a bar shape extending along the first direction X, a first end of the sixth connection electrode 56 is connected to the first region of the first active layer through the first via hole V1, and a second end of the sixth connection electrode 56 is connected to the first initial connection block 41-1 through the eleventh via hole V11. Since the first initial connection block 41-1 is connected to the first initial signal line 41, the sixth connection electrode 56 implements that the first initial signal line 41 writes the first initial signal to the first pole of the first transistor T1.

In an exemplary embodiment, the seventh connection electrode 57 may have a bar shape extending along the first direction X, a first end of the seventh connection electrode 57 is connected to the first region of the seventh active layer through the sixth via hole V6, and a second end of the seventh connection electrode 57 is connected to the second initial connection block 42-1 through the twelfth via hole V12. Since the second initial connection block 42-1 is connected to the second initial signal line 42, the seventh connection electrode 57 implements that the second initial signal line 42 writes the second initial signal to the first pole of the seventh transistor T7.

In an exemplary embodiment, the first data link line 81 may have a shape of a straight line or a folded line extending along the first direction X, and may be located between the second scan signal line 22 and the first initial signal line 41.

In an exemplary embodiment, the first data link line 81 in at least one circuit unit may be provided with a first break K1, and the first break K1 may intercept the first data link line 81 such that the first data link lines 81 at both sides of the first break K1 are insulated from each other.

In an exemplary embodiment, the first data link line 81 may include first connection sub-lines 81-1 located at opposite sides of the first direction X of the first break K1, respectively, and second connection sub-lines 81-2 located at the first direction X side of the first break K1, the first connection sub-lines 81-1 being configured to be connected with one data signal line in the display area, and the second connection sub-lines 81-2 being configured as first dummy lines.

In an exemplary embodiment, at least one first break K1 may be provided in the circuit cells of the n+1th cell column, the orthographic projection of the first break K1 on the substrate overlapping at least partially the orthographic projection of the first break stop 61 on the substrate.

In an exemplary embodiment, the orthographic projection of the first fracture K1 on the substrate may be located within the range of the orthographic projection of the first fracture shielding block 61 on the substrate, so that the first fracture shielding block 61 may shield the first fracture K1 from the lower side, not only may effectively eliminate the film layer difference in different areas, be beneficial to shadow elimination, avoid the poor appearance of the display substrate, but also may shield the first fracture K1 from the lower side, and be beneficial to improving the transmittance.

In an exemplary embodiment, a data connection block 83 may be disposed on the first connection sub-line 81-1 in at least one circuit unit, and the data connection block 83 may have a block shape (e.g., rectangular shape). In the first direction X, the data connection block 83 may be disposed between the nth cell column and the n+1th cell column. In the second direction Y, the data connection block 83 may be disposed at a side of the first connection sub-line 81-1 near the third scan signal line 23 and connected to the first connection sub-line 81-1, and the data connection block 83 is configured to be connected to a second data connection line between the nth cell column and the n+1th cell column, which is formed later.

In an exemplary embodiment, the first connection sub-line 81-1 and the data connection block 83 may be an integral structure connected to each other.

In an exemplary embodiment, the second connection sub-line 81-2, which is the first dummy line, may not be connected to any signal line, or may be connected to the first power line, or may be connected to the second power line, or may be connected to the first initial signal line, or may be connected to the second initial signal line, the disclosure is not limited herein.

In an exemplary embodiment, the position and shape of the third conductive layer (except for the data connection block and the first break) in the adjacent two circuit cells may be symmetrically disposed with respect to the column center line in one cell row. For example, the third conductive layers of the nth cell column and the n+1th cell column may be positioned and shaped symmetrically with respect to the column center line. In an exemplary embodiment, the positions and shapes of the third conductive layers in the plurality of circuit cells in one cell column may be substantially the same.

(17) A first planarization layer pattern is formed. In an exemplary embodiment, forming the first planarization layer pattern may include: and coating a first flat film on the substrate with the patterns, and patterning the first flat film by a patterning process to form a first flat layer covering the fourth conductive layer patterns, wherein a plurality of through holes are formed on the first flat layer, as shown in fig. 14.

In an exemplary embodiment, the plurality of vias in each circuit unit includes at least: twenty-first via V21, twenty-second via V22, and twenty-third via V23.

In an exemplary embodiment, the orthographic projection of the twenty-first via V21 on the substrate is within the orthographic projection of the second connection electrode 52 on the substrate, the first planarization layer within the twenty-first via V21 is removed to expose the surface of the second connection electrode 52, and the twenty-first via V21 is configured to connect a data signal line formed later to the second connection electrode 52 therethrough.

In an exemplary embodiment, the orthographic projection of the twenty-second via V22 on the substrate is within the range of the orthographic projection of the fifth connection electrode 55 on the substrate, the first planarization layer within the twenty-second via V22 is removed to expose the surface of the fifth connection electrode 55, and the twenty-second via V22 is configured to connect the subsequently formed first power line with the fifth connection electrode 55 therethrough.

In an exemplary embodiment, the orthographic projection of the twenty-third via V23 on the substrate is within the orthographic projection of the fourth connection electrode 54 on the substrate, the first planarization layer within the twenty-third via V23 is removed to expose the surface of the fourth connection electrode 54, and the twenty-third via V23 is configured to connect the anode connection electrode formed later with the fourth connection electrode 54 therethrough.

In an exemplary embodiment, the at least one circuit unit may further include a twenty-fourth via V24. The front projection of the twenty-fourth via V24 on the substrate is within the range of the front projection of the data connection block 83 of the first data connection line 81 on the substrate, the first planarization layer within the twenty-fourth via V24 is removed, exposing the surface of the data connection block 83, and the twenty-fourth via V24 is configured to connect the subsequently formed second data connection line 82 with the data connection block 83 therethrough.

(18) And forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: on the substrate with the patterns, a fourth conductive film is deposited, and patterned by a patterning process to form a fourth conductive layer disposed on the first flat layer, as shown in fig. 15A and 15B, fig. 15B is a schematic plan view of the fourth conductive layer in fig. 15A. In an exemplary embodiment, the fourth conductive layer may be referred to as a second source drain metal (SD 2) layer.

In an exemplary embodiment, the fourth conductive layer of each circuit unit includes at least: a first power supply line 71, a second power supply line 72, a data signal line 73, and an anode connection electrode 74.

In an exemplary embodiment, the first power line 71 may have a shape of a straight line or a folded line in which the body portion extends along the second direction Y, and the first power line 71 is connected to the fifth connection electrode 55 through the twenty-second via hole V22. Since the fifth connection electrode 55 is connected to the second plate 32 through the via hole, the second plate 32 is connected to the first region of the fifth active layer through the plate connection electrode 35 and the third connection electrode 53, so that it is realized that the first power line 71 can write the first power signal to the second plate 32 and the first electrode of the fifth transistor T5.

In an exemplary embodiment, the first power line 71 may be a fold line of a widening width, and an orthographic projection of the first power line 71 on the substrate at least partially overlaps with an orthographic projection of the first connection electrode 51 on the substrate. Since the first connection electrode 51 serves as the first node N1 of the pixel driving circuit, the first power line 71 having a constant potential can shield the first node N1, and can prevent the influence of the data voltage jump on the first node N1, thereby improving the working stability of the pixel driving circuit and the display effect.

In an exemplary embodiment, the second power line 72 may have a shape of a straight line or a folded line in which the body portion extends along the second direction Y, and may be disposed between the first power line 71 and the data signal line 73, and the second power line 72 is configured to be connected to a cathode in the light emitting device. According to the embodiment of the disclosure, the second power line is arranged in the display area, so that the structure of the VSS in pixel is realized, the resistance of the second power line can be effectively reduced, the voltage drop of the second power signal is reduced, the uniformity of the second power signal in the display substrate is effectively improved, the display uniformity is effectively improved, the display quality and the display quality are improved, the width of a frame power lead can be greatly reduced, the width of a left frame and a right frame is greatly reduced, the screen occupation ratio is improved, and the full-screen display is facilitated.

In an exemplary embodiment, the data signal line 73 may have a shape of a straight line or a folded line in which the body portion extends along the second direction Y, and the data signal line 73 is connected to the second connection electrode 52 through the twenty-first via hole V21. Since the second connection electrode 52 is connected to the first region of the fourth active layer through a via hole, it is realized that the data signal line 73 can write a data signal to the first electrode of the fourth transistor T4.

In the exemplary embodiment, the orthographic projection of the data signal line 73 on the substrate does not overlap with the orthographic projection of the channel regions of the first transistor T1 to the seventh transistor T7 on the substrate, so that signal crosstalk caused by data voltage jump of the data signal line 73 can be avoided, the influence of the data voltage jump on the first transistor T1 to the seventh transistor T7 is avoided, the working stability of the pixel driving circuit is improved, and the display effect is improved.

In an exemplary embodiment, the anode connection electrode 74 may have a block shape (e.g., rectangular shape), and the anode connection electrode 74 is connected to the fourth connection electrode 54 through the twenty-third via hole V23, and the anode connection electrode 74 is configured to be connected to an anode to be formed later. Since the fourth connection electrode 54 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through a via hole, it is possible to realize that the pixel driving circuit outputs a driving current to the light emitting device.

In an exemplary embodiment, the fourth conductive layer of the at least one circuit unit may further include a second data connection line 82. The second data link line 82 may have a shape of a straight line or a folded line in which the body portion extends in the second direction Y, and may be disposed between adjacent cell columns. The second data link line 82 may be connected to the data connection block 83 on the first link sub-line 81-1 through the twenty-fourth via hole V24, and the second data link line 82 is configured to be connected to the data out line in the bonding area. Since the data connection block 83 is connected to the first connection sub-line 81-1 of the first data connection line 81, the first connection sub-line 81-1 is configured to be connected to the data signal line in the display area, and the second data connection line 82 is configured to be connected to the data outgoing line in the bonding area, the interconnection between the first data connection line 81 in which the body portion extends along the first direction X and the second data connection line 82 in which the body portion extends along the second direction Y is achieved, and the data outgoing line in the bonding area is connected to the data signal line in the display area through the first data connection line 81 and the second data connection line 82.

In an exemplary embodiment, the second data link line 82 may be disposed between the first power line 71 of the nth cell column and the first power line 71 of the n+1th cell column, and the first power line 71 having a constant potential may shield an influence of a data voltage jump of the second data link line 82 on a key node of the pixel driving circuit, improve operational stability of the pixel driving circuit, and improve a display effect.

In an exemplary embodiment, the second data link line 82 of the at least one circuit unit may be provided with a second break K2, and the second break K2 may intercept the second data link line 82 such that the second data link lines 82 at both sides of the second break K2 are insulated from each other.

In an exemplary embodiment, the second data link line 82 may include a third link sub-line 82-3 located at one side (a side close to the bonding region) of the second break K2 in the second direction Y and a fourth link sub-line 82-4 located at one side (a side far from the bonding region) of the second break K2 in the opposite direction Y, the third link sub-line 82-3 being connected with the first link sub-line 81-1 of the first data link line 81 and configured to be connected with the data lead line in the bonding region, the fourth link sub-line 82-4 being configured as a second dummy line.

In an exemplary embodiment, the orthographic projection of the second fracture K2 onto the substrate at least partially overlaps the orthographic projection of the second fracture stop 62 onto the substrate.

In an exemplary embodiment, the orthographic projection of the second fracture K2 on the substrate may be located within the range of the orthographic projection of the second fracture shielding block 62 on the substrate, so that the second fracture shielding block 62 may shield the second fracture K2 from below, which not only may effectively eliminate the film layer differences in different areas, be beneficial to shadow elimination, avoid poor appearance of the display substrate, but also may shield the second fracture K2 from below, and be beneficial to improving the transmittance.

In an exemplary embodiment, the fourth connection sub-line 82-4, which is the second dummy line, may not be connected to any signal line, or may be connected to the first power line, or may be connected to the second power line, or may be connected to the first initial signal line, or may be connected to the second initial signal line, the disclosure is not limited herein.

The subsequent fabrication process may include forming a second planar layer having an anode via disposed thereon, the anode via exposing a surface of the anode connection electrode, the anode via configured to connect a subsequently formed anode with the anode connection electrode through the via.

To this end, the driving structure layer of the present embodiment was prepared on the substrate. In a plane parallel to the display substrate, the driving structure layer may include a plurality of circuit units, each of which may include a pixel driving circuit, and a first scan signal line, a second scan signal line, a third scan signal line, a first light emitting signal line, a second light emitting signal line, a first initial signal line, a second initial signal line, a first power supply line, and a data signal line connected to the pixel driving circuit.

In a plane perpendicular to the display substrate, the driving structure layer may include a shielding layer, a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a first planarization layer, a fourth conductive layer, and a second planarization layer, which are sequentially disposed on the base. The shielding layer may include at least a shielding electrode, a plurality of shielding connection bars and a plurality of shielding stoppers, the semiconductor layer may include at least an active layer of a plurality of transistors, the first conductive layer may include at least a first scanning signal line, a second scanning signal line, a third scanning signal line and a first plate of a storage capacitor, the second conductive layer may include at least a first initial signal line, a second initial signal line and a second plate of a storage capacitor, the third conductive layer may include at least a first light emitting signal line, a second light emitting signal line, a first data connection line and a plurality of connection electrodes, and the fourth conductive layer may include at least a first power line, a second power line, a data signal line and a second data connection line.

In an exemplary embodiment, the substrate may be a flexible substrate, or may be a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass, quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, ethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyimide, polyvinyl chloride, polyethylene, textile fibers. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on a glass carrier plate. The first and second flexible material layers may be Polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer soft films, the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx) for improving the water-oxygen resistance of the substrate, the first and second inorganic material layers may be referred to as Barrier (Barrier) layers, and the semiconductor layer may be amorphous silicon (a-si).

In an exemplary embodiment, the first, second, third, and fourth insulating layers may employ any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multi-layer, or a composite layer. The shielding layer, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer may be made of a metal material such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), or molybdenum (Mo), or an alloy material composed of a metal such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), or a single-layer structure, or a multi-layer composite structure such as Ti/Al/Ti, or the like. The first and second planarization layers may be made of an organic material such as resin or polyimide.

In an exemplary embodiment, after the driving structure layer is prepared, the light emitting structure layer may be prepared on the driving structure layer, and the encapsulation structure layer may be prepared on the light emitting structure layer, which will not be described again.

The exemplary embodiment of the disclosure provides a display substrate, through setting up first data connecting wire and second data connecting wire in the display region, the data lead-out wire of binding region is connected with data signal line through first data connecting wire and second data connecting wire for need not set up fan-shaped's slash in the lead-out wire district, effectively reduced the length in lead-out wire district, reduced the lower frame width greatly, improved screen occupation ratio, be favorable to realizing comprehensive screen display.

According to the embodiment of the disclosure, the first fracture on the first data connecting line is shielded from the lower side by the first fracture shielding block, and the first fracture shielding block is connected with the first initial signal line, so that the transmittance is effectively improved, the film layer difference of different areas can be effectively eliminated, shadow elimination is facilitated, poor appearance of the display substrate is avoided, and the display quality are improved.

According to the embodiment of the disclosure, the second fracture is shielded from the lower side by the second fracture shielding block, and the second fracture shielding block is connected with the second initial signal line, so that the transmittance can be further improved, the sensor (sensor) identification can be realized, and the display quality can be further improved.

According to the embodiment of the disclosure, the first fracture shielding block is overlapped with the first node of the pixel driving circuit to form the node capacitor, so that the potential of the first node in the pixel driving circuit can be effectively stabilized, and the driving performance of the pixel driving circuit is improved.

According to the embodiment of the disclosure, the first light-emitting signal wire and the second light-emitting signal wire are arranged on the first source drain metal layer, so that the resistance of the light-emitting signal wire is effectively reduced, the voltage drop of a light-emitting signal is reduced, the quality of light-emitting control can be improved, and the display quality is improved.

According to the embodiment of the disclosure, the pixel driving circuits in the adjacent circuit units can share the same connecting via hole and connecting electrode by adopting the mirror symmetry design, so that the number of the via holes and the number of the electrodes are effectively reduced, the occupied space of the pixel driving circuits can be effectively reduced, and the resolution ratio is improved.

According to the embodiment of the disclosure, the second power line is arranged in the display area, so that the structure of the VSS in pixel is realized, the resistance of the second power line can be effectively reduced, the voltage drop of the second power signal is reduced, the uniformity of the second power signal in the display substrate is effectively improved, the display uniformity is effectively improved, the display quality and the display quality are improved, the width of a frame power lead can be greatly reduced, the width of a left frame and a right frame is greatly reduced, the screen occupation ratio is improved, and the full-screen display is facilitated.

The preparation process of the embodiment of the disclosure can be well compatible with the existing preparation process, and has the advantages of simple process implementation, easy implementation, high production efficiency, low production cost and high yield.

Fig. 16 is a schematic structural view of another display substrate according to an exemplary embodiment of the present disclosure, fig. 17A is a schematic plan view of the second conductive layer in fig. 16, and fig. 17B is a schematic plan view of the third conductive layer in fig. 16. As shown in fig. 16, 17A and 17B, the present embodiment shows that the substrate structure is substantially the same as that shown in fig. 7, except that the positions of the first fracture stopper 61 and the first fracture K1 are different.

In an exemplary embodiment, the structure of the second conductive layer of the present embodiment is substantially the same as that of the embodiment shown in fig. 7, except that the first fracture shielding block 61 provided on the first preliminary signal line 41 may be provided between the nth cell column and the n+1th cell column. The structure of the third conductive layer of this embodiment is substantially the same as that of the embodiment shown in fig. 7, except that the first break K1 on the first data link 81 may be disposed between the nth cell column and the n+1th cell column, and the front projection of the first break K1 on the substrate at least partially overlaps with the front projection of the first break stop 61 on the substrate.

In an exemplary embodiment, the orthographic projection of the first fracture K1 on the substrate may be located within the range of the orthographic projection of the first fracture shielding block 61 on the substrate, so that the first fracture shielding block 61 may shield the first fracture K1 from below, thereby not only effectively improving the transmittance, but also effectively eliminating the film layer difference in different areas, being beneficial to shadow elimination, avoiding the poor appearance of the display substrate, and improving the display quality and the display quality.

In an exemplary embodiment, the first data link line 81 may include first link sub-lines 81-1 located at opposite sides of the first direction X of the first break K1 and second link sub-lines 81-2 located at the first direction X side of the first break K1, respectively, and a data link block (not shown) may be disposed on the first link sub-lines 81-1. For example, for the first break K1 disposed between the nth cell column and the n+1th cell column, a data connection block may be disposed between the N-2 th cell column and the N-1 th cell column, configured to be connected with a second data connection line between the N-2 th cell column and the N-1 th cell column, which is formed later.

In an exemplary embodiment, the second conductive layer of the at least one circuit unit may further include a second fracture mask (not shown), and the at least one second data connection line 82 may have a second fracture (not shown) disposed thereon, and an orthographic projection of the second fracture on the substrate may be within an orthographic projection of the second fracture mask on the substrate. For example, for the first fracture shielding block 61 and the first fracture K1 to be provided in the M-th cell row, the second fracture shielding block and the second fracture may be provided in the M-1-th cell row, and M may be a positive integer greater than or equal to 2.

The present embodiment provides a display substrate, which not only has the technical effect of the display substrate shown in fig. 7, but also can improve the consistency of the pixel driving circuit structures in a plurality of circuit units and improve the process quality by arranging the first fracture and the first fracture shielding block between the unit columns.

Fig. 18 is a schematic structural view of a display substrate according to still another exemplary embodiment of the present disclosure, fig. 19A is a schematic plan view of the second conductive layer in fig. 18, and fig. 19B is a schematic plan view of the third conductive layer in fig. 18. As shown in fig. 18, 19A and 19B, the present embodiment shows that the substrate structure is substantially the same as that shown in fig. 7, except that the positions of the first fracture stopper 61 and the first fracture K1 are different.

In an exemplary embodiment, the structure of the second conductive layer of the present embodiment is substantially the same as that of the previous embodiment, except that the first fracture shielding block 61 may be disposed at a side of the second preliminary signal line 42 close to the first scanning signal line 21, and the second fracture shielding block 62 may be disposed at a side of the first preliminary signal line 41 close to the second scanning signal line 22, the first preliminary signal line 41 functioning as a constant potential signal line of the present disclosure.

In an exemplary embodiment, the first end of the first fracture shielding block 61 is connected to a side of the second shielding electrode 44 close to the first scanning signal line 21, and the second end of the first fracture shielding block 61 extends toward a side close to the first scanning signal line 21. The first end of the second fracture shielding block 62 is connected to a side of the first initial signal line 41 close to the second scanning signal line 22, and the second end of the second fracture shielding block 62 extends toward a side of the second scanning signal line 22.

In an exemplary embodiment, the first fracture shielding block 61 may be disposed in the circuit unit of the n+1 cell row, and the second fracture shielding block 62 may be disposed between the N cell row and the n+1 cell row.

In an exemplary embodiment, the second preliminary signal line 42, the second shielding electrode 44, and the first fracture shielding block 61 may be an integrally connected structure, and the first preliminary signal line 41 and the second fracture shielding block 62 may be an integrally connected structure.

In an exemplary implementation, the structure of the third conductive layer of the present embodiment is substantially the same as that of the embodiment shown in fig. 7, except that the first data link line 81 may be located between the first scan signal line 21 and the second initial signal line 42.

In an exemplary implementation, the structure of the fourth conductive layer of the present embodiment is substantially the same as that of the embodiment shown in fig. 7, and the second data link line 82 may be disposed between the first power line 71 of the nth cell column and the first power line 71 of the n+1th cell column, and the second data link line 82 is connected to the data link block 83 through a via hole, and the orthographic projection of the second break K2 on the second data link line 82 on the substrate at least partially overlaps with the orthographic projection of the second break shadow block 62 on the substrate.

The embodiment provides a display substrate, utilizes first fracture to hide the dog and second fracture to hide the dog from the below respectively and shelters from first fracture and second fracture, has not only effectively improved the improvement transmissivity, can effectively eliminate the rete difference in different regions moreover, is favorable to eliminating the shadow, avoids display substrate's outward appearance poor, has improved display quality and display quality.

Fig. 20 is a schematic structural view of a display substrate according to another exemplary embodiment of the present disclosure, fig. 21A is a schematic plan view of the second conductive layer in fig. 20, and fig. 21B is a schematic plan view of the third conductive layer in fig. 20. As shown in fig. 20, 21A and 21B, the present embodiment shows that the substrate structure is substantially the same as that shown in fig. 18, except that the positions of the first fracture stopper 61 and the first fracture K1 are different.

In an exemplary embodiment, the structure of the second conductive layer of the present embodiment is substantially the same as that of the embodiment shown in fig. 18, except that the first fracture shielding block 61 provided on the second preliminary signal line 42 may be provided between the nth cell column and the n+1th cell column. The structure of the third conductive layer of this embodiment is substantially the same as that of the embodiment shown in fig. 18, except that the first break K1 on the first data link 81 may be disposed between the nth cell column and the n+1th cell column, and the front projection of the first break K1 on the substrate at least partially overlaps with the front projection of the first break stop 61 on the substrate.

The present embodiment provides a display substrate, which not only has the technical effect of the display substrate shown in fig. 18, but also can improve the consistency of the pixel driving circuit structure in a plurality of circuit units and improve the process quality by arranging the first fracture and the first fracture shielding block between the unit columns.

Fig. 22 is a schematic structural view of a display substrate according to still another exemplary embodiment of the present disclosure, and fig. 23 is a schematic plan view of the fourth conductive layer in fig. 22. As shown in fig. 22 and 23, the present embodiment shows that the substrate structure is substantially the same as that shown in fig. 7, except that the first fracture shielding block 61 and the third fracture shielding block 63 are used as fracture shielding structures of the present disclosure, the first fracture shielding block 61 shields the first fracture K1 from below, and the third fracture shielding block 63 shields the first fracture K1 from above.

In an exemplary embodiment, the structures of the second conductive layer and the third conductive layer of the present embodiment are substantially the same as the embodiment shown in fig. 7, except that the orthographic projection of the first fracture shielding block 61 on the substrate at least partially overlaps with the orthographic projection of the first region of the first active layer on the substrate, i.e. the position of the first fracture shielding block 61 is adjusted from the position of the second region of the first active layer to the position of the first region of the first active layer in the first direction X. The first fracture K1 on the first data connection line 81 is adjusted to the position of the first fracture shielding block 61, and the orthographic projection of the first fracture K1 on the substrate is located within the orthographic projection range of the first fracture shielding block 61 on the substrate.

In an exemplary embodiment, the structure of the fourth conductive layer of the present embodiment is substantially the same as that of the embodiment shown in fig. 7, except that the third fracture shielding block 63 is provided on the second power line 72 of at least one circuit unit.

In an exemplary embodiment, the third fracture shielding block 63 may have a block shape (e.g., rectangular shape) and may be disposed at a side of the second power line 72 adjacent to the first power line 71. The first end of the third fracture shielding block 63 is connected to the side, close to the first power line 71, of the second power line 72, the second end of the third fracture shielding block 63 extends towards the direction close to the first power line 71, and the orthographic projection of the third fracture shielding block 63 on the substrate at least partially overlaps with the orthographic projection of the first fracture K1 on the substrate.

In an exemplary embodiment, the orthographic projection of the first fracture K1 on the substrate may be located within the range of the orthographic projection of the second power line 72 and the third fracture shielding block 63 on the substrate, so that the second power line 72 and the third fracture shielding block 63 may shield the first fracture K1 from above, which is beneficial to shadow elimination and avoids poor appearance of the display substrate.

In the exemplary embodiment, the first initial signal line 41 and the second power line 72 simultaneously serve as constant potential signal lines of the present disclosure, the first fracture shielding block 61 is connected to the first initial signal line 41, and the third fracture shielding block 63 is connected to the second power line 72.

The present embodiment provides a display substrate, which not only has the technical effect of the display substrate shown in fig. 7, but also makes the first fracture K1 be shielded by shielding blocks above and below the first fracture K1 by setting the third fracture shielding block 63 on the second power line 72, so that the film layer differences in different areas can be further eliminated, the shadow is removed, and the poor appearance of the display substrate is further avoided.

Fig. 24 is a schematic structural view of a display substrate according to still another exemplary embodiment of the present disclosure. As shown in fig. 24, the present embodiment shows a substrate structure substantially the same as that shown in fig. 22, except that the third fracture shielding block 63 shields from above the first fracture K1, and the first fracture shielding block is not provided below the first fracture K1.

In an exemplary embodiment, the structures of the second conductive layer, the third conductive layer, and the fourth conductive layer in this embodiment are substantially the same as those of the embodiment shown in fig. 22, except that the first fracture shielding block is not provided on the first initial signal line 41 in the second conductive layer, the third fracture shielding block 63 serves as a fracture shielding structure of the present disclosure, and the second power line 72 serves as a constant potential signal line of the present disclosure.

The embodiment provides a display substrate, through set up third fracture and hide dog 63 on second power cord 72, third fracture hides dog 63 and can shelter from first fracture K1 from the top, is favorable to eliminating the shadow, avoids display substrate's outward appearance bad, has simplified the structure of second conducting layer simultaneously, is favorable to improving the transmissivity.

Fig. 25 is a schematic structural view of a display substrate according to still another exemplary embodiment of the present disclosure, and fig. 26 is a schematic plan view of the fourth conductive layer in fig. 25. As shown in fig. 25 and 26, the present embodiment shows that the substrate structure is substantially the same as that shown in fig. 7, except that the first fracture shielding block 61 and the third fracture shielding block 63 are used as fracture shielding structures of the present disclosure, the first fracture shielding block 61 shields the first fracture K1 from below, and the third fracture shielding block 63 shields the first fracture K1 from above.

In an exemplary embodiment, the structures of the second conductive layer, the third conductive layer, and the fourth conductive layer in this embodiment are substantially the same as those of the embodiment shown in fig. 7, except that the third fracture shielding block 63 is provided on the first power line 71 of at least one circuit unit.

In an exemplary embodiment, the third fracture shielding block 63 may have a block shape (e.g., rectangular shape) and may be disposed at a side of the first power line 71 adjacent to the second power line 72. The first end of the third fracture shielding block 63 is connected to the side, close to the second power line 72, of the first power line 71, the second end of the third fracture shielding block 63 extends towards the direction close to the second power line 72, and the orthographic projection of the third fracture shielding block 63 on the substrate at least partially overlaps with the orthographic projection of the first fracture K1 on the substrate.

In an exemplary embodiment, the orthographic projection of the first fracture K1 on the substrate may be located within the range of the orthographic projection of the first power line 71 and the third fracture shielding block 63 on the substrate, so that the first power line 71 and the third fracture shielding block 63 may shield the first fracture K1 from above, which is beneficial to shadow elimination and avoids poor appearance of the display substrate.

In the exemplary embodiment, the first initial signal line 41 and the first power supply line 71 simultaneously serve as constant potential signal lines of the present disclosure, the first fracture shielding block 61 is connected to the first initial signal line 41, and the third fracture shielding block 63 is connected to the first power supply line 71.

The present embodiment provides a display substrate, which not only has the technical effect of the display substrate shown in fig. 7, but also makes the upper and lower parts of the first fracture K1 have shielding blocks to shield the first fracture K1 by arranging the third fracture shielding block 63 on the first power line 71, so that the film layer differences in different areas can be further eliminated, shadow elimination is facilitated, and poor appearance of the display substrate is further avoided.

Fig. 27 is a schematic structural view of a display substrate according to still another exemplary embodiment of the present disclosure. As shown in fig. 27, the present embodiment shows a substrate structure substantially the same as that shown in fig. 25, except that the third fracture shielding block 63 shields from above the first fracture K1, and the first fracture shielding block is not provided below the first fracture K1.

In an exemplary embodiment, the structures of the second conductive layer, the third conductive layer, and the fourth conductive layer in this embodiment are substantially the same as those of the embodiment shown in fig. 25, except that the first fracture shielding block is not provided on the first initial signal line 41 in the second conductive layer, the third fracture shielding block 63 serves as a fracture shielding structure of the present disclosure, and the first power line 71 serves as a constant potential signal line of the present disclosure.

The embodiment provides a display substrate, through set up third fracture and hide dog 63 on first power cord 71, third fracture hides dog 63 and can shelter from first fracture K1 from the top, is favorable to eliminating the shadow, avoids display substrate's outward appearance bad, has simplified the structure of second conducting layer simultaneously, is favorable to improving the transmissivity.

Fig. 28 is a schematic structural view of a display substrate according to still another exemplary embodiment of the present disclosure. As shown in fig. 28, the structure of the display substrate of the present embodiment is substantially the same as that shown in fig. 7, except that the first data link line 81 in the embodiment shown in fig. 7 is located between the second scan signal line 22 and the first initial signal line 41, and the first data link line 81 of the present embodiment is disposed at a side of the first initial signal line 41 away from the second scan signal line 22.

In an exemplary embodiment, the structure of the second conductive layer of the present embodiment is substantially the same as that of the embodiment shown in fig. 7, except that the first initial signal line 41 is located close to the second scanning signal line 22 and away from the third scanning signal line 23, i.e., the position of the first initial signal line 41 of the present embodiment is shifted upward with respect to the embodiment of fig. 7.

In an exemplary embodiment, the distance between the first initial signal line 41 and the second scanning signal line 22 in the present embodiment is smaller than the distance between the first initial signal line 41 and the second scanning signal line 22 in the embodiment of fig. 7, the extension length of the first initial connection block 41-1 in the second direction Y in the present embodiment is longer than the extension length of the first initial connection block 41-1 in the second direction Y in the embodiment of fig. 7, and the first initial signal line 41 is not provided with the first fracture shielding block.

In an exemplary implementation, the structure of the third conductive layer of the present embodiment is substantially the same as that of the embodiment shown in fig. 7, except that the first data link line 81 may be located between the third scan signal line 23 and the first initial signal line 41, i.e., the first data link line 81 is located at a side of the first initial signal line 41 away from the second scan signal line 22, and the position of the first data link line 81 of the present embodiment is shifted downward with respect to the embodiment of fig. 7.

In an exemplary implementation, the front projection of the first data link line 81 on the substrate in the embodiment of fig. 7 does not overlap with the front projection of the first initial connection block 41-1 on the substrate, the front projection of the first data link line 81 on the substrate in the embodiment at least partially overlaps with the front projection of the first initial connection block 41-1 on the substrate,

In an exemplary embodiment, the structure of the fourth conductive layer of the present embodiment is substantially the same as that of the embodiment shown in fig. 7. Since the first power line 71 is a broken line with a variable width, the position of the first data connection line 81 moves down, so that the first break K1 corresponds to a position with a larger width in the first power line 71, and the first power line 71 serves as a break shielding structure of the disclosure and also serves as a constant potential signal line of the disclosure, and the orthographic projection of the first break K1 on the substrate may be located within the range of the orthographic projection of the first power line 71 on the substrate.

The embodiment provides a display substrate, through adjusting the positions of first initial signal line 41 and first data connection line 81, make first fracture K1 correspond to the great position of width in the first power cord 71, first power cord 71 both as the fracture shielding structure of this disclosure, still as the constant potential signal line of this disclosure, first power cord 71 can shelter from first fracture K1 from the top, be favorable to the shadow that disappears, avoid the outward appearance bad of display substrate, neither need additionally widen the processing to first power cord 71, can not influence the transmissivity, can simplify the structure of second conducting layer again, be favorable to improving the transmissivity.

In some possible implementations, the embodiment shown in fig. 28 may be extended accordingly. For example, the second conductive layer may be provided with a first fracture shielding block, where the first fracture shielding block may be disposed on a side of the first initial signal line 41 near the third scanning signal line 23, and the orthographic projection of the first fracture K1 on the substrate is within the orthographic projection range of the first fracture shielding block on the substrate, which is not limited herein.

The foregoing illustrated structure of the present disclosure and the process of preparing the same are merely exemplary, and in exemplary embodiments, the corresponding structure may be modified and patterning processes may be added or subtracted according to actual needs. For example, a first fracture masking block in various embodiments may be provided in the first conductive layer, the first fracture masking block masking the first fracture from below. As another example, a second fracture shielding block in various embodiments may be disposed in the first conductive layer or the third conductive layer, where the second fracture shielding block shields the second fracture from below, which is not limited herein.

In an exemplary embodiment, the display substrate of the present disclosure may be applied to a display device having a pixel driving circuit, such as an OLED, a quantum dot display (QLED), a light emitting diode display (Micro LED or Mini LED), or a quantum dot light emitting diode display (QDLED), etc., which is not limited herein.

The disclosure also provides a preparation method of the display substrate, so as to manufacture the display substrate provided by the embodiment. In an exemplary embodiment, the display substrate includes a plurality of circuit units, at least one first data link line extending along a first direction, and at least one second data link line extending along a second direction, the first direction and the second direction crossing; at least one circuit unit includes a pixel driving circuit, a data signal line configured to supply a data signal to the pixel driving circuit, and at least one constant potential signal line configured to supply a constant potential signal to the pixel driving circuit, the data signal line being connected to the first data link line, the first data link line being connected to the second data link line; the at least one circuit unit further comprises at least one first fracture and at least one fracture shielding structure, the first fracture is arranged on the first data connecting line and cuts off the first data connecting line, and the fracture shielding structure is connected with the constant potential signal line; the preparation method can comprise the following steps:

The disclosure also provides a display device, which comprises the display substrate. The display device may be: the embodiment of the invention is not limited to any product or component with display function such as mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, etc.

While the embodiments disclosed in the present disclosure are described above, it should be noted that the above-described embodiments are merely exemplary and not limiting. Accordingly, the present disclosure is not limited to what has been particularly shown and described herein. Various modifications, substitutions, or omissions may be made in the form and details of the implementations without departing from the scope of the disclosure.

Claims

1. A display substrate, characterized in that in a direction parallel to the display substrate, the display substrate comprises a plurality of circuit units, at least one first data link line extending along a first direction, and at least one second data link line extending along a second direction, the first direction and the second direction intersecting; at least one circuit unit includes a pixel driving circuit, a data signal line configured to supply a data signal to the pixel driving circuit, and at least one constant potential signal line configured to supply a constant potential signal to the pixel driving circuit, the data signal line being connected to the first data link line, the first data link line being connected to the second data link line; the at least one circuit unit further comprises at least one first fracture and at least one fracture shielding structure, the first fracture is arranged on the first data connecting line and cuts off the first data connecting line, and the fracture shielding structure is connected with the constant potential signal line; in the direction perpendicular to the display substrate, the display substrate at least comprises a plurality of conductive layers arranged on a base, the first data connecting wire is arranged in one conductive layer, and the fracture shielding structure is arranged in any conductive layer or a plurality of conductive layers except the conductive layer where the first data connecting wire is arranged; the orthographic projection of the first fracture on the substrate at least partially overlaps the orthographic projection of the fracture shielding structure on the substrate.

2. The display substrate of claim 1, wherein the at least one fracture shielding structure comprises a first fracture shielding block, an orthographic projection of the first fracture on the substrate at least partially overlaps an orthographic projection of the first fracture shielding block on the substrate, and the first fracture shielding block is disposed in a conductive layer of a side of the conductive layer of the first data link line adjacent to the substrate.

3. The display substrate according to claim 2, wherein the plurality of conductive layers includes at least a first conductive layer disposed on the base, a second conductive layer disposed on a side of the first conductive layer away from the base, a third conductive layer disposed on a side of the second conductive layer away from the base, and a fourth conductive layer disposed on a side of the third conductive layer away from the base, the first data link line is disposed in the third conductive layer, and the first fracture shielding block is disposed in the first conductive layer and/or the second conductive layer.

4. The display substrate according to claim 2, wherein at least one constant potential signal line includes a first initial signal line, the pixel driving circuit includes at least a first transistor and a second transistor, a gate electrode of the first transistor is connected to a second scanning signal line, a first pole of the first transistor is connected to the first initial signal line, a gate electrode of the second transistor is connected to a third scanning signal line, and a first pole of the second transistor is connected to a second pole of the first transistor; in at least one circuit unit, the first initial signal line is disposed between the second scanning signal line and the third scanning signal line, and the first fracture shielding block is connected with the first initial signal line.

5. The display substrate according to claim 4, wherein in at least one circuit unit, the first data link line is disposed between the second scan signal line and the first initial signal line, and the first break barrier is disposed at a side of the first initial signal line close to the second scan signal line.

6. The display substrate according to claim 4, wherein the first transistor comprises at least a first active layer, the second transistor comprises at least a second active layer, a second region of the first active layer is connected to a first region of the second active layer, and an orthographic projection of the first break shielding block on the substrate and an orthographic projection of the second region of the first active layer on the substrate at least partially overlap in at least one circuit unit.

7. The display substrate according to claim 2, wherein at least one constant potential signal line includes a second initial signal line, wherein the pixel driving circuit includes at least a third transistor and a seventh transistor as driving transistors, wherein a gate electrode of the seventh transistor is connected to the first scanning signal line, and wherein a first electrode of the seventh transistor is connected to the second initial signal line; in at least one circuit unit, the second initial signal line is disposed at a side of the first scanning signal line far away from the third transistor, and the first fracture shielding block is connected with the second initial signal line.

8. The display substrate according to claim 7, wherein in at least one circuit unit, the first data link line is disposed between the first scan signal line and the second initial signal line, and the first break barrier is disposed at a side of the second initial signal line close to the first scan signal line.

9. The display substrate of claim 2, wherein at least one first break is disposed between the first direction adjacent circuit units and at least one first break stop is disposed between the first direction adjacent circuit units.

10. The display substrate according to claim 1, wherein at least one circuit unit further comprises at least one second break and at least one second break stop, the second break being provided on the second data connection line and cutting off the second data connection line, the orthographic projection of the second break on the substrate overlapping at least partially the orthographic projection of the second break stop on the substrate.

11. The display substrate of claim 10, wherein the plurality of conductive layers includes at least a first conductive layer disposed on a base, a second conductive layer disposed on a side of the first conductive layer away from the base, a third conductive layer disposed on a side of the second conductive layer away from the base, and a fourth conductive layer disposed on a side of the third conductive layer away from the base, the second data connection line disposed in the fourth conductive layer, the second break barrier disposed in any one or more of the first conductive layer, the second conductive layer, and the third conductive layer.

12. The display substrate according to claim 10, wherein at least one constant potential signal line includes a first initial signal line configured to supply a first initial signal to the pixel driving circuit, and wherein the second break barrier is connected to the first initial signal line in at least one circuit unit.

13. The display substrate according to claim 10, wherein at least one constant potential signal line includes a second initial signal line configured to supply a second initial signal to the pixel driving circuit, and wherein the second break barrier is connected to the second initial signal line in at least one circuit unit.

14. The display substrate of claim 10, wherein at least one second break is disposed between the first direction adjacent circuit units and at least one second break stop is disposed between the first direction adjacent circuit units.

15. The display substrate of any one of claims 1 to 14, wherein at least one fracture shielding structure comprises a third fracture shielding block, wherein an orthographic projection of the first fracture on the substrate at least partially overlaps an orthographic projection of the third fracture shielding block on the substrate, and wherein the third fracture shielding block is disposed in a conductive layer on a side of the conductive layer where the first data link is located away from the substrate.

16. The display substrate of claim 15, wherein the plurality of conductive layers includes at least a first conductive layer disposed on a base, a second conductive layer disposed on a side of the first conductive layer away from the base, a third conductive layer disposed on a side of the second conductive layer away from the base, and a fourth conductive layer disposed on a side of the third conductive layer away from the base, the first data link is disposed in the third conductive layer, and the third fracture mask is disposed in the fourth conductive layer.

17. The display substrate according to claim 15, wherein at least one constant potential signal line includes a first power supply line configured to supply a first power supply signal to the pixel driving circuit; in at least one circuit unit, the third fracture shielding block is connected with the first power line.

18. The display substrate according to claim 15, wherein the at least one potentiostatic signal line includes a second power line configured to provide a second power signal to the light emitting device; in at least one circuit unit, the third fracture shielding block is connected with the second power line.

19. The display substrate according to claim 1, wherein at least one circuit unit further comprises a first power supply line configured to supply a first power supply signal to the pixel driving circuit, the first power supply line functioning as the fracture shielding structure and the constant potential signal line at the same time; the orthographic projection of the first fracture on the substrate at least partially overlaps with the orthographic projection of the first power line on the substrate, and the first power line is arranged in a conductive layer on one side of the conductive layer where the first data connection line is located, which is far away from the substrate.

20. The display substrate according to claim 19, wherein the pixel driving circuit comprises at least a first transistor and a second transistor, wherein a gate electrode of the first transistor is connected to a second scanning signal line, a first electrode of the first transistor is connected to a first initial signal line, a gate electrode of the second transistor is connected to a third scanning signal line, and a first electrode of the second transistor is connected to a second electrode of the first transistor; in at least one circuit unit, the first initial signal line is disposed between the second scan signal line and the third scan signal line, and the first data link line is disposed between the first initial signal line and the third scan signal line.

21. A display device comprising the display substrate according to any one of claims 1 to 20.

22. A method for manufacturing a display substrate, wherein the display substrate comprises a plurality of circuit units, at least one first data link line extending along a first direction, and at least one second data link line extending along a second direction, the first direction and the second direction intersecting; at least one circuit unit includes a pixel driving circuit, a data signal line configured to supply a data signal to the pixel driving circuit, and a constant potential signal line configured to supply a constant potential signal to the pixel driving circuit, the data signal line being connected to the first data link line, the first data link line being connected to the second data link line; the at least one circuit unit further comprises at least one first fracture and at least one fracture shielding structure, the first fracture is arranged on the first data connecting line and cuts off the first data connecting line, and the fracture shielding structure is connected with the constant potential signal line; the preparation method comprises the following steps: