CN117979694A - Flash memory layout, flash memory and manufacturing method thereof - Google Patents

Abstract

The invention provides a flash memory layout, a flash memory and a manufacturing method thereof. The word line lead-out area is provided with word lines and word line contact holes which are distributed from bottom to top. No active region is provided under the word line in the word line extraction region. The word line leading-out area is provided with a first floating gate pattern which extends across each row of first floating gate patterns along the Y direction; and removing the control gate polysilicon layer corresponding to the pattern region of the second floating gate pattern I. In this way, in the word line leading-out region, control gates are not arranged on two sides of each row of word lines along the Y direction, so that bridging between the word lines and the control gates caused by alignment deviation of the word line contact holes in the photoetching process is fundamentally avoided. The process (alignment) window of the word line contact hole lithography can be effectively enlarged. The word line contact holes are not arranged in the group active area, so that alignment deviation of the word line contact holes in the photoetching process cannot influence the flash memory cells in the group active area.

Description

Flash memory layout, flash memory and manufacturing method thereof

Technical Field

The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a flash memory layout, a flash memory and a manufacturing method thereof.

Background

Flash has been widely used as the best choice for non-volatile memory applications due to its high density, low cost, and electrically programmable and erasable advantages. In general, floating gate type flash memories have similar original memory cells, which have a stacked gate structure including a floating gate and a control gate at least covering the floating gate. The control gate is coupled to control the storage and release of electrons in the floating gate. The erasing of the flash memory is tunneling between the floating gate and the word line, and by applying high and low voltages on the word line and the control gate, a higher potential difference and electric field strength are formed between the floating gate and the word line, and electrons stored in the floating gate tunnel through the tunneling oxide layer, so that the potential on the floating gate is changed from negative to positive, and the storage state is changed.

Along with the gradual shrinkage of the flash memory size, the overlay error window of the contact hole to the flash memory cell array is gradually reduced, and in the flash memory with 40nm, the overlay error of the contact hole to the word line becomes a bottleneck, and the overlay error window is smaller than +/-10 nm. In the case of overlay shift of the contact hole relative to the lithography of the flash memory cell array, bridging between the word line and the control gate is caused.

Disclosure of Invention

The invention aims to provide a flash memory layout, a flash memory and a manufacturing method thereof. In the word line leading-out area, control gates are not arranged on two sides of each row of word lines along the Y direction, so that bridging between the word lines and the control gates caused by alignment deviation of the word line contact holes in the photoetching process is fundamentally avoided. The process (alignment) window of the word line contact hole lithography can be effectively enlarged.

The invention provides a flash memory layout, which defines mutually perpendicular X direction and Y direction in a plane parallel to the flash memory layout, and comprises the following steps:

The active area layout layer comprises a plurality of active areas which are arranged in parallel along the X direction and extend along the Y direction and are positioned in a group of active areas;

The first floating gate layout layer comprises a plurality of first floating gate patterns which are arranged in parallel along the Y direction and extend along the X direction; the first floating gate pattern sequentially spans the word line leading-out region, the first connecting region, the group active region and the second connecting region; each first floating gate pattern corresponds to a group of isolated first control gates and second control gates;

The second floating gate layout layer comprises a second floating gate pattern I which extends across each row of the first floating gate patterns in the Y direction in the word line lead-out area; removing the control gate corresponding to the pattern area of the second floating gate layout layer;

The word line contact hole layout layer comprises word line contact holes which are distributed in the middle area of each row of the first floating gate pattern along the Y direction in the word line lead-out area; the second floating gate pattern covers all of the word line contact holes.

Further, the second floating gate layout layer further comprises a second floating gate pattern, and the second floating gate pattern extends across each row of the first floating gate patterns along the Y direction in the second connection region.

Further, a group of isolated first control gates and second control gates on the first floating gate patterns of the odd rows are led out in the second connection region; a group of isolated first control gates and second control gates on the first floating gate patterns of even rows are led out from the first connection region; or alternatively; a group of isolated first control gates and second control gates on the first floating gate patterns of the odd rows are led out from the first connection region; and a group of isolated first control gates and second control gates on the first floating gate patterns of even rows are led out from the second connection region.

Further, the second floating gate layout layer further comprises a second floating gate pattern III and a second floating gate pattern IV; the second floating gate patterns III are distributed in an interlaced manner along the Y direction in the first connecting region, and the second floating gate patterns III span the first floating gate patterns of the odd-numbered rows; the second floating gate patterns four are distributed in an interlaced manner along the Y direction in the second connection region, and the second floating gate patterns four span the first floating gate patterns of even lines.

Further, the flash memory layout further includes: a control gate contact hole layout layer; the control gate contact hole layout layer comprises a first control gate contact hole pattern and a second control gate contact hole pattern;

The control gate contact hole patterns are distributed in the Y direction in the first connection region and cross each row of the first floating gate patterns; the pattern area of the first control gate contact hole pattern comprises a plurality of first control gate contact holes distributed along the Y direction, and the first control gate contact holes are distributed on two sides of each row of the first floating gate pattern along the Y direction;

The second control gate contact hole patterns are distributed in the second connection region along the Y direction and span each row of the first floating gate patterns; the pattern area of the second control gate contact hole pattern comprises a plurality of second control gate contact holes distributed along the Y direction, and the second control gate contact holes are distributed on two sides of each row of the first floating gate pattern along the Y direction.

Further, the number of the active regions included in the group of active regions is 128 to 1024.

Further, the active region is in a straight stripe shape, and the first floating gate pattern is in a straight stripe shape.

A manufacturing method of a flash memory adopts the flash memory layout to manufacture, and the manufacturing method comprises the following steps:

providing a substrate, wherein the substrate comprises word line leading-out areas, first connecting areas, group active areas and second connecting areas which are distributed in sequence along the X direction; forming a floating gate polysilicon layer and a control gate polysilicon layer on the substrate;

patterning the control gate polysilicon layer by using a mask plate with a second floating gate layout layer; removing the control gate polysilicon layer of the second floating gate pattern region;

Patterning the control gate polysilicon layer and the floating gate polysilicon layer by using a mask plate with a first floating gate layout layer; the control gate polysilicon layer and the floating gate polysilicon layer of the first floating gate pattern region remain;

patterning the control gate polysilicon layer and the floating gate polysilicon layer by using a mask plate with a control gate contact hole layout layer, and removing the control gate polysilicon layer and the floating gate polysilicon layer outside the first floating gate pattern region and the control gate contact hole pattern region;

etching to remove the control gate polysilicon layer and the floating gate polysilicon layer in the middle area of the first floating gate pattern to form an opening, forming an isolation layer on the side wall of the opening, and filling the opening after forming the isolation layer with a word line; forming the first control gate and the second control gate on two sides of the word line by the remaining control gate polysilicon layer;

Forming an insulating layer covering the substrate, the word line, the first control gate and the second control gate; and patterning the insulating layer of the word line lead-out area by using a mask plate with a word line contact hole layout layer to form a word line contact hole positioned above the word line.

Further, the manufacturing method further comprises the following steps: and patterning the insulating layers of the first connection region and the second connection region by using a mask plate with a control gate contact hole layout layer to form a first control gate contact hole and a second control gate contact hole.

Further, the word line contact hole of the word line lead-out region, the first control gate contact hole of the first connection region, and the second control gate contact hole of the second connection region are formed in the same etching process.

The invention also provides a flash memory, which is manufactured by adopting the manufacturing method of the flash memory, and comprises the following steps:

The semiconductor device comprises a substrate, a first connecting region, a group active region and a second connecting region, wherein the substrate comprises word line leading-out regions, first connecting regions, group active regions and second connecting regions which are sequentially distributed along the X direction; the group of active areas comprise memory cells arranged in an array;

A plurality of word lines which are arranged in parallel along the Y direction and extend along the X direction are formed on the substrate; each row of the word lines spans the word line lead-out region, the first connection region, the set of active regions, and the second connection region;

a first floating gate and a first control gate which are stacked are formed on one side of the word lines in the group of active areas along the Y direction, and a second floating gate and a second control gate which are stacked are formed on the other side of the word lines in the group of active areas along the Y direction;

the two sides of the word line in the word line leading-out area along the Y direction are not provided with stacked floating gates and control gates;

An insulating layer covering the substrate, the word line, the first control gate, and the second control gate; a word line contact hole positioned above each row of word lines is formed in the insulating layer positioned at the word line leading-out area; no active region is provided under the word line within the word line extraction region.

Further, isolation layers are arranged on two sides of the word line in the Y direction, wherein the word line is located in the word line leading-out area.

Compared with the prior art, the invention has the following beneficial effects:

The invention provides a flash memory layout, a flash memory and a manufacturing method thereof. The word line lead-out area is provided with word lines and word line contact holes which are distributed from bottom to top. No active region is provided under the word line in the word line extraction region. The word line extraction region is provided with a second floating gate pattern one extending across the first floating gate pattern of each row in the Y direction. And removing the control gate polysilicon layer corresponding to the pattern region of the second floating gate pattern I. In this way, in the word line leading-out region, control gates are not arranged on two sides of each row of word lines along the Y direction, so that bridging between the word lines and the control gates caused by alignment deviation of the word line contact holes in the photoetching process is fundamentally avoided. The process (alignment) window of the word line contact hole lithography can be effectively enlarged. The word line contact holes are not arranged in the group active area, so that alignment deviation of the word line contact holes in the photoetching process cannot influence the flash memory cells in the group active area.

Drawings

FIG. 1 is a diagram illustrating a layout of a flash memory according to an embodiment of the present invention.

Fig. 2 is a schematic cross-sectional view of a first dotted line Nn along the Y-direction of a memory cell in the group active area of the flash memory in fig. 1.

Fig. 3 is a schematic cross-sectional view of a second broken line Ee of the flash memory in fig. 1 along the Y-direction at the word line lead-out area.

Fig. 4 is a schematic cross-sectional view of the flash memory before modification in the Y direction in the word line lead-out area.

Fig. 5 is a flowchart of a method for manufacturing a flash memory according to an embodiment of the present invention.

Wherein, the reference numerals are as follows:

01-word line lead-out hole; 02-word line; an L-word line lead-out region; a group A active region; b-a first connection region; a C-word line extraction region; d-a second connection region;

10-a substrate; 11-an active region; 20-a first floating gate pattern; 21-a first floating gate; 22-a second floating gate; 30-a control gate; 31-a first control gate; 32-a second control gate; 41-second floating gate pattern one; 42-a second floating gate pattern II; 43-second floating gate pattern three; 44-a second floating gate pattern four; 51-control gate contact hole pattern one; 52-a second control gate contact hole pattern; 61-word line contact holes; 62-a first control gate contact hole; 63-a second control gate contact hole; 70-word line; 81-isolating layer; 82-insulating layer.

Detailed Description

The invention is described in further detail below with reference to the drawings and the specific examples. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are not to scale precisely, but rather merely for the purpose of facilitating and clearly aiding in the description of the embodiments of the invention.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present.

Spatially relative terms, such as "under … …," "under … …," "below," "under … …," "over … …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below … …" and "under … …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

The embodiment of the invention provides a flash memory layout, which defines mutually perpendicular X direction and Y direction in a plane parallel to the flash memory layout, and comprises the following steps:

the active area layout layer comprises a plurality of active areas which are arranged in parallel along the X direction and extend along the Y direction and are positioned in the group of active areas;

The first floating gate layout layer comprises a plurality of first floating gate patterns which are arranged in parallel along the Y direction and extend along the X direction; the first floating gate pattern sequentially spans the word line leading-out region, the first connecting region, the group active region and the second connecting region; each first floating gate pattern corresponds to a group of isolated first control gates and second control gates;

The second floating gate layout layer comprises a second floating gate pattern I which extends across each row of first floating gate patterns in the Y direction in the word line lead-out area; removing the control gate corresponding to the pattern area of the second floating gate layout layer;

The word line contact hole layout layer comprises word line contact holes which are distributed in the middle area of each row of first floating gate patterns along the Y direction in a word line lead-out area; the second floating gate pattern covers all word line contact holes.

Fig. 2 is a schematic cross-sectional view of a first dotted line Nn along the Y-direction of a memory cell in the group active area a of the flash memory in fig. 1. Fig. 3 is a schematic cross-sectional view of the flash memory in fig. 1 along a second imaginary line Ee along the Y-direction at the word line lead-out area C.

Specifically, the flash memory is sequentially provided with a word line lead-out area C, a first connection area B, a group active area A and a second connection area D along the X direction. The connection region includes a first connection region B and a second connection region D located at both sides of the group active region a in the X direction. And the connecting area (also called as a strip area and a strap area) is used for leading out the control gate. The layout of the flash memory includes a plurality of group active areas a. A word line lead-out region C and a first connection region B are disposed between adjacent group active regions a, or a second connection region D is disposed between adjacent group active regions a.

The active region layout layer includes a plurality of active regions 11 arranged in parallel in the X direction and extending in the Y direction within each group of active regions a. The plurality of active regions 11 are in the shape of straight stripes. The number of active regions 11 included in each group of active regions a is 128 to 1024.

The first floating gate layout layer includes a plurality of first floating gate patterns 20 arranged in parallel in the Y direction and extending in the X direction. The width of each row of the first floating gate patterns 20 in the Y direction is m. The first floating gate pattern 20 is in the shape of a straight bar, for example. The first floating gate pattern 20 spans the word line drawing region C, the first connection region B, the group active region a, and the second connection region D; and the first floating gate pattern 20 of each row is disconnected in the word line lead-out area C and the second connection area D; i.e. the first floating gate pattern 20 between adjacent two groups of active regions a is disconnected. Each first floating gate pattern 20 corresponds to a set of isolated first and second control gates 31 and 32 extending in the X-direction.

The second floating gate layout layer includes a second floating gate pattern one 41, a second floating gate pattern two 42, a second floating gate pattern three 43, and a second floating gate pattern four 44. Illustratively, the second floating gate pattern one 41, the second floating gate pattern two 42, the second floating gate pattern three 43, and the second floating gate pattern four 44 are all in the shape of straight bars. And removing the control gate corresponding to the pattern area of the second floating gate layout layer. The second floating gate pattern one 41 extends across each row of the first floating gate pattern 20 in the Y direction at the word line extraction region C. The second floating gate pattern two 42 extends across each row of the first floating gate pattern 20 in the Y direction at the second connection region D. The second floating gate patterns three 43 are arranged in the first connection region B in an interlaced manner in the Y direction, and the second floating gate patterns three 43 span the first floating gate patterns 20 of the odd numbered rows. The second floating gate patterns four 44 are arranged in an interlaced manner in the Y direction in the second connection region D, and the second floating gate patterns four 44 span the first floating gate patterns 20 of the even numbered rows.

The flash memory layout further includes: and a control gate contact hole layout layer. The control gate contact hole layout layer comprises a first control gate contact hole pattern 51 and a second control gate contact hole pattern 52. The first control gate contact hole patterns 51 are distributed in the Y direction in the first connection region B, and the first control gate contact hole patterns 51 span each row of the first floating gate patterns 20. The control gate contact hole pattern-51 pattern region includes a plurality of first control gate contact holes 62 distributed along the Y direction, and each row of first floating gate patterns 20 has first control gate contact holes 62 distributed along both sides of the Y direction.

The second control gate contact hole patterns 52 are distributed in the second connection region along the Y direction, and the second control gate contact hole patterns 52 span each row of the first floating gate patterns 20. The second pattern region of the second control gate contact hole pattern 52 includes a plurality of second control gate contact holes 63 distributed along the Y direction, and the second control gate contact holes 63 are distributed on both sides of each row of the first floating gate pattern 20 along the Y direction. The control gate polysilicon layer remains in the areas of the first 51 and second 52 control gate contact hole patterns. The first control gate contact hole pattern 51 covers the second floating gate pattern three 43 and the first control gate contact hole 62. The second control gate contact hole pattern 52 covers the second floating gate pattern second 42, the second floating gate pattern fourth 44, and the second control gate contact hole 63.

The word line contact hole layout layer includes word line contact holes 61 distributed in the middle area of each row of the first floating gate patterns 20 in the Y direction at the word line lead-out area C. The second floating gate pattern one 41 covers all the word line contact holes 61.

Fig. 4 is a schematic cross-sectional view of the flash memory before modification in the Y direction in the word line lead-out area L.

The word line leading-out area L of the flash memory before improvement is distributed with a substrate 10, word lines 02 and word line leading-out holes 01 from bottom to top, and conductive layers are filled in the word line leading-out holes 01 to lead out the word lines 02. Control gates are arranged on two sides of a word line 02 in the Y direction in the word line leading-out area L, an isolation layer 81 is arranged between the word line 02 and the first control gate 31 and between the word line 02 and the second control gate 32, the distance from the word line leading-out hole 01 to the isolation layer 81 in the Y direction is less than 10nm, and the structure of the isolation layer 81 can be damaged under the condition of overlay offset, so that bridging between the word line 02 and the control gates occurs under high voltage.

Compared with the flash memory before improvement in fig. 4, in the flash memory layout of the embodiment of the invention, the word line lead-out area C is distributed with the substrate 10, the word line 70 and the word line contact hole 61 from bottom to top, and the word line contact hole 61 is filled with the conductive layer to lead out the word line 70. No active region is provided under the word line 70 within the word line extraction region C. The word line lead-out area C is provided with a second floating gate pattern I41, and the second floating gate pattern I41 extends across each row of the first floating gate patterns 20 along the Y direction; the control gate polysilicon layer corresponding to the pattern region of the second floating gate pattern one 41 is removed. In this way, in the word line lead-out region C, the control gates are not disposed on both sides of the word line 70 along the Y direction, so that bridging between the word line 70 and the control gates due to overlay misalignment of the word line contact hole 61 in the photolithography process is fundamentally avoided. The process (alignment) window of the photolithography of the word line contact hole 61 can be effectively enlarged. In the group active region a, the word lines 70 are provided with stacked floating gates and control gates on both sides in the Y direction, and the word line contact holes 61 are not provided in the group active region a, so that alignment deviation of the word line contact holes 61 in the photolithography process does not affect the flash memory cells in the group active region a.

Fig. 5 is a flowchart of a method for manufacturing a flash memory according to an embodiment of the invention. Referring to fig. 1 to 3 and 5, the method for manufacturing the flash memory includes the following steps:

step S1, providing a substrate, wherein the substrate comprises word line leading-out areas, first connecting areas, group active areas and second connecting areas which are distributed in sequence along the X direction; forming a floating gate polysilicon layer and a control gate polysilicon layer on a substrate;

Step S2, patterning the control gate polysilicon layer by using a mask plate with a second floating gate layout layer; removing the control gate polysilicon layer of the second floating gate pattern region;

step S3, patterning the control gate polysilicon layer and the floating gate polysilicon layer by using a mask plate with a first floating gate layout layer; the control gate polysilicon layer and the floating gate polysilicon layer of the first floating gate pattern region remain;

Step S4, patterning the control gate polysilicon layer and the floating gate polysilicon layer by using a mask plate with a control gate contact hole layout layer, and removing the control gate polysilicon layer and the floating gate polysilicon layer outside the first floating gate pattern region and the control gate contact hole pattern region;

S5, etching to remove the control gate polysilicon layer and the floating gate polysilicon layer in the middle area of the first floating gate pattern to form an opening, forming an isolation layer on the side wall of the opening, and filling the opening after forming the isolation layer with a word line; the rest control grid polycrystalline silicon layer forms a first control grid and a second control grid which are positioned at two sides of the word line;

S6, forming an insulating layer covering the substrate, the word line, the first control gate and the second control gate; and patterning the insulating layer of the word line lead-out area by using a mask plate with a word line contact hole layout layer to form a word line contact hole positioned above the word line.

The following describes the method for manufacturing the flash memory provided by the invention in detail.

In step S1, a substrate 10 is provided, the substrate 10 including a word line lead-out region C, a first connection region B, a group active region a, and a second connection region D sequentially distributed in the X direction; a floating gate polysilicon layer and a control gate polysilicon layer are formed on the substrate 10. The first connecting region B and the second connecting region D are used for leading out control gates formed subsequently in a staggered mode row by row. The step further includes performing ion implantation on the substrate 10 by using a mask plate made of the active region layout layer (or a mask plate having the active region layout layer) to form a plurality of active regions 11. Illustratively, the number of active regions 11 included in each group of active regions a is 128 to 1024. The active region layout layer comprises a plurality of active regions 11 which are arranged in parallel along the X direction and extend along the Y direction and are positioned in the group active region A, and the plurality of active regions 11 are in a straight strip shape.

A floating gate polysilicon layer and a control gate polysilicon layer are formed on the substrate 10. The floating gate polysilicon layer then eventually forms a first floating gate 21 and a second floating gate 22 on either side of the word line 70. The control gate polysilicon layer then eventually forms a first control gate 31 and a second control gate 32 on either side of the word line 70. The first control gate 31 is stacked with the first floating gate 21, and the second control gate 32 is stacked with the second floating gate 22. Of course, a dielectric layer may be formed between the floating gate polysilicon layer and the control gate polysilicon layer, and a gate oxide layer may be formed on the substrate prior to forming the floating gate polysilicon layer.

In step S2, the control gate polysilicon layer is patterned using a mask having a second floating gate layout layer. The second floating gate layout layer comprises a second floating gate pattern I41, a second floating gate pattern II 42, a second floating gate pattern III 43 and a second floating gate pattern IV 44; and exposing and developing through a mask plate with the second floating gate layout layer to remove the control gate polysilicon layer of the second floating gate pattern coverage area, namely removing the control gate polysilicon layer corresponding to the pattern area of the second floating gate layout layer. The floating gate polysilicon layer is only on the group active region A, and the circumference of the group active region A is STI (shallow trench isolation). The floating gate polysilicon layer on the STI is removed when the active area is being formed. The second floating gate pattern is arranged on the STI (shallow trench isolation), and the word line leading-out area C, the first connecting area B and the second connecting area D are all arranged on the STI, so that the control gate polysilicon layer of the pattern area of the second floating gate pattern layer is removed in the manufacturing process.

In step S3, patterning the control gate polysilicon layer and the floating gate polysilicon layer by using a mask plate with a first floating gate layout layer; the control gate polysilicon layer and the floating gate polysilicon layer of the first floating gate pattern region remain.

The first floating gate layout layer includes a plurality of first floating gate patterns 20 arranged in parallel in the Y direction and extending in the X direction. Illustratively, the plurality of first floating gate patterns 20 are in the shape of straight bars. The first floating gate pattern 20 spans the word line drawing region C, the first connection region B, the group active region a, and the second connection region D; and the first floating gate pattern 20 of each row is disconnected in the word line lead-out area C and the second connection area D; i.e. the first floating gate pattern 20 between two adjacent groups of active regions a is disconnected; each first floating gate pattern 20 corresponds to a set of isolated first and second control gates 31 and 32 extending in the X-direction.

In step S4, patterning the control gate polysilicon layer and the floating gate polysilicon layer by using a mask plate with a control gate contact hole layout layer; and removing the control gate polysilicon layer and the floating gate polysilicon layer outside the first floating gate pattern region and the control gate contact hole pattern region.

The control gate contact hole layout layer comprises a first control gate contact hole pattern 51 and a second control gate contact hole pattern 52. The first control gate contact hole patterns 51 are distributed in the Y direction in the first connection region B, and the first control gate contact hole patterns 51 span each row of the first floating gate patterns 20. The second control gate contact hole patterns 52 are distributed in the Y direction in the second connection region D, and the second control gate contact hole patterns 52 span each row of the first floating gate patterns 20. The control gate polysilicon layer and the floating gate polysilicon layer outside the first floating gate pattern 20 area, the first control gate contact hole pattern 51 area and the second control gate contact hole pattern 52 area can be etched and removed until the substrate is exposed by exposing and developing the mask plate with the control gate contact hole pattern layer to protect the control gate polysilicon layer in the control gate contact hole pattern coverage area. After step S4, the entire width m of the first floating gate pattern 20 is in the range of the stacked bottom-up floating gate polysilicon layer and control gate polysilicon layer.

Step S5, etching and removing the control gate polysilicon layer and the floating gate polysilicon layer in the middle area of the first floating gate pattern 20 to form an opening, forming an isolation layer 81 on the side wall in the opening, and filling the opening after forming the isolation layer 81 with the word line 70; the remaining control gate polysilicon layer forms a first control gate 31 and a second control gate 32 on either side of the word line 70. The first control gate 31 is stacked with the first floating gate 21, and the second control gate 32 is stacked with the second floating gate 22. Thus, there is a corresponding set of isolated first and second control gates 31, 32 on each first floating gate pattern 20.

Each row of the first floating gate pattern 20 regions is formed with a first control gate 31 and a second control gate 32 isolated from each other. In fig. 1, to illustrate the different emphasis, a first control gate 31 and a second control gate 32 are shown isolated from each other only on a part of the first floating gate pattern 20. In step S5, a sidewall may be formed above the first control gate 31 and the second control gate 32, and the sidewall 60 is used as a hard mask, and a non-exposure process is used to form an opening, so that the mask in the flash memory layout is not used.

Step S7 of forming an insulating layer 82 covering the substrate 10, the word line 70, the first control gate 31, and the second control gate 32; the insulating layer 82 of the word line lead-out region C is patterned using a reticle having a word line contact hole layout layer to form the word line contact holes 61 over the word lines 70. The word line contact hole 61 of the word line lead-out region C, the first control gate contact hole 62 of the first connection region B, and the second control gate contact hole 63 of the second connection region D may be formed in the same etching process.

The first connection region B and the second connection region D are used for leading out the control gates in a staggered mode row by row. For example, in fig. 1, from top to bottom, the first floating gate patterns 20 (corresponding to forming control gates) of the first row are disconnected by the second floating gate patterns three 43 in the first connection region B, and the control gates of the first row are led out from the second control gate contact holes 63 of the second connection region D. The first floating gate pattern 20 (corresponding to forming a control gate) of the second row is disconnected from the second floating gate pattern four 44 in the second connection region D, and the control gates of the second row are led out from the first control gate contact hole 62 of the first connection region B.

It will be appreciated that other masks or other fabrication steps may be included between the steps described above, as the invention is not limited in this regard.

The invention also provides a flash memory, which is manufactured by adopting the manufacturing method of the flash memory. The flash memory includes:

a substrate 10, the substrate 10 including a word line lead-out region C, a first connection region B, a group active region a, and a second connection region D sequentially distributed in an X direction; the group active area A comprises memory cells arranged in an array;

a plurality of word lines 70 arranged in parallel in the Y direction and extending in the X direction are formed on the substrate 10; each row of word lines 70 spans the word line lead-out region C, the first connection region B, the group active region a, and the second connection region D;

the word line 70 located in the group active region a is formed with the first floating gate 21 and the first control gate 31 stacked on one side in the Y direction, and the word line 70 located in the group active region a is formed with the second floating gate 22 and the second control gate 32 stacked on the other side in the Y direction;

The word line 70 located in the word line extraction region C is provided with no stacked floating gate and control gate on both sides in the Y direction;

An insulating layer 82, the insulating layer 82 covering the substrate 10, the word line 70, the first control gate and 31 the second control gate 32; the insulating layer 82 located in the word line lead-out region C has formed therein the word line contact holes 61 located above each row of word lines 70; no active region is provided under the word line 70 within the word line extraction region C.

The word lines 70 located at the word line extraction region C are provided with isolation layers 81 on both sides in the Y direction.

In summary, in the flash memory layout, the flash memory and the manufacturing method thereof provided by the invention, the word line lead-out area is distributed with the substrate, the word lines and the word line contact holes from bottom to top, and the word line contact holes are filled with the conductive layers to lead out the word lines. No active region is provided under the word line in the word line extraction region. The word line leading-out area is provided with a first floating gate pattern which extends across each row of the first floating gate patterns along the Y direction; and removing the control gate polysilicon layer corresponding to the pattern region of the second floating gate pattern I. In this way, in the word line leading-out region, the control gates are not arranged on two sides of the word line along the Y direction, so that bridging between the word line and the control gates caused by alignment deviation of the word line contact holes in the photoetching process is fundamentally avoided. The process (alignment) window of the word line contact hole lithography can be effectively enlarged. In the group active region, the two sides of the word line along the Y direction are provided with stacked floating gates and control gates, and the word line contact holes are not arranged in the group active region, so that alignment deviation of the word line contact holes in a photoetching process can not influence flash memory storage units in the group active region.

In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the method disclosed in the embodiment, the description is relatively simple since it corresponds to the device disclosed in the embodiment, and the relevant points refer to the description of the method section.

The foregoing description is only illustrative of the preferred embodiments of the present invention, and is not intended to limit the scope of the claims, and any person skilled in the art may make any possible variations and modifications to the technical solution of the present invention using the method and technical content disclosed above without departing from the spirit and scope of the invention, so any simple modification, equivalent variation and modification made to the above embodiments according to the technical matter of the present invention fall within the scope of the technical solution of the present invention.

Claims (12)

1. A flash memory layout defining mutually perpendicular X-and Y-directions in a plane parallel to the flash memory layout, comprising:

The active area layout layer comprises a plurality of active areas which are arranged in parallel along the X direction and extend along the Y direction and are positioned in a group of active areas;

The first floating gate layout layer comprises a plurality of first floating gate patterns which are arranged in parallel along the Y direction and extend along the X direction; the first floating gate pattern sequentially spans the word line leading-out region, the first connecting region, the group active region and the second connecting region; each first floating gate pattern corresponds to a group of isolated first control gates and second control gates;

The second floating gate layout layer comprises a second floating gate pattern I which extends across each row of the first floating gate patterns in the Y direction in the word line lead-out area; removing the control gate corresponding to the pattern area of the second floating gate layout layer;

The word line contact hole layout layer comprises word line contact holes which are distributed in the middle area of each row of the first floating gate pattern along the Y direction in the word line lead-out area; the second floating gate pattern covers all of the word line contact holes.

2. The flash memory layout of claim 1 wherein,

The second floating gate layout layer further comprises a second floating gate pattern II, and the second floating gate pattern II extends across each row of the first floating gate patterns along the Y direction in the second connection region.

3. The flash memory layout of claim 1 wherein,

A group of isolated first control gates and second control gates on the first floating gate patterns of the odd rows are led out from the second connection region; a group of isolated first control gates and second control gates on the first floating gate patterns of even rows are led out from the first connection region; or alternatively;

a group of isolated first control gates and second control gates on the first floating gate patterns of the odd rows are led out from the first connection region; and a group of isolated first control gates and second control gates on the first floating gate patterns of even rows are led out from the second connection region.

4. The flash memory layout of claim 3, wherein,

The second floating gate layout layer further comprises a second floating gate pattern III and a second floating gate pattern IV;

the second floating gate patterns III are distributed in an interlaced manner along the Y direction in the first connecting region, and the second floating gate patterns III span the first floating gate patterns of the odd-numbered rows;

The second floating gate patterns four are distributed in an interlaced manner along the Y direction in the second connection region, and the second floating gate patterns four span the first floating gate patterns of even lines.

5. The flash memory layout of claim 3, wherein,

The flash memory layout further includes: a control gate contact hole layout layer; the control gate contact hole layout layer comprises a first control gate contact hole pattern and a second control gate contact hole pattern;

The control gate contact hole patterns are distributed in the Y direction in the first connection region and cross each row of the first floating gate patterns; the pattern area of the first control gate contact hole pattern comprises a plurality of first control gate contact holes distributed along the Y direction, and the first control gate contact holes are distributed on two sides of each row of the first floating gate pattern along the Y direction;

The second control gate contact hole patterns are distributed in the second connection region along the Y direction and span each row of the first floating gate patterns; the pattern area of the second control gate contact hole pattern comprises a plurality of second control gate contact holes distributed along the Y direction, and the second control gate contact holes are distributed on two sides of each row of the first floating gate pattern along the Y direction.

6. The flash memory layout of claim 1 wherein the number of active regions included in the set of active regions is 128 to 1024.

7. The flash memory layout of claim 1 wherein the active region is in the shape of a straight stripe and the first floating gate pattern is in the shape of a straight stripe.

8. A method for manufacturing a flash memory, characterized in that the flash memory layout according to any one of claims 1 to 7 is used for manufacturing, the manufacturing method comprising:

providing a substrate, wherein the substrate comprises word line leading-out areas, first connecting areas, group active areas and second connecting areas which are distributed in sequence along the X direction; forming a floating gate polysilicon layer and a control gate polysilicon layer on the substrate;

patterning the control gate polysilicon layer by using a mask plate with a second floating gate layout layer; removing the control gate polysilicon layer of the second floating gate pattern region;

Patterning the control gate polysilicon layer and the floating gate polysilicon layer by using a mask plate with a first floating gate layout layer; the control gate polysilicon layer and the floating gate polysilicon layer of the first floating gate pattern region remain;

patterning the control gate polysilicon layer and the floating gate polysilicon layer by using a mask plate with a control gate contact hole layout layer, and removing the control gate polysilicon layer and the floating gate polysilicon layer outside the first floating gate pattern region and the control gate contact hole pattern region;

etching to remove the control gate polysilicon layer and the floating gate polysilicon layer in the middle area of the first floating gate pattern to form an opening, forming an isolation layer on the side wall of the opening, and filling the opening after forming the isolation layer with a word line; forming the first control gate and the second control gate on two sides of the word line by the remaining control gate polysilicon layer;

Forming an insulating layer covering the substrate, the word line, the first control gate and the second control gate; and patterning the insulating layer of the word line lead-out area by using a mask plate with a word line contact hole layout layer to form a word line contact hole positioned above the word line.

9. The method for manufacturing a flash memory according to claim 8, wherein,

The manufacturing method further comprises the following steps: and patterning the insulating layers of the first connection region and the second connection region by using a mask plate with a control gate contact hole layout layer to form a first control gate contact hole and a second control gate contact hole.

10. The method for manufacturing a flash memory according to claim 9, wherein,

The word line contact hole of the word line lead-out region, the first control gate contact hole of the first connection region, and the second control gate contact hole of the second connection region are formed in the same etching process.

11. A flash memory device manufactured by the method of any one of claims 8 to 10, comprising:

The semiconductor device comprises a substrate, a first connecting region, a group active region and a second connecting region, wherein the substrate comprises word line leading-out regions, first connecting regions, group active regions and second connecting regions which are sequentially distributed along the X direction; the group of active areas comprise memory cells arranged in an array;

A plurality of word lines which are arranged in parallel along the Y direction and extend along the X direction are formed on the substrate; each row of the word lines spans the word line lead-out region, the first connection region, the set of active regions, and the second connection region;

a first floating gate and a first control gate which are stacked are formed on one side of the word lines in the group of active areas along the Y direction, and a second floating gate and a second control gate which are stacked are formed on the other side of the word lines in the group of active areas along the Y direction;

the two sides of the word line in the word line leading-out area along the Y direction are not provided with stacked floating gates and control gates;

An insulating layer covering the substrate, the word line, the first control gate, and the second control gate; a word line contact hole positioned above each row of word lines is formed in the insulating layer positioned at the word line leading-out area; no active region is provided under the word line within the word line extraction region.

12. The flash memory of claim 11, wherein,

And isolation layers are arranged on two sides of the word line in the Y direction.