CN117976716A

CN117976716A - Semiconductor device with a semiconductor layer having a plurality of semiconductor layers

Info

Publication number: CN117976716A
Application number: CN202410038230.0A
Authority: CN
Inventors: 蔡俊雄; 林佑明; 游国丰; 林裕庭; 陈明德; 黄诣琇
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2023-01-10
Filing date: 2024-01-10
Publication date: 2024-05-03

Abstract

A semiconductor device includes: a stack of nanostructure channels over a substrate; a gate structure surrounding the stack; and source/drain regions on the substrate. The source/drain regions include: a first epitaxial layer in direct contact with the channel; and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a higher germanium concentration than the first epitaxial layer. The semiconductor device further includes a bottom isolation structure between the source/drain region and the substrate, the bottom isolation structure being a dielectric layer in direct contact with the source/drain region.

Description

Semiconductor device with a semiconductor layer having a plurality of semiconductor layers

Technical Field

Embodiments of the present invention relate to semiconductor devices.

Background

The Integrated Circuit (IC) industry has experienced an exponential growth. Technological advances in IC materials and design have resulted in several generations of ICs, each generation of circuitry being smaller and more complex than the previous generation. During the evolution of ICs, the functional density (i.e., the number of interconnected devices per chip area) has generally increased while the geometry (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. Such a downscaling process generally provides benefits by improving production efficiency and reducing associated costs. This scaling down also increases the complexity of IC processing and fabrication.

Disclosure of Invention

Some embodiments of the present invention provide a semiconductor device including: a stack of nanostructure channels over a substrate; a gate structure surrounding the stack; a source/drain region on the substrate, the source/drain region comprising: a first epitaxial layer in direct contact with the nanostructure channel; and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a higher germanium concentration than the first epitaxial layer; and a bottom isolation structure between the source/drain region and the substrate, the bottom isolation structure being a dielectric layer in direct contact with the source/drain region.

Further embodiments of the present invention provide a semiconductor device including: a semiconductor substrate; a first semiconductor channel over the semiconductor substrate; a second semiconductor channel over the first semiconductor channel; a gate structure surrounding the first semiconductor channel and the second semiconductor channel; a first internal spacer abutting a lower surface of the second semiconductor channel, an upper surface of the first semiconductor channel, and a first sidewall surface of the gate structure; a second internal spacer abutting a lower surface of the first semiconductor channel, an upper surface of the semiconductor substrate, and a second sidewall surface of the gate structure; a recess in the semiconductor substrate; a liner layer in the recess, the liner layer having an upper surface substantially flush with an upper surface of the semiconductor substrate, the liner layer being of the same material as the semiconductor substrate; a bottom isolation structure on the liner layer and abutting a sidewall of the second inner spacer; and source/drain regions located on the bottom isolation structure and physically isolated from the semiconductor substrate by the bottom isolation structure.

Still further embodiments of the present invention provide a semiconductor device including: a substrate; an N-type transistor on the substrate, the N-type transistor comprising: a first stack of first nanostructure channels; a bottom isolation structure; and a first source/drain region in direct contact with the first nanostructure channel and the bottom isolation structure, the first source/drain region being physically isolated from the substrate by the bottom isolation structure; and a P-type transistor on the substrate, the P-type transistor comprising: a second stack of second nanostructure channels; and a second source/drain region in direct contact with the second nanostructure channel and the substrate.

Drawings

Aspects of the disclosure may be best understood from the following detailed description when read in connection with the accompanying drawings. It is noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A and 1B are schematic cross-sectional side views of portions of an IC device fabricated in accordance with an embodiment of the present disclosure.

Fig. 2A-17 are views of an IC device at various stages of manufacture in accordance with an embodiment of the present disclosure.

Fig. 18A-19F are views of an IC device according to aspects of the present disclosure.

Fig. 20 is a flowchart illustrating a method of manufacturing a semiconductor device according to aspects of the present disclosure.

Fig. 21 is a diagram of an IC device in accordance with various aspects of the present disclosure.

Detailed Description

The following disclosure provides many different embodiments, or examples, of the different components used to implement the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Moreover, spatially relative terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The present disclosure relates generally to semiconductor devices, and more particularly to Field Effect Transistors (FETs), such as planar FETs, three-dimensional fin line FETs (finfets), or nanostructure devices. Examples of nanostructure devices include full Gate (GAA) devices, nanoflake FETs (NSFETs), nanowire FETs (NWFETs), and the like. In prior art nodes, scaling may result in difficulty in forming contacts and vias to the gate, source and drain of the FET.

Dual flexible bottom insulators (flexible bottominsulator, FBI) are typically designed to be placed at the bottom of the N/P Metal Oxide Semiconductor (MOS) source/drain (S/D) of a nanostructured transistor, such as a full-gate-all-around (GAA) transistor. The dual FBI structure can prevent bottom parasitic transistor leakage while also reducing parasitic capacitance (e.g., effective capacitance Ceff), which is advantageous for improved device (e.g., ring oscillator) performance. In some GAA transistor structures, a germanium-free epitaxial layer (e.g., si: as or Si: P) is formed in the NFET source/drain regions, without using an FBI structure.

By using a dual FBI structure in the GAA transistor, the compressive stressor of a germanium-containing epitaxial layer (e.g., siGe: P or SiGe: as) in the source/drain regions of an N-type field effect transistor (NFET) can become a Sidewall (SW) deposited predominantly film. Sidewall deposition compressive stressors can create tensile stresses on the NFET silicon nanoplatelets, which can induce corresponding tensile strain in the Si nanoplatelets, which can increase NFET channel carrier mobility. A wide range of tensile stress adjustment can be achieved for the N-type channel. The Flexible Bottom Isolation (FBI) method eliminates Si substrate to Ge lattice mismatch.

The nanostructure transistor structure may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithographic processes, including a double patterning process or a multiple patterning process. Typically, a double patterning process or a multiple patterning process combines a lithographic process and a self-aligned process, allowing for the creation of patterns with smaller pitches than those obtainable using a single direct lithographic process, for example. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. Spacers are formed beside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers may then be used to pattern the nanostructure transistor structure.

Fig. 1A and 1B illustrate schematic cross-sectional side views of portions of IC devices 10A, 10B fabricated in accordance with embodiments of the present disclosure, wherein IC devices 10A, 10B include nanostructure devices 20A, 20B. To simplify the illustration, certain components may be intentionally removed from the views of fig. 1A and 1B.

Fig. 1A shows a portion of an IC device 10A that includes nanostructure devices 20A, 20B. In some embodiments, the nanostructure devices 20A, 20B may include at least an N-type FET (NFET), a P-type FET (PFET), or both. IC device 10A may include transistors having different threshold voltages based on the function of the transistor in the IC device. For example, input/output (IO) transistors typically have the highest threshold voltage, core logic transistors typically have the lowest threshold voltage, and a third threshold voltage between the threshold voltage of the IO transistor and the threshold voltage of the core logic transistor may also be employed for some other functional transistors, such as Static Random Access Memory (SRAM) transistors. Some circuit blocks within IC device 10A may include two or more NFETs and/or PFETs having two or more different threshold voltages.

Referring to fig. 1A, nanostructure devices 20A, 20B are formed over and/or in substrate 110, and nanostructure devices 20A, 20B generally include a gate structure 200 that spans and/or surrounds semiconductor channels 22A, 22B, 22C, alternatively referred to as "nanostructures", over semiconductor fins 32 that protrude from and are separated by isolation structures (e.g., shallow trench isolation structures; not shown). The channels 22A-22C are contiguous with respective source/drain regions 82. Each gate structure 200 controls the flow of current between the source/drain regions 82 through the channels 22A-22C. Trenches 22A-22C are optionally located over fin 32. In some embodiments, fins 32 and substrate 110 are absent, such as when fins 32 and substrate 110 are removed in a process of forming backside interconnect structures (e.g., including backside power rails). The source/drain regions may refer to sources or drains, either individually or collectively depending on the context.

The channels 22A-22C comprise a semiconductor material, for example silicon or a silicon compound such as silicon germanium or the like. In some embodiments, fin structure 32 comprises silicon. The channels 22A-22C are nanostructures (e.g., having dimensions in the range of a few nanometers) and may also each have an elongated shape and extend in the X-direction. In some embodiments, channels 22A-22C each have a Nanowire (NW) shape, a Nanoplatelet (NS) shape, a Nanotube (NT) shape, or other suitable nanoscale shape. The cross-sectional profile of channels 22A-22C may be rectangular, spherical, square, circular, oval, hexagonal, or a combination thereof.

In some embodiments, the lengths of the channels 22A-22C (e.g., measured in the X-axis direction) may be different from one another, for example, due to tapering during the fin etching process. In some embodiments, the length of channel 22A may be less than the length of channel 22B, and the length of channel 22B may be less than the length of channel 22C. The channels 22A-22C may not each have a uniform thickness, for example, due to a channel trimming process for expanding the spacing between the channels 22A-22C (e.g., measured in the Z-direction) to improve the gate structure fabrication process window. For example, the middle portion of each channel 22A-22C may be thinner than the two ends of each channel 22A-22C. Such shapes may be collectively referred to as "dog bone" shapes. In fig. 1A and 1B, the ends of channels 22A-22C are tapered and narrower than the middle portions of channels 22A-22C.

In some embodiments, the spacing between adjacent pairs of channels 22A-22C (e.g., between channel 22B and channel 22A or channel 22C) is in a range between about 8 nanometers (nm) and about 12 nm. In some embodiments, the thickness of each of the channels 22A-22C (e.g., measured in the Z direction) is in a range between about 5nm and about 8nm. In some embodiments, the width of each of the channels 22A-22C (e.g., measured in the Y-axis direction orthogonal to the X-Z plane, not shown in fig. 1A and 1B) is at least about 8nm.

Gate structure 200 is disposed over channels 22A-22C and between channels 22A-22C, respectively. In some embodiments, gate structure 200 is disposed over channels 22A-22C and between channels 22A-22C, channels 22A-22C being silicon channels for N-type devices or silicon germanium channels for P-type devices. In some embodiments, the gate structure 200 includes an Interface Layer (IL) 210, one or more gate dielectric layers 600, one or more work function adjustment layers 900, and a metal fill layer 290, which are shown and described in more detail with reference to fig. 17.

The source/drain regions 82 may include SiB, siGe, siGeB and may include dopants, such as Ge, sb, B, and the like. In some embodiments, the source/drain regions 82 include silicon phosphorus (SiP; si: P), silicon arsenic (SiAs, si: as), and the like. In some embodiments, the source/drain regions 82 have a width (e.g., in the Y-axis direction) in the range of about 0.5nm to about 100 nm. In some embodiments, the height (e.g., in the Z-axis direction) of the source/drain regions 82 is in the range of about 0.1nm to about 100 nm. The height of the source/drain regions 82 may be measured from the interface between the respective source/drain regions 82 and the dielectric layer 800 (or "FBI layer 800" or "bottom isolation structure 800") on which the source/drain regions 82 are disposed to the top of the source/drain regions 82.

The nanostructure devices 20A, 20B may include gate spacers or "sidewall" spacers 41 and internal spacers 74 disposed on sidewalls of the gate dielectric layer 600 and IL 210. An inner spacer 74 is also disposed between channels 22A-22C. The sidewall spacers 41 and the inner spacers 74 may comprise a dielectric material, for example a low-k material such as SiOCN, siON, siN, siCN or SiOC. In some embodiments, sidewall spacers 41 may include one or more spacer layers. For example, as shown in fig. 1A and 1B, the sidewall spacer 41 includes two spacer layers. In some embodiments, the thickness of the inner spacer 74 (e.g., in the X-axis direction) is in the range of about 3nm to about 10 nm. In some embodiments, the thickness of the sidewall spacers 41 (e.g., in the X-axis direction) is in the range of about 3nm to about 10 nm.

The nanostructure devices 20A, 20B include a bottom isolation structure 800 located under the source/drain regions 82. The bottom isolation structure 800 is formed at the bottom of the source/drain region 82 cavity and facilitates reducing the volume of the source/drain region 82, which reduces the effective capacitance. The bottom isolation structure 800 is or includes SiN, siCN, siCON, siOC, siC, siO or the like. The shape of the bottom isolation structure 800 may be horizontal I-shaped, bowl-shaped, disk-shaped, U-shaped, V-shaped, etc., and the shape of the bottom isolation structure 800 may be selected by an etching process used to form the source/drain regions 82. The bottom isolation structure 800 may have a thickness in the range of about 1nm to about 5 nm. The bottom isolation structure 800 may be formed by one or more conformal film deposition processes (e.g., plasma enhanced atomic layer deposition or "PEALD") followed by a film treatment (e.g., etch back), and the bottom isolation structure 800 may be a conformal thin film that inherits the shape of the underlying structure on which the bottom isolation structure 800 is formed. Film deposition may be performed by a cyclic PEALD process using a reactive gas such as Dichlorosilane (DCS) and NH ₃/Ar plasma. Film processing (e.g., etching) may be performed by an Ar/N ₂ plasma.

In fig. 1A, a liner or "L0" layer 84 may optionally be disposed between the bottom isolation structure 800 and the substrate 110, the fin 32, or the substrate 110 and the fin 32. In some embodiments, liner layer 84 may be a silicon layer. In fig. 1B, pad layer 84 is absent. When pad layer 84 is present, bottom isolation structure 800 may be a substantially horizontal lamina, as shown in fig. 1A. When liner layer 84 is not present, bottom isolation structure 800 may have a U-shaped or V-shaped profile, as shown in fig. 1B, and may be in contact with fin 32.

The source/drain regions 82 may include one or more epitaxial regions, such as a first epitaxial region 82A and a second epitaxial region 82B. The first epitaxial region 82A may be referred to as a first epitaxial layer or "L1" layer 82A, and the first epitaxial region 82A may include a first epitaxial sub-layer 82A1 in contact with the channels 22A-22B and a second epitaxial sub-layer 82A2 on the first epitaxial sub-layer 82A 1. The second epitaxial region 82B may also be referred to as a second epitaxial layer or "L2" layer 82B, and the second epitaxial region 82B is in contact with the second epitaxial sub-layer 82A2. Seam 810 may be present in second epitaxial layer 82B. In some embodiments, seam or void 810 has a width in the X-axis direction of less than 1 nm.

Each of the first epitaxial sub-layer 82A1, the second epitaxial sub-layer 82A2, and the second epitaxial layer 82B may be a germanium-containing epitaxial layer for an NMOS transistor formed in the S/D trench. The sequentially compressed SiGe: P or SiGe: as deposition allows the epitaxial growth mechanism to be Sidewall (SW) growth rather than bottom-up growth (e.g., growth from fin 32 or substrate 110). The bottom isolation structure 800 is provided at the bottom of the S/D trench, and thus the SiGe: P or SiGe: as film formed at the bottom of the S/D trench may become amorphous and be removed during the etching process of selective epitaxial growth. The sidewalls SiGe-P or SiGe-As become crystalline and remain on the sidewalls, e.g., on the channels 22A-22B and the inner spacers 74. The germanium-containing epitaxial layer for the NMOS may be formed by a plurality of selective epitaxial growth processes (or so-called "cyclical deposition and etching processes") which may include deposition operations and etching operations performed alternately or simultaneously. For SW-based grown SiGe-to-P or SiGe-to-As epitaxial films, the SW-grown SiGe-to-P or SiGe-to-As films may impart tensile strain to the Si nanoplatelets 22A-22C rather than compressive strain, although the epitaxial films still generate compressive stress. In some embodiments, the tensile strain on the nanoplatelets 22B is greater than the tensile strain on the nanoplatelets 22A, 22C. That is, the nanoplatelets 22A, 22C on the periphery of the vertical stack (e.g., closer to the top or bottom) may have a lower tensile strain than the nanoplatelets 22B in the middle of the vertical stack. For example, the nanoplatelets located at the center of the vertical stack may have the highest tensile strain, and the tensile strain may decrease with increasing distance from the center, where "center" refers to the center of the vertical stack along the Z-axis direction.

In the L1 layer 82A and the L2 layer 82B, the germanium concentration or "Ge%" (e.g., ge/Si atomic ratio) may be less than about 70%, and the Ge% (Ge/Si atomic ratio) of the L1 layer 82A is less than the Ge% (Ge/Si atomic ratio) of the L2 layer 82B. For example, L1 layer 82A may have a Ge% in the range of about 10% to about 50%, and L2 layer 82B may have a Ge% in the range of about 25% to about 70%. The atomic ratio of N-type dopants (e.g., as or P) to Si in L1 layer 82A and L2 layer 82B may be less than about 10%, and the atomic ratio of N-type dopants in L1 layer 82A may be less than the atomic ratio of N-type dopants in L2 layer 82B. For example, the atomic ratio of the N-type dopant in the L1 layer 82A may be in the range of about 0.5% to about 4%, and the atomic ratio of the N-type dopant in the L2 layer may be in the range of about 0.5% to about 8%. In some embodiments, the N-type dopant concentration in L1 layer 82A is in the range of about 2.5e20 cm ^-3 to about 2E21 cm ^-3, and the N-type dopant concentration in L2 layer 82B is in the range of about 2.5e20 cm ^-3 to about 4E21 cm ^-3. The thickness of each of the L1 layer 82A and the L2 layer 82B may be less than about 15nm, and the thickness of the L1 layer 82A may be less than the thickness of the L2 layer 82B. As one non-limiting example, L1 layer 82A may have a Ge% of 15% -50% and a phosphide atomic ratio of 4% -8%, and L2 layer 82B may have a Ge% of 25% -50% and a phosphide atomic ratio of 1% -4%, and the phosphide dopant concentration may be 5e20 cm ^-3-2E21 cm^-3. In another non-limiting example, L1 layer 82A may have a Ge% of 15% -50% and an arsenic atomic ratio of 2% -6%, and L2 layer 82B may have a Ge% of 15% -50% and an arsenic atomic ratio of 0.5% -6%, and the arsenic dopant concentration may be 2.5e20 cm ^-3-3E21cm^-3. Although two epitaxial layers 82A, 82B are shown in fig. 1A and 1B, the number of epitaxial layers is not limited thereto. In some embodiments, the number of epitaxial layers in the source/drain regions 82 may be three or more layers, or one layer.

The nanostructure devices 20A, 20B may include source/drain contacts 120 over one or more source/drain regions 82. The source/drain contacts 120 may include one or more pad layers and a core conductive layer (not separately shown in fig. 1A and 1B). A silicide layer 118 may also be formed between the source/drain regions 82 and the source/drain contacts 120 to reduce the source/drain contact resistance. In some embodiments, silicide layer 118 is or includes one or more of nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. For example, the silicide layer 118 may be TiSi, tiNiSi, niSi, WSi, coSi, moSi, ruSi or the like. In some embodiments, the thickness (in the Z direction) of the silicide layer 118 is in the range of about 0.5nm to about 10nm, such as in the range of about 3nm to about 10 nm. In some embodiments, the height of the source/drain contacts 120 may be in the range of about 1nm to about 100nm, such as about 10nm to about 100nm.

Although not shown in the views of fig. 1A and 1B, the nanostructure devices 20A, 20B include an interlayer dielectric (ILD) 130 and an etch stop layer 131 (see, e.g., fig. 16). ILD 130 provides electrical isolation between the various components of nanostructure devices 20A, 20B discussed above, such as between gate structure 200 and source/drain contact 120 therebetween. An etch stop layer 131 may be formed prior to forming ILD 130, and etch stop layer 131 may be located laterally between ILD 130 and sidewall spacer 41 and vertically between ILD 130 and source/drain region 82. In some embodiments, the etch stop layer 131 is or includes SiN, siCN, siC, siOC, siOCN, hfO ₂、ZrO₂、ZrAlOx、HfAlOx、HfSiOx、Al₂O₃ or other suitable material. In some embodiments, the thickness of the etch stop layer 131 is in the range of about 1nm to about 5 nm.

Fig. 20 illustrates a flow diagram of a method 1000 for forming an IC device or portion thereof from a workpiece in accordance with one or more aspects of the present disclosure. Method 1000 is merely an example and is not intended to limit the present disclosure to what is explicitly shown in method 1000. Additional actions may be provided before, during, and after method 1000, and some of the actions described may be replaced, eliminated, or moved for additional embodiments of the methods. For simplicity, not all acts are described in detail herein. For example, the operations of forming source/drain contacts 120, front-side interconnect structures, back-side interconnect structures, etc., may follow method 1000. For example, act 1300 may be optional. For example, additional epitaxial layers may be formed after act 1600 and before act 1700. The method 1000 is described below in connection with partial perspective and/or cross-sectional views of a workpiece at different stages of manufacture according to an embodiment of the method 1000 shown in fig. 2A-16. In order to avoid ambiguity, in all figures, the X-axis direction is perpendicular to the Y-axis direction, and the Z-axis direction is perpendicular to the X-axis direction and the Y-axis direction. Note that since a workpiece can be manufactured as a semiconductor device, the workpiece can be referred to as a semiconductor device according to the context. Method 1000 may be used to form devices 10A, 10B shown in fig. 1A, 1B, and 18A-19F.

Fig. 2A-16 are perspective and cross-sectional views of intermediate stages in the fabrication of a nanostructure device, such as a full-gate field effect transistor (GAAFET), in accordance with some embodiments. Fig. 2A, 3A, 4A, 5A, 6A, 7A, 8A, 14A, and 15A show perspective views. Fig. 2B, 3B, 4B, 5B, 6B, 7B, 8B, 14B, and 15B show reference sections B-B' (gate cut planes) shown in fig. 2A, 3A, and 4A. Fig. 4C, 5C, 6C, 7C, 9A-13B, 14C, 15C, and 16 illustrate reference cross-sections C-C' (channel/fin cut) shown in fig. 4A.

In fig. 2A and 2B, a substrate 110 is provided. The substrate 110 may be a semiconductor substrate, such as a bulk semiconductor, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The semiconductor material of the substrate 110 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or a combination thereof. Other substrates may be used, such as single layer, multi-layer or gradient substrates.

Further, in fig. 2A and 2B, a multi-layer stack 25 or "lattice" formed of alternating layers of first semiconductor layers 21A, 21B, 21C (collectively referred to as first semiconductor layers 21) and second semiconductor layers 23A, 23B, 23C (collectively referred to as second semiconductor layers 23) is formed over the substrate 110. In some embodiments, the first semiconductor layer 21 may be formed of a first semiconductor material suitable for an n-type nanostructure device, such as silicon, silicon carbide, or the like, and the second semiconductor layer 23 may be formed of a second semiconductor material suitable for a p-type nanostructure device, such as silicon germanium, or the like. Each layer of the multilayer stack 25 may be epitaxially grown using techniques such as Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), vapor Phase Epitaxy (VPE), molecular Beam Epitaxy (MBE), and the like.

Three layers of each of the first semiconductor layer 21 and the second semiconductor layer 23 are shown. In some embodiments, the multi-layer stack 25 may include one or two or four, five or more of each of the first semiconductor layer 21 and the second semiconductor layer 23. Although the multilayer stack 25 is shown as including the second semiconductor layer 23C as the bottommost layer, in some embodiments, the bottommost layer of the multilayer stack 25 may be the first semiconductor layer 21.

Due to the high etch selectivity between the first semiconductor material and the second semiconductor material, the second semiconductor layer 23 of the second semiconductor material may be removed without significantly removing the first semiconductor layer 21 of the first semiconductor material, thereby allowing the first semiconductor layer 21 to be patterned to form a channel region of the nanostructure device. In some embodiments, the first semiconductor layer 21 is removed and the second semiconductor layer 23 is patterned to form a channel region. The high etch selectivity allows the first semiconductor layer 21 of the first semiconductor material to be removed without significantly removing the second semiconductor layer 23 of the second semiconductor material, thereby allowing the second semiconductor layer 23 to be patterned to form a channel region of the nanostructure device.

In fig. 3A and 3B, corresponding to act 1100 of fig. 20, fins 32 are formed in substrate 110 and nanostructures 22, 24 are formed in multilayer stack 25. In some embodiments, the nanostructures 22, 24 and fin 32 may be formed by etching trenches in the multilayer stack 25 and the substrate 110. The etching may be any acceptable etching process, such as Reactive Ion Etching (RIE), neutral Beam Etching (NBE), or the like, or a combination thereof. The etching may be anisotropic. The first nanostructures 22A-22C (hereinafter also referred to as "channels") are formed by the first semiconductor layer 21, and the second nanostructures 24A-24C are formed by the second semiconductor layer 23. The distance CD1 between adjacent fins 32 and nanostructures 22, 24 may be about 18nm to about 100nm. For simplicity of illustration, a portion of device 10A or device 10B is shown in fig. 3A and 3B, including two fins 32. The method 1000 shown in fig. 2A-16 may be extended to any number of fins and is not limited to the two fins 32 shown in fig. 3A-16.

Fig. 3A and 3B illustrate fins 32 having tapered sidewalls such that the width of each of the fins 32 and/or nanostructures 22, 24 continuously increases in a direction toward the substrate 110. In such embodiments, each of the nanostructures 22, 24 may have a different width and be trapezoidal in shape. In other embodiments, the sidewalls are substantially vertical (non-tapered) such that the width of the fin 32 and the nanostructures 22, 24 are substantially similar, and each shape of the nanostructures 22, 24 is rectangular.

In fig. 3A and 3B, isolation regions 36 are formed adjacent to fins 32, and isolation regions 36 may be Shallow Trench Isolation (STI) regions. Isolation regions 36 may be formed by depositing an insulating material over substrate 110, fins 32, and nanostructures 22, 24, and between adjacent fins 32 and nanostructures 22, 24. The insulating material may be an oxide such as silicon oxide, nitride, or the like, or a combination thereof, and may be formed by high density plasma CVD (HDP-CVD), flowable CVD (FCVD), or the like, or a combination thereof. In some embodiments, a liner (not separately shown) may first be formed along the surfaces of the substrate 110, fin 32, and nanostructures 22, 24. Thereafter, a filler material, such as those discussed above, may be formed over the liner.

The insulating material is subjected to a removal process, such as a Chemical Mechanical Polishing (CMP), an etchback process, combinations thereof, or the like, to remove excess insulating material over the nanostructures 22, 24. After the removal process is completed, the top surfaces of the nanostructures 22, 24 may be exposed and level with the insulating material. In some embodiments, one or more hard mask layers are present over the nanostructures 22, 24 to protect the nanostructures 22, 24 during the removal process that removes excess insulating material over the nanostructures 22, 24. After the removal process is completed, the hard mask layer may be exposed and level with the insulating material.

The insulating material is then recessed to form isolation regions 36. After recessing, the nanostructures 22, 24 and the upper portion of the fin 32 may protrude from between adjacent isolation regions 36. The isolation region 36 may have a top surface that is planar, convex, concave, or a combination thereof as shown. In some embodiments, isolation region 36 is recessed by an acceptable etching process, such as oxide removal using, for example, dilute hydrofluoric acid (dHF), which is selective to the insulating material and leaves fin 32 and nanostructures 22, 24 substantially unchanged.

Fig. 2A-3B illustrate one embodiment (e.g., post etch) of forming fins 32 and nanostructures 22, 24. In some embodiments, fins 32 and/or nanostructures 22, 24 are epitaxially grown (e.g., etched first) in trenches in the dielectric layer. The epitaxial structure may include alternating semiconductor materials discussed above, such as a first semiconductor material and a second semiconductor material.

Furthermore, in fig. 3A and 3B, suitable wells (not separately shown) may be formed in fin 32, nanostructures 22, 24, and/or isolation region 36. Using the mask, an n-type dopant implantation may be performed in the p-type region of the substrate 110, and a p-type dopant implantation may be performed in the n-type region of the substrate 110. Exemplary n-type dopants may include phosphorus, arsenic, antimony, and the like. Exemplary p-type dopants may include boron, boron fluoride, indium, and the like. An anneal may be performed after implantation to repair the implant damage and activate the p-type and/or n-type dopants. In some embodiments, in-situ doping during epitaxial growth of fin 32 and nanostructures 22, 24 may avoid separate implants, but in-situ doping and implant doping may be used together.

The fins 32 and nanostructures 22, 24 may be patterned by any suitable method. For example, one or more photolithographic processes including a double pattern process or a multiple pattern process may be used to form the fins 32 and the nanostructures 22, 24. Typically, a double patterning process or multiple patterning process combines a photolithography process and a self-aligned process, allowing for smaller pitches than those obtainable using a single direct photolithography process. As an example of a multiple patterning process, a sacrificial layer may be formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers may then be used to pattern fin 32.

In fig. 4A-4C, a dummy (or "sacrificial") gate structure 40 is formed over fin 32 and/or nanostructures 22, 24. A dummy gate layer 45 or sacrificial gate layer 45 is formed over the fins 32 and/or nanostructures 22, 24. The dummy gate layer 45 may be formed of a material having a high etching selectivity with respect to the isolation region 36. The dummy gate layer 45 may be a conductive, semiconductive, or nonconductive material, and may be selected from the group consisting of amorphous silicon, polysilicon (poly-silicon), poly-silicon-germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. Dummy gate layer 45 may be deposited by Physical Vapor Deposition (PVD), CVD, sputter deposition, or other techniques for depositing the selected material. A mask layer 47 is formed over the dummy gate layer 45, and the mask layer 47 may include, for example, silicon nitride, silicon oxynitride, or the like. In some embodiments, a gate dielectric layer (not shown for simplicity) is formed before the dummy gate layer 45 and the dummy gate layer 45 between the fins 32 and/or nanostructures 22, 24. In some embodiments, a gate dielectric layer (not shown for simplicity) is formed between the dummy gate layer 45 and the fin 32 and/or the nanostructures 22, 24 prior to the dummy gate layer 45.

A spacer layer or sidewall spacer 41 is formed over the sidewalls of the mask layer 47 and the dummy gate layer 45. According to some embodiments, the spacer layer 41 is made of an insulating material, such as silicon nitride, silicon oxide, silicon carbonitride, silicon oxynitride, silicon carbonitride oxide, or the like, and the spacer layer 41 may have a single-layer structure or a multi-layer structure including a plurality of dielectric layers. Spacer layer 41 may be formed by depositing a spacer material layer (not shown) over mask layer 47 and dummy gate layer 45. According to some embodiments, portions of the spacer material layer between the dummy gate structures 40 are removed using an anisotropic etching process.

Fig. 4A to 4C illustrate one process for forming the spacer layer 41. In some embodiments, spacer layer 41 is alternatively or additionally formed after dummy gate layer 45 is removed. In such embodiments, dummy gate layer 45 is removed, leaving behind an opening, and spacer layer 41 may be formed by conformally coating the material of spacer layer 41 along the sidewalls of the opening. The conformally coated material may then be removed from the bottom of the opening corresponding to the top surface of the uppermost channel (e.g., channel 22A) prior to forming an active gate, such as any active gate of gate structure 200.

In fig. 5A-5C, corresponding to act 1200 of fig. 20, an etching process is performed to form source/drain trenches 57 that recess the protruding fins 32 and/or portions of the nanostructures 22, 24 not covered by the dummy gate structure 40, resulting in the illustrated structure. The recess may be anisotropic so that the portion of fin 32 directly under dummy gate structure 40 and spacer layer 41 is protected and not etched. According to some embodiments, the top surface of recessed fin 32 may be substantially coplanar with the top surface of isolation region 36, as shown. According to some other embodiments, the top surface of recessed fin 32 may be lower than the top surface of isolation region 36. For simplicity, fig. 5C shows two vertical stacks of nanostructures 22, 24 after the etching process. In general, an etching process may be used to form a vertical stack of any number of nanostructures 22, 24 over fin 32. In general, an etching process may be used to form any number of vertical stacks of nanostructures 22, 24 over fin 32.

Fig. 6A to 6C and fig. 7A to 7C illustrate the formation of the inner spacer 74. A selective etching process is performed to recess the ends of the nanostructures 24 exposed by the openings in the spacer layer 41 without substantially attacking the nanostructures 22. After the selective etching process, grooves 64 are formed in the nanostructures 24 where the removed ends were located. The resulting structure is shown in fig. 6A-6C.

Next, an inner spacer layer is formed to fill the grooves 64 in the nanostructures 24 formed by the previous selective etching process. The inner spacer layer may be a suitable dielectric material such as silicon carbonitride (SiCN), silicon oxynitride (SiOCN), or the like, formed by a suitable deposition method such as PVD, CVD, ALD. For example, ALD may be performed to deposit a SiN layer. An etching process, such as an anisotropic etching process, is performed to remove portions of the inner spacer layer that are disposed outside the grooves in the nanostructures 24. The remaining portion of the inner spacer layer (e.g., the portion disposed inside the recess 64 in the nanostructure 24) forms the inner spacer 74. The resulting structure is shown in fig. 7A-7C. The inner spacers 74 may have the same or different widths from each other in the X-axis direction. For example, as shown in fig. 7A to 7C, the inner spacers 74 all have the same width. In some embodiments, the inner spacers 74 have substantially the same width and the remainder of the nanostructures 24 have increasing width toward the substrate 110 as the channels 22 taper after etching in fig. 5A-5C.

Fig. 8A and 8B and fig. 9A-13B illustrate the formation of source/drain regions 82 corresponding to acts 1300, 1400, 1500, and 1600 of fig. 20. In the illustrated embodiment, the source/drain regions 82 are epitaxially grown from epitaxial material. In some embodiments, the source/drain regions 82 exert stress in the respective channels 22A-22C, thereby improving performance. For example, as described with reference to fig. 1A and 1B and fig. 9A-13B, the source/drain regions 82 exert tensile stress in the respective channels 22A-22C that are N-type channels. The source/drain regions 82 are formed such that each dummy gate structure 40 is disposed between a respective adjacent pair of source/drain regions 82. In some embodiments, spacer layer 41 separates source/drain regions 82 from dummy gate layer 45 by an appropriate lateral distance to prevent electrical bridging to the subsequently formed gates of the resulting device.

Source/drain regions 82 may comprise any acceptable material, such as a material suitable for n-type or p-type devices. In some embodiments, for n-type devices, the source/drain regions 82 comprise a material that imparts a tensile strain in the channel region, such as silicon, siC, siCP, siP, or the like. According to some embodiments, when forming a p-type device, the source/drain regions 82 comprise a material that imparts a compressive strain in the channel region, such as SiGe, siGeB, ge, geSn or the like. The source/drain regions 82 may have surfaces protruding from the corresponding surfaces of the fins and may have facets. In some embodiments, adjacent source/drain regions 82 may merge to form a single source/drain region 82 adjacent to two adjacent fins 32.

The source/drain regions 82 may be implanted with dopants and then annealed. The source/drain regions may have a dopant concentration between about 10 ¹⁹cm^-3 and about 10 ²¹cm^-3, or the source/drain regions may be any of the dopant concentrations described with reference to fig. 1A and 1B. The N-type and/or p-type dopants for source/drain regions 82 may be any of the dopants discussed with reference to the previous figures. In some embodiments, the source/drain regions 82 are doped in-situ during growth. Then, a Contact Etch Stop Layer (CESL) 131 and an interlayer dielectric (ILD) 130 shown in fig. 16 may be formed to cover the dummy gate structure 40 and the source/drain regions 82. For simplicity of illustration, CESL 131 and ILD 130 are omitted from fig. 8A-15C.

Fig. 9A-13B are cross-sectional side views illustrating the formation of source/drain regions 82 according to various embodiments. Fig. 9A, 10A, 11A, 12A, 13A illustrate a structure including a cushion layer 84 therein. Fig. 9B, 10B, 11B, 12B, 13B illustrate a structure in which the cushion layer 84 is omitted.

In fig. 9A, spacer layer 84 is formed, corresponding to optional action 1300 of fig. 20. Liner layer 84 may be a silicon layer formed by a suitable growth operation. After growth of liner layer 84, liner layer 84 may have an upper surface that is substantially coplanar with an upper surface of fin 32. In some embodiments, the upper surface of liner layer 84 is slightly above the bottom surface of bottommost interior spacer 74. In some embodiments, pad layer 84 is not formed, as shown in FIG. 9B.

In fig. 10A, 10B, 11A and 11B, a bottom isolation structure 800 is formed in the source/drain trench 57, corresponding to act 1400 of fig. 20. In fig. 10A and 10B, a bottom isolation layer 800L is provided at the bottom of the S/D trench 57. In this way, the bottom SiGe: P or SiGe: as film formed in the subsequent operation may be amorphous, and the bottom SiGe: P or SiGe: as film may be removed during the etching process of the selective epitaxial growth process. The sidewalls SiGe: P or SiGe: as of the source/drain regions 82 become crystalline and remain on the sidewalls. In fig. 10A, a bottom isolation layer 800L is formed on the exposed surfaces of sidewall spacers 41, trenches 22, internal spacers 74, and liner layer 84. In fig. 10B, a bottom isolation layer 800L is formed on exposed surfaces of sidewall spacers 41, channel 22, inner spacer 74, and fin 32. In fig. 10A and 10B, a bottom isolation layer 800L is formed by a suitable process such as plasma enhanced ALD, and the bottom isolation layer 800L is or includes a dielectric material such as SiN. The bottom spacer 800L may include SiN, siCN, siCON, siOC, siC, siO or the like and may be deposited to a thickness of about 1nm-5nm or slightly thicker. After a conformal film deposition process (e.g., PEALD), a film process (e.g., etch back) may be performed. The film deposition process may include a cyclic PEALD process using a reactive gas of DCS and NH ₃/Ar plasma, and the film treatment (e.g., etching) may be performed by Ar/N ₂ plasma. The resulting structure is shown in fig. 11A and 11B. After film processing, the bottom isolation structure 800 may have a thickness in the range of about 1nm to about 5nm and may have a shape that is horizontal I-shaped, bowl-shaped, disk-shaped, U-shaped, V-shaped, or other suitable shape that may conform to the shape of the S/D trench 57 and optional liner layer 84 as selected by the S/D trench etch process described with reference to fig. 5A-5C.

In fig. 12A, 12B, 13A and 13B, source/drain regions 82 are epitaxially grown in the S/D trenches 57. In fig. 12A and 12B, an L1 layer 82A including a first epitaxial sub-layer 82A1 and a second epitaxial sub-layer 82A2 is formed in the S/D trench 57, corresponding to act 1500 of fig. 20. In fig. 13A and 13B, an L2 layer 82B is formed on L1 layer 82A in S/D trench 57, corresponding to act 1600 of fig. 20.

In fig. 12A, liner layer 84 is disposed between bottom isolation structure 800 and substrate 110, fin 32, or substrate 110 and fin 32. In fig. 12B, pad layer 84 is absent. Each of the first and second epitaxial sublayers 82A1 and 82A2 may be a germanium-containing epitaxial layer for NMOS transistors formed in the S/D trench 57. The sequentially compressed SiGe: P or SiGe: as deposition allows the epitaxial growth mechanism to be Sidewall (SW) growth rather than bottom-up growth (e.g., growth from fin 32 or substrate 110). The bottom isolation structure 800 is provided at the bottom of the S/D trench, so that the SiGe: P or SiGe: as film formed at the bottom of the S/D trench may become amorphous and may be removed in a selective epitaxial growth etching process. The sidewall SiGe P or SiGe As becomes crystalline and remains on the sidewall, e.g., on the channels 22A-22B and the inner spacer 74. The germanium-containing epitaxial layer for the NMOS may be formed by a plurality of selective epitaxial growth processes (or so-called "cyclical deposition and etching processes") which may include deposition operations and etching operations performed alternately or simultaneously. For example, a first epitaxial growth process may be performed to form the first epitaxial sub-layer 82A1. First epitaxial sub-layer 82A1 may be grown outwardly from channel 22. In some embodiments, first epitaxial sublayer 82A1 does not merge and is offset from one another in the X-axis direction and the Z-axis direction as shown.

After forming the first epitaxial sub-layer 82A1, the second epitaxial sub-layer 82A2 may be formed by performing a second epitaxial growth process. In some embodiments, the first epitaxial growth process and the second epitaxial growth process are different, similar, or the same. In some embodiments, the first epitaxial growth process and the second epitaxial growth process are different stages of a single continuous growth process. In some embodiments, there is a visible interface between the first epitaxial sublayer 82A1 and the second epitaxial sublayer 82A2. In some embodiments, the first epitaxial sublayer 82A1 and the second epitaxial sublayer 82A2 have the same or substantially the same Ge%, dopant atomic ratio, and dopant concentration. In some embodiments, one or more of Ge%, dopant atomic ratio, and dopant concentration between the first epitaxial sublayer 82A1 and the second epitaxial sublayer 82A2 are different. The bottom isolation structure 800 is provided at the bottom of the S/D trench, so the SiGe: P or SiGe: as film formed at the bottom of the S/D trench may become amorphous and be removed during the etching process of selective epitaxial growth. As shown in fig. 12B, for example, after forming L1 layer 82A, surface 84S of bottom isolation structure 800 may be substantially free of L1 layer 82A.

In fig. 13A and 13B, after the L1 layer 82A is formed, the L2 layer 82B is formed. A third epitaxial growth process may be performed to form the L2 layer 82B. In some embodiments, seam 810 is formed during the formation of L2 layer 82B. Seam 810 may be formed due to the consolidation at the upper portion of L2 layer 82B before the middle portion of L2 layer 82B can be consolidated. In some embodiments, seam 810 is absent. The third epitaxial growth process may be similar in many respects to the first and second epitaxial growth processes, but may use different proportions of reactant gases and dopants, thereby making the L2 layer 82B different from the L1 layer 82A. In the L1 layer 82A and the L2 layer 82B, the germanium concentration or "Ge%" (e.g., ge/Si atomic ratio) may be less than about 70%, and the Ge% (Ge/Si atomic ratio) of the L2 layer 82B is higher than the Ge% (Ge/Si atomic ratio) of the L1 layer 82A. For example, L1 layer 82A may have a Ge% in the range of about 10% to about 50%, and L2 layer 82B may have a Ge% in the range of about 25% to about 70%.

The atomic ratio of N-type dopants (e.g., as or P) to Si in L1 layer 82A and L2 layer 82B may be less than about 10%, and the atomic ratio of N-type dopants in L2 layer 82B may be higher than the atomic ratio of N-type dopants in L1 layer 82A. For example, the atomic ratio of the N-type dopant in the L1 layer 82A may be in the range of about 0.5% to about 4%, and the atomic ratio of the N-type dopant in the L2 layer may be in the range of about 0.5% to about 8%. In some embodiments, the N-type dopant concentration in L1 layer 82A is in the range of about 2.5e20 cm ^-3 to about 2E21 cm ^-3, and the N-type dopant concentration in L2 layer 82B is in the range of about 2.5e20 cm ^-3 to about 4E21 cm ^-3. The thickness of each of the L1 layer 82A and the L2 layer 82B may be less than about 15nm, and the thickness of the L1 layer 82A may be less than the thickness of the L2 layer 82B.

As one non-limiting example, L1 layer 82A may have a Ge% of 15% -50% and a phosphide atomic ratio of 4% -8%, and L2 layer 82B may have a Ge% of 25% -50% and a phosphide atomic ratio of 1% -4%, and the phosphide dopant concentration may be 5e20cm ^-3-2E21 cm^-3. In another non-limiting example, L1 layer 82A may have a Ge% of 15% -50% and an arsenic atomic ratio of 2% -6%, and L2 layer 82B may have a Ge% of 15% -50% and an arsenic atomic ratio of 0.5% -6%, and the arsenic dopant concentration may be 2.5E20cm_3-3E 21 cm_3. Although two epitaxial layers 82A, 82B are shown in fig. 13A and 13B, the number of epitaxial layers is not limited thereto. In some embodiments, the number of epitaxial layers of source/drain regions 82 may be three or more layers, or one layer.

For sidewall dominated grown SiGe-to-P or SiGe-to-As epitaxial films, the SW grown SiGe-to-P or SiGe-to-As films may exert a tensile strain on the Si nanoplatelets 22A-22C instead of a compressive strain, although the epitaxial films still produce compressive stress. In some embodiments, the tensile strain on the nanoplatelets 22B is greater than the tensile strain on the nanoplatelets 22A, 22C. That is, the nanoplatelets 22A, 22C on the periphery of the vertical stack (e.g., closer to the top or bottom) may have a lower tensile strain than the nanoplatelets 22B in the middle of the vertical stack. For example, the nanoplatelets located at the center of the vertical stack may have the highest tensile strain, and the tensile strain may decrease with increasing distance from the center, where "center" refers to the center of the vertical stack along the Z-axis direction.

Fig. 14A, 14B, and 14C illustrate the release of fin channels 22A-22C by removing nanostructures 24A-24C, mask layer 47, and dummy gate layer 45. A planarization process such as CMP is performed to make the top surfaces of the dummy gate layer 45 and the sidewall spacers 41 flush. The planarization process may also remove the mask layer 47 (see fig. 8A) on the dummy gate layer 45 and portions of the sidewall spacers 41 along the sidewalls of the mask layer 47. Accordingly, the top surface of the dummy gate layer 45 is exposed.

Next, the dummy gate layer 45 is removed in an etching process, thereby forming a groove 92. In some embodiments, the dummy gate layer 45 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate layer 45 without etching the spacer layer 41. When the dummy gate layer 45 is etched, a dummy gate dielectric (when present) may be used as an etch stop layer. The dummy gate dielectric may then be removed after the dummy gate layer 45 is removed.

The nanostructures 24 are removed to release the nanostructures 22. After removal of the nanostructures 24, the nanostructures 22 form a plurality of nanoplatelets that extend horizontally (e.g., parallel to the major upper surface of the substrate 110). The nanoplates may be collectively referred to as the channels 22 of the formed nanostructure devices 20A, 20B.

In some embodiments, the nanostructures 24 are removed by a selective etching process using an etchant that is selective to the material of the nanostructures 24, such that the nanostructures 24 are removed without substantially eroding the nanostructures 22. In some embodiments, the etching process is an isotropic etching process using an etching gas, including F ₂ and HF, and optionally a carrier gas, which may be an inert gas such as Ar, he, N ₂, combinations thereof, and the like.

In some embodiments, the nanostructures 24 are removed and the nanostructures 22 are patterned to form channel regions for both PFETs and NFETs. However, in some embodiments, the nanostructures 24 may be removed and the nanostructures 22 may be patterned to form channel regions of NFETs, and the nanostructures 22 may be removed and the nanostructures 24 may be patterned to form channel regions of PFETs. In some embodiments, the nanostructures 22 may be removed and the nanostructures 24 may be patterned to form channel regions of NFETs, and the nanostructures 24 may be removed and the nanostructures 22 may be patterned to form channel regions of PFETs. In some embodiments, the nanostructures 22 may be removed and the nanostructures 24 may be patterned to form channel regions for both PFETs and NFETs.

In some embodiments, the nanoplatelets 22 are reshaped (e.g., thinned) by a further etching process to improve the gate fill window. Reshaping may be performed by an isotropic etching process selective to the nanoplatelets 22. After reshaping, the nanoplatelets 22 may take on a dog bone shape in which the middle portion of the nanoplatelets 22 is thinner along the X-direction than the peripheral portion of the nanoplatelets 22.

In fig. 15A-15C, a replacement gate 200 is formed, corresponding to act 1700 of fig. 20. The gate structure 200 generally includes an interfacial layer (IL, or "first IL") 210, at least one gate dielectric layer 600, a work function metal layer 900, and a gate fill layer 290. In some embodiments, each replacement gate 200 further includes at least one of the second interfacial layer 240 or the work function barrier layer 700. The detailed structure and formation of the gate structure 200 is described with reference to fig. 17. Fig. 16 shows the structure of fig. 15C, including ILD 130 and ESL 131. In some embodiments, ESL 131 is formed after source/drain regions 82 are formed and before sacrificial gate layer 45 is removed. ILD 130 is formed over ESL 131.

Fig. 17 is a detailed cross-sectional side view of a gate structure 200 in accordance with various embodiments. The gate structure 200 shown in fig. 17 includes an interfacial layer 210, a gate dielectric layer 600, a second interfacial layer 240, a work function blocking layer 700, a work function adjustment layer 900, and a core layer 290.

When present, interface layer 210 is formed over the exposed areas of channels 22A-22C and the top surfaces of fins 32, and interface layer 210 may be an oxide of the material of channels 22A-22C. Interface layer 210 promotes adhesion of gate dielectric layer 600 to channels 22A-22C. In some embodiments, interface layer 210 has a thickness of about 5 angstroms (a) to about 50 angstroms (a). In some embodiments, interface layer 210 has a thickness of about 10 angstroms. An interfacial layer 210 having too thin a thickness may exhibit voids or insufficient adhesion. Too thick an interfacial layer 210 consumes gate fill window, which is related to threshold voltage adjustment and resistance as described above. In some embodiments, interface layer 210 is doped with a dipole, such as lanthanum, for threshold voltage adjustment.

A gate dielectric layer 600 is located on the interfacial layer 210. In some embodiments, gate dielectric layer 600 includes at least one high-k gate dielectric material, which may refer to a dielectric material having a high dielectric constant greater than that of silicon oxide (k≡3.9). Exemplary high-k dielectric materials include HfO ₂、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、ZrO₂、Ta₂O₅ or a combination thereof. In some embodiments, gate dielectric layer 600 has a thickness of about 5 angstroms to about 100 angstroms. In some embodiments, the gate dielectric layer 600 may comprise a non-high-k dielectric material such as silicon oxide. In some embodiments, the gate dielectric layer 600 includes more than one high-k dielectric layer, at least one of which includes a dopant, such as lanthanum, magnesium, yttrium, etc., that can be driven in by an annealing process to modify the threshold voltage of the nanostructure devices 20A, 20B.

In some embodiments, the gate dielectric layer 600 may include a dopant such as metal ions driven into the high-k gate dielectric from La₂O₃、MgO、Y₂O₃、TiO₂、Al₂O₃、Nb₂O₅ or the like, or boron ions driven from B ₂O₃, at a concentration that achieves threshold voltage adjustment. As one example, for N-type transistor devices, a higher concentration of lanthanum ions lowers the threshold voltage relative to a layer with a lower concentration or no lanthanum ions, and vice versa for P-type devices. In some embodiments, the gate dielectric layer 600 of some transistor devices (e.g., IO transistors) is free of dopants present in some other transistor devices (e.g., N-type core logic transistors or P-type IO transistors). In an N-type IO transistor, for example, a relatively high threshold voltage is desired so that the IO transistor high-k dielectric layer may preferably be free of lanthanum ions that would otherwise lower the threshold voltage.

The second IL 240 is formed on the gate dielectric layer 600 and the work function barrier layer 700 is formed on the second IL 240. The second IL 240 promotes better metal gate adhesion to the gate dielectric layer 600. In many embodiments, the second IL 240 further provides improved thermal stability to the gate structure 200, and the second IL 240 serves to limit diffusion of metal dopants from the work function metal layer 900 and/or the work function barrier layer 700 into the gate dielectric layer 600. In some embodiments, the formation of the second IL 240 is accomplished by first depositing a high-k capping layer (not shown for simplicity) over the gate dielectric layer 600. In various embodiments, the high-k capping layer comprises one or more of the following materials: hfSiON, hfTaO, hfTiO, hfTaO, hfAlON, hfZrO or other suitable materials. In a specific embodiment, the high-k capping layer comprises titanium silicon nitride (TiSiN). In some embodiments, the high-k cap layer is deposited by ALD using about 40 to about 100 cycles at a temperature of about 400 degrees celsius to about 450 degrees celsius. A thermal anneal is then performed to form the second IL 240, in some embodiments, the second IL 240 may be or include TiSiNO. After forming the second IL 240 by thermal annealing, an Atomic Layer Etch (ALE) with Artificial Intelligence (AI) control may be performed cyclically to remove the high-k capping layer while substantially not removing the second IL 240. Each cycle may include a first pulse of WCl ₅, followed by an Ar purge, followed by a second pulse of O ₂, followed by another Ar purge. The high-k capping layer is removed to increase the gate fill window for further adjustment of the plurality of threshold voltages by metal gate patterning.

According to some embodiments, a work function barrier layer 700 is optionally included in the gate structure 200. The work function barrier layer 700 is or includes a metal nitride such as TiN, WN, moN, taN or the like. In a specific embodiment, work function barrier layer 700 is TiN. The work function barrier layer 700 may have a thickness in the range of about 5 angstroms to about 20 angstroms. The inclusion of work function barrier layer 700 provides additional threshold voltage adjustment flexibility. In general, work function barrier layer 700 increases the threshold voltage for NFET transistor devices and decreases the threshold voltage (amplitude) for PFET transistor devices.

In some embodiments, work function metal layer 900 is formed on work function barrier layer 700, and work function metal layer 900 may include one or more of an N-type work function metal layer, an in-situ capping layer, and an oxygen barrier layer. The N-type workfunction metal layer is or includes an N-type metal material, such as TiAlC, tiAl, taAlC, taAl or the like. The N-type work function metal layer may be formed by one or more deposition methods, such as CVD, PVD, ALD, plating, and/or other suitable methods, and has a thickness of between about 10 angstroms and 20 angstroms. An in-situ capping layer is formed over the N-type workfunction metal layer. In some embodiments, the in-situ coating is or includes TiN, tiSiN, taN or another suitable material, and the in-situ coating has a thickness of between about 10 angstroms and 20 angstroms. An oxygen barrier layer is formed on the in-situ capping layer to prevent diffusion of oxygen into the N-type work function metal layer, which would result in an undesirable shift in threshold voltage. The oxygen barrier layer is formed of a dielectric material that can prevent oxygen from penetrating into the N-type workfunction metal layer and that can protect the N-type workfunction metal layer from further oxidation. The oxygen barrier layer may comprise an oxide of silicon, germanium, siGe, or another suitable material. In some embodiments, the oxygen barrier layer is formed using ALD and has a thickness between about 10 angstroms and about 20 angstroms.

Metal fill layer 290 is located on work function metal layer 900. In some embodiments, a glue layer (not separately shown) is formed between the oxygen barrier layer of the work function metal layer and the metal fill layer 290. The glue layer may promote and/or enhance adhesion between the metal fill layer 290 and the workfunction metal layer 900. In some embodiments, the glue layer may be formed of a metal nitride using ALD, such as TiN, taN, moN, WN or another suitable material. In some embodiments, the thickness of the glue layer is between about 10 angstroms and about 25 angstroms. The metal fill layer 290 may be formed on the glue layer and may include a conductive material such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or a combination thereof. In some embodiments, the metal fill layer 290 may be deposited using methods such as CVD, PVD, plating, and/or other suitable processes. Between trenches 22A-22C, metal fill layer 290 is circumferentially surrounded (in cross-section) by one or more work function metal layers 900, and then work function metal layers 900 are circumferentially surrounded by gate dielectric layer 600.

In some embodiments, the seam 510 is formed in the metal fill layer 290 vertically between the channels 22A, 22B, the seam 510 may be an air gap. In some embodiments, the metal fill layer 290 is conformally deposited on the work function metal layer 900. Seam 510 may be formed during conformal deposition due to the incorporation of sidewall deposited films. In some embodiments, seam 510 is not present between adjacent channels 22A, 22B.

Fig. 18A-18D are cross-sectional side views illustrating a device 10B according to various embodiments. In device 10B, liner layer 84 is absent. In fig. 18A, L2 layer 82B extends from the bottom surface of source/drain contact 120 to a depth L1, depth L1 being flush with bottommost channel 22C. In fig. 18B, L2 layer 82B extends from the bottom surface of source/drain contact 120 to a depth L2, depth L2 being approximately flush with the upper surface of bottommost channel 22C and the interface of gate structure 200 thereabove. In fig. 18C, L2 layer 82B extends from the bottom surface of source/drain contact 120 to a depth L3, depth L3 being approximately flush with the bottom surface of gate structure 200 and slightly above the bottom surface of bottommost inner spacer 74. In fig. 18D, the bottom isolation structure 800 extends from the bottom of the S/D trench 57 to a level slightly above the bottom surface of the gate structure 200. L2 layer 82B extends from the bottom surface of source/drain contact 120 to the upper surface of bottom isolation structure 800.

Fig. 19A-19F illustrate a device 10B according to various embodiments. In fig. 19A, the bottom isolation structure 800 is a substantially horizontal thin film layer that extends from one interior spacer 74 (left side) to the other interior spacer 74 (right side). The bottom isolation structure 800 has a thickness in the Z-axis direction of about 1nm-5nm. In fig. 19B, the bottom isolation structure 800A, which is identical in most respects to the bottom isolation structure 800, has a triangular or convex profile, as shown. The thickness of the bottom isolation structure 800A may decrease toward the periphery of the bottom isolation structure 800A. The bottom isolation structure 800A may extend beyond the source/drain regions 82 in a horizontal direction to provide isolation between the source/drain regions 82 and the fin 32 and/or the substrate 110. In some embodiments, the upper surface of the bottom isolation structure 800A is flat, concave, or another suitable shape. Seam 810 is shown in fig. 19A and 19B, but seam 810 may not be present, for example, when L2 layer 82B is fully consolidated during its growth.

In fig. 19C and 19D, a third epitaxial layer or "L3" layer 82C is formed on the upper surfaces of L1 layer 82A and L2 layer 82B. The L3 layer 82C may be formed by a fourth epitaxial growth process, which is similar in many respects to the first, second, and third epitaxial growth processes. In fig. 19C and 19D, the L1 layer 82A may have Ge% in the range of 10% to 50%, the L2 layer 82B may have Ge% in the range of 25% to 70%, and the L3 layer 82C may have Ge% in the range of 50% to 70%. The N-type dopant in L1 layer 82A may be in the range of 0.5% to 4%, the N-type dopant in L2 layer 82B may be in the range of 0.5% to 8%, and the N-type dopant in L3 layer 82C may be in the range of 2% to 8%. The N-type dopant concentration in L1 layer 82A may be in the range of 2.5e20 cm ^-3 to 2E21 cm ^-3, the N-type dopant concentration in L2 layer 82B may be in the range of 2.5e20 cm ^-3 to 4E21 cm ^-3, and the N-type dopant concentration in L3 layer 82C may be in the range of 1E21 cm ^-3 to 4E21 cm ^-3. Seam 810 is shown in fig. 19C and 19D, but in some embodiments seam 810 may not be present in device 10B including L3 layer 82C.

In fig. 19E and 19F, as shown, only the L1 layer 82A is present in the source/drain region 82. Thus, the source/drain regions 82 may have a uniform or substantially uniform Ge% concentration in the range of 25% to 70%, and an average N-type dopant concentration in the range of 2e20 cm ^-3 to 5e20 cm ^-3.

Fig. 21 is a cross-sectional side view of IC device 70 in accordance with various embodiments. IC device 70 may be a Complementary MOS (CMOS) device such as a portion of a memory cell (e.g., a static random access memory cell) that includes NFET 720 and PFET 740. NFET 720 may be similar to or identical to device 10A or device 10B. For example, as shown in fig. 21, NFET 720 may be similar to device 10B described with reference to fig. 19B. As shown in fig. 21, the source/drain regions 82 of the NFET apply a tensile strain (shown by arrows) to the channel 22. PFET 740 may be different from NFET in some respects. For example, PFET 740 includes source/drain region 382, source/drain region 382 includes L1 layer 382A and L2 layer 382B, and PFET 740 does not include a bottom isolation structure (e.g., bottom isolation structure 800) between source/drain region 382 and fin 32. As such, the L1 layer 382A may be grown in a bottom-up manner rather than in a sidewall dominated manner, such that the L1 layer 382A is present on the sidewalls of the channel 22 and the inner spacer 74, and also on the upper surface of the fin 32. Because the L1 layer 382A is not grown in a sidewall dominated manner, the source/drain regions 382 impart a compressive strain to the channel 22 of the PFET 740, which is beneficial for improving carrier mobility in the channel 22 of the PFET 740.

In PFET 740, L1 layer 382A has a Ge% that may range from 10% to 35%, and L2 layer 382B has a Ge% that may range from 25% to 80%. The P-type dopant in the L1 layer 382A may be in the range of 0.5% to 4%, and the P-type dopant in the L2 layer 382B may be in the range of 1% to 8%. The P-type dopant concentration in the L1 layer 382A may be in the range of 2.5e20 cm ^-3 to 2E21 cm ^-3, and the P-type dopant concentration in the L2 layer 382B may be in the range of 3e20 cm ^-3 to 4E21 cm ^-3.

Embodiments may provide advantages. The bottom isolation structure 800 in the NFETs 10A, 10B promotes the growth of the sidewall dominant of the L1 layer 82A and L2 layer 82B of the source/drain regions 82, which creates tensile strain in the channels 22A-22C of the NFETs 10A, 10B. The tensile strain increases the carrier mobility in NFETs 10A, 10B. In a CMOS device such as device 70, bottom isolation structure 800 may be omitted from PFET 740, which facilitates bottom-up growth of source/drain regions 382, which creates compressive strain in channels 22A-22C of PFET 740. Compressive strain increases carrier mobility in PFET 740.

According to at least one embodiment, a device comprises: a stack of nanostructure channels over a substrate; a gate structure surrounding the stack; and source/drain regions on the substrate. The source/drain regions include: a first epitaxial layer in direct contact with the nanostructure channel; and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a higher germanium concentration than the first epitaxial layer. The device further includes a bottom isolation structure between the source/drain regions and the substrate, the bottom isolation structure being a dielectric layer in direct contact with the source/drain regions. In some embodiments, the device further comprises: a substrate; and a recess in the substrate below the bottom isolation structure; wherein the source/drain regions extend into the recess. In some embodiments, the bottom isolation structure pads on the upper surface of the recess and extends to a level above the recess. In some embodiments, the bottom isolation structure has a thickness in the range of 1 nm to 5 nm. In some embodiments, the bottom isolation structure comprises SiN, siCN, siCON, siOC, siC or SiO. In some embodiments, the source/drain region further comprises a third epitaxial layer in direct contact with upper surfaces of the first epitaxial layer and the second epitaxial layer, the third epitaxial layer extending to a level above an uppermost channel of the stack of nanostructure channels.

According to at least one embodiment, a device comprises: a semiconductor substrate; a first semiconductor channel over the semiconductor substrate; a second semiconductor channel over the first semiconductor channel; a gate structure surrounding the first semiconductor channel and the second semiconductor channel; a first internal spacer abutting a lower surface of the second semiconductor channel, an upper surface of the first semiconductor channel, and a first sidewall surface of the gate structure; a second internal spacer abutting a lower surface of the first semiconductor channel, an upper surface of the semiconductor substrate, and a second sidewall surface of the gate structure; a recess in the semiconductor substrate; a liner layer in the recess, the liner layer having an upper surface substantially flush with an upper surface of the semiconductor substrate, the liner layer being of the same material as the semiconductor substrate; a bottom isolation structure on the liner layer and abutting a sidewall of the second inner spacer; and source/drain regions located on the bottom isolation structure and physically isolated from the semiconductor substrate by the bottom isolation structure. In some embodiments, the source/drain regions comprise: a first epitaxial layer having a germanium concentration in the range of 10% to 50%; and a second epitaxial layer having a germanium concentration in a range of 25% to 70% higher than that of the first epitaxial layer. In some embodiments, the source/drain regions comprise: a first epitaxial layer having an N-type dopant atomic ratio in the range of 0.5% to 4%; and a second epitaxial layer having an N-type dopant atomic ratio in a range of 0.5% to 8% that is higher than the N-type dopant atomic ratio of the first epitaxial layer. In some embodiments, the source/drain regions comprise: a first epitaxial layer having an N-type dopant concentration in the range of 2.5e20 cm ^-3 to 2E21 cm ^-3; and a second epitaxial layer having an N-type dopant concentration in the range of 2.5e20 cm ^-3 to 4E21 cm ^-3 that is greater than the N-type dopant concentration of the first epitaxial layer. In some embodiments, the source/drain regions comprise: a first epitaxial layer having a germanium concentration in a range of about 10% to 50%; and a second epitaxial layer having a germanium concentration in the range of 25% to 70% greater than the germanium concentration of the first epitaxial layer; and a third epitaxial layer on upper surfaces of the first epitaxial layer and the second epitaxial layer, the third epitaxial layer having a germanium concentration in a range of about 50% to about 70%. In some embodiments, the source/drain regions comprise: a first epitaxial layer in direct contact with the first semiconductor channel and the second semiconductor channel; the second epitaxial layer is positioned on the first epitaxial layer; and source/drain contacts on the first epitaxial layer and the second epitaxial layer. In some embodiments, the second epitaxial layer extends from the lower surface of the source/drain contact to a level above the first semiconductor channel.

According to at least one embodiment, a device comprises: a substrate; an N-type transistor on the substrate, the N-type transistor comprising: a first stack of first nanostructure channels; a bottom isolation structure; and a first source/drain region in direct contact with the first nanostructure channel and the bottom isolation structure, the first source/drain region being physically isolated from the substrate by the bottom isolation structure; and a P-type transistor on the substrate, the P-type transistor comprising: a second stack of second nanostructure channels; and a second source/drain region in direct contact with the second nanostructure channel and the substrate. In some embodiments, the N-type transistor further comprises a liner layer between the substrate and the bottom isolation structure. In some embodiments, the first source/drain region comprises: a first epitaxial layer in direct contact with the first nanostructure channel; and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a higher germanium concentration than the first epitaxial layer. In some embodiments, the first epitaxial layer comprises: a plurality of first epitaxial sublayers, each first epitaxial sublayer in direct contact with a respective one of the first nanostructure channels and isolated from other first epitaxial sublayers of the plurality of first epitaxial sublayers; and a second epitaxial sublayer located on the plurality of first epitaxial sublayers. In some embodiments, the device further comprises: and a third epitaxial layer on upper surfaces of the first epitaxial layer and the second epitaxial layer, the third epitaxial layer extending to a level above an upper surface of an uppermost first nanostructure channel of the first stack. In some embodiments, the second source/drain region comprises: a third epitaxial layer in direct contact with the second nanostructure channel; and a fourth epitaxial layer on the third epitaxial layer, the fourth epitaxial layer having a higher germanium concentration than the third epitaxial layer. In some embodiments, the germanium concentration is: in the first epitaxial layer in the range of 10% to 50%; in the second epitaxial layer in the range of 25% to 70%; in the range of 10% to 35% in the third epitaxial layer; and in the fourth epitaxial layer in the range of 25% to 80%.

The foregoing outlines features of a drop-off embodiment so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising:

a stack of nanostructure channels over a substrate;

a gate structure surrounding the stack;

a source/drain region on the substrate, the source/drain region comprising:

A first epitaxial layer in direct contact with the nanostructure channel; and

A second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a higher germanium concentration than the first epitaxial layer; and

A bottom isolation structure is located between the source/drain regions and the substrate, the bottom isolation structure being a dielectric layer in direct contact with the source/drain regions.

2. The semiconductor device of claim 1, further comprising:

The substrate; and

A recess in the substrate below the bottom isolation structure;

wherein the source/drain regions extend into the recess.

3. The semiconductor device of claim 2, wherein the bottom isolation structure pads on an upper surface of the recess and extends to a level above the recess.

4. The semiconductor device of claim 3, wherein the bottom isolation structure has a thickness in a range of 1 nanometer to 5 nanometers.

5. The semiconductor device of claim 3, wherein the bottom isolation structure comprises SiN, siCN, siCON, siOC, siC or SiO.

6. The semiconductor device of claim 1, wherein the source/drain region further comprises a third epitaxial layer in direct contact with upper surfaces of the first and second epitaxial layers, the third epitaxial layer extending to a level above an uppermost channel of the stack of nanostructure channels.

7. A semiconductor device, comprising:

A semiconductor substrate;

a first semiconductor channel located above the semiconductor substrate;

A second semiconductor channel located above the first semiconductor channel;

a gate structure surrounding the first semiconductor channel and the second semiconductor channel;

A first internal spacer abutting a lower surface of the second semiconductor channel, an upper surface of the first semiconductor channel, and a first sidewall surface of the gate structure;

A second inner spacer abutting a lower surface of the first semiconductor channel, an upper surface of the semiconductor substrate, and a second sidewall surface of the gate structure;

A recess in the semiconductor substrate;

a liner layer in the recess, the liner layer having an upper surface substantially flush with an upper surface of the semiconductor substrate, the liner layer being of the same material as the semiconductor substrate;

a bottom isolation structure on the liner layer and abutting sidewalls of the second inner spacer; and

Source/drain regions are located on the bottom isolation structure and are physically isolated from the semiconductor substrate by the bottom isolation structure.

8. The semiconductor device of claim 7, wherein the source/drain regions comprise:

a first epitaxial layer having a germanium concentration in the range of 10% to 50%; and

A second epitaxial layer having a germanium concentration in the range of 25% to 70% higher than the germanium concentration of the first epitaxial layer.

9. The semiconductor device of claim 7, wherein the source/drain regions comprise:

a first epitaxial layer having an N-type dopant atomic ratio in the range of 0.5% to 4%; and

A second epitaxial layer having an N-type dopant atomic ratio in the range of 0.5% to 8% that is higher than the N-type dopant atomic ratio of the first epitaxial layer.

10. A semiconductor device, comprising:

A substrate;

An N-type transistor on the substrate, the N-type transistor comprising:

A first stack of first nanostructure channels;

A bottom isolation structure; and

A first source/drain region in direct contact with the first nanostructure channel and the bottom isolation structure, the first source/drain region being physically isolated from the substrate by the bottom isolation structure; and

A P-type transistor on the substrate, the P-type transistor comprising:

A second stack of second nanostructure channels; and

A second source/drain region in direct contact with the second nanostructure channel and the substrate.