CN117976709A - Transistor structure, manufacturing method thereof and chip - Google Patents

Abstract

The invention provides a transistor structure, a manufacturing method thereof and a chip, wherein the transistor structure comprises: a substrate, wherein an epitaxial buffer layer, a hetero-conjunctiva layer and an electrode layer which are arranged on the substrate are sequentially laminated along a direction away from the substrate; the electrode layer includes a drain electrode; the substrate base plate comprises an insulating substrate and a conductive substrate; an orthographic projection of the drain electrode on the substrate is at least partially overlapped with the insulating substrate, and at least part of the conductive substrate is positioned at the periphery of the orthographic projection of the drain electrode on the substrate in a direction parallel to the substrate. In the invention, the current path is changed by setting a part of the low-resistance substrate to be high-resistance, so that the current path is prolonged, and the vertical pressure resistance of the device is further improved.

Description

Transistor structure, manufacturing method thereof and chip

Technical Field

The embodiment of the invention relates to the technical field of semiconductors, in particular to a transistor structure, a manufacturing method thereof and a chip.

Background

Gallium nitride high electron mobility transistors (GaN High electron mobility transistor, gaN HEMTs) are lateral power devices, but the withstand voltage capability of silicon-based gallium nitride process (GaN-on-Si) devices is limited by epitaxial materials in addition to lateral device structural dimensions. In general, the voltage endurance capability of the epitaxial material needs to be greater than that of the device, and the thicker the epitaxial material, the higher the vertical voltage endurance capability of the device and the corresponding higher the voltage endurance capability of the device. The withstand voltage capability of the epitaxial material is determined by the average breakdown field strength and the total thickness, and the expression can be written as bvd=e×t, and in general, increasing the withstand voltage class of GaN HEMTs requires increasing the total thickness of the epitaxial material to meet the withstand voltage requirement.

However, the thicker the thickness of the epitaxial material, the larger the stress of the gallium nitride material, the more serious the bending bow value of the epitaxial material, and when the bow value is large, the process flow sheet cannot be carried out and the process flow sheet needs to be scrapped; and thicker silicon substrate materials are also required to control deformation in order to suppress the stress of the gallium nitride material. And the thicker the epitaxial material, the longer the growth time required, the lower the throughput and the higher the cost. Therefore, how to improve the voltage-resistant capability of the epitaxial material and ensure that the thickness of the epitaxial material meets the requirement is also a technical bottleneck for manufacturing the high-voltage gallium nitride high-electron mobility transistor.

Disclosure of Invention

The embodiment of the invention provides a transistor structure, a manufacturing method thereof and a chip, which are used for solving the problem that the existing method can not improve the voltage-resistant capability of an epitaxial material and simultaneously ensure that the thickness of the epitaxial material meets the requirement.

In order to solve the technical problems, the invention is realized as follows:

in a first aspect, an embodiment of the present invention provides a transistor structure, including:

A substrate, wherein an epitaxial buffer layer, a hetero-conjunctiva layer and an electrode layer which are arranged on the substrate are sequentially laminated along a direction away from the substrate; the electrode layer includes a drain electrode;

The substrate base plate comprises an insulating substrate and a conductive substrate;

an orthographic projection of the drain electrode on the substrate is at least partially overlapped with the insulating substrate, and at least part of the conductive substrate is positioned at the periphery of the orthographic projection of the drain electrode on the substrate in a direction parallel to the substrate.

Optionally, an orthographic projection of the drain electrode on the substrate base plate is surrounded by the insulating substrate.

Optionally, the electrode layer further includes a gate electrode and a source electrode; the grid comprises at least one grid part, the source electrode comprises at least one source electrode part, the drain electrode comprises at least one drain electrode part, and the orthographic projection of the grid part on the substrate is positioned between the orthographic projection of the adjacent source electrode part on the substrate and the orthographic projection of the drain electrode part on the substrate;

The insulating substrate comprises at least one first insulating substrate portion, the orthographic projection of the drain electrode on the substrate base plate is surrounded by the corresponding first insulating substrate portion, the first insulating substrate portion comprises first boundaries oppositely arranged along a first direction, and the first boundaries are located between the orthographic projections of the adjacent drain electrode on the substrate base plate and the orthographic projections of the grid electrode on the substrate base plate.

Optionally, the gate includes a plurality of gate portions coupled, the source includes a plurality of source portions coupled, and the drain includes a plurality of drain portions coupled;

The source electrode parts and the drain electrode parts are alternately arranged along a first direction, the grid electrode parts are arranged along the first direction, and the orthographic projection of one source electrode part on the substrate is arranged between the orthographic projections of the adjacent grid electrode parts on the substrate, or the orthographic projection of one drain electrode part on the substrate is arranged between the orthographic projections of the adjacent grid electrode parts on the substrate;

The insulating substrate comprises a plurality of first insulating substrate portions, the substrate base plate comprises a plurality of conductive substrates, the first insulating substrate portions and the conductive substrates are alternately arranged along the first direction, the orthographic projection of the source electrode on the substrate base plate at least partially overlaps with the corresponding conductive substrate, and/or the orthographic projection of the gate electrode on the substrate base plate at least partially overlaps with the corresponding conductive substrate.

Optionally, the insulating substrate includes a second insulating substrate portion surrounding the plurality of first insulating substrate portions and the plurality of conductive substrates, the second insulating substrate portion being formed as a unitary structure with each of the first insulating substrate portions.

Optionally, the conductive substrate completely covers the insulating substrate.

Optionally, the gate part further includes: a gate electrode and a gate layer;

the gate layer is positioned between the hetero-conjunctiva layer and the gate electrode;

The orthographic projection of the gate electrode on the heteroconjunctival layer at least partially overlaps with the orthographic projection of the gate electrode on the heteroconjunctival layer;

wherein the gate layer comprises a P-type gallium nitride layer;

The hetero-conjunctiva layer comprises a gallium nitride layer and an aluminum gallium nitride layer which are arranged in a stacked mode, and the gallium nitride layer is located between the substrate and the aluminum gallium nitride layer.

In a second aspect, embodiments of the present invention provide a chip comprising a transistor junction as claimed in any of the first aspects.

In a third aspect, an embodiment of the present invention provides a method for fabricating a transistor structure, which is used for fabricating a transistor structure according to any one of the first aspect, the method including:

Providing a substrate base plate;

Manufacturing an epitaxial buffer layer on the substrate;

manufacturing a heteroconjunctiva layer on the epitaxial buffer layer;

Manufacturing an electrode layer on the heteroconjunctival layer, wherein the electrode layer comprises a drain electrode;

Patterning the substrate base plate to form an insulating substrate; orthographic projection of the drain electrode on the substrate base plate is at least partially overlapped with the insulating substrate;

And manufacturing a conductive substrate on one side of the epitaxial buffer layer, which is opposite to the electrode layer, wherein at least part of the conductive substrate is positioned at the periphery of orthographic projection of the drain electrode on the substrate.

Optionally, the step of patterning the substrate base plate to form an insulating substrate specifically includes:

thinning the substrate base plate at one side of the substrate base plate, which is opposite to the electrode;

and carrying out a through silicon via technology on the substrate after the thinning operation, removing a local substrate, and forming an insulating substrate, so that orthographic projections of the insulating substrate and the drain electrode on the substrate at least partially overlap.

In the invention, a substrate is arranged, and an epitaxial buffer layer, a heteroconjunctival layer and an electrode layer which are arranged on the substrate are sequentially stacked along the direction away from the substrate; the electrode layer includes a drain electrode; the substrate base plate comprises an insulating substrate and a conductive substrate; an orthographic projection of the drain electrode on the substrate is at least partially overlapped with the insulating substrate, and at least part of the conductive substrate is positioned at the periphery of the orthographic projection of the drain electrode on the substrate in a direction parallel to the substrate. By setting a part of the low-resistance substrate as high resistance, the current which directly flows from the drain electrode to the low-resistance substrate is forced to change the path, and the current needs to bypass a part of the insulating substrate, which is equivalent to increasing the length of the current path, reducing the breakdown risk of the transistor in high-voltage application, further improving the vertical pressure resistance of the device, and solving the problem that the thickness of the epitaxial material can not be ensured to meet the requirement while improving the pressure resistance of the epitaxial material.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:

fig. 1 is a schematic structural diagram of a transistor structure according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of an electrode arrangement of a transistor structure according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of an electrode arrangement of another transistor structure according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of another transistor structure according to an embodiment of the present invention;

fig. 5 is a flowchart of a method for manufacturing a transistor structure according to an embodiment of the present invention;

Fig. 6 is a schematic structural diagram of a transistor structure after an electrode layer is formed according to an embodiment of the present invention;

Fig. 7 is a schematic structural diagram of a thinned substrate of a transistor structure according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of a transistor structure after forming an insulating substrate according to an embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Referring to fig. 1, an embodiment of the present invention provides a transistor structure, including:

a substrate 1, an epitaxial buffer layer 2, a hetero-conjunctiva layer 3 and an electrode layer 4 which are sequentially stacked on the substrate in a direction away from the substrate 1; the electrode layer includes a drain electrode 41;

the substrate base 1 includes an insulating substrate 11 and a conductive substrate 12;

The orthographic projection of the drain electrode on the substrate is at least partially overlapped with the insulating substrate, and at least part of the conductive substrate is positioned at the periphery of the orthographic projection of the drain electrode on the substrate in the direction parallel to the substrate.

In the embodiment of the present invention, the substrate 1 is a basic part of a transistor, the substrate 1 includes an insulating substrate 11 and a conductive substrate 12, and the insulating substrate 11 may be made of a material including, but not limited to, silicon (Si), doped Si, silicon carbide (SiC), germanium silicide (SiGe), gallium arsenide (GaAs), gallium nitride (GaN), or other semiconductor materials. The insulating substrate 11 may include, but is not limited to, sapphire, silicon-on-insulator (SOI, silicon on insulator), or other suitable materials. The insulating substrate 11 provides support and foundation for other parts of the transistor, and can enable the electric leakage to be required to move laterally to reach the bottom substrate, which is equivalent to increasing the effective thickness of material breakdown; the orthographic projection of the drain electrode on the substrate is at least partially overlapped with the insulating substrate, the conductive substrate 12 is made of conductive metal in the direction parallel to the substrate, and at least part of the conductive substrate 12 is positioned at the periphery of the orthographic projection of the drain electrode 41 on the substrate 1; the conductive substrate 12 can guide and change the current trend, so that the electric leakage also needs to move transversely to reach the bottom substrate, so that the current path is prolonged, which is equivalent to increasing the effective thickness of material breakdown, and further improving the vertical voltage resistance of the device.

The epitaxial buffer layer 2 is stacked on the substrate 1 in a direction away from the substrate 1, and the purpose of the epitaxial buffer layer 2 is to reduce crystal defects between the substrate 1 and improve the performance of the device. The epitaxial buffer layer 2 serves to reduce charge migration and electric field effects in the transistor, and serves to reduce instability caused by lattice mismatch between materials during fabrication of the transistor, while also helping to reduce leakage current in the transistor.

The hetero-conjunctiva layer3 is disposed next to the epitaxial buffer layer2, and the hetero-conjunctiva layer3 is far from the substrate 1 to a higher extent than the epitaxial buffer layer2, and in the hetero-conjunctiva layer3, the heterojunction refers to a junction formed by two different semiconductor materials in contact, which has different band gap widths. This structure is very important for regulating the current flow and the electronic characteristics.

Further, the hetero-conjunctival layer 3 may include: a first nitride semiconductor layer 31 and a second nitride semiconductor layer 32, the first nitride semiconductor layer 31 may include a group III-V layer. The first nitride semiconductor layer 31 may include, but is not limited to, a group III nitride. The first nitride semiconductor layer may include a gallium nitride (GaN) layer. The energy gap of GaN is about 3.4eV.

The second nitride semiconductor layer 32 may be disposed on the first nitride semiconductor layer 31 and has a band gap greater than that of the first nitride semiconductor layer 31. The second nitride semiconductor layer 32 may include a group III-V layer. The second nitride semiconductor layer 32 may include, but is not limited to, group III nitrides, such as compounds InaAlbGa-a-bN, where a+b+.ltoreq.1. The group III nitride may further include, but is not limited to, for example, compound AlaGa (1-a) N, where a+.1. The energy gap of the second nitride semiconductor layer 32 may be larger than that of the first nitride semiconductor layer 31. The second nitride semiconductor layer 32 may include an aluminum gallium nitride (AlGaN) layer. The energy gap of AlGaN is about 4.0eV. A heterojunction may be formed between the second nitride semiconductor layer 32 and the first nitride semiconductor layer 31, and polarization of the heterojunction forms a two-dimensional electron gas (two-dimensional electron gas,2 DEG) region in the first nitride semiconductor layer 31.

In a specific application scenario, the hetero-conjunctiva layer 3 may include a gallium nitride layer and an aluminum gallium nitride layer that are stacked, with the gallium nitride layer being located between the epitaxial buffer layer and the aluminum gallium nitride layer.

The electrode layer 4 is a conductive portion connected to the transistor for controlling inflow and outflow of current, and the electrode layer 4 includes: and a drain electrode 41. The orthographic projection of the drain electrode on the substrate is at least partially overlapped with the insulating substrate, and at least part of the conductive substrate is positioned at the periphery of the orthographic projection of the drain electrode on the substrate in the direction parallel to the substrate. The orthographic projection of the drain electrode at least partially overlaps, which means that a portion of the drain electrode overlaps the insulating substrate 11 in the vertical direction, which design helps to optimize the current control and overall performance of the transistor.

In the embodiment of the invention, a substrate is arranged, and an epitaxial buffer layer, a heteroconjunctival layer and an electrode layer which are arranged on the substrate are sequentially laminated along the direction away from the substrate; the electrode layer includes a drain electrode; the substrate base plate comprises an insulating substrate and a conductive substrate; an orthographic projection of the drain electrode on the substrate is at least partially overlapped with the insulating substrate, and at least part of the conductive substrate is positioned at the periphery of the orthographic projection of the drain electrode on the substrate in a direction parallel to the substrate. By setting a part of the low-resistance substrate as high resistance, the current which directly flows from the drain electrode to the low-resistance substrate is forced to change the path, and the current needs to bypass the insulating substrate, which is equivalent to increasing the length of the current path, reducing the breakdown risk of the transistor in high-voltage application, further improving the vertical pressure resistance of the device, and solving the problem that the thickness of the epitaxial material can not be ensured to meet the requirement while the pressure resistance of the epitaxial material is improved.

In an embodiment of the invention, optionally, the orthographic projection of the drain 41 on the substrate base plate 1 is surrounded by the insulating substrate 11.

In the embodiment of the present invention, the contour of the insulating substrate 11 formed on the substrate 1 completely surrounds the contour of the drain electrode 41 formed on the substrate, that is, the orthographic projection of the drain electrode 41 on the substrate 1 is located inside the insulating substrate 11. By surrounding the drain electrode 41 with the insulating substrate 11, the current passing through the drain electrode 41 can be precisely controlled, the length of the current path is prolonged, which corresponds to an increase in the effective thickness of the material breakdown, and the vertical withstand voltage of the device is further improved.

Referring to fig. 2, in an embodiment of the present invention, the electrode layer 4 further includes a gate electrode 42 and a source electrode 43; the gate electrode 42 comprises at least one gate electrode portion, the source electrode 43 comprises at least one source electrode portion, the drain electrode 41 comprises at least one drain electrode portion, and the orthographic projection of the gate electrode portion on the substrate 1 is positioned between the orthographic projection of the adjacent source electrode portion on the substrate 1 and the orthographic projection of the drain electrode portion on the substrate 1;

The insulating substrate 11 comprises at least one first insulating substrate portion, the orthographic projection of the drain electrode 41 on the substrate 1 being surrounded by a corresponding first insulating substrate portion, the first insulating substrate portion comprising first boundaries oppositely arranged along a first direction, the first boundaries being located between the orthographic projection of the adjacent drain electrode 41 on the substrate 1 and the orthographic projection of the gate electrode 42 on the substrate 1.

In the embodiment of the present invention, the drain 41, the gate 42, and the source 43 are main constituent parts in the transistor. Drain 41 is the output of the transistor and is responsible for receiving electrons or charges. The drain portion depends from the drain, referring to one or more regions of the drain. The Gate 42 (Gate) is the control terminal of the transistor, by which the conductivity of the channel region can be adjusted. The gate portion belongs to the gate, and the gate portion refers to one or more regions of the gate. The source 43 is the input of the transistor and is responsible for providing electrons or charges. The source portion depends from the source, referring to one or more regions of the source. Among them, the drain electrode 41 and the drain electrode portion, the gate electrode 42 and the gate electrode portion, and the source electrode 43 and the source electrode portion may form a comb-like structure.

In addition, the insulating substrate 11 comprises at least one first insulating substrate portion, the orthographic projection of the drain electrode 41 on the substrate base plate 1 being surrounded by a corresponding first insulating substrate portion, the first insulating substrate portion comprising first boundaries oppositely arranged along a first direction, the first boundaries being located between the orthographic projection of the adjacent drain electrode 41 on the substrate base plate 1 and the orthographic projection of the gate electrode 42 on the substrate base plate 1.

In an embodiment of the present invention, optionally, the gate includes a plurality of gate portions coupled to each other, the source includes a plurality of source portions coupled to each other, and the drain includes a plurality of drain portions coupled to each other, which may form a comb structure.

The source electrode parts and the drain electrode parts are alternately arranged along a first direction, the grid electrode parts are arranged along the first direction, and the orthographic projection of one source electrode part on the substrate is arranged between the orthographic projections of the adjacent grid electrode parts on the substrate, or the orthographic projection of one drain electrode part on the substrate is arranged between the orthographic projections of the adjacent grid electrode parts on the substrate;

The insulating substrate comprises a plurality of first insulating substrate portions, the substrate base plate comprises a plurality of conductive substrates, the first insulating substrate portions and the conductive substrates are alternately arranged along the first direction, the orthographic projection of the source electrode on the substrate base plate at least partially overlaps with the corresponding conductive substrate, and/or the orthographic projection of the gate electrode on the substrate base plate at least partially overlaps with the corresponding conductive substrate.

In the embodiment of the present invention, the source portions and the drain portions are alternately arranged along the first direction, where the first direction may be a horizontal direction, and the alternate arrangement means that one drain portion is disposed beside each source portion, and vice versa (but not representing that two source portions must be disposed adjacently, as shown in fig. 2, there is a source portion, and two adjacent sides of the source portion are disposed with gate portions), where a front projection of a source portion on the substrate is between front projections of adjacent gate portions on the substrate, or a front projection of a drain portion on the substrate is between front projections of adjacent gate portions on the substrate. That is, the two gates are not disposed adjacently, and the source portion or the drain portion needs to be spaced apart from each other in the middle. Thus, by creating a specific spatial arrangement between gate, source and drain, the flow of current and the overall performance of the transistor can be optimized. This alternating design helps achieve higher integration and more accurate current control, which is critical to the fabrication of high performance, high density transistors.

In this embodiment of the present invention, as shown in fig. 1 and 2, the length of the first insulating substrate portion along the first direction exceeds the length of the drain portion, and is greater than the width of the drain portion along the first direction; and/or the conductive substrate exceeds the length of the grid along a first direction and is larger than the width of the grid along the first direction; and/or the length of the conductive substrate along the first direction exceeds the length of the source electrode and is larger than the width of the source electrode along the first direction. The design can further improve the voltage-resistant capability of the device and is beneficial to reducing leakage current.

It should be noted that, since bvd=e×d, that is, the withstand voltage capability of the epitaxial material is determined by the average breakdown field strength and the total thickness of the epitaxial material, after the insulating substrate and the conductive substrate are disposed, it is achieved that the length d of the leakage path in the off state is greater than the total thickness t of the epitaxial material, and the length d of the leakage path in the off state is related to the total thickness t (not shown as t in fig. 1) of the epitaxial material (as shown in fig. 1) and the dimension I (as shown in fig. 2) of the insulating substrate, where the larger I is in the case where t is fixed, the larger d is in the length of the leakage path in the off state, so in the embodiment of the present invention, the vertical withstand voltage of the device is greater than the vertical withstand voltage of the epitaxial material, and the vertical withstand voltage capability of the device is higher. That is, the path of the current can be changed by changing the dimension I of the insulating substrate, thereby changing the vertical withstand voltage capability of the device. In a specific application, the same epitaxial material can be used for manufacturing devices with higher voltage withstand grades according to practical situations, or thinner epitaxial material can be used for manufacturing devices with the same voltage withstand grade.

In an embodiment of the present invention, optionally, the insulating substrate includes a second insulating substrate portion, and the second insulating substrate portion surrounds the plurality of first insulating substrate portions and the plurality of conductive substrates, and the second insulating substrate portion is formed as a unitary structure with each of the first insulating substrate portions.

Referring to fig. 3, in an embodiment of the present invention, the second insulating substrate portion extends beyond the length of the drain portion and beyond the length of the conductive substrate in the first direction, and surrounds the plurality of first insulating substrate portions and the plurality of conductive substrates, and the second insulating substrate portion and each of the first insulating substrate portions are formed as a unitary structure. The design can further improve the voltage-resistant capability of the device and is beneficial to reducing leakage current.

In an embodiment of the present invention, optionally, the conductive substrate completely covers the insulating substrate.

Referring to fig. 4, in the embodiment of the present invention, after the insulating substrate 11 is processed, the conductive substrate 12 is completely covered on the insulating substrate 11 by adopting a method of back thinning (Backside Gridding, BG) and back metallization (Backside Metallization, BM) or depositing a metal material, and the conductive substrate 12 is made of a conductive metal.

In an embodiment of the present invention, optionally, the gate portion further includes: a gate electrode and a gate layer;

the gate layer is positioned between the hetero-conjunctiva layer and the gate electrode;

The orthographic projection of the gate electrode on the heteroconjunctival layer at least partially overlaps with the orthographic projection of the gate electrode on the heteroconjunctival layer;

wherein the gate layer comprises a P-type gallium nitride layer;

The hetero-conjunctiva layer comprises a gallium nitride layer and an aluminum gallium nitride layer which are arranged in a stacked mode, and the gallium nitride layer is located between the substrate and the aluminum gallium nitride layer.

In an embodiment of the present invention, the gate portion further includes: a gate electrode 421 and a gate layer 422; the gate layer 422 is located between the hetero-conjunctiva layer 3 and the gate electrode 421; the orthographic projection of the gate electrode 422 onto the hetero-conjunctiva layer 3 at least partially overlaps with the orthographic projection of the gate electrode 421 onto the hetero-conjunctiva layer 3; wherein the gate layer 422 may be doped. The gate layer 422 may comprise a p-type dopant, and in particular, the gate layer 422 may comprise a p-type doped GaN layer, a p-type doped AlGaN layer, a p-type doped AlN layer, or other suitable III-V layer. The p-type dopant may include magnesium (Mg), beryllium (Be), zinc (Zn), and cadmium (Cd). In a specific application scenario, the gate layer 422 may include a P-type gallium nitride layer. The gate layer 422 is typically used to regulate the flow of current and control the distribution of charge.

The orthographic projection of the gate portion on the substrate 1 is located between the orthographic projection of the adjacent source portion on the substrate 1 and the orthographic projection of the drain portion on the substrate 1, that is, the gate portion is located between the source portion and the drain portion when viewed from above.

In the embodiment of the invention, by setting a part of the low-resistance substrate as the high-resistance insulating substrate, the breakdown risk of the transistor in high-voltage application is reduced, and meanwhile, the extra stress and the cost caused by the traditional method (increasing the thickness of the epitaxial material) are avoided, so that if the method disclosed by the embodiment of the invention is applied, the epitaxial buffer layer can be designed to be thinner, so that the extra stress and the cost are avoided.

Referring to fig. 1, in the embodiment of the present invention, M1 is an upper metal layer, and SFP is a field plate. M1 generally refers to a layer of metal connections in a transistor that are generally located at an upper layer in a multi-layer metal interconnect structure for providing electrical connection and signal transmission. The main roles of M1 include: connection circuit element: the M1 layer connects different elements inside the transistor, such as source, drain and gate; and (3) signal transmission: m1 is responsible for transmitting signals so that electrons inside the transistor can move according to the circuit design; power distribution and thermal management: in some designs, the upper layer metal is also used to distribute power and aid in heat dissipation. SFP is the part of a transistor that is used to control the electric field distribution. Its roles and functions include: regulating and controlling an electric field: the field plates help control and adjust the electric field distribution within the transistor by their structure and placement; improving the device performance: by controlling the electric field, the leakage current is reduced, the threshold voltage stability is improved, and the switching characteristic of the device is improved; the reliability of the device is improved: the proper electric field distribution can reduce hot spots in the transistor, thereby improving the reliability and durability of the device.

In summary, in the embodiment of the present invention, the flow direction of the current under the drain in the off state is changed by setting a portion of the low-resistance substrate as the high-resistance insulating substrate, and the average electric field is reduced by increasing the distance of the current flowing from the drain to the substrate, so as to improve the vertical withstand voltage capability of the device. In a specific application scene, devices with higher voltage withstand grades can be manufactured by using the same epitaxial material, for example, 900V can be manufactured by using the epitaxial material of the existing 650V device, devices with the same voltage withstand grade can be manufactured by using thinner epitaxial material, and the growth time and cost of the epitaxial material are reduced; different vertical withstand voltages can be obtained by adjusting the length of the insulating material, or devices with different withstand voltage grades can be manufactured by using the same epitaxial structure.

In general, the transistor in the embodiment of the invention improves the vertical voltage endurance capability of the device and simultaneously increases the flexibility and the cost efficiency of manufacturing devices with different voltage endurance levels. By providing a portion of the low-resistance substrate as a high-resistance insulating substrate, the layout not only changes the flow path of the current but also increases the withstand voltage capability of the device. In conventional transistor designs, current flows primarily in the vertical direction, and by changing the current path to move it laterally, the vertical withstand voltage capability of the device can be significantly improved. And by adjusting the dimensions of the insulating substrate portion, the vertical withstand voltage capability of the device can be flexibly controlled, which is an important advantage in the design of high electron mobility transistors, as it allows devices of different performance levels to be fabricated using the same basic structure. In addition, by using thinner epitaxial materials or the same epitaxial materials to fabricate devices of higher withstand voltage levels, production costs and time can be effectively reduced, which not only improves performance, but also improves manufacturing efficiency and cost effectiveness.

The embodiment of the invention also provides a chip, which comprises the transistor structure provided by the embodiment and also has the technical effects as described above.

Referring to fig. 5, an embodiment of the present invention provides a method for manufacturing a transistor structure, which is used for manufacturing the transistor structure provided in the above embodiment, and the method includes:

step S101: providing a substrate base plate;

In an embodiment of the present invention, a substrate is provided as a starting point for transistor fabrication. The substrate base plate is typically made of silicon or other semiconductor material as a support platform for subsequent layers.

Step S102: manufacturing an epitaxial buffer layer on the substrate;

In the embodiment of the invention, the epitaxial buffer layer is manufactured on the substrate, the epitaxial buffer layer 2 is stacked on the substrate 1 along the direction away from the substrate 1, and the purpose of the epitaxial buffer layer 2 is to reduce crystal defects between the substrate 1 and the active layer and improve the performance of the device. The epitaxial buffer layer 2 serves to reduce charge migration and electric field effects in the transistor, and serves to reduce instability caused by lattice mismatch between materials during fabrication of the transistor, while also helping to reduce leakage current in the transistor.

Step S103: manufacturing a heteroconjunctiva layer on the epitaxial buffer layer;

In an embodiment of the invention, a hetero-conjunctiva layer is fabricated on an epitaxial buffer layer. The hetero-conjunctiva layer 3 is disposed next to the epitaxial buffer layer 2, and the hetero-conjunctiva layer 3 is far from the substrate 1 to a higher extent than the epitaxial buffer layer 2, and in the hetero-conjunctiva layer 3, the heterojunction refers to a junction formed by two different semiconductor materials in contact, which has different band gap widths. This structure is very important for regulating the current flow and the electronic characteristics. The hetero-conjunctiva layer is composed of different semiconductor materials, such as gallium nitride and aluminum gallium nitride, for forming a two-dimensional electron gas channel.

Step S104: manufacturing an electrode layer on the heteroconjunctival layer, wherein the electrode layer comprises a drain electrode;

In an embodiment of the invention, an electrode layer is fabricated on the hetero-conjunctival layer. The electrode layer 4 is a conductive portion connected to the transistor for controlling inflow and outflow of current, and the electrode layer 4 includes: and a drain electrode 41. The orthographic projection of the drain electrode on the substrate is at least partially overlapped with the insulating substrate, and at least part of the conductive substrate is positioned at the periphery of the orthographic projection of the drain electrode on the substrate in the direction parallel to the substrate. The orthographic projection of the drain electrode at least partially overlaps, which means that a portion of the drain electrode overlaps the insulating substrate 11 in the vertical direction, which design helps to optimize the current control and overall performance of the transistor. Which includes a drain electrode, the electrode layer being responsible for connection to the conductive portion of the transistor for controlling the inflow and outflow of current. The product after the electrode layer is formed is shown in fig. 6.

Step S105: patterning the substrate base plate to form an insulating substrate; orthographic projection of the drain electrode on the substrate base plate is at least partially overlapped with the insulating substrate;

In an embodiment of the present invention, the step of patterning the substrate to form the insulating substrate specifically includes: carrying out thinning operation on the substrate base plate at one side of the substrate base plate, which is opposite to the electrode, wherein the thinning operation is shown in fig. 7; and carrying out through silicon via technology on the substrate after the thinning operation, removing a local substrate, and forming an insulating substrate, so that orthographic projection of the insulating substrate and the drain electrode on the substrate at least partially overlaps, as shown in fig. 8. The insulating substrate 11 may be made of a material including, but not limited to, silicon (Si), doped Si, silicon carbide (SiC), germanium silicide (SiGe), gallium arsenide (GaAs), gallium nitride (GaN), or other semiconductor materials. Insulating substrate 11 may include, but is not limited to, sapphire, silicon-on-insulator (SOI, silicon on insulator) or other suitable materials, insulating substrate 11 providing support and foundation for other portions of the transistor, and may enable leakage to also require lateral movement to reach the underlying substrate, equivalent to increasing the effective thickness of material breakdown; the orthographic projection of the drain electrode on the substrate base plate at least partially overlaps the insulating substrate in a direction parallel to the substrate base plate.

Step S106: and manufacturing a conductive substrate on one side of the epitaxial buffer layer, which is opposite to the electrode layer, wherein at least part of the conductive substrate is positioned at the periphery of orthographic projection of the drain electrode on the substrate.

In the embodiment of the present invention, after the substrate is patterned to form the insulating substrate 11, the conductive substrate 12 completely covers the insulating substrate 11 by adopting a method of back thinning (Backside Gridding, BG) and back metallization (Backside Metallization, BM) or depositing a metal material, as shown in fig. 4; or such that the insulating substrates 11 and the conductive substrates 12 are alternately arranged along the first direction, the insulating substrates 11 completely covering the conductive substrates 12 as shown in fig. 1 to 3. The conductive substrate 12 is made of conductive metal, and at least part of the conductive substrate 12 is positioned at the periphery of orthographic projection of the drain electrode 41 on the substrate 1; the current is guided and changed through the conductive substrate 12, so that the electric leakage also needs to move laterally to reach the bottom substrate, so that the current path is prolonged, which is equivalent to increasing the effective thickness of material breakdown, and further improving the vertical voltage resistance of the device.

In the embodiment of the invention, the passivation layer can be manufactured on the electrode layer, and the addition of the passivation layer is beneficial to protecting the electrode and preventing damage caused by environmental factors, so that the service life of the transistor is prolonged.

In the embodiment of the invention, a substrate is arranged, and an epitaxial buffer layer, a heteroconjunctival layer and an electrode layer which are arranged on the substrate are sequentially laminated along the direction away from the substrate; the electrode layer includes a drain electrode; the substrate base plate comprises an insulating substrate and a conductive substrate; an orthographic projection of the drain electrode on the substrate is at least partially overlapped with the insulating substrate, and at least part of the conductive substrate is positioned at the periphery of the orthographic projection of the drain electrode on the substrate in a direction parallel to the substrate. By setting a part of the low-resistance substrate as the high-resistance insulating substrate, the current which originally directly flows vertically from the drain electrode to the insulating substrate is forced to change the path, and the current needs to bypass the insulating substrate, which is equivalent to increasing the current path length, reducing the breakdown risk of the transistor in high-voltage application, further improving the vertical pressure resistance of the device, and solving the problem that the thickness of the epitaxial material can not be ensured to meet the requirement while the pressure resistance of the epitaxial material can not be improved.

In some embodiments, the step of patterning the substrate base plate to form an insulating substrate specifically includes:

thinning the substrate base plate at the side of the substrate base plate facing away from the electrode, as shown in fig. 7;

And carrying out through silicon via technology on the substrate after the thinning operation, removing a local substrate, and forming an insulating substrate, so that orthographic projection of the insulating substrate and the drain electrode on the substrate at least partially overlaps, as shown in fig. 8.

Unless otherwise specified, spatial descriptions as "on …", "under …", "upward", "left", "right", "downward", "top", "bottom", "vertical", "horizontal", "side", "above", "below", "upper", "above …", "below …" are indicated with respect to the orientation shown in the drawings. It should be understood that the spatial descriptions used herein are for illustration purposes only, and that the actual implementation of the structures described herein may be spatially arranged in any orientation or manner, provided that the advantages of the embodiments of the present disclosure do not deviate from such an arrangement.

As used herein, the term "vertical" is used to refer to both upward and downward directions, while the term "horizontal" refers to a direction transverse to the vertical direction.

As used herein, the terms "about," "substantially," "generally," and "about" are used to describe and explain minor variations. When used in connection with an event or circumstance, the term can refer to instances where the event or circumstance occurs precisely and instances where it occurs to the close approximation. For example, when used in connection with a numerical value, the term can refer to a range of variation of less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, a first value may be considered "substantially" the same as or equal to a second value if the first value is within less than or equal to ±10% of the second value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, "substantially" perpendicular may refer to a range of angular variation of less than or equal to ±10° relative to 90 °, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1° or less than or equal to ±0.05°.

Two surfaces may be considered to be coplanar or substantially coplanar if the displacement between the surfaces is no more than 5 μm, no more than 2 μm, no more than 1 μm, or no more than 0.5 μm. A surface may be considered substantially flat if the shift between the highest point and the lowest point of the surface is no more than 5 μm, no more than 2 μm, no more than 1 μm, or no more than 0.5 μm.

As used herein, the singular terms "a" and "an" may include plural referents unless the context clearly dictates otherwise.

As used herein, the terms "conductive", "conductive (ELECTRICALLY CONDUCTIVE)" and "conductivity" refer to the ability to carry electrical current. Conductive materials generally indicate those materials that exhibit little or no opposition to the flow of current. One measure of conductivity is Siemens per meter (S/m). Typically, the conductive material is one having a conductivity greater than about 104S/m (e.g., at least 105S/m or at least 106S/m). The conductivity of a material can sometimes vary with temperature. Unless specified otherwise, the conductivity of the material is measured at room temperature.

Further, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity and should be interpreted flexibly to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited.

While the present disclosure has been depicted and described with reference to particular embodiments thereof, such depicted and described are not meant to be limiting. It will be understood by those skilled in the art that various changes may be made and equivalents substituted without departing from the true spirit and scope of the disclosure as defined by the appended claims. The illustrations may not be drawn to scale. There may be a distinction between process reproduction and actual equipment in the present disclosure due to manufacturing processes and tolerances. Other embodiments of the present disclosure are possible that are not specifically described. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to particular operations being performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of operations is not a limitation of the present disclosure.

Claims (10)

1. A transistor structure, comprising:

A substrate, wherein an epitaxial buffer layer, a hetero-conjunctiva layer and an electrode layer which are arranged on the substrate are sequentially laminated along a direction away from the substrate; the electrode layer includes a drain electrode;

The substrate base plate comprises an insulating substrate and a conductive substrate;

an orthographic projection of the drain electrode on the substrate is at least partially overlapped with the insulating substrate, and at least part of the conductive substrate is positioned at the periphery of the orthographic projection of the drain electrode on the substrate in a direction parallel to the substrate.

2. The transistor structure according to claim 1, wherein,

An orthographic projection of the drain electrode on the substrate base plate is surrounded by the insulating substrate.

3. A transistor structure according to claim 1 or 2, characterized in that,

The electrode layer further comprises a grid electrode and a source electrode; the grid comprises at least one grid part, the source electrode comprises at least one source electrode part, the drain electrode comprises at least one drain electrode part, and the orthographic projection of the grid part on the substrate is positioned between the orthographic projection of the adjacent source electrode part on the substrate and the orthographic projection of the drain electrode part on the substrate;

The insulating substrate comprises at least one first insulating substrate portion, the orthographic projection of the drain electrode on the substrate base plate is surrounded by the corresponding first insulating substrate portion, the first insulating substrate portion comprises first boundaries oppositely arranged along a first direction, and the first boundaries are located between the orthographic projections of the adjacent drain electrode on the substrate base plate and the orthographic projections of the grid electrode on the substrate base plate.

4. The transistor structure according to claim 3, wherein,

The grid comprises a plurality of grid parts which are coupled, the source electrode comprises a plurality of source electrode parts which are coupled, and the drain electrode comprises a plurality of drain electrode parts which are coupled;

The source electrode parts and the drain electrode parts are alternately arranged along a first direction, the grid electrode parts are arranged along the first direction, and the orthographic projection of one source electrode part on the substrate is arranged between the orthographic projections of the adjacent grid electrode parts on the substrate, or the orthographic projection of one drain electrode part on the substrate is arranged between the orthographic projections of the adjacent grid electrode parts on the substrate;

The insulating substrate comprises a plurality of first insulating substrate portions, the substrate base plate comprises a plurality of conductive substrates, the first insulating substrate portions and the conductive substrates are alternately arranged along the first direction, the orthographic projection of the source electrode on the substrate base plate at least partially overlaps with the corresponding conductive substrate, and/or the orthographic projection of the gate electrode on the substrate base plate at least partially overlaps with the corresponding conductive substrate.

5. The transistor structure according to claim 4, wherein,

The insulating substrate includes a second insulating substrate portion surrounding the plurality of first insulating substrate portions and the plurality of conductive substrates, the second insulating substrate portion being formed as a unitary structure with each of the first insulating substrate portions.

6. The transistor structure according to claim 3, wherein,

The conductive substrate completely covers the insulating substrate.

7. The transistor structure according to claim 1, wherein,

The gate portion further includes: a gate electrode and a gate layer;

the gate layer is positioned between the hetero-conjunctiva layer and the gate electrode;

The orthographic projection of the gate electrode on the heteroconjunctival layer at least partially overlaps with the orthographic projection of the gate electrode on the heteroconjunctival layer;

wherein the gate layer comprises a P-type gallium nitride layer;

The hetero-conjunctiva layer comprises a gallium nitride layer and an aluminum gallium nitride layer which are arranged in a stacked mode, and the gallium nitride layer is located between the substrate and the aluminum gallium nitride layer.

8. A chip comprising a transistor junction according to any of claims 1-7.

9. A method of fabricating a transistor structure according to any of claims 1-7, the method comprising:

Providing a substrate base plate;

Manufacturing an epitaxial buffer layer on the substrate;

manufacturing a heteroconjunctiva layer on the epitaxial buffer layer;

Manufacturing an electrode layer on the heteroconjunctival layer, wherein the electrode layer comprises a drain electrode;

Patterning the substrate base plate to form an insulating substrate; orthographic projection of the drain electrode on the substrate base plate is at least partially overlapped with the insulating substrate;

And manufacturing a conductive substrate on one side of the epitaxial buffer layer, which is opposite to the electrode layer, wherein at least part of the conductive substrate is positioned at the periphery of orthographic projection of the drain electrode on the substrate.

10. The method of fabricating a transistor structure according to claim 9, wherein the patterning the substrate base plate to form an insulating substrate comprises:

thinning the substrate base plate at one side of the substrate base plate, which is opposite to the electrode;

and carrying out a through silicon via technology on the substrate after the thinning operation, removing a local substrate, and forming an insulating substrate, so that orthographic projections of the insulating substrate and the drain electrode on the substrate at least partially overlap.