CN117976540A

CN117976540A - Semiconductor power device and manufacturing method thereof

Info

Publication number: CN117976540A
Application number: CN202410189280.9A
Authority: CN
Inventors: 吴毅锋; 曾凡明; 高吴昊
Original assignee: Zhuhai Ga Future Technology Co ltd
Current assignee: Zhuhai Ga Future Technology Co ltd
Priority date: 2024-02-20
Filing date: 2024-02-20
Publication date: 2024-05-03

Abstract

The invention discloses a manufacturing method of a semiconductor power device, which comprises the steps of preparing an epitaxial layer, preparing a dielectric lamination, preparing a source electrode and a drain electrode, growing an interface barrier layer, and preparing a grid electrode and a grid electrode field plate. The invention also provides a semiconductor power device. According to the invention, before gate metal evaporation or gate etching, an interface barrier layer is grown, so that the contact position of the gate field plate and the functional insulating layer/dielectric stack is covered in advance. In this way, the insulating region contacting the bottom of the field plate is modified from a boundary surface originally comprising a plurality of layers of low quality materials damaged by the process to a single high quality dielectric material.

Description

Semiconductor power device and manufacturing method thereof

Technical Field

The invention relates to a semiconductor device, in particular to a semiconductor power device and a manufacturing method thereof.

Background

Gallium nitride high electron mobility transistor GaN HEMT (High Electron Mobility Transistors) is representative of Wide Bandgap (WBG) power semiconductor devices, which has great potential for high frequency power applications. In a GaN HEMT device, the introduction of a field plate can reduce the original electric field peak, but for a high-voltage device, an ideal electric field distribution is often difficult to realize by a single field plate, and each layer of field plate from a gate to a drain direction can further modulate the electric field peak generated by the previous field plate by using a stepped multipole gate field plate, so that an optimized electric field distribution can be obtained by adjusting the length and the height of each layer of field plate, so as to realize higher withstand voltage. However, in the existing step-shaped multilayer field plates, different dielectric materials are used in the manufacturing process and are alternately overlapped to generate the step-shaped field plates, and each electric field peak is possibly caused to be exactly positioned at the junction of the three materials of the field plate/the dielectric/the functional insulating layer. The interface morphology at the junction is complex, different laminated materials are difficult to align in the manufacturing process, etching damage exists to a certain extent, if the material quality and the material interface quality are not good enough, local electric field distribution is possibly uneven, and an uncontrollable electric field peak area is easy to break down and lose efficacy in use.

Disclosure of Invention

The invention provides a manufacturing method of a semiconductor power device, which is used for solving the problems that in the existing manufacturing process of the semiconductor power device, when a field plate structure is directly contacted with side sections of multiple layers of different media, the contact surface formed by the sections of the multiple layers of materials is generally uneven and flat due to the limitation of a process, the uniformity of electric field distribution near the contact surface is poor, the reliability of a product is influenced and the like.

The invention also provides a semiconductor power device.

In order to achieve the purpose of the invention, the invention provides a manufacturing method of a semiconductor power device, which comprises the following steps:

a. Preparing an epitaxial layer: sequentially growing a buffer layer, a channel layer, a barrier layer and a passivation layer on a substrate to obtain the epitaxial layer;

b. Preparing a medium lamination: growing a dielectric lamination layer on the upper surface of the passivation layer, wherein the dielectric lamination layer comprises a plurality of dielectric layers and a functional insulating layer arranged between two adjacent dielectric layers;

c. Source and drain electrodes were prepared: defining a source electrode position and a drain electrode position on the dielectric lamination, removing dielectric layer, passivation layer and barrier layer materials corresponding to the source electrode position and the drain electrode position, arranging source electrode metal at the source electrode position, and arranging drain electrode metal at the drain electrode position;

d. And (3) growing an interface barrier layer: defining the positions of a grid electrode and a grid electrode field plate on a dielectric stack layer between a source electrode and a drain electrode, removing part of dielectric stack layer materials, and growing an interface barrier layer on the upper surface of the rest dielectric stack layer and the removed position of the dielectric stack layer; ;

e. Preparing a grid electrode and a grid electrode field plate: and removing the interface barrier layer material corresponding to the gate position or removing the interface barrier layer material and part of the dielectric lamination material corresponding to the gate position, and respectively arranging a gate and a gate field plate at the gate and the gate field plate position to obtain the semiconductor power device.

In some embodiments of the present invention, in some embodiments,

In the step b, the dielectric stack comprises a first dielectric layer, a first functional insulating layer, a second dielectric layer, a second functional insulating layer and a third dielectric layer which are stacked;

In the step d, etching the third dielectric layer and the second dielectric layer between the source electrode and the drain electrode, removing the first functional insulating layer and the second functional insulating layer, and growing an interface barrier layer on the upper surface of the third dielectric layer and at the positions of the etching of the dielectric layer and the removal of the functional insulating layer;

and e, removing the interface barrier layer and the first dielectric layer material corresponding to the gate position at the position of defining the gate position and the gate field plate, and respectively arranging the gate and the gate field plate at the gate position and the gate field plate position to obtain the semiconductor power device.

In some embodiments of the present invention, in some embodiments,

In the step d, etching the third dielectric layer and the second dielectric layer between the source electrode and the drain electrode, removing the second functional insulating layer before etching the second dielectric layer, and growing an interface barrier layer on the upper surface of the third dielectric layer, the etching position of the dielectric layer and the exposed functional insulating layer;

in step e, the interface barrier layer, the functional insulating layer and the first dielectric layer material corresponding to the gate position are removed at the positions of defining the gate position and the gate field plate, and the gate field plate are respectively arranged at the positions of the gate and the gate field plate, so that the semiconductor power device is obtained.

In some embodiments of the present invention, in some embodiments,

In the step b, the dielectric lamination comprises a first dielectric layer, a first functional insulating layer and a second dielectric layer which are laminated;

In the step d, etching the first dielectric layer and the second dielectric layer between the source electrode and the drain electrode, removing the first functional insulating layer, and growing an interface barrier layer on the upper surface of the second dielectric layer, the etching position of the dielectric layer, the removing position of the functional insulating layer and the upper surface of part of the passivation layer;

And e, removing the interface barrier layer material corresponding to the gate position at the position of defining the gate position and the gate field plate, and respectively arranging the gate and the gate field plate at the gate position and the gate field plate position to obtain the semiconductor power device.

In some embodiments of the present invention, in some embodiments,

In the step d, etching the first dielectric layer and the second dielectric layer between the source electrode and the drain electrode, removing the first functional insulating layer before etching the first dielectric layer, and growing an interface barrier layer on the upper surface of the second dielectric layer, the etching position of the dielectric layer and the upper surface of part of the passivation layer;

Further, the gate field plate is a stepped multilayer field plate, and the shape of the upper surface of the interface barrier layer corresponding to the position of the gate field plate is the same as the shape of the gate field plate.

Further, the interfacial barrier layer is made of silicon dioxide, silicon nitride, diamond, aluminum nitride, or gallium oxide material.

Further, the semiconductor power device is a switching device or an amplifier made of one semiconductor material of gallium nitride, diamond, gallium oxide, aluminum nitride, silicon carbide and silicon.

Further, the gate metal and the gate field plate are made of one or more of aluminum, nickel, titanium, copper, tungsten, and titanium nitride materials.

The invention also provides a semiconductor power device, comprising:

An epitaxial layer comprising a substrate, a buffer layer, a channel layer, a barrier layer and a passivation layer which are stacked;

The dielectric lamination is arranged on the upper surface of the passivation layer and comprises a plurality of dielectric layers and a functional insulating layer arranged between two adjacent dielectric layers;

the source electrode and the drain electrode are distributed on two sides of the grid electrode at intervals;

An interface barrier layer which is arranged on the dielectric stack between the source electrode and the drain electrode and covers the upper surface of the dielectric stack, part of the dielectric stack or part of the upper surface of the passivation layer;

The grid electrode covers part of the upper surface of the passivation layer and forms ohmic contact with the passivation layer, and the grid electrode field plate is connected with the grid electrode and is arranged on the upper surface of the interface barrier layer.

The beneficial effects of the invention are as follows: according to the invention, before gate metal evaporation or gate etching, an interface barrier layer is grown, so that the contact position of the gate field plate and the functional insulating layer/dielectric stack is covered in advance. Thus, the insulating area contacted with the bottom of the field plate is changed from the interface originally containing a plurality of layers of low-quality materials damaged by the process to a single high-quality dielectric material, thereby improving the reliability of the device. On the other hand, as the newly grown interface barrier layer is covered on the original etched sharp dielectric step, a more gentle new step can be generated, and the electric field concentration effect can be further weakened, so that the reliability is improved. In addition, compared with the traditional structure, the invention does not need to add extra photoetching steps, and even can reduce the etching times, thereby reducing the production complexity and the cost.

Drawings

Fig. 1 is a flow chart of the method of the present invention.

Fig. 2 is a cross-sectional view of the structure obtained after step S10 is performed in embodiment 1 of the present invention.

Fig. 3 is a cross-sectional view of the structure obtained after step S20 is performed in embodiment 1 of the present invention.

Fig. 4 is a cross-sectional view of the structure obtained after step S30 is performed in embodiment 1 of the present invention.

Fig. 5 is a cross-sectional view of the structure obtained after step S40 is performed in embodiment 1 of the present invention.

Fig. 6 is a cross-sectional view of the structure obtained after step S50 is performed in embodiment 1 of the present invention.

Fig. 7 is a cross-sectional view of the structure obtained after step S50 is performed in embodiment 2 of the present invention.

Fig. 8 is a cross-sectional view of the structure obtained after step S50 is performed in embodiment 3 of the present invention.

Fig. 9 is a cross-sectional view of the structure obtained after step S50 is performed in embodiment 4 of the present invention.

In the figure, 10, epitaxial layer, 11, substrate, 12, buffer layer, 13, channel layer, 14, barrier layer, 15, passivation layer, 20, dielectric stack, 21, first dielectric layer, 22, first functional insulating layer, 23, second dielectric layer, 24, second functional insulating layer, 25, third dielectric layer, 30, source, 40, drain, 50, interface barrier layer, 51, bottom, 52, first side, 53, second side, 60, gate, 61, extension, 70, gate field plate, 71, first gate field plate, 72, second gate field plate, 73, third gate field plate.

Detailed Description

The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings and specific embodiments, and it is apparent that the described embodiments are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Example 1

The semiconductor power device provided in this embodiment is described by taking a D-Mode GaN HEMT with a MIS gate structure as an example, and the semiconductor power device may be applied to other types of GaN HEMT chips, such as a trench gate GaN HEMT, a fluorine ion implanted gate GaN HEMT, and the like. In addition, the semiconductor device of the present embodiment may be a switching device, and further includes a high-power application device such as an amplifying device.

Referring to fig. 1, the method for manufacturing a semiconductor power device provided in this embodiment includes the following steps:

s10, preparing an epitaxial layer.

In this step, as shown in fig. 2, a buffer layer 12, a channel layer 13, a barrier layer 14, and a passivation layer 15 are grown in this order from bottom to top on a substrate 11, to obtain an epitaxial layer 10. Specifically, the substrate 11 may be one of a sapphire substrate, a silicon carbide substrate, and a gallium nitride substrate. A buffer layer 12, a channel layer 13, and a barrier layer 14 are sequentially grown on a substrate 11 by a Metal Organic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy (MBE) method, and a passivation layer 15 is deposited on the barrier layer 14 by a MOCVD or Plasma Enhanced Chemical Vapor Deposition (PECVD) method. The buffer layer 12 may have a single-layer Al _xGa_1-x N (x is 0 to 1) film structure or a multi-layer Al _xGa_1-x N (x is 0 to 1) film structure. The thickness of the buffer layer is between 4 and 7 microns. The channel layer 13 is a gallium nitride channel layer having a thickness of 50 to 600nm. The barrier layer 14 is an AlGaN barrier layer having a thickness of 20 to 60nm. The passivation layer 15 is made of silicon nitride or silicon oxide material, which serves as a gate insulator to prevent gate leakage current.

S20, preparing a dielectric stack.

In this step, a dielectric stack 20 is grown on the upper surface of the passivation layer 15, wherein the dielectric stack 20 comprises a plurality of dielectric layers and a functional insulating layer between two adjacent dielectric layers. The dielectric stack 20 is used to define the electrodes and to effect electrical separation. In addition, the spacing between the grid field plate and the channel can be accurately controlled through the etching selection ratio of the functional insulating layer and the dielectric layer, so that the regulation and control of the electric field intensity are realized.

In this embodiment, as shown in fig. 3, the dielectric stack 20 includes three dielectric layers and two functional insulating layers, wherein the material of the dielectric layers includes but is not limited to SiO ₂、Si₃N₄, and the material of the functional insulating layers includes but is not limited to AlN, al ₂O₃. Specifically, in the embodiment shown in fig. 3, the dielectric stack 20 includes a first dielectric layer 21, a first functional insulating layer 22, a second dielectric layer 23, a second functional insulating layer 24, and a third dielectric layer 25 that are stacked in this order. The thickness of each dielectric layer and the thickness of each functional insulating layer are set according to actual requirements.

S30, preparing a source electrode and a drain electrode.

In this step, as shown in fig. 4, a source position and a drain position are defined in the dielectric stack, the dielectric layer, passivation layer and barrier layer materials corresponding to the source position and the drain position are removed, then source metal is disposed at the source position, and drain metal is disposed at the drain position.

Specifically, the positions of the source electrode 30 and the drain electrode 40 are defined by a photolithography method, and the materials of the dielectric stack 20, the passivation layer 15 and a part of the barrier layer 14 corresponding to the positions of the source electrode and the drain electrode are removed by a dry etching or wet etching method. Wherein the barrier layer 14 material need only be partially removed. The source electrode metal and the drain electrode metal can be manufactured by metal evaporation methods such as magnetron sputtering, electron beam evaporation, thermal evaporation and the like, and the drain ohmic contact electrode and the source ohmic contact electrode can be manufactured by alloy annealing of the drain electrode and the source electrode. In the embodiment shown in fig. 4, the source and drain electrodes are disposed on either side of the dielectric stack 20, respectively, and the source 30 and drain 40 electrodes form ohmic contacts with the barrier layer through source and drain ohmic contact electrodes, respectively.

S40, growing an interface barrier layer.

In this step, gate and gate field plate locations are defined on the dielectric stack 20 between the source 30 and drain 40, the dielectric stack material is removed, and an interfacial barrier layer 50 is grown on the top surface of the remaining dielectric stack 20 and the removed locations of the dielectric stack.

As shown in fig. 5, an interfacial barrier layer position is defined in the dielectric stack 20, wherein an interfacial barrier layer 50 is disposed in the dielectric stack 20 between the source 30 and the drain 40, the third dielectric layer 25 and the second dielectric layer 23 at the interfacial barrier layer 50 position are etched and the second functional insulating layer 24 and the first functional insulating layer 22 are removed, and then the interfacial barrier layer 50 is grown on the upper surface of the third dielectric layer 25 and the removed portion of the dielectric stack. In this embodiment, the interfacial barrier layer 50 may be made of SiO ₂、Si₃N₄ or the like. The etching of the dielectric layer and the functional insulating layer can be performed by adopting a dry etching process or a wet etching process.

In the embodiment shown in fig. 5, the interface barrier layer 50 is defined in the dielectric stack 20 between the source 30 and the drain 40, and then the third dielectric layer 25, the second functional insulating layer 24, the second dielectric layer 23, and the first functional insulating layer 22 are etched in sequence at the interface barrier layer location. And growing an interface barrier layer 50 on the upper surface of the third dielectric layer 25, the side surface of the second functional insulating layer 24, a part of the upper surface of the second dielectric layer 23, the side surface of the first functional insulating layer 22 and a part of the upper surface of the first dielectric layer 21.

Specifically, the interfacial barrier 50 includes a bottom 51, a first side 52 and a second side 53, wherein two sides of the bottom 51 are respectively connected to the first side 52 and the second side 53, and a lower surface of the bottom 51 covers a portion of an upper surface of the first dielectric layer 21, a side of the first functional insulating layer 22 and a portion of a side of the second dielectric layer, respectively, and the bottom 51 is used for setting a gate. The first side portion 52 is disposed on a side of the interface barrier layer 50 near the source electrode 30, and the lower surface of the first side portion covers the upper surface of the third dielectric layer, the side surface of the second functional insulating layer, a part of the upper surface of the second dielectric layer, and a part of the side surface of the second dielectric layer, where the upper surface of the first side portion is provided with three steps extending toward the source electrode. The second side portion 53 is disposed on the side of the interface barrier layer 50 near the drain electrode 40, and the lower surface thereof covers the upper surface of the third dielectric layer, the side surface of the second functional insulating layer, part of the upper surface of the second dielectric layer, and part of the side surface of the second dielectric layer, respectively, and the upper surface thereof is provided with three steps extending toward the drain electrode. It should be noted that the lengths of the three steps of the first side portion 52 and the second side portion 53 of the interfacial barrier layer may be set according to actual needs.

S50, preparing a grid electrode and a grid electrode field plate.

In this step, as shown in fig. 6, the positions of the gate 60 and the gate field plate 70 are defined first, the materials of the interface barrier layer 50 and the first dielectric layer 21 corresponding to the gate positions are removed, and the gate 60 and the gate field plate 70 are disposed at the gate positions and the gate field plate positions, respectively, so as to obtain the semiconductor power device.

Specifically, in the embodiment shown in fig. 6, a gate position is defined at the bottom 51 of the interfacial barrier layer 50, the interfacial barrier layer and the first dielectric layer at the gate position are etched, and a gate field plate position is defined at the bottom 51 and the second side 53. Then, arranging gate metal at the gate position, enabling the gate metal to be in contact with the upper surface of the passivation layer, arranging a gate field plate at the gate field plate position, and arranging an extension portion 61 at the first side portion 52, wherein the extension portion 61 is connected with the gate 60, and thus the semiconductor power device of the embodiment is obtained. Wherein the material of the gate 60 metal includes, but is not limited to Al, ti, tiN and the material of the gate field plate 70 includes, but is not limited to Al, ti, tiN. The gate field plate 70 is a stepped multi-layer field plate, and in the embodiment shown in fig. 6, the gate field plate 70 is a stepped tri-layer field plate, which includes a first gate field plate 71, a second gate field plate 72 and a third gate field plate 73 extending gradually toward the drain electrode 40, and the first gate field plate 71 is connected to the gate electrode 60. The shape of the gate field plate 70 corresponds to the shape of the upper surface of the second side 53 of the interfacial barrier 50, wherein the first gate field plate 71 is located on a first step of the second side 63, the second gate field plate 72 is located on a second step of the second side 53, and the third gate field plate 73 is located on a third step of the second side 53. The extension 61 is provided with three steps extending toward the source electrode 30, which is identical in structure to the upper surface of the first side portion 52. It should be noted that the width of each layer of the gate field plate 70 and the width of each step of the extension portion 61 may be set according to actual requirements to meet the performance requirements.

In this embodiment, the interface barrier layer 50 is grown before the first dielectric layer 21 is etched, and the interface barrier layer 50 and the first dielectric layer 21 are etched simultaneously when the gate 60 is windowed, that is, the interface barrier layer and the first dielectric layer are used together as the bottom dielectric of the first gate field plate 71, so that the interface between the gate metal and the passivation layer is only etched once, thereby ensuring the reliability between the gate and the passivation layer, and meanwhile, no obvious increase in production complexity and cost exists. Meanwhile, before gate metal evaporation, an interface barrier layer is grown in the semiconductor power device of the embodiment, and the interface barrier layer is covered to the contact position of the gate field plate and the functional insulating layer/dielectric stack in advance. Then, the metal of the grid electrode field plate and the grid electrode field plate can not be directly contacted with the functional insulating layer and the dielectric layer, and the electric field peak value at the complex juncture of the low-quality and multi-material juncture which is originally damaged by etching can be transferred to the new simple juncture of the high-quality and metal/interface barrier layer which is not damaged by etching, thereby improving the reliability of the device. In addition, as the newly grown interface barrier layer is covered on the original etched sharp dielectric step, a more gentle new step can be generated, and the electric field concentration effect can be further weakened, so that the reliability is improved.

Example 2

s10, preparing an epitaxial layer.

In this step, as shown in fig. 7, a buffer layer 12, a channel layer 13, a barrier layer 14, and a passivation layer 15 are grown in this order from bottom to top on a substrate 11, to obtain an epitaxial layer 10. Specifically, the substrate 11 may be one of a sapphire substrate, a silicon carbide substrate, and a gallium nitride substrate. A buffer layer 12, a channel layer 13, and a barrier layer 14 are sequentially grown on a substrate 11 by a Metal Organic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy (MBE) method, and a passivation layer 15 is deposited on the barrier layer 14 by a MOCVD or Plasma Enhanced Chemical Vapor Deposition (PECVD) method. The buffer layer 12 may have a single-layer Al _xGa_1-x N (x is 0 to 1) film structure or a multi-layer Al _xGa_1-x N (x is 0 to 1) film structure. The thickness of the buffer layer is between 4 and 7 microns. The channel layer 13 is a gallium nitride channel layer having a thickness of 50 to 600nm. The barrier layer 14 is an AlGaN barrier layer having a thickness of 20 to 60nm. The passivation layer 15 is made of silicon nitride or silicon oxide material, which serves as a gate insulator to prevent gate leakage current.

S20, preparing a dielectric stack.

In this step, a dielectric stack 20 is grown on the upper surface of the passivation layer 15, wherein the dielectric stack 20 comprises a plurality of dielectric layers and a functional insulating layer between two adjacent dielectric layers. The dielectric stack 20 is used to define the electrodes and to effect electrical separation. In addition, the spacing between the grid field plate and the channel can be precisely controlled through the etching selection ratio of the functional insulating layer and the dielectric layer, so that the regulation and control of the electric field intensity are realized.

In this embodiment, as shown in fig. 7, the dielectric stack includes three dielectric layers and two functional insulating layers, where the material of the dielectric layers includes but is not limited to SiO ₂、Si₃N₄, and the material of the functional insulating layers includes but is not limited to AlN, al ₂O₃. Specifically, in the embodiment shown in fig. 7, the dielectric stack 20 includes a first dielectric layer 21, a first functional insulating layer 22, a second dielectric layer 23, a second functional insulating layer 24, and a third dielectric layer 25 that are stacked in this order. The thickness of each dielectric layer and the thickness of each functional insulating layer are set according to actual requirements.

S30, preparing a source electrode and a drain electrode.

In the step, a source electrode position and a drain electrode position are defined in a dielectric lamination, dielectric layer, passivation layer and barrier layer materials corresponding to the source electrode position and the drain electrode position are removed, source electrode metal is arranged at the source electrode position, and drain electrode metal is arranged at the drain electrode position.

Specifically, the positions of the source electrode 30 and the drain electrode 40 are defined by a photolithography method, and the materials of the dielectric stack 20, the passivation layer 15 and a part of the barrier layer 14 corresponding to the positions of the source electrode and the drain electrode are removed by a dry etching or wet etching method. Wherein the barrier layer 14 material need only be partially removed. The source electrode metal and the drain electrode metal can be manufactured by metal evaporation methods such as magnetron sputtering, electron beam evaporation, thermal evaporation and the like, and the drain ohmic contact electrode and the source ohmic contact electrode can be manufactured by alloy annealing of the drain electrode and the source electrode. In the embodiment shown in fig. 7, the source and drain electrodes are disposed on either side of the dielectric stack 20, respectively, and the source 30 and drain 40 electrodes form ohmic contacts with the barrier layer through source and drain ohmic contact electrodes, respectively.

S40, growing an interface barrier layer.

Specifically, an interface barrier layer is defined in the dielectric stack 20, wherein the interface barrier layer 50 is disposed in the dielectric stack 20 between the source 30 and the drain 40, the third dielectric layer 25 and the second dielectric layer 23 at the interface barrier layer 50 are etched, and then the interface barrier layer is grown on the upper surface of the third dielectric layer 25, the etching position of the dielectric layer and the exposed functional insulating layer. In this embodiment, the interfacial barrier layer 50 may be made of silicon dioxide, silicon nitride, diamond, aluminum nitride, gallium oxide, or the like.

In the embodiment shown in fig. 7, the interface barrier layer 50 is first defined in the dielectric stack 20 between the source 30 and the drain 40, and then the third dielectric layer 25 and the second dielectric layer 23 are etched sequentially at the interface barrier layer location. And then growing an interface barrier layer 50 on the upper surface of the third dielectric layer 25, the side surface of the third dielectric layer 25, the exposed part of the second functional insulating layer 24, the side surface of the second dielectric layer 23, the exposed part of the first functional insulating layer 22 and part of the upper surface of the first dielectric layer 21.

Specifically, as shown in fig. 7, the interfacial barrier 50 includes a bottom 51, a first side 52 and a second side 53, wherein two sides of the bottom 51 are respectively connected to the first side 52 and the second side 53, and a lower surface of the bottom 51 covers a portion of an upper surface of the first functional insulating layer 22 and a portion of a side of the second dielectric layer 23, and the bottom 51 is used for disposing a gate. The first side portion 52 is disposed on a side of the interface barrier layer 50 near the source electrode 30, and the lower surface of the first side portion covers the upper surface of the third dielectric layer near the source electrode, the side surface of the third dielectric layer, the upper surface of the exposed second functional insulating layer, the side surface of the second functional insulating layer, and a part of the side surface of the second dielectric layer, and the upper surface of the first side portion is provided with three steps extending toward the source electrode. The second side portion 53 is disposed on the side close to the drain electrode 40 in the interface barrier layer 50, and the lower surface of the second side portion covers the upper surface of the third dielectric layer, the side surface of the third dielectric layer, the upper surface of the exposed second functional insulating layer, the side surface of the second functional insulating layer, and a portion of the side surface of the second dielectric layer, where the upper surface of the second side portion is provided with three steps extending toward the drain electrode. It should be noted that the lengths of the three steps of the first side portion 52 and the second side portion 53 of the interfacial barrier layer may be set according to actual needs.

S50, preparing a grid electrode and a grid electrode field plate.

In this step, the gate electrode 60 and the gate electrode field plate 70 are defined on the interface barrier layer 50, the materials of the interface barrier layer 50, the functional insulating layer and the first dielectric layer 21 corresponding to the gate electrode are removed, and the gate electrode 60 and the gate electrode field plate 70 are respectively arranged on the gate electrode and the gate electrode field plate, so as to obtain the semiconductor power device.

Specifically, in the embodiment shown in fig. 7, a gate position is defined at the bottom of the interfacial barrier layer 50, and the interfacial barrier layer, the first functional insulating layer, and the first dielectric layer at the gate position are etched sequentially, and a gate field plate position is defined at the bottom 51 and the second side 53. Then, arranging gate metal at the gate position, arranging a gate field plate at the gate field plate position, and arranging an extension part 61 at the first side part 52, wherein the extension part 61 is connected with the gate 60, thus obtaining the semiconductor power device of the embodiment. Wherein the material of the gate 60 metal includes, but is not limited to, one or more of aluminum, nickel, titanium, copper, tungsten, titanium nitride materials, and the material of the gate field plate 70 includes, but is not limited to, one or more of aluminum, nickel, titanium, copper, tungsten, titanium nitride materials. The gate field plates are stepped multi-layer field plates, and in the embodiment shown in fig. 7, the gate field plate 70 is a stepped tri-layer field plate, which includes a first gate field plate 71, a second gate field plate 72, and a third gate field plate 73 extending stepwise toward the drain electrode 40, and the first gate field plate 71 is connected to the gate electrode 60. The shape of the gate field plate 70 corresponds to the shape of the upper surface of the second side 53 of the interfacial barrier 50, wherein the first gate field plate 71 is located on a first step of the second side 63, the second gate field plate 72 is located on a second step of the second side 53, and the third gate field plate 73 is located on a third step of the second side 53. The extension 61 is provided with three steps extending toward the source electrode 30, which is identical in structure to the upper surface of the first side portion 52. It should be noted that the width of each layer of the gate field plate 70 and the width of each step of the extension portion 61 may be set according to actual requirements to meet the performance requirements.

In this embodiment, when removing the material of the dielectric stack 20, only the third dielectric layer 25 and the second dielectric layer 23 are etched, but the functional insulating layer is not removed, the growth of the interface barrier layer 50 is performed before the etching of the first dielectric layer 21, and the etching of the interface barrier layer, the removal of the first functional insulating layer 22 and the etching of the first dielectric layer 21 are performed during the gate opening. Because after etching the third dielectric layer, if the functional insulating layer needs to be removed, the functional insulating layer needs to be switched to a machine for wet etching removal after dielectric etching, which is more complicated. In this embodiment, the removal process of the functional insulating layer is set to perform etching before the etching with the next layer of medium, and because the functional insulating layer is on the medium layer, the influence on the surface roughness after the whole etching is small, so that wet etching can be used, dry etching can also be performed simultaneously with the medium layer, the etching process steps of the independent functional insulating layer are saved, and the cost is reduced. Although part of the functional insulating layer is not removed, the reliability of the gate field plate metal and the interface barrier layer is not affected, and new risks are not brought. Meanwhile, before gate metal evaporation, an interface barrier layer is grown in the semiconductor power device of the embodiment, and the interface barrier layer is covered to the contact position of the gate field plate and the functional insulating layer/dielectric stack in advance. Then, the metal of the grid electrode field plate and the grid electrode field plate can not be directly contacted with the functional insulating layer and the dielectric layer, and the electric field peak value at the complex juncture of the low-quality and multi-material juncture which is originally damaged by etching can be transferred to the new simple juncture of the high-quality and metal/interface barrier layer which is not damaged by etching, thereby improving the reliability of the device. In addition, as the newly grown interface barrier layer is covered on the original etched sharp dielectric step, a more gentle new step can be generated, and the electric field concentration effect can be further weakened, so that the reliability is improved.

Example 3

The D-Mode GaN HEMT of the MIS gate structure is taken as an example for illustration, and the semiconductor power device provided in this embodiment may be applied to other types of GaN HEMT chips, such as trench gate GaN HEMT, fluorine ion implanted gate GaN HEMT, and the like. In addition, the semiconductor device of the present embodiment may be a switching device, and further includes a high-power application device such as an amplifying device.

s10, preparing an epitaxial layer.

In this step, as shown in fig. 8, a buffer layer 12, a channel layer 13, a barrier layer 14, and a passivation layer 15 are grown in this order from bottom to top on a substrate 11, to obtain an epitaxial layer 10. Specifically, the substrate 11 may be one of a sapphire substrate, a silicon carbide substrate, and a gallium nitride substrate. A buffer layer 12, a channel layer 13, and a barrier layer 14 are sequentially grown on a substrate 11 by a Metal Organic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy (MBE) method, and a passivation layer 15 is deposited on the barrier layer 14 by a MOCVD or Plasma Enhanced Chemical Vapor Deposition (PECVD) method. The buffer layer 12 may have a single-layer Al _xGa_1-x N (x is 0 to 1) film structure or a multi-layer Al _xGa_1-x N (x is 0 to 1) film structure. The thickness of the buffer layer is between 4 and 7 microns. The channel layer 13 is a gallium nitride channel layer having a thickness of 50 to 600nm. The barrier layer 14 is an AlGaN barrier layer having a thickness of 20 to 60nm. The passivation layer 15 is made of silicon nitride or silicon oxide material, which serves as a gate insulator to prevent gate leakage current.

S20, preparing a dielectric stack.

In this embodiment, as shown in fig. 8, the dielectric stack 20 includes two dielectric layers and one functional insulating layer, where the material of the dielectric layers includes but is not limited to SiO ₂、Si₃N₄, and the material of the functional insulating layer includes but is not limited to AlN, al ₂O₃. Specifically, in the embodiment shown in fig. 8, the dielectric stack 20 includes a first dielectric layer 21, a first functional insulating layer 22, and a second dielectric layer 23 that are stacked in this order. The thickness of each dielectric layer and the thickness of each functional insulating layer are set according to actual requirements.

S30, preparing a source electrode and a drain electrode.

In this step, as shown in fig. 8, a source position and a drain position are defined in the dielectric stack, the dielectric layer, passivation layer and barrier layer materials corresponding to the source position and the drain position are removed, then source metal is disposed at the source position, and drain metal is disposed at the drain position.

Specifically, the positions of the source electrode 30 and the drain electrode 40 are defined by a photolithography method, and then the dielectric layer, the passivation layer 15 and part of the barrier layer 14 materials corresponding to the positions of the source electrode and the drain electrode are removed by dry etching or wet etching. Wherein the barrier layer 14 material need only be partially removed. The source electrode metal and the drain electrode metal can be manufactured by metal evaporation methods such as magnetron sputtering, electron beam evaporation, thermal evaporation and the like, and the drain ohmic contact electrode and the source ohmic contact electrode can be manufactured by alloy annealing of the drain electrode and the source electrode. In the embodiment shown in fig. 8, the source and drain electrodes are disposed on either side of the dielectric stack 20, respectively, and the source 30 and drain 40 electrodes form ohmic contacts with the barrier layer through source and drain ohmic contact electrodes, respectively.

S40, growing an interface barrier layer.

Specifically, an interfacial barrier layer is defined in the dielectric stack 20, wherein the interfacial barrier layer 50 is disposed in the dielectric stack 20 between the source 30 and the drain 40, the second dielectric layer 23 and the first dielectric layer 21 at the position of the interfacial barrier layer 50 are etched and the first functional insulating layer 22 is removed, and then the interfacial barrier layer 50 is grown on the upper surface of the second dielectric layer 23 and the removed portion of the dielectric stack. In this embodiment, the interfacial barrier layer may be made of SiO ₂、Si₃N₄ or the like. The etching of the dielectric layer and the functional insulating layer can be performed by adopting a dry etching process or a wet etching process.

In the embodiment shown in fig. 8, the interface barrier layer 50 is defined in the dielectric stack 20 between the source 30 and the drain 40, and then the second dielectric layer 23, the first functional insulating layer 22 and the first dielectric layer 21 are etched in sequence at the interface barrier layer 50. And then growing an interface barrier layer 50 on the upper surface of the second dielectric layer 23, the side surface of the first functional insulating layer 22, part of the upper surface of the first dielectric layer 21, the side surface of the first dielectric layer 21 and part of the upper surface of the passivation layer 15.

Specifically, as shown in fig. 8, the interfacial barrier 50 includes a bottom 51, a first side 52 and a second side 53, wherein two sides of the bottom 51 are respectively connected to the first side 52 and the second side 53, a lower surface of the bottom 51 covers a portion of a side surface of the first dielectric layer 21 and a portion of an upper surface of the passivation layer 15, and the bottom 51 is used for disposing a gate. The first side portion 52 is disposed on the side of the interface barrier layer 50 near the source electrode 30, and the lower surface thereof covers the upper surface of the second dielectric layer 23 near the source electrode, the side surface of the second dielectric layer 23, the side surface of the first functional insulating layer 22, part of the upper surface of the first dielectric layer 21, and part of the side surface of the first dielectric layer 21, respectively, and the upper surface thereof is provided with three steps extending toward the source electrode. The second side portion 53 is disposed on the side close to the drain electrode 40 in the interfacial barrier 50, and the lower surface thereof covers the upper surface of the second dielectric layer 23, the side surface of the first functional insulating layer 22, a part of the upper surface of the first dielectric layer, and a part of the side surface of the first dielectric layer 21, respectively, and the upper surface thereof is provided with three steps extending toward the drain electrode. It should be noted that the lengths of the three steps of the first side portion 52 and the second side portion 53 of the interfacial barrier layer may be set according to actual needs.

S50, preparing a grid electrode and a grid electrode field plate.

In this step, the gate electrode 60 and the gate field plate 70 are defined on the interface barrier layer 50, the material of the interface barrier layer 50 corresponding to the gate electrode is removed, and the gate electrode 60 and the gate field plate 70 are respectively disposed on the gate electrode and the gate field plate, so as to obtain the semiconductor power device.

Specifically, in the embodiment shown in fig. 8, gate sites are defined at the bottom of the interfacial barrier layer 50 and the interfacial barrier layer 50 at the gate sites is etched, defining gate field plate sites at the bottom 51 and the second side 53. Then, arranging gate metal at the gate position, enabling the gate metal to be in contact with the upper surface of the passivation layer, arranging a gate field plate at the gate field plate position, and arranging an extension portion 61 at the first side portion 52, wherein the extension portion 61 is connected with the gate 60, and thus the semiconductor power device of the embodiment is obtained. Wherein the material of the gate 60 metal includes, but is not limited to Al, ti, tiN and the material of the gate field plate includes, but is not limited to Al, ti, tiN. The gate field plates are stepped multi-layer field plates, such as the embodiment shown in fig. 8, and are stepped tri-layer field plates, which include a first gate field plate 71, a second gate field plate 72, and a third gate field plate 73 that extend stepwise toward the drain electrode 40, and the first gate field plate 71 is connected to the gate electrode 60. The shape of the gate field plate 70 corresponds to the shape of the upper surface of the second side 53 of the interfacial barrier 50, wherein the first gate field plate 71 is located on a first step of the second side 63, the second gate field plate 72 is located on a second step of the second side 53, and the third gate field plate 73 is located on a third step of the second side 53. The extension 61 is provided with three steps extending toward the source electrode 30, which is identical in structure to the upper surface of the first side portion 52. It should be noted that the width of each layer of the gate field plate 70 and the width of each step of the extension portion 61 may be set according to actual requirements to meet the performance requirements.

Compared with embodiment 1, the dielectric stack 20 of this embodiment has one dielectric layer reduced, thereby reducing the process steps of dielectric layer growth and etching. Meanwhile, the first dielectric layer 21 is etched and then the interface barrier layer 50 is grown, and the interface barrier layer is etched when the grid electrode 60 is windowed, and only the interface barrier layer is used as the bottom dielectric of the first grid electrode field plate, so that the complexity of process steps and structures is reduced, and the cost is saved. Meanwhile, before gate metal evaporation, an interface barrier layer is grown in the semiconductor power device of the embodiment, and the interface barrier layer is covered to the contact position of the gate field plate and the functional insulating layer/dielectric stack in advance. Then, the metal of the grid electrode field plate and the grid electrode field plate can not be directly contacted with the functional insulating layer and the dielectric layer, and the electric field peak value at the complex juncture of the low-quality and multi-material juncture which is originally damaged by etching can be transferred to the new simple juncture of the high-quality and metal/interface barrier layer which is not damaged by etching, thereby improving the reliability of the device. In addition, as the newly grown interface barrier layer is covered on the original etched sharp dielectric step, a more gentle new step can be generated, and the electric field concentration effect can be further weakened, so that the reliability is improved.

Example 4

s10, preparing an epitaxial layer.

In this step, as shown in fig. 9, a buffer layer 12, a channel layer 13, a barrier layer 14, and a passivation layer 15 are grown in this order from bottom to top on a substrate 11, to obtain an epitaxial layer 10. Specifically, the substrate 11 may be one of a sapphire substrate, a silicon carbide substrate, and a gallium nitride substrate. A buffer layer 12, a channel layer 13, and a barrier layer 14 are sequentially grown on a substrate 11 by a Metal Organic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy (MBE) method, and a passivation layer 15 is deposited on the barrier layer 14 by a MOCVD or Plasma Enhanced Chemical Vapor Deposition (PECVD) method. The buffer layer 12 may have a single-layer Al _xGa_1-x N (x is 0 to 1) film structure or a multi-layer Al _xGa_1-x N (x is 0 to 1) film structure. The thickness of the buffer layer is between 4 and 7 microns. The channel layer 13 is a gallium nitride channel layer having a thickness of 50 to 600nm. The barrier layer 14 is an AlGaN barrier layer having a thickness of 20 to 60nm. The passivation layer 15 is made of silicon nitride or silicon oxide material, which serves as a gate insulator to prevent gate leakage current.

S20, preparing a dielectric stack.

In this embodiment, as shown in fig. 9, the dielectric stack 20 includes two dielectric layers and one functional insulating layer, where the material of the dielectric layers includes but is not limited to SiO ₂、Si₃N₄, and the material of the functional insulating layer includes but is not limited to AlN, al ₂O₃. Specifically, in the embodiment shown in fig. 9, the dielectric stack 20 includes a first dielectric layer 21, a first functional insulating layer 22, and a second dielectric layer 23 that are stacked in this order. The thickness of each dielectric layer and the thickness of each functional insulating layer are set according to actual requirements.

S30, preparing a source electrode and a drain electrode.

In this step, as shown in fig. 9, a source position and a drain position are defined in the dielectric stack, the dielectric layer, passivation layer and barrier layer materials corresponding to the source position and the drain position are removed, then source metal is disposed at the source position, and drain metal is disposed at the drain position.

S40, growing an interface barrier layer.

Specifically, the position of the interfacial barrier layer 50 is defined in the dielectric stack 20, wherein the interfacial barrier layer 50 is disposed in the dielectric stack 20 between the source electrode 30 and the drain electrode 40, the second dielectric layer 23 and the first dielectric layer 21 at the position of the interfacial barrier layer 20 are etched, and then the interfacial barrier layer is grown on the upper surface of the second dielectric layer 23 and the removed portion of the dielectric stack. In this embodiment, the interfacial barrier layer 50 may be made of silicon dioxide, silicon nitride, diamond, aluminum nitride, gallium oxide, or the like.

In the embodiment shown in fig. 9, the interface barrier layer 50 is defined in the dielectric stack between the source and the drain, and then the second dielectric layer 23 and the first dielectric layer 21 are etched in sequence at the interface barrier layer 50. And then growing an interface barrier layer 50 on the upper surface of the second dielectric layer 23, the side surface of the second dielectric layer 23, the exposed first functional insulating layer 22, the side surface of the first dielectric layer 21 and part of the upper surface of the passivation layer 15.

Specifically, as shown in fig. 9, the interfacial barrier 50 includes a bottom 51, a first side 52 and a second side 53, wherein two sides of the bottom 51 are respectively connected to the first side 52 and the second side 53, a lower surface of the bottom 51 covers a portion of a side surface of the first dielectric layer 21 and a portion of an upper surface of the passivation layer 15, and the bottom 51 is used for disposing a gate. The first side portion 52 is disposed on the side of the interface barrier layer 50 near the source electrode 30, and the lower surface thereof covers the upper surface of the second dielectric layer 23 near the source electrode, the side surface of the second dielectric layer 23, the exposed upper surface of the first functional insulating layer, the side surface of the first functional insulating layer 22, and a portion of the side surface of the first dielectric layer 21, and the upper surface thereof is provided with three steps extending toward the source electrode. The second side portion 53 is disposed on the side close to the drain electrode 40 in the interfacial barrier 50, and the lower surface thereof covers the upper surface of the second dielectric layer 23, the side surface of the second dielectric layer 23, the exposed upper surface of the first functional insulating layer 22, the side surface of the first functional insulating layer 22, and a portion of the side surface of the first dielectric layer 21, respectively, and the upper surface thereof is provided with three steps extending toward the drain electrode. It should be noted that the lengths of the three steps of the first side portion 52 and the second side portion 53 of the interfacial barrier layer may be set according to actual needs.

S50, preparing a grid electrode and a grid electrode field plate.

In this step, the gate electrode 60 and the gate electrode field plate 70 are defined on the interface barrier layer 50, the interface barrier layer material corresponding to the gate electrode is removed, and the gate electrode 60 and the gate electrode field plate 70 are respectively disposed on the gate electrode and the gate electrode field plate, thereby obtaining the semiconductor power device.

Specifically, in the embodiment shown in fig. 9, the gate 60 is defined at the bottom 51 of the interfacial barrier layer 50, and the interfacial barrier layer 50 at the gate location is etched, defining the gate field plate location at the bottom 51 and the second side 53. Then, arranging gate metal at the gate position, arranging a gate field plate at the gate field plate position, and arranging an extension part 61 at the first side part 52, wherein the extension part 61 is connected with the gate 60, thus obtaining the semiconductor power device of the embodiment. Wherein the material of the gate 60 metal includes, but is not limited to, one or more of aluminum, nickel, titanium, copper, tungsten, titanium nitride materials, and the material of the gate field plate 70 includes, but is not limited to, one or more of aluminum, nickel, titanium, copper, tungsten, titanium nitride materials. The gate field plates are stepped multi-layer field plates, as in the embodiment shown in fig. 9, the gate field plates are stepped tri-layer field plates comprising a first gate field plate 71, a second gate field plate 72 and a third gate field plate 73 extending stepwise towards the drain electrode 40, and the first gate field plate 71 is connected to the gate electrode 60. The shape of the gate field plate 70 corresponds to the shape of the upper surface of the second side 53 of the interfacial barrier 50, wherein the first gate field plate 71 is located on a first step of the second side 63, the second gate field plate 72 is located on a second step of the second side 53, and the third gate field plate 73 is located on a third step of the second side 53. The extension 61 is provided with three steps extending toward the source electrode 30, which is identical in structure to the upper surface of the first side portion 52. It should be noted that the width of each layer of the gate field plate 70 and the width of each step of the extension portion 61 may be set according to actual requirements to meet the performance requirements.

Compared with embodiment 3, the functional insulating layer is not removed after each etching of the dielectric layer, the growth of the interface barrier layer is performed after the etching of the first dielectric layer, and the etching of the interface barrier layer is performed when the gate is windowed. Because after etching the second dielectric layer, if the functional insulating layer needs to be removed, the functional insulating layer needs to be switched to a machine for wet etching removal after dielectric etching, which is more complicated. In this embodiment, the removal process of the functional insulating layer is set to perform etching before the etching with the next layer of medium, and because the functional insulating layer is on the medium layer, the influence on the surface roughness after the whole etching is small, so that wet etching can be used, dry etching can also be performed simultaneously with the medium layer, the etching process steps of the independent functional insulating layer are saved, and the cost is reduced. Although part of the functional insulating layer is not removed, the reliability of the gate field plate metal and the interface barrier layer is not affected, and new risks are not brought. Meanwhile, before gate metal evaporation, an interface barrier layer is grown in the semiconductor power device of the embodiment, and the interface barrier layer is covered to the contact position of the gate field plate and the functional insulating layer/dielectric stack in advance. Then, the metal of the grid electrode field plate and the grid electrode field plate can not be directly contacted with the functional insulating layer and the dielectric layer, and the electric field peak value at the complex juncture of the low-quality and multi-material juncture which is originally damaged by etching can be transferred to the new simple juncture of the high-quality and metal/interface barrier layer which is not damaged by etching, thereby improving the reliability of the device. In addition, as the newly grown interface barrier layer is covered on the original etched sharp dielectric step, a more gentle new step can be generated, and the electric field concentration effect can be further weakened, so that the reliability is improved.

Example 5

As shown in fig. 6, the semiconductor power device provided in this embodiment includes an epitaxial layer 10, a dielectric stack 20, a source electrode 30, a drain electrode 40, an interface barrier layer 50, a gate electrode 60, and a gate field plate 70. The semiconductor power device of the embodiment is described by taking a D-Mode GaN HEMT of a MIS gate structure as an example, and the semiconductor power device can be applied to other types of GaN HEMT chips, such as a trench gate GaN HEMT, a fluorine ion implanted gate GaN HEMT, and the like. In addition, the semiconductor device of the present embodiment may be a switching device, and further includes a high-power application device such as an amplifying device.

Specifically, as shown in fig. 6, the epitaxial layer 10 includes a substrate 11, a buffer layer 12, a channel layer 13, a barrier layer 14, and a passivation layer 15, which are stacked. Among them, the substrate 11 may be one of a sapphire substrate, a silicon carbide substrate, and a gallium nitride substrate. The buffer layer 12 has a single-layer Al _xGa_1-x N (x is 0 to 1) film structure or a multi-layer Al _xGa_1-x N (x is 0 to 1) film structure. The channel layer 13 is made of gallium nitride material. The barrier layer is made of aluminum gallium nitride material. The passivation layer 14 is selected from silicon nitride or silicon dioxide material, which acts as a gate insulator to prevent gate leakage.

The dielectric stack 20 is disposed on the upper surface of the passivation layer 15, and includes a plurality of dielectric layers disposed in a stacked manner and a functional insulating layer disposed between two adjacent dielectric layers. The dielectric stack may include three dielectric layers and two functional insulating layers disposed between two adjacent dielectric layers. In some embodiments, the dielectric stack may further include two dielectric layers and a functional insulating layer disposed between adjacent two dielectric layers. The material of each dielectric layer comprises but is not limited to SiO ₂、Si₃N₄, and the material of the functional insulating layer comprises but is not limited to AlN and Al ₂O₃. In the embodiment shown in fig. 6, the dielectric stack 20 includes a first dielectric layer 21, a first functional insulating layer 22, a second dielectric layer 23, a second functional insulating layer 24, and a third dielectric layer 25 that are stacked.

The source electrode 30 and the drain electrode 40 are respectively disposed on two sides of the dielectric stack 20, and the source electrode 30 and the drain electrode 40 respectively form ohmic contact with the barrier layer through a source ohmic contact electrode and a drain ohmic contact electrode.

An interfacial barrier layer 50 is provided on the dielectric stack 20 between the source 30 and drain 40 that covers the upper surface of the dielectric stack, a portion of the dielectric stack, or a portion of the upper surface of the passivation layer. Wherein the interface barrier layer is made of SiO ₂、Si₃N₄ and other materials. In the embodiment shown in fig. 6, the interfacial barrier layer 50 covers the upper surface of the third dielectric layer 25, the side surface of the second functional insulating layer 24, a part of the upper surface of the second dielectric layer 23, the side surface of the first functional insulating layer 22, and a part of the upper surface of the first dielectric layer 21. In the embodiment shown in fig. 7, the interfacial barrier layer 50 may further cover the upper surface of the third dielectric layer 25, the side surface of the third dielectric layer 25, a part of the upper surface of the second functional insulating layer 24, the side surface of the second dielectric layer 23, and a part of the upper surface of the first functional insulating layer 22. In the embodiment shown in fig. 8, the interfacial barrier layer 50 covers the upper surface of the second dielectric layer 23, the side surface of the first functional insulating layer 22, a part of the upper surface of the first dielectric layer 21, the side surface of the first dielectric layer 21, and a part of the upper surface of the passivation layer 15. In the embodiment shown in fig. 9, the interfacial barrier layer 50 covers the upper surface of the second dielectric layer 23, the side surface of the second dielectric layer 23, a part of the upper surface of the first functional insulating layer 22, the side surface of the first dielectric layer 21, and a part of the upper surface of the passivation layer 15. The interfacial barrier layer 50 covers the contact position of the gate field plate 70 and the dielectric stack 20 in advance, so as to avoid the contact of the gate field plate 70 and the dielectric stack 20, and the electric field peak value at the complex junction where etching damage exists and the junction of low quality and multiple materials can be transferred to the new simple junction where etching damage does not exist and the junction of high quality and only the metal/interfacial barrier layer exists, thereby improving the reliability of the device. In addition, as the newly grown interface barrier layer is covered on the original etched sharp dielectric step, a more gentle new step can be generated, and the electric field concentration effect can be further weakened, so that the reliability is improved.

Specifically, as shown in fig. 6, the interfacial barrier 50 includes a bottom 51, a first side 52 and a second side 53, wherein two sides of the bottom 51 are respectively connected to the first side 52 and the second side 53, and a lower surface of the bottom 51 covers a portion of an upper surface of the first dielectric layer 21, a side of the first functional insulating layer 22 and a portion of a side of the second dielectric layer, respectively, and the bottom 51 is used for disposing a gate. The first side portion 52 is disposed on a side of the interface barrier layer 50 near the source electrode 30, and the lower surface of the first side portion covers the upper surface of the third dielectric layer, the side surface of the second functional insulating layer, a part of the upper surface of the second dielectric layer, and a part of the side surface of the second dielectric layer, where the upper surface of the first side portion is provided with three steps extending toward the source electrode. The second side portion 53 is disposed on the side of the interface barrier layer 50 near the drain electrode 40, and the lower surface thereof covers the upper surface of the third dielectric layer, the side surface of the second functional insulating layer, part of the upper surface of the second dielectric layer, and part of the side surface of the second dielectric layer, respectively, and the upper surface thereof is provided with three steps extending toward the drain electrode. It should be noted that the lengths of the three steps of the first side portion 52 and the second side portion 53 of the interfacial barrier layer may be set according to actual needs.

The gate 60 and the gate field plate 70 are disposed on the interfacial barrier layer 50, wherein the gate 60 covers a portion of the upper surface of the passivation layer 15, the gate field plate 70 is connected to the gate 60 and disposed on the surface of the interfacial barrier layer, and an extension portion 61 is disposed on a side of the gate 60 away from the gate field plate 70, and the extension portion 61 is connected to the gate 60 and disposed on the surface of the interfacial barrier layer. Specifically, the gate field plate is a stepped multi-pole field plate, each layer of field plate from the gate to the drain can further modulate an electric field peak generated by the previous field plate, and an optimized electric field distribution is obtained by adjusting the length and the height of each layer of field plate, so that higher withstand voltage is realized. In the embodiment shown in fig. 6, the gate field plate 70 is a stepped three-layer field plate, which includes a first gate field plate 71, a second gate field plate 72 and a third gate field plate 73 extending gradually toward the drain electrode 40, and the first gate field plate 71 is connected to the gate electrode 60. The shape of the gate field plate 70 corresponds to the shape of the upper surface of the second side 53 of the interfacial barrier 50, wherein the first gate field plate 71 is located on a first step of the second side 63, the second gate field plate 72 is located on a second step of the second side 53, and the third gate field plate 73 is located on a third step of the second side 53. The extension 61 is provided with three steps extending toward the source electrode 30, which is identical in structure to the upper surface of the first side portion 52. It should be noted that the width of each layer of the gate field plate 70 and the width of each step of the extension portion 61 may be set according to actual requirements to meet the performance requirements.

In summary, according to the method for manufacturing the semiconductor power device, the interface barrier layer is arranged between the gate electrode and the gate electrode field plate and the dielectric stack layer, so that the gate electrode field plate is prevented from being contacted with the dielectric stack layer, the electric field peak value at the complex junction of the low-quality and multi-material junction with etching damage can be transferred to the new simple junction of the high-quality and metal/interface barrier layer without etching damage, and the reliability of the device is improved. On the other hand, in the manufacturing process, the first dielectric layer and the interface barrier layer are used as the bottom dielectric of the first-layer grid electrode field plate together, so that no extra photoetching step is needed, or the third dielectric layer is reduced, the growth and etching processes of the dielectric layer are reduced, and the production cost is saved. The semiconductor power device is provided with the interface barrier layer between the grid electrode and the grid electrode field plate and the dielectric lamination layer so as to avoid the contact between the grid electrode field plate and the dielectric lamination layer, so that the electric field peak value at the complex junction of the low-quality and multi-material junction with etching damage originally can be transferred to the new simple junction of the high-quality and metal/interface barrier layer without etching damage, and the reliability of the device is improved. In addition, as the newly grown interface barrier layer is covered on the original etched sharp dielectric step, a more gentle new step can be generated, and the electric field concentration effect can be further weakened, so that the reliability is improved.

Although the present invention has been disclosed by the above embodiments, the scope of the present invention is not limited thereto, and modifications, substitutions, etc. made to the above components will fall within the scope of the claims of the present invention without departing from the spirit of the present invention.

Claims

1. The manufacturing method of the semiconductor power device is characterized by comprising the following steps:

d. And (3) growing an interface barrier layer: defining the positions of a grid electrode and a grid electrode field plate on a dielectric stack layer between a source electrode and a drain electrode, removing part of dielectric stack layer materials, and growing an interface barrier layer on the upper surface of the rest dielectric stack layer and the removed position of the dielectric stack layer;

2. The method for manufacturing a semiconductor power device according to claim 1, wherein,

3. The method for manufacturing a semiconductor power device according to claim 1, wherein,

4. The method for manufacturing a semiconductor power device according to claim 1, wherein,

5. The method for manufacturing a semiconductor power device according to claim 1, wherein,

6. The method of manufacturing a semiconductor power device of claim 1, wherein the gate field plate is a stepped multilayer field plate, and the shape of the upper surface of the interfacial barrier layer corresponding to the gate field plate is the same as the shape of the gate field plate.

7. The method for manufacturing a semiconductor power device according to claim 1, wherein,

In step e, the interfacial barrier material at the gate location may be removed entirely, partially or not.

8. The method of manufacturing a semiconductor power device of claim 1, wherein the interfacial barrier layer is made of silicon dioxide, silicon nitride, diamond, aluminum nitride, or gallium oxide material.

9. The method of manufacturing a semiconductor power device according to claim 1, wherein the semiconductor power device is a switching device or an amplifier made of one semiconductor material of gallium nitride, diamond, gallium oxide, aluminum nitride, silicon carbide, and silicon; the gate metal and the gate field plate are made of one or more of aluminum, nickel, titanium, copper, tungsten and titanium nitride materials.

10. A semiconductor power device, comprising: