CN117975895A - Scan driving circuit and display panel - Google Patents

Abstract

The embodiment of the application discloses a scanning driving circuit and a display panel, which comprise n scanning driving units which are sequentially cascaded, wherein the n scanning driving units are used for sequentially outputting scanning signals. The a-th scanning driving unit comprises an output module, a pull-down module, an output control node and a scanning signal output end, wherein the output module is connected with the output control node and the scanning signal output end, the pull-down module is connected with the output control node and the scanning signal output end, when the voltage of the output control node is a first potential, the pull-down module controls the scanning signal output end to stop outputting the scanning signal and maintain the scanning signal at the first potential, and when the voltage of the output control node is a second potential, the output module controls the scanning signal output end to output the scanning signal, and the second potential is larger than the first potential. By optimizing the circuit structure of the scanning driving unit, the space occupation of the scanning driving circuit is effectively reduced.

Description

Scan driving circuit and display panel

Technical Field

The present application relates to the field of display technologies, and in particular, to a scan driving circuit and a display panel.

Background

The less gate driver technology (GATE DRIVER LESS, GDL) is to use the original array process of the liquid crystal display panel to manufacture the driving circuit of the horizontal scanning line on the substrate around the display area, so that the driving circuit can replace the external integrated circuit board (INTEGRATED CIRCUIT, IC) to finish the driving of the horizontal scanning line. The GDL technology can reduce the welding procedure of an external IC, and can make the liquid crystal display panel more suitable for manufacturing display products with narrow frames or without frames.

At present, since the scan driving circuit is fabricated on the array substrate, the size of the scan driving circuit directly affects the size of the display panel frame, so how to simplify the scan driving circuit to reduce the space occupation of the scan driving circuit is a problem to be solved.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, the present application provides a scan driving circuit and a display panel that can effectively simplify the circuit structure and reduce the space occupation.

The application provides a scanning driving circuit, which comprises n scanning driving units which are sequentially cascaded, wherein n is an integer larger than 1, and the n scanning driving units are used for sequentially outputting corresponding scanning signals which are used for controlling a pixel unit to receive data signals for image display so as to display images. The a-th scanning driving unit comprises an output module, a pull-down module, an output control node and a scanning signal output end, wherein a is more than or equal to 1 and less than or equal to n, the output module is connected with the output control node and the scanning signal output end, the pull-down module is connected with the output control node and the scanning signal output end, when the voltage of the output control node is a first potential, the pull-down module controls the scanning signal output end to stop outputting the scanning signal and maintain the scanning signal at the first potential, and when the voltage of the output control node is a second potential, the output module controls the scanning signal output end to output the scanning signal, and the second potential is larger than the first potential.

Optionally, the output module is further connected to a clock signal end, the pull-down module is further connected to a first low voltage end, when the output control node is located at the first potential, the output module stops controlling the scan signal output end to output the scan signal according to the clock signal output by the clock signal end, and meanwhile, the pull-down module controls the scan signal output end to be connected to the first low voltage end, so that charges in the scan signal output end are transmitted to the first low voltage end.

Optionally, the output module includes a first switching tube, the first switching tube includes control end, first conductive end and second conductive end, the control end of first switching tube connect in output control node, the first conductive end of first switching tube connect in the clock signal end, the second conductive end of first switching tube connect in the scanning signal output end, the first switching tube switches on when output control node is located the second potential, the clock signal passes through first conductive end with the second conductive end transmits to the scanning signal output end and regard as scanning signal output.

Optionally, the pull-down module includes a second switching tube, the second switching tube includes control end, first conductive end and second conductive end, the control end of second switching tube connect in output control node, the first conductive end of second switching tube connect in scanning signal output end, the second conductive end of second switching tube connect in first low voltage end, the second switching tube is used for switching on when output control node is located first potential, in order to with scanning signal output end access first low voltage end.

Optionally, the first switching tube is an N-type transistor, and the second switching tube is a P-type transistor.

Optionally, the first switching tube and the second switching tube are disposed on the same substrate and are disposed adjacently, the control end of the first switching tube is disposed on the surface of the substrate, and the first conductive end and the second conductive end of the first switching tube are disposed on the control end of the first switching tube in a stacked manner, and are far away from one side of the substrate. The control end of the second switching tube is overlapped and arranged on the substrate, and the first conductive end and the second conductive end of the second switching tube are arranged on one side, far away from the substrate, of the control end of the second switching tube in the same overlapped and arranged mode. The control end of the first switching tube and the control end of the second switching tube are located on the same layer, and the first conductive end and the second conductive end of the first switching tube and the first conductive end and the second conductive end of the second switching tube are located on the same layer.

Optionally, the first switch tube with the second switch tube stacks gradually and sets up the substrate, first switch tube with the same control end of second switch tube sharing, first switch tube include first active layer the second switch tube includes the second active layer, first active layer, public control end with the second active layer stacks gradually set up in the substrate, first active layer with between the public control end and second active layer with be provided with the insulating layer between the public control end. The first conducting end lamination of the first switch tube is arranged on one side, far away from the first active layer, of the insulating layer and is connected to the first active layer, and the second conducting end lamination of the first switch tube is arranged on one side, far away from the first active layer, of the insulating layer and is connected to the first active layer. The first conducting end and the second conducting end of the second switching tube are arranged on one side, far away from the common control end, of the insulating layer in a stacked mode and are respectively located on two sides of the second active layer, the first conducting end of the second switching tube and the second conducting end of the first switching tube are located on the same layer, and the first conducting end of the second switching tube is connected to the second conducting end of the first switching tube.

Optionally, the scan driving circuit further includes a pull-up module and a reset module, where the pull-up module is connected to the scan signal output ends of the a-4 th scan driving units and the output control node, and is configured to pull up the output control node from the first potential to the second potential under the control of the scan signals output by the a-4 th scan driving units. The reset module is connected to the scan signal output end of the (a+4) th scan driving unit and the output control node, and is used for pulling down the output control node from the second potential to the first potential under the control of the scan signal output by the (a+4) th scan driving unit.

Optionally, the pull-up module includes a third switching tube, the reset module includes a fourth switching tube, the third switching tube includes a control end, a first conductive end and a second conductive end, the control end and the first conductive end of the third switching tube are connected to the scan signal output ends of the a-4 scan driving units, and the second conductive end of the third switching tube is connected to the output control node, and is used for being turned on under the control of the scan signals output by the a-4 scan driving units so as to pull up the output control node to the second potential. The fourth switching tube comprises a control end, a first conductive end and a second conductive end, wherein the control end of the fourth switching tube is connected with the (a+4) th scanning signal output end of the scanning driving unit, the first conductive end of the fourth switching tube is connected with the output control node, the second conductive end of the fourth switching tube is connected with the second low-voltage end and is used for being conducted under the control of the (a+4) th scanning signal output by the scanning driving unit, and the output control node is controlled to be connected with the second low-voltage end so as to pull down the output control node to the first potential.

The application also provides a display panel which comprises a plurality of pixel units, a data driving circuit and the scanning driving circuit, wherein the pixel units are arranged in a display area and are arranged in a matrix, the data driving circuit is arranged in a non-display area, the scanning driving circuit is used for outputting scanning signals to the pixel units through the scanning lines and controlling the pixel units to receive the data signals output by the data driving circuit from the data lines for image display.

Compared with the prior art, under the condition of maintaining the functions of the scanning driving unit, the arrangement of the functional units and the circuit elements in the scanning driving circuit is reduced, the size of the scanning driving unit is effectively reduced, the space occupation of the scanning driving circuit is reduced, and the arrangement of the elements in the scanning driving circuit is reduced, the signal delay caused by the redundancy of the circuit elements is reduced, the signal transmission speed is improved, and the driving capability of the scanning driving unit is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a display device according to a first embodiment of the present application;

FIG. 2 is a schematic side view of the display panel of FIG. 1;

FIG. 3 is a schematic plan layout of the display panel of FIG. 2;

FIG. 4 is a schematic circuit diagram of the scan driving circuit in FIG. 3;

FIG. 5 is an equivalent circuit schematic diagram of the scan driving unit in FIG. 4;

FIG. 6 is a schematic diagram showing the variation of the turn-on voltages of the first and second switching transistors in FIG. 5;

FIG. 7 is a timing diagram of the scan signal output of FIG. 5;

FIG. 8 is a schematic diagram of the first switching tube and the second switching tube in FIG. 5;

Fig. 9 is a schematic diagram of the structure of the first switching tube and the second switching tube as shown in fig. 5 according to the second embodiment.

Reference numerals illustrate: the display device-100, the display panel-10, the power module-20, the support frame 30, the array substrate-10 c, the display medium layer-10 e, the opposite substrate-10 d, the display area-10 a, the non-display area-10 b, the time sequence control circuit-11, the data driving circuit-12, the scanning driving circuit-13, the pixel unit-P, the backlight module-17, the first direction-F1, the second direction-F2, M data lines-S1-Sm, n scanning lines-G1-Gn, the clock signal-CLK, the start signal-STV, the reset signal-R, the scanning driving unit-GDL, the output module-131, the pull-down module-132, the pull-up module-133, the reset module-134, the clock signal terminal-CK, the first switch tube-M1 a second switching tube-M2, a third switching tube-M3, a fourth switching tube-M4, an output control node-Q, a scanning signal output end-Gout, a first low voltage end-Vss 1, a second low voltage end-Vss 2, a gate source voltage-Vgs, a source drain current-Ids, a first time period-T1, a second time period-T2, a third time period-T3, a fourth time period-T4, a first potential-V1, a second potential-V2, a third potential-V3, a control end-G1 of a first switching tube, a first conductive end-S1 of the first switching tube, a second conductive end-d 1 of the first switching tube, a control end-G2 of the second switching tube, a first conductive end-S2 of the second switching tube, a second conductive end-d 2 of the second switching tube, common control terminal-g.

Detailed Description

In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. The drawings illustrate preferred embodiments of the application. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

The following description of the embodiments refers to the accompanying drawings, which illustrate specific embodiments in which the application may be practiced. The numbering of the components itself, e.g. "first", "second", etc., is used herein merely to distinguish between the described objects and does not have any sequential or technical meaning. The term "coupled" as used herein includes both direct and indirect coupling (coupling), unless otherwise indicated. Directional terms, such as "upper", "lower", "front", "rear", "left", "right", "inner", "outer", "side", etc., in the present application are merely referring to the directions of the attached drawings, and thus, directional terms are used for better, more clear explanation and understanding of the present application, rather than indicating or implying that the apparatus or element being referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application.

In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; may be a mechanical connection; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art. It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and in the drawings are used for distinguishing between different objects and not for describing a particular sequential order.

Furthermore, the terms "comprises," "comprising," "includes," "including," or "having," when used in this specification, are intended to specify the presence of stated features, operations, elements, etc., but do not limit the presence of one or more other features, operations, elements, etc., but are not limited to other features, operations, elements, etc. Furthermore, the terms "comprises" or "comprising" mean that there is a corresponding feature, number, step, operation, element, component, or combination thereof disclosed in the specification, and that there is no intention to exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof. Furthermore, when describing embodiments of the application, use of "may" means "one or more embodiments of the application. Also, the term "exemplary" is intended to refer to an example or illustration.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a display device according to a first embodiment of the present application. The display device 100 includes a display panel 10, a power module 20 and a supporting frame 30, wherein the display panel 10 and the power module 20 are fixed on the supporting frame 30, and the power module 20 is disposed on a back surface of the display panel 10, i.e. a non-display surface of the display panel 10. The power module 20 is used for providing power voltage for the display panel 10 to display images, and the support frame 30 provides fixing and protecting functions for the display panel 10 and the power module 20.

In other embodiments of the present application, the display device 100 may not need to be provided with the supporting frame 30, for example, a portable electronic device, such as a mobile phone, a tablet computer, etc.

Referring to fig. 2, fig. 2 is a schematic side view of the display panel in fig. 1.

The display panel 10 includes an array substrate 10c, an opposite substrate 10d, and a display medium layer 10e sandwiched between the array substrate 10c and the opposite substrate 10 d. The driving elements disposed on the array substrate 10c and the opposite substrate 10d generate corresponding electric fields according to the Data signals (Data), so as to drive the display medium in the display medium layer 10e to emit light with corresponding brightness, so as to execute image display. Wherein the display medium may be liquid crystal molecules, miniLED, micro-LEDs, OLEDs, etc., which the present application is not limited to.

Taking the liquid crystal display panel as an example, the display medium in the display medium layer 10e is liquid crystal molecules, and the display panel 10 further includes a backlight module 17 (Back light Module, BM), wherein the backlight module 17 is configured to provide light for display to the display medium layer 10e, and the liquid crystal molecules deflect by an opposite angle according to the data signal, so as to emit the light transmitted by the backlight module 17 to the opposite substrate to perform image display.

Referring to fig. 3, fig. 3 is a schematic plan layout structure of the display panel in fig. 2.

As shown in fig. 3, the display panel 10 further includes a timing control circuit 11, a data driving circuit 12, and a scan driving circuit 13. The timing control circuit 11, the data driving circuit 12, and the scan driving circuit 13 are provided in the non-display region 10b of the display panel 10.

M data lines (Source lines) S1 to Sm and n scanning lines (Gate lines) G1 to Gn are provided in a grid-like arrangement in the display region 10a of the display panel 10. Wherein, m data lines S1-Sm extend along a first direction F1, and n scanning lines G1-Gn extend along a second direction F2. Wherein the first direction F1 and the second direction F2 are perpendicular to each other. The pixel units P are provided at intersections of the n scanning lines G1-Gn and the data lines S1-Sm.

The timing control circuit 11 receives an image signal representing image information, a clock signal CLK for synchronization, a horizontal synchronization signal Hsyn, and a vertical synchronization signal Vsyn from an external signal source, and outputs a gate output control signal Cg for controlling the scan driving circuit 13, a source output control signal Cs for controlling the data driving circuit 12, and a data signal representing image information. In this embodiment, the timing control circuit 11 performs data adjustment processing on the original data signal to obtain a data signal, and transmits the data signal to the data driving circuit 12.

The m data lines S1 to Sm are connected to the data driving circuit 11 for receiving the data signals stored and transmitted in the form of gray scale values supplied from the data driving circuit 12, and the n scan lines G1 to Gn are connected to the scan driving circuit 13 for receiving the scan signals from the scan driving circuit 13.

The pixel unit P receives data voltages corresponding to gray scale values in the data signals provided by the data lines S1 to Sm in a predetermined period under the control of the n scan lines G1 to Gn, and drives the display medium layer 10e to deflect by a corresponding angle accordingly, so that the received backlight emits light rays with corresponding brightness according to the deflected corresponding angle, and image display is performed by emitting the light rays with corresponding brightness according to the image signals.

The scan driving circuit 13 receives the gate output control signal Cg output from the timing control circuit 11, and outputs scan signals to the respective scan lines G1 to Gn. The data driving circuit 12 receives the source output control signal Cs output from the timing control circuit 11, and outputs data signals for performing image display to the driving elements in the respective pixel units P in the display area 10a to the respective data lines S1 to Sm. Wherein the data signal provided to the display panel 10 is a gray scale voltage in analog form. The scan driving circuit 13 outputs a scan signal to control the pixel unit P to receive the data signal output from the data driving circuit 12, so as to control the pixel unit P to display a corresponding image.

Referring to fig. 4, fig. 4 is a schematic circuit diagram of the scan driving circuit in fig. 3.

As shown in fig. 4, the scan driving circuit 13 includes n cascaded scan driving units GDL1 to GDLn, eight clock signals CLK1 to CLK8, a start signal STV, a reset signal R, and a low voltage terminal Vss, where n is an integer greater than or equal to 1.

In the exemplary embodiment, the clock signal may also be set to other numbers according to specific needs, and the present application is not limited.

In the scan driving circuit 13, each scan driving unit correspondingly outputs a scan signal to one scan line in the display area 10a, and n scan driving units sequentially output n scan signals in a frame image display process.

Eight clock signals CLK1-CLK8 are used to provide scan drive timing for the scan drive unit to output scan signals. The start signal STV is an initial start signal of the first scan driving unit GDL1, and the other scan driving units use the stage signal output by the cascade scan unit as a start signal. The low voltage terminal Vss is used to supply a low voltage to the node in the scan driving unit.

Referring to fig. 5, fig. 5 is an equivalent circuit schematic diagram of the scan driving unit in fig. 4.

As shown in fig. 5, taking an a-th scan driving unit as an example, where 5.ltoreq.a.ltoreq.n, the scan driving unit GDL includes an output module 131, a pull-down module 132, a pull-up module 133, a reset module 134, and an output control node Q, where the output module 131 is connected to the output control node Q and the scan signal output terminal Gout (a) and is configured to output the scan signal from the scan signal output terminal Gout (a) under the control of the output control node Q.

The pull-down module 132 is connected to the output control node Q, the scan signal output terminal Gout (a), and the first low voltage terminal Vss1, and is configured to connect the scan signal output terminal Gout (a) to the first low voltage terminal Vss1 under the control of the output control node Q, and is configured to pull down the potential of the scan signal output terminal Gout (a) to a low potential, that is, control the scan signal output terminal Gout (a) to stop outputting the scan signal.

The pull-up module 133 is connected to the scan signal output terminal Gout (a-4) of the a-4 th stage scan driving unit and the output control node Q, and is configured to pull up the output control node Q from the first potential to the second potential under the control of the scan signal output from the a-4 th stage scan driving unit.

The reset module 134 is connected to the output control node Q, the scan signal output terminal Gout (a+4) of the a+4 stage scan driving unit, and the low voltage terminal Vss2, and is configured to pull down the output control node Q from the second potential to the first potential under the control of the scan signal output from the a+4 stage scan driving unit.

Specifically, the output module 131 includes a first switching tube M1, where the first switching tube M1 includes a control end, a first conductive end and a second conductive end, the control end of the first switching tube M1 is connected to the output control node Q, the first conductive end is connected to the clock signal end CK, the second conductive end is connected to the scan signal output end Gout (a), and the first switching tube M1 is configured to conduct the first conductive end and the second conductive end when the output control node Q is at the second potential, receive the clock signal from the clock signal end CK, and output the clock signal as the scan signal from the scan signal output end Gout (a).

The pull-down module 132 includes a second switching tube M2, where the second switching tube M2 includes a control end, a first conductive end and a second conductive end, the control end of the second switching tube M2 is connected to the output control node Q, the first conductive end is connected to the first low voltage end Vss1, the second conductive end is connected to the scan signal output end Gout (a), and the second switching tube M2 is turned on when the output control node Q is at a first potential, i.e., a low potential, for electrically connecting the scan signal output end Gout (a) with the first low voltage end Vss1, so as to pull down the potential of the scan signal output end Gout (a) to the first potential, i.e., the low potential, that is, to control the scan signal output end Gout (a) to stop outputting the scan signal.

The pull-up module comprises a third switching tube M3, the third switching tube M3 comprises a control end, a first conductive end and a second conductive end, the control end and the first conductive end of the third switching tube M3 are connected to a scanning signal output end Gout (a-4) of the a-4 th stage scanning driving unit, and the second conductive end is connected to an output control node Q and used for being conducted under the control of a scanning signal output by the a-4 th stage scanning driving unit and pulling up the potential of the output control node Q to a second potential.

The reset module 134 includes a fourth switching tube M4, where the fourth switching tube M4 includes a control end, a first conductive end and a second conductive end, the control end of the fourth switching tube M4 is connected to the scan signal output end Gout (a+4) of the a+4 stage scan driving unit, the first conductive end is connected to the output control node Q, the second conductive end is connected to the second low voltage end Vss2, and is used for conducting under the control of the scan signal output by the a+4 stage scan driving unit, so that the output control node Q is electrically connected to the second low voltage end Vss2, and is used for pulling the potential of the output control node Q down to the first potential, i.e. the low potential.

In an exemplary embodiment, the control end is a gate of the switching tube, the first conductive end is a source of the switching tube, the second conductive end is a drain of the switching tube, when a voltage is applied to the control end, the switching tube is turned on, and the first conductive end may be disposed on the drain of the switching tube, and the second conductive end may be disposed as a source of the switching tube, which is not limited in the present application.

Referring to fig. 6, fig. 6 is a schematic diagram showing a variation of the turn-on voltages of the first switching tube and the second switching tube in fig. 5. As shown in fig. 6, the first switching transistor M1 and the second switching transistor M2 are transistors with opposite characteristics, the first switching transistor M1 may be an N-type transistor, and as the gate-source voltage Vgs increases, the current that the first switching transistor M1 turns on, i.e., the source-drain current Ids gradually increases, that is, turns on when the control terminal is at a high level, and turns off when the control terminal is at a low level. The second switching tube M2 may be a P-type transistor, and as the gate-source voltage Vgs increases, the current that the second switching tube M2 conducts, that is, the source-drain current Ids decreases, that is, the second switching tube M2 turns on when the control terminal is at a low level, and the second switching tube M2 turns off when the control terminal is at a high level. That is, when the output control node Q is at the second potential, the first switching tube M1 is turned on, the second switching tube M2 is turned off, the scan signal output terminal Gout (a) outputs the scan signal, when the output control node Q is at the first potential, the first switching tube M1 is turned off, the second switching tube M2 is turned on, the scan signal output terminal Gout (a) stops outputting the scan signal, and the residual charge is turned on to the second voltage terminal Vss2 through the second switching tube M2, so as to avoid the influence of the residual charge on the output of the scan signal.

Because the first switching tube M1 and the second switching tube M2 are simultaneously controlled by the output control node Q, the first switching tube M1 and the second switching tube M2 can synchronously control the scanning signal output end Gout (a), so that the scanning signal output end Gout (a) immediately pulls down the scanning signal output end Gout (a) to a low potential when stopping outputting the scanning signal, the influence of residual charges on the scanning signal is effectively avoided when the scanning signal output end Gout (a) stops receiving the clock signal until the scanning signal is pulled down to the low potential, and the occurrence of multiple signals in the scanning line is prevented.

When the fourth switching tube M4 is turned on, the output control node Q is connected to the second low voltage terminal Vss2, that is, the control terminals of the first switching tube M1 and the second switching tube M2 are simultaneously connected to the second low voltage terminal Vss2, so that the first switching tube M1 is turned off under the control of the second low voltage terminal Vss, and the second switching tube M2 is turned on under the control of the second low voltage terminal Vss2, so that the scan signal output terminal Gout (a) is connected to the first low voltage terminal Vss1 through the second switching tube M2 while the first switching tube M1 is stopping receiving the clock signal, thereby controlling the scan signal output terminal Gout (a) to stop outputting the scan signal and directly transmitting the residual charges to the first low voltage terminal Vss1 in a very short time, and effectively avoiding the decrease of the scan signal delay caused by the signal transmission delay, thereby affecting the display effect. And the first low voltage terminal Vss1 and the second low voltage terminal Vss2 are respectively set, that is, the second low voltage terminal Vss2 controls the conduction of the first switching tube M1 and the second switching tube M2, and the first low voltage terminal Vss1 controls the discharge of the charges of the scanning signal output terminal Gout (a), so that the influence of the charges on the electric potential of the second low voltage terminal Vss2 at the first low voltage terminal Vss1 can be effectively prevented, and the node electric potential change is further influenced, so that the signal fluctuation of the scanning signal output terminal Gout (a) affects the display effect.

After the fourth switching tube M4 is controlled to be conducted, the output and the stop of the scanning signals can be realized only through the internal control of the scanning driving unit GDL, the external cascade signals are not required to control the stop of the scanning signals, the power consumption is effectively reduced, the space occupation of a circuit is reduced, meanwhile, each scanning driving unit GDL only needs four switching tubes, the size of the scanning driving unit is greatly reduced, the overall size of the scanning driving circuit is effectively reduced, and the occupation of the frame of the display panel is further reduced.

Referring to fig. 7, fig. 7 is a timing diagram of the scan signal output in fig. 5.

As shown in fig. 7, one frame image display includes consecutive first, second, third, and fourth periods T1, T2, T3, and T4, in which a-4 th scan driving units output scan signals in the first period T1, and an output control node Q in the a-th scan driving unit performs precharge according to the a-4 th scan driving unit output scan signals and rises to a second potential V2 due to a first potential V1.

In the second period T2, the output control node Q rises from the second potential V2 to the third potential V3, at this time, the first switching transistor M1 is turned on, the clock signal CLK is at a high level, and the scan signal output terminal Gout (a) outputs the scan signal according to the clock signal CLK.

In the third period T3, the output control node Q falls from the third potential V3 to the second potential V2, the clock signal CLK falls from the high level to the low level, and the scan signal output from the scan signal output terminal Gout (a) falls according to the clock signal, i.e., the scan signal output terminal Gout (a) outputs the scan signal of the low level.

In the fourth period T4, the (a+4) th scan driving unit outputs the scan signal, the fourth switching tube M4 in the (a) th scan driving unit is turned on, the potential of the output control node Q is pulled down to the first potential V1, and at this time, the second switching tube M2 is turned on to turn on the scan signal output terminal Gout (a) and the first low voltage terminal Vss1, thereby controlling the scan signal output terminal Gout (a) to stop outputting the scan signal.

Referring to fig. 8, fig. 8 is a schematic diagram of the first switching tube and the second switching tube in fig. 5.

As shown in fig. 8, the first switching tube M1 and the second switching tube M2 are disposed adjacently, and the first switching tube M1 and the second switching tube M2 are completed in the same process, the control end g1 of the first switching tube is disposed on the substrate u in a stacked manner, the insulating layer in is disposed on the control end g1 of the first switching tube far away from the substrate u, the first conductive end s1 of the first switching tube and the second conductive end d1 of the first switching tube are disposed on the insulating layer in far away from the control end g1 of the first switching tube, the first switching tube M1 further includes a first active layer a1, and the first active layer a1 is disposed between the first conductive end s1 of the first switching tube and the second conductive end d1 of the first switching tube. When a voltage is applied to the control terminal g1 of the first switching tube, conduction is performed between the first conductive terminal s1 of the first switching tube and the second conductive terminal d1 of the first switching tube through the first active layer a 1.

The layer structure of the second switching tube M2 is the same as that of the first switching tube M1, the control end g2 of the second switching tube is arranged on the substrate u in a laminated mode, the insulating layer in is arranged on the control end g2 of the second switching tube, far away from one side of the substrate u, the first conductive end s2 of the second switching tube and the second conductive end d2 of the second switching tube are arranged on the insulating layer in, far away from one side of the control end g1 of the second switching tube, the second switching tube M2 further comprises a second active layer a2, and the second active layer a2 is arranged between the first conductive end s2 and the second conductive end d2 of the second switching tube. When a voltage is applied to the control terminal g2 of the second switching tube, the first conductive terminal s2 of the second switching tube and the second conductive terminal d2 of the second switching tube are turned on via the second active layer a 2.

The control end g1 of the first switching tube and the control end g2 of the second switching tube are located on the same layer, the first conductive end s1 of the first switching tube and the first conductive end s2 of the second switching tube are located on the same layer, and the second conductive end d1 of the first switching tube and the second conductive end d2 of the second switching tube are arranged on the same layer.

Referring to fig. 9, fig. 9 is a schematic diagram of a first switching tube and a second switching tube according to the second embodiment shown in fig. 5.

As shown in fig. 9, a first switching tube M1 and a second switching tube M2 are sequentially stacked and provided with a substrate u, the first switching tube M1 and the second switching tube M2 are of a shared control end structure, the first switching tube M1 comprises a first active layer a1, the second switching tube M2 comprises a second active layer a2, the first active layer a1, a common control end g and the second active layer a2 are sequentially stacked and provided, wherein an insulating layer in is arranged between the first active layer a1 and the common control end g, and an insulating layer in is arranged between the second active layer a2 and the common control end g.

The first conductive end s1 of the first switching tube M1 is disposed on a side of the insulating layer away from the first active layer a1 and connected to the first active layer a1, and the second conductive end d1 of the first switching tube M1 is disposed on a side of the insulating layer away from the first active layer a1 and connected to the first active layer a1, and when the second voltage is applied to the common control end g, the first conductive end s1 and the second conductive end d1 of the first switching tube M1 are conducted through the first active layer a 1.

The first conductive end s2 and the second conductive end d2 of the second switching tube M2 are stacked on one side of the insulating layer in far away from the common control end g and are respectively located at two sides of the second active layer a2, the first conductive end s2 of the second switching tube M2 is connected to the second conductive end of the first switching tube M1, and when the first voltage is applied to the common control end g, the first conductive end s2 and the second conductive end d2 of the second switching tube M2 are conducted through the second active layer a 2.

By manufacturing the first switching tube M1 and the second switching tube M2 as a common control end structure, space occupation can be further saved.

It is to be understood that the invention is not limited in its application to the examples described above, but is capable of modification and variation in light of the above teachings by those skilled in the art, and that all such modifications and variations are intended to be included within the scope of the appended claims.

Claims (10)

1. The scanning driving circuit comprises n scanning driving units which are sequentially cascaded, wherein n is an integer greater than 1, and the n scanning driving units are used for sequentially outputting corresponding scanning signals which are used for controlling the pixel units to receive data signals for image display so as to display images;

The scanning driving unit a comprises an output module, a pull-down module, an output control node and a scanning signal output end, wherein a is more than or equal to 1 and less than or equal to n, the output module is connected with the output control node and the scanning signal output end, the pull-down module is connected with the output control node and the scanning signal output end, when the voltage of the output control node is a first potential, the pull-down module controls the scanning signal output end to stop outputting the scanning signal and maintain the scanning signal at the first potential, and when the voltage of the output control node is a second potential, the output module controls the scanning signal output end to output the scanning signal, and the second potential is larger than the first potential.

2. The scan driving circuit as claimed in claim 1, wherein the output module is further connected to a clock signal terminal, the pull-down module is further connected to a first low voltage terminal, and when the output control node is at the first potential, the output module stops controlling the scan signal output terminal to output the scan signal according to the clock signal output from the clock signal terminal, and the pull-down module controls the scan signal output terminal to be connected to the first low voltage terminal, so as to transfer charges in the scan signal output terminal to the first low voltage terminal.

3. The scan driving circuit according to claim 2, wherein the output module comprises a first switching tube, the first switching tube comprises a control end, a first conductive end and a second conductive end, the control end of the first switching tube is connected to the output control node, the first conductive end of the first switching tube is connected to the clock signal end, the second conductive end of the first switching tube is connected to the scan signal output end, the first switching tube is turned on when the output control node is at the second potential, and the clock signal is transmitted to the scan signal output end through the first conductive end and the second conductive end and is output as the scan signal.

4. The scan driving circuit as recited in claim 3, wherein said pull-down module comprises a second switching tube, said second switching tube comprising a control terminal, a first conductive terminal and a second conductive terminal, said control terminal of said second switching tube being connected to said output control node, said first conductive terminal of said second switching tube being connected to said scan signal output terminal, said second conductive terminal of said second switching tube being connected to said first low voltage terminal, said second switching tube being adapted to be turned on when said output control node is at said first potential to switch said scan signal output terminal to said first low voltage terminal.

5. The scan driving circuit according to claim 4, wherein the first switching transistor is an N-type transistor and the second switching transistor is a P-type transistor.

6. The scan driving circuit according to claim 5, wherein the first switching tube and the second switching tube are disposed on the same substrate and are disposed adjacent to each other, a control end of the first switching tube is disposed on a surface of the substrate, and a first conductive end and a second conductive end of the first switching tube are disposed on a side of the control end of the first switching tube away from the substrate in a stacked manner;

The control end of the second switching tube is overlapped on the substrate, and the first conductive end and the second conductive end of the second switching tube are arranged on one side, far away from the substrate, of the control end of the second switching tube in the same-layer mode;

The control end of the first switching tube and the control end of the second switching tube are located on the same layer, and the first conductive end and the second conductive end of the first switching tube and the first conductive end and the second conductive end of the second switching tube are located on the same layer.

7. The scan driving circuit according to claim 5, wherein the first switching tube and the second switching tube are sequentially stacked and arranged on a substrate, the first switching tube and the second switching tube share a same control end, the first switching tube comprises a first active layer, the second switching tube comprises a second active layer, the first active layer, a common control end and the second active layer are sequentially stacked and arranged on the substrate, and an insulating layer is arranged between the first active layer and the common control end and between the second active layer and the common control end;

The first conducting end of the first switch tube is arranged on one side, far away from the first active layer, of the insulating layer in a stacked mode and is connected with the first active layer, and the second conducting end of the first switch tube is arranged on one side, far away from the first active layer, of the insulating layer in a stacked mode and is connected with the first active layer;

The first conducting end and the second conducting end of the second switching tube are arranged on one side, far away from the common control end, of the insulating layer in a stacked mode and are respectively located on two sides of the second active layer, the first conducting end of the second switching tube and the second conducting end of the first switching tube are located on the same layer, and the first conducting end of the second switching tube is connected to the second conducting end of the first switching tube.

8. The scan driving circuit according to any one of claims 1 to 7, further comprising a pull-up module and a reset module, wherein the pull-up module is connected to the scan signal output terminal of the a-4 th scan driving unit and the output control node, and is configured to pull up the output control node from the first potential to the second potential under control of the scan signals output from the a-4 th scan driving unit;

The reset module is connected to the scan signal output end of the (a+4) th scan driving unit and the output control node, and is used for pulling down the output control node from the second potential to the first potential under the control of the scan signal output by the (a+4) th scan driving unit.

9. The scan driving circuit according to claim 8, wherein the pull-up module includes a third switching tube, the reset module includes a fourth switching tube, the third switching tube includes a control terminal, a first conductive terminal and a second conductive terminal, the control terminal and the first conductive terminal of the third switching tube are connected to the scan signal output terminals of the a-4 th scan driving units, the second conductive terminal of the third switching tube is connected to the output control node, and is used for being turned on under the control of the scan signals output by the a-4 th scan driving units to pull up the output control node to the second potential;

The fourth switching tube comprises a control end, a first conductive end and a second conductive end, wherein the control end of the fourth switching tube is connected with the (a+4) th scanning signal output end of the scanning driving unit, the first conductive end of the fourth switching tube is connected with the output control node, the second conductive end of the fourth switching tube is connected with the second low-voltage end and is used for being conducted under the control of the (a+4) th scanning signal output by the scanning driving unit, and the output control node is controlled to be connected with the second low-voltage end so as to pull down the output control node to the first potential.

10. A display panel, comprising a plurality of data lines, a plurality of scanning lines, a plurality of pixel units arranged in a matrix, a data driving circuit arranged in a non-display area, and a scanning driving circuit according to any one of claims 1 to 9, wherein the scanning driving circuit is configured to output a scanning signal to the pixel units through the scanning lines, and is configured to control the pixel units to receive the data signals output by the data driving circuit from the data lines for displaying images.