CN117973274A - Logic optimization method and related equipment - Google Patents

Abstract

The embodiment of the application provides a logic optimization method and related equipment. The method comprises the following steps: searching a logic netlist diagram according to N first input nodes in the logic netlist diagram, determining a first sub-diagram, wherein the first sub-diagram comprises P first intermediate nodes, the P first intermediate nodes in the P first intermediate nodes comprise N ₁ outputs, and nodes corresponding to N ₁ outputs of the P first intermediate nodes belong to the first sub-diagram; determining a second sub-graph equivalent to the first sub-graph; and optimizing the first sub-graph according to the second sub-graph. According to the method, searching can be started from N input nodes, and the first sub-graph is determined, so that all nodes corresponding to all outputs of each intermediate node in the first sub-graph belong to the first sub-graph, namely all the intermediate nodes in the first sub-graph are replaceable nodes, and after the first sub-graph is optimized, the number of nodes in a logic netlist containing the first sub-graph is reduced, and the optimization rate is improved.

Description

Logic optimization method and related equipment

Technical Field

Embodiments of the present application relate to the field of computers, and more particularly, to a logic optimization method, a computing device, a computing apparatus, and a computer-readable storage medium.

Background

In the design flow of an integrated circuit, after a register transfer level circuit (REGISTER TRANSFER LEVEL, RTL) level circuit described by a hardware description language is converted into a boolean circuit, logic optimization and process mapping, such as nand graph (AND INVERTER GRAPH, AIG) optimization or majority inverter graph (majority-INVERTER GRAPH, MIG) optimization, are required to be performed on the boolean circuit (or logic netlist) on the premise of meeting design constraints. Wherein the logic optimization is a non-deterministic polynomial (non-DETERMINISTIC POLYNOMIAL) difficult problem. The existing logic optimization method comprises a logic rewriting operator (rewrite) method, which searches an input direction according to an output node in a logic netlist and determines a cutting substructure (or cutting subgraph) of the output node. The cutting sub-structure comprises an output node, at least one input node and at least one intermediate node, wherein the output node is connected with the at least one input node through the at least one intermediate node. Each intermediate node of the at least one intermediate node may comprise at least one input and at least one output, all inputs of the each intermediate node belonging to the cut substructure, but the logical overwrite operator method does not guarantee that all outputs of the each intermediate node belong to the cut substructure. If there is at least one output of an intermediate node that does not belong to the cutting substructure, then replacing the intermediate node may affect other cutting substructures. The other cutting substructures include the intermediate node and/or at least one node corresponding to the output of the intermediate node. After determining the cutting substructure, the logic rewriting operator method also needs to determine non-replaceable nodes and/or replaceable nodes in the cutting substructure, so as to determine a proper equivalent structure to replace the cutting substructure, and further realize logic optimization of the cutting substructure on the basis of not affecting other cutting substructures. That is, the implementation process of the logic rewrite operator method is complex, and it is easy to cause that the cutting sub-structure includes more non-replaceable intermediate nodes, so that the optimized cutting sub-structure still includes more nodes, and further, the optimized logic netlist still includes more nodes.

Therefore, how to reduce the number of nodes in the optimized logic netlist, so as to improve the optimization rate of the logic optimization method is a problem to be solved.

Disclosure of Invention

The embodiment of the application provides a logic optimization method, a computing device, computing equipment and a computer readable storage medium, which can reduce the number of nodes in an optimized logic netlist, thereby providing a higher optimization rate.

In a first aspect, a logic optimization method is provided. The method comprises the following steps: searching the logic netlist diagram according to N first input nodes in the logic netlist diagram, and determining a first subgraph; determining a second sub-graph equivalent to the first sub-graph; and optimizing the first sub-graph according to the second sub-graph.

Wherein the first sub-graph belongs to the logical net-table graph. The first subgraph comprises M first output nodes, P first intermediate nodes and N first input nodes, wherein the N first input nodes are connected with the M first output nodes through the P first intermediate nodes. The P first intermediate node in the P first intermediate nodes comprises n ₁ outputs, and a node corresponding to n ₁ outputs of the P first intermediate node belongs to the first subgraph. The second sub-graph comprises N second input nodes, M second output nodes and Q second intermediate nodes. P epsilon P, N, M, P, Q, n ₁ is a positive integer greater than or equal to 1.

In the embodiment of the application, the computing device can start searching from at least one input node and determine the first sub-graph comprising at least one output node and at least one intermediate node, so that all the nodes corresponding to all the outputs of each intermediate node in the first sub-graph belong to the first sub-graph, namely all the intermediate nodes in the first sub-graph are replaceable nodes. The computing device may also determine an equivalent second sub-graph from the first sub-graph, thereby logically optimizing the first sub-graph. Because all the intermediate nodes included in the first sub-graph are replaceable nodes, the number of replaceable nodes of the computing equipment is large when the first sub-graph is logically optimized, so that the number of nodes in the optimized logic netlist is small, and the optimization rate is improved.

With reference to the first aspect, in certain implementation manners of the first aspect, determining P first intermediate nodes according to the N first input nodes; m first output nodes are determined according to the P first intermediate nodes.

The P-th first intermediate node in the P-th first intermediate nodes comprises n ₂ inputs, the node corresponding to n ₂ inputs of the P-th first intermediate node belongs to the first subgraph, and n ₂ is a positive integer greater than or equal to 1. The M first output nodes in the M first output nodes comprise M ₁ outputs, at least one node corresponding to at least one output in M ₁ outputs of the M first output nodes does not belong to the first subgraph, M epsilon M, and M ₁ is a positive integer greater than or equal to 1.

In the embodiment of the application, the computing device can mark the nodes of which all the nodes corresponding to the input belong to the first sub-graph as the first intermediate nodes, and mark the nodes of which one node corresponding to the output does not belong to the first sub-graph as the first output nodes, so that each first intermediate node in the first sub-graph is ensured to be a replaceable node.

With reference to the first aspect, in certain implementations of the first aspect, a third sub-graph is determined from the first sub-graph; and determining a second sub-graph according to the third sub-graph.

The third sub-graph comprises N third input nodes, M third output nodes and P third intermediate nodes. The first sub-graph is different from at least one of the following in the third sub-graph: the polarity of at least one input node, the order of arrangement of at least two input nodes, or the polarity of at least one output node. When the value of the nth third input point in the N third input nodes is the same as the value of the nth second input node in the N second input nodes, the value of the mth third output node in the M third output nodes is the same as the value of the mth second output node in the M second output nodes. N epsilon N and M epsilon M.

In the embodiment of the application, the computing device can determine whether the third sub-graph is logically equivalent to the second sub-graph according to whether the values of the corresponding output nodes are the same when the values of the corresponding input nodes are the same, so as to determine the second sub-graph. In other words, the computing device may determine the second sub-graph that is logically equivalent to the third sub-graph based on whether the truth table of the third sub-graph matches the truth table of the second sub-graph.

With reference to the first aspect, in some implementations of the first aspect, the second sub-graph is adjusted according to the first adjustment mode, to obtain an adjusted second sub-graph; and replacing the first sub-graph with the adjusted second sub-graph.

The first adjustment mode is an inverse mode of the second adjustment mode, and the second adjustment mode is used for adjusting the first sub-graph into a third sub-graph, wherein P is larger than Q.

In the embodiment of the application, the computing device can adjust the second sub-graph when the number of the nodes contained in the second sub-graph is smaller than the number of the nodes contained in the third sub-graph, so that the adjusted second sub-graph is equivalent to the first sub-graph, and further, the situation that other sub-graphs in the logic network graph cannot be influenced after the first sub-graph is replaced is ensured.

With reference to the first aspect, in some implementation manners of the first aspect, according to a first adjustment manner, a polarity of at least one second input node of N second input nodes in the second sub-graph is adjusted, so as to obtain an adjusted second sub-graph; and/or according to the first adjustment mode, adjusting the arrangement sequence of at least two second input nodes in the N second input nodes in the second subgraph to obtain an adjusted second subgraph; and/or according to the first adjustment mode, adjusting the polarity of at least one second output node in the M second output nodes in the second subgraph to obtain an adjusted second subgraph.

In the embodiment of the present application, the computing device may make the adjusted second subgraph equivalent to the first subgraph by adjusting any one or more of the polarity of at least one second input node, the arrangement order of at least two second input nodes, or the polarity of at least one second output node in the second subgraph, or by a manner opposite (or inverse) to the adjustment manner in which the third subgraph is obtained.

With reference to the first aspect, in certain implementations of the first aspect, when P is less than Q, the second sub-graph is replaced with the third sub-graph in the optimal sub-graph set. The optimal sub-graph set comprises at least one optimal sub-graph, and the second sub-graph belongs to the optimal sub-graph set.

In the embodiment of the application, the computing device can update the optimal sub-graph set when the second sub-graph is logically equivalent to the third sub-graph and the number of nodes in the second sub-graph is more than the number of nodes in the third sub-graph, thereby ensuring that the optimal sub-graph included in the optimal sub-graph set is the sub-graph with the least number of nodes in the logical equivalent class to which the optimal sub-graph belongs.

In a second aspect, embodiments of the present application provide a computing device comprising means for implementing the first aspect or any one of the possible implementations of the first aspect.

In a third aspect, embodiments of the present application provide a computing device comprising a processor for coupling with a memory, reading and executing instructions and/or program code in the memory to perform the first aspect or any one of the possible implementations of the first aspect.

In a fourth aspect, embodiments of the present application provide a chip system comprising logic circuitry for coupling with an input/output interface through which data is transferred for performing the first aspect or any one of the possible implementations of the first aspect.

In a fifth aspect, embodiments of the present application provide a computer readable storage medium storing program code which, when run on a computer, causes the computer to perform any one of the possible implementations as in the first aspect or the first aspect.

Drawings

FIG. 1 is a schematic block diagram of a logic optimization system 100 in accordance with one embodiment of the application.

FIG. 2 is a schematic flow chart diagram of a logic optimization method in accordance with one embodiment of the application.

Fig. 3 is a schematic diagram of a first sub-graph according to one embodiment of the application.

FIG. 4 is a schematic flow chart diagram of a logic optimization method in accordance with one embodiment of the application.

FIG. 5 is a schematic diagram of a computing device according to one embodiment of the application.

FIG. 6 is a schematic diagram of a computing device according to one embodiment of the application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings.

The technical solution of the embodiment of the present application may be applied to logic optimization in various scenarios, for example, logic optimization in a field programmable gate array (field programmable GATE ARRAY, FPGA), application SPECIFIC INTEGRATED Circuit (ASIC), or simulator (emulator), which is not limited by the embodiment of the present application. The technical scheme of the embodiment of the application can also be applied to the optimization of various logic network table diagrams, such as the logic network table diagrams of AIG, MIG, AND or AND diagrams and other characterization forms, and the embodiment of the application is not limited to the optimization. The technical solution of the embodiment of the present application may also be applied to various computing devices, such as a host, a server, a notebook computer, a desktop computer, a workstation, etc., which is not limited thereto.

FIG. 1 is a schematic block diagram of a logic optimization system 100 provided by an embodiment of the present application. The logic optimization system 100 as shown in FIG. 1 includes a determination component 110 and an optimization component 120. The determining component 110 includes a searching module 111, a negative permutation-negation (NPN) calculating module 112, and a storing module 113.

The determining component 110 may search the logic netlist diagram according to the N first input nodes in the logic netlist diagram to determine a first subgraph. The first sub-graph belongs to the logic network table graph, and the logic network table graph comprises at least one sub-graph. The first subgraph comprises M first output nodes, P first intermediate nodes and N first input nodes, wherein the N first input nodes are connected with the M first output nodes through the P first intermediate nodes. The P-th first intermediate node in the P first intermediate nodes comprises n ₁ outputs, the node corresponding to n ₁ outputs of the P-th first intermediate node belongs to a first subgraph, P epsilon P and N, M, P, n ₁ are positive integers which are larger than or equal to 1. The step of determining the first sub-graph may be performed by the search module 111.

The search module 111 may determine P first intermediate nodes from the N first input nodes. The P-th first intermediate node in the P first intermediate nodes comprises n ₂ inputs, the node corresponding to n ₂ inputs of the P-th first intermediate node belongs to the first subgraph, and n ₂ is a positive integer greater than or equal to 1. That is, the search module 111 may first mark N first input nodes and then mark nodes conforming to the first marking rule, thereby determining P first intermediate nodes. The first marking rule includes that all the nodes corresponding to the inputs of the nodes are marked nodes, and the marked nodes are marked nodes. The search module 111 may further determine M first output nodes from the P first intermediate nodes. The mth first output node in the M first output nodes comprises M ₁ outputs, at least one node corresponding to M ₁ outputs of the mth first output node does not belong to the first subgraph, and M ₁ is a positive integer greater than or equal to 1. That is, when a node conforming to the second marking rule is searched, the search module 111 marks the node as an output node, thereby determining M first output nodes. The second marking rule includes that at least one input of a node corresponding to at least one output of the node is an unmarked node, and the unmarked node is an unmarked node. Or the second marking rule includes that a node corresponding to at least one output of the node is an unlabeled node. Since the search module 111 searches the logic netlist diagram starting from the input node and determines intermediate nodes and output nodes according to the first and second labeling rules, all outputs of each first intermediate node included in the first sub-graph determined by the search module 111 belong to the first sub-graph. That is, each intermediate node in the first sub-graph is replaced without affecting other nodes in the logical network table graph, including any node in the logical network table graph other than the node included in the first sub-graph. That is, each intermediate node in the first sub-graph is an alternative node.

The determination component 110 can also determine a second sub-graph that is logically equivalent to the first sub-graph. The second sub-graph comprises N second input nodes, M second output nodes and Q second intermediate nodes, wherein Q is a positive integer greater than or equal to 1. When the logic equivalence of the first sub-graph and the second sub-graph is the same value of each first input node in the first sub-graph and the second input node in the corresponding second sub-graph, the logic equivalence of each first output node in the first sub-graph and the second output node in the corresponding second sub-graph is the same value. N first input nodes in the first sub-graph are in one-to-one correspondence with N second input nodes in the second sub-graph, and M first output nodes in the first sub-graph are in one-to-one correspondence with M second output nodes in the second sub-graph. The step of determining the second sub-graph may be performed by NPN calculation module 112.

NPN calculation module 112 may determine a third subgraph from the first subgraph. The third sub-graph includes N third input nodes, M third output nodes, and P third intermediate nodes. The first sub-graph is different from at least one of the following in the third sub-graph: the polarity of at least one input node, the order of arrangement of at least two input nodes, or the polarity of at least one output node. The polarity of the nodes includes either positive or negative. If the polarity of the node is positive, the node does not need to be reversed; if the polarity of the node is reversed, the node needs to be reversed. Inverting a node refers to making the value output by the node 0 when the value input by the node is 1, and making the value output by the node 1 when the value input by the node is 0. NPN calculation module 112 may adjust the first subgraph according to the second adjustment manner to obtain a third subgraph. The second adjustment means comprises adjusting at least one of: the polarity of at least one first input node, the order of arrangement of at least two first input nodes, or the polarity of at least one first output node. NPN calculation module 112 may also determine a second subgraph from the third subgraph. When the value of the nth third input point in the N third input nodes is the same as the value of the nth second input node in the N second input nodes, the value of the mth third output node in the M third output nodes is the same as the value of the mth second output node in the M second output nodes, and N is N epsilon N and M epsilon M. Alternatively, the truth table of the third sub-graph matches the truth table of the second sub-graph.

The storage module 113 may store therein information of at least one sub-graph determined by the search module 111. For example, the topology information of the first sub-graph may be stored in the storage module 113. The topology information of the first sub-graph includes nodes included in the first sub-graph and connection relations between the nodes. The connection relationship between nodes is used to represent a logical operation relationship between nodes, which may include not, and, or, exclusive or, etc., and the embodiment of the present application is not limited thereto. The number of nodes included in the first sub-graph may also be stored in the storage module 113. The storage module 113 may also store therein an optimal sub-graph set. The optimal sub-graph set comprises at least one optimal sub-graph, and each optimal sub-graph in the at least one optimal sub-graph is the sub-graph with the least number of nodes contained in the logical equivalence class to which the sub-graph belongs. All sub-graphs contained in a logical equivalence class are logically equivalent to each other. The logical equivalent may be, for example, N equivalent, NP equivalent, NPN equivalent, or the like. The second sub-graph belongs to the optimal sub-graph set.

The optimization component 120 can optimize the first subgraph based on the second subgraph. Specifically, the optimizing component 120 may adjust the second sub-graph according to the first adjustment manner, and obtain an adjusted second sub-graph. The first adjustment mode is the inverse mode of the second adjustment mode, and P is greater than Q. In other words, the optimizing component 120 may adjust the second sub-graph according to the first adjustment manner when the number of nodes included in the second sub-graph is smaller than the number of nodes included in the third sub-graph, to obtain an adjusted second sub-graph. For example, the optimization component 120 may adjust the polarity of at least one of the N second input nodes in the second sub-graph according to the first adjustment manner, to obtain an adjusted second sub-graph. Or the optimizing component 120 may adjust the arrangement order of at least two second input nodes in the N second input nodes in the second sub-graph according to the first adjustment manner, to obtain an adjusted second sub-graph. Or the optimizing component 120 may adjust the polarity of at least one second output node of the M second output nodes in the second sub-graph according to the first adjustment manner, to obtain an adjusted second sub-graph. Or the optimization component 120 can adjust any of the following in the second sub-graph according to the first adjustment: the polarity of at least one of the N second input nodes, the arrangement order of at least two of the N second input nodes, or the polarity of at least one of the M second output nodes. The optimization component 120 can also replace the first sub-graph with the adjusted second sub-graph. The optimization component 120 can also replace the second sub-graph with the third sub-graph in the optimal sub-graph set when P is less than Q. In other words, the optimization component 120 can update the second sub-graph in the optimal sub-graph set to the third sub-graph when the number of nodes included in the second sub-graph is greater than the number of nodes included in the third sub-graph.

The logic optimization system 100 shown in fig. 1 may be run in a computing device. The logic optimization system 100 as shown in fig. 1 may start searching from at least one input node and determine a first sub-graph including at least one output node and at least one intermediate node, so that all the nodes corresponding to all the outputs of each intermediate node in the first sub-graph belong to the first sub-graph, that is, all the intermediate nodes in the first sub-graph are replaceable nodes. The logic optimization system 100 may also determine an equivalent second sub-graph from the first sub-graph to logically optimize the first sub-graph. Because all the intermediate nodes included in the first sub-graph are replaceable nodes, the logic optimization system 100 can replace more nodes when performing logic optimization on the first sub-graph, so that the number of nodes in the optimized logic netlist is less, and the optimization rate is improved.

FIG. 2 is a schematic flow chart of a logic optimization method provided by an embodiment of the present application, where the method of FIG. 2 may be performed by the logic optimization system 100 of FIG. 1. The method of fig. 2 includes the following steps.

S210, searching the logic netlist diagram according to N first input nodes in the logic netlist diagram, and determining a first subgraph.

The computing device may search the logical netlist graph according to the at least one input node to determine at least one subgraph. Each sub-graph of the at least one sub-graph belongs to the logical net-list graph. For example, the computing device may search the logical netlist diagram according to the N first input nodes in the logical netlist diagram to determine a first subgraph. The first subgraph comprises M first output nodes, P first intermediate nodes and N first input nodes, wherein the N first input nodes are connected with the M first output nodes through the P first intermediate nodes. The P-th first intermediate node in the P-th first intermediate nodes comprises n ₁ outputs, and nodes corresponding to n ₁ outputs of the P-th first intermediate node belong to the first subgraph. P epsilon P, N, M, P, n ₁ is a positive integer greater than or equal to 1.

Alternatively, the computing device may determine N first input nodes prior to step S210. The logic network table diagram may include at least one input node, and the N first input nodes are N nodes in the at least one input node in the logic network table diagram. The value of N is a preset value, for example, may be 3,4, 5, etc. If the value of N is larger, the number of the nodes contained in the obtained first sub-graph is larger. If the value of N is smaller, the number of the nodes contained in the obtained first sub-graph is smaller.

Alternatively, the computing device may determine P first intermediate nodes from the determined N first input nodes. The P-th first intermediate node in the P-th first intermediate nodes comprises n ₂ inputs, the node corresponding to n ₂ inputs of the P-th first intermediate node belongs to the first subgraph, and n ₂ is a positive integer greater than or equal to 1.

Optionally, the computing device may further determine M first output nodes from the P first intermediate nodes. The M first output nodes in the M first output nodes comprise M ₁ outputs, and a node corresponding to at least one of M ₁ outputs of the M first output nodes does not belong to the first subgraph. m.epsilon.M, M ₁ is a positive integer greater than or equal to 1.

In some embodiments, the first sub-graph determined by the computing device is as shown in fig. 3.

Fig. 3 is a schematic diagram of a first sub-graph according to an embodiment of the present application. The first sub-graph shown in fig. 3 includes 5 first input nodes, I1, I2, I3, I4, and I5, respectively. The first sub-graph also comprises 9 first intermediate nodes, namely A1, A2, A3, A4, A5, A6, A7, A8 and A9. The first subgraph also comprises 3 first output nodes, namely O1, O2 and O3. The first sub-graph shown in fig. 3 belongs to an AIG graph. Each node in fig. 3 represents an and operation, and a broken line represents a non-operation (or an inverse operation). For example, the node A1 in fig. 3 represents performing an and operation on the values output by I2 and I3, and the node A3 represents performing a non-operation on the value output by A1, and then performing an and operation on the result of the non-operation and the value output by I1.

In some embodiments, the computing device determines, from the 5 first input nodes as shown in fig. 3, the first subgraph as shown in fig. 3 by: first, the determined N first input nodes are marked, i.e. the nodes I1 to I5 are marked. The marked nodes belong to the first subgraph and the unmarked nodes do not belong to the first subgraph. And secondly, marking the nodes conforming to the first marking rule, thereby determining P first intermediate nodes. The first marking rule includes that all the nodes corresponding to the inputs of the nodes are marked nodes, and the marked nodes are marked nodes. For example, since nodes I2 and I3 are marked nodes, node A1 may be marked in compliance with the first marking rule. Similarly, nodes A2 through A9 may be marked to determine 9 first intermediate nodes. And finally, marking the nodes conforming to the second marking rule as output nodes, thereby determining M first output nodes. The second marking rule includes that at least one input of a node corresponding to at least one output of the node is an unmarked node, and the unmarked node is an unmarked node. For example, it is assumed that two nodes a10 and a11 are also included in the AIG graph to which the first sub-graph shown in fig. 3 belongs. The node a11 is used to and the values output by the nodes a10 and O1, i.e. the node a11 is connected to the nodes a10, O1, and the node a10 is not connected to any node as shown in fig. 3 in the AIG graph, i.e. the node a10 is an unlabeled node. Since one input a10 of the node a11 to which one output of O1 corresponds is an unlabeled node, O1 complies with the second labeling rule, i.e., O1 is labeled as the first output node. Or the second marking rule includes that a node corresponding to at least one output of the node is an unlabeled node. For example, since node a10 is an unlabeled node, node a11 does not meet the first labeling rule, i.e., node a11 is an unlabeled node. Also, since the node a11 corresponding to one output of O1 belongs to an unlabeled node, O1 conforms to the second labeling rule, i.e., O1 is labeled as the first output node. Similarly, nodes O2 and O3 may be marked to determine 3 first output nodes. Since each first intermediate node in the first sub-graph as shown in fig. 3 meets the first marking rule and each first output node meets the second marking rule, all outputs of each first intermediate node in the first sub-graph as shown in fig. 3 belong to the first sub-graph, i.e. each first intermediate node is a replaceable node.

Optionally, the computing device may search the logic netlist diagram according to the at least one first input node to determine a first sub-graph. The computing device may also search the logic netlist diagram according to at least one fourth input node to determine a fourth sub-graph. The at least one first input node and the at least one fourth input node belong to the logical network table diagram, the at least one fourth input node not being identical to the at least one first input node. For example, the at least one first input node may include input nodes I1, I2, I3, and I4 as shown in fig. 3, and the at least one fourth input node may include input nodes I2, I3, I4, and I5 as shown in fig. 3. The first sub-graph and the fourth sub-graph belong to the logical net-table graph, and the first sub-graph is different from the fourth sub-graph.

S220, determining a second sub-graph logically equivalent to the first sub-graph.

The computing device may determine, after determining the first sub-graph, a second sub-graph from the optimal sub-graph set that is logically equivalent to the first sub-graph. The second sub-graph comprises N second input nodes, M second output nodes and Q second intermediate nodes, wherein Q is a positive integer greater than or equal to 1. When the logic equivalence of the first sub-graph and the second sub-graph is the same value of each first input node in the first sub-graph and the second input node in the corresponding second sub-graph, the logic equivalence of each first output node in the first sub-graph and the second output node in the corresponding second sub-graph is the same value. N first input nodes in the first sub-graph are in one-to-one correspondence with N second input nodes in the second sub-graph, and M first output nodes in the first sub-graph are in one-to-one correspondence with M second output nodes in the second sub-graph. In other words, the first sub-graph and the second sub-graph are logically equivalent to the truth table of the first sub-graph matching the truth table of the second sub-graph.

Optionally, at least one optimal sub-graph is included in the optimal sub-graph set. Each optimal sub-graph in the at least one optimal sub-graph is the sub-graph with the least number of nodes contained in the logical equivalence class to which the sub-graph belongs. All sub-graphs contained in a logical equivalence class are logically equivalent to each other. The logical equivalence class may be an N equivalence class, an NP equivalence class, or an NPN equivalence class. The second sub-graph belongs to the optimal sub-graph set.

Optionally, prior to step S220, the computing device may obtain an optimal sub-graph set. The computing device may determine the optimal sub-graph set itself or the computing device may obtain the optimal sub-graph set through other devices connected to the computing device, as the embodiments of the application are not limited in this respect.

Alternatively, the computing device may determine the second sub-graph logically equivalent to the first sub-graph through an exhaustive approach. Specifically, the computing device may obtain the truth table of the first subgraph by adjusting any one or more of the polarities of the N first output nodes, the arrangement order of the N first output nodes, or the polarities of the M first output nodes of the first subgraph. The computing device may also determine a second sub-graph that matches the truth table of the first sub-graph based on the truth table of the first sub-graph. Matching the truth table of the first sub-graph with the truth table of the second sub-graph means: when the value of each first input node in the first sub-graph is the same as the value of the second input node in the corresponding second sub-graph, the value of each first output node in the first sub-graph is the same as the value of the second output node in the corresponding second sub-graph.

Alternatively, the computing device may determine a third sub-graph from the first sub-graph and determine a second sub-graph from the third sub-graph. The third sub-graph includes N third input nodes, M third output nodes, and P third intermediate nodes. The first sub-graph is different from at least one of the following in the third sub-graph: the polarity of at least one input node, the order of arrangement of at least two input nodes, or the polarity of at least one output node. The polarity of the nodes includes either positive or negative. If the polarity of the node is positive, the node does not need to be reversed; if the polarity of the node is reversed, the node needs to be reversed. Inverting a node refers to making the value output by the node 0 when the value input by the node is 1, and making the value output by the node 1 when the value input by the node is 0. The node being not inverted means that the value output through the node is made to be 1 when the value input by the node is 1, and the value output through the node is made to be 0 when the value input by the node is 0.

Optionally, the computing device may determine a second adjustment manner according to the semi-normalization rule and the first sub-graph, thereby adjusting the first sub-graph to a third sub-graph according to the second adjustment manner.

When the semi-normalized rule includes an input negation rule, the second adjustment mode is used for indicating to negate at least one first input node of the N first input nodes in the first sub-graph, so as to obtain a third sub-graph. Or, the second adjustment mode is used for indicating to adjust the polarity of at least one first input node in the N first input nodes in the first sub-graph.

For example, the inverting rule of the input may be to sequentially fix the value of one first input node of the N first input nodes, and determine the number of 0 and 1 in the values of the M first output nodes under various values, so as to determine whether the first input node needs to be inverted, that is, determine the second adjustment mode. The various values include the case that one of the N first input nodes is fixed with a value, and the other of the N first input nodes is arbitrarily valued.

For example, it is assumed that the first sub-graph is shown in fig. 3, that is, it is assumed that 5 first input nodes I1 to I5 and 3 first output nodes O1 to O3 are included in the first sub-graph. First, the value of the first input node I1 is fixed to 0, and any value of the first input nodes I2 to I5 is 0 or 1, so as to obtain a first type of value condition. The first class of value cases comprises 2x2 = 16 values. According to 16 value cases in the first type of value cases, the number of the value 0 and 1 in M (at this time M=3) first output nodes in each value case is determined, so that the total number of the value 0 and 1 in M first output nodes in the first type of value case is determined. Then, the value of the first input node I1 is fixed to be1, and any value of the first input nodes I2 to I5 is set to be 0 or 1, so that a second type of value condition is obtained. The second class of value case comprises 2x2 = 16 values. And determining the number of the values of 0 and 1 in the M first output nodes under each value condition according to 16 value conditions in the second class value condition, thereby determining the total number of the values of 0 and 1 in the M first output nodes under the second class value condition. If the total number of 0 s in the values of the M first output nodes is greater than the total number of 1 s under the condition of the first class of values, and the total number of 0 s in the values of the M first output nodes is less than the total number of 1 s under the condition of the second class of values, determining that the second adjustment mode includes inverting the first input node I1. If the total number of 0 s in the values of the M first output nodes is less than the total number of 1 s under the condition of the first class of values, and the total number of 0 s in the values of the M first output nodes is more than the total number of 1 s under the condition of the second class of values, determining that the second adjustment mode does not include inverting the first input node I1. Similarly, it is determined whether the second adjustment mode includes inverting the first input nodes I2 through I5.

Or if the total number of 0s in the values of the M first output nodes is more than the total number of 1s under the condition of the first class of values, and the total number of 0s in the values of the M first output nodes is less than the total number of 1s under the condition of the second class of values, determining that the second adjustment mode does not comprise inverting the first input node I1. If the total number of 0s in the values of the M first output nodes is less than the total number of 1s in the case of the first class of values, and the total number of 0s in the values of the M first output nodes is more than the total number of 1s in the case of the second class of values, determining the second adjustment mode includes inverting the first input node I1, which is not limited in the embodiment of the present application. Similarly, it is determined whether the second adjustment mode includes inverting the first input nodes I2 through I5.

Or the computing device may determine only the total number of 0 s and 1 s of the M first output nodes in the case of the first class of values. If the total number of 0 s in the M first output nodes is less than the total number of 1 s under the condition of the first class of values, determining the second adjustment mode includes inverting the first input node I1. If the total number of 0 in the values of the M first output nodes is greater than the total number of 1 under the condition of the first class value, determining that the second adjustment mode does not include inverting the first input node I1. Or if the total number of 0 in the values of the M first output nodes is less than the total number of 1 under the condition of the first class value, determining that the second adjustment mode does not include inverting the first input node I1. If the total number of 0 s in the M first output nodes is greater than the total number of 1 s under the condition of the first class of values, determining the second adjustment mode includes inverting the first input node I1, which is not limited by the embodiment of the present application. Similarly, it is determined whether the second adjustment mode includes inverting the first input nodes I2 through I5.

Or the computing device may determine only the total number of 0 s and 1 s of the values of the M first output nodes in the case of the second class of values. If the total number of 0 in the values of the M first output nodes is less than the total number of 1 under the condition of the second class of values, determining the second adjustment mode includes inverting the first input node I1. If the total number of 0 in the values of the M first output nodes is greater than the total number of 1 under the condition of the second class of values, determining that the second adjustment mode does not include inverting the first input node I1. Or if the total number of 0 in the values of the M first output nodes is less than the total number of 1 under the condition of the second class of values, determining that the second adjustment mode does not include inverting the first input node I1. If the total number of 0 s in the values of the M first output nodes is greater than the total number of 1 s under the condition of the second class of values, determining the second adjustment mode includes inverting the first input node I1, which is not limited by the embodiment of the present application. Similarly, it is determined whether the second adjustment mode includes inverting the first input nodes I2 through I5.

It is assumed that the second adjustment mode determined by the above method includes inverting the first input nodes I1 and I2. Since neither of I1 and I2 is required to be inverted in the first sub-graph shown in fig. 3, it is possible to adjust the connection line between I1 and A3 in the first sub-graph shown in fig. 3 to be a broken line, and adjust the connection line between I2 and A1 to be a broken line, and the connection relationship between the remaining nodes is unchanged, thereby obtaining the third sub-graph. That is, the difference between the third sub-graph and the first sub-graph determined according to the second adjustment mode is: the polarities of the first input node I1 and the third input node I1 are different, and the polarities of the first input node I2 and the third input node I2 are different.

When the semi-normalized rule includes an input arrangement rule, the second adjustment mode is used for indicating to adjust the sequence of at least two first input nodes in the N first input nodes in the first sub-graph, so as to obtain a third sub-graph. Or, the second adjustment mode is used for indicating to adjust the arrangement sequence of at least two first input nodes in the N first input nodes in the first sub-graph.

For example, the input arrangement rule may be to sequentially fix the value of one first input node of the N first input nodes, and determine the number of 0 and 1 in the values of the M first output nodes under various values, so as to determine whether to adjust the arrangement sequence of at least two first input nodes of the N first input nodes, that is, determine the second adjustment manner. The various values include the case that one of the N first input nodes is fixed with a value, and the other of the N first input nodes is arbitrarily valued.

For example, it is assumed that the first sub-graph is shown in fig. 3, that is, it is assumed that 5 first input nodes I1 to I5 and 3 first output nodes O1 to O3 are included in the first sub-graph. First, similar to the input inversion rule, a second type of value case when the value of the first input node I1 is determined, and the total number of values of 0 in M (at this time, m=3) first output nodes in the second type of value case is determined. Secondly, according to a similar method, a third class value case when the value of the first input node I2 is 1, a fourth class value case when the value of the first input node I3 is 1, a fifth class value case when the value of the first input node I4 is 1, and a sixth class value case when the value of the first input node I5 is 1 are determined, and the total number of 0 in the M first output nodes from the third class value case to the sixth class value case is respectively determined. And then, according to the total number of 0 in the values of the M first output nodes from the second class value to the sixth class value, the first input nodes I1 to I5 are ordered in a descending order, so that a second adjustment mode is determined.

For example, if the total number of 0s in the values of the M first output nodes is the largest in the values of the second class to the sixth class, and the total number of 0s in the values of the M first output nodes is inferior to the third class, determining that the second adjustment method includes adjusting the arrangement order of the first input nodes I1 and I2.

Or the computing device may perform ascending order on the first input nodes I1 to I5 according to the total number of 0 in the values of the M first output nodes from the second class of values to the sixth class of values, so as to determine the second adjustment mode.

Or the computing device may determine 5 types of value cases when each of the first input nodes I1 to I5 respectively takes a value of 0, and determine a total number of 0 in the values of M first output nodes under each type of value case. The computing device may further sort the first input nodes I1 to I5 in ascending order according to the total number of 0 in the values of the M first output nodes under the 5-class value condition, so as to determine the second adjustment mode. Or the computing device may further sort the first input nodes I1 to I5 in descending order according to the total number of 0 in the values of the M first output nodes under the 5-class value condition, so as to determine the second adjustment mode, which is not limited by the embodiment of the present application.

Assuming that the second adjustment manner determined by the above method includes adjusting the arrangement order of the first input nodes I1 and I2, the difference between the third sub-graph and the first sub-graph determined according to the second adjustment manner is: the first input nodes I1, I2 are arranged in a different order from the third input nodes I1, I2. For example, assuming that the arrangement order of the first input nodes in the first sub-graph is I1, I2, I3, I4, I5, the arrangement order of the third input nodes in the third sub-graph is I2, I1, I3, I4, I5.

When the semi-normalized rule includes an output negation rule, the second adjustment manner is used for indicating to negate at least one first output node of the M first output nodes in the first sub-graph, thereby obtaining a third sub-graph. Or, the second adjustment mode is used for indicating to adjust the polarity of at least one first output node in the M first output nodes in the first sub-graph.

For example, the inverting rule of the output may be that after determining the polarity and the arrangement order of the N first input nodes, the number of 0 and 1 in the value of each of the M first output nodes under various values is determined, so as to determine whether the first output node needs to be inverted, that is, determine the second adjustment manner. The various values include the case where the N first input nodes respectively take a value of 0 or 1, in the case where the polarities and the arrangement order of the N first input nodes are fixed. The specific manner of determining the polarity of the N first input nodes may be similar to the inverting rule of the input, and the specific manner of determining the arrangement sequence of the N first input nodes may be similar to the arrangement rule of the input, which is not described herein.

For example, it is assumed that the first sub-graph is shown in fig. 3, that is, it is assumed that 5 first input nodes I1 to I5 and 3 first output nodes O1 to O3 are included in the first sub-graph. Firstly, the values of the 5 first input nodes are respectively 0 or 1, obtain 2X 2 =32 values. Then, in the case of determining the 32 values, the value of each of the 3 first output nodes is the total of 0 and 1. If the total number of 0s in the values of the 32 kinds of values is less than the total number of 1 s, determining the second adjustment mode includes inverting the first output node O1. If the total number of 0s in the values of the 32 kinds of values is greater than the total number of 1 s, the second adjustment method is determined not to include inverting the first output node O1. Similarly, it is determined whether the second adjustment mode includes inverting the first output nodes O2 and O3.

Or if the total number of 0s in the values of the 32 kinds of values is less than the total number of 1 s, determining that the second adjustment mode does not include inverting the first output node O1. If the total number of 0s in the values of the 32 kinds of values is greater than the total number of 1 s, the determining the second adjustment method includes inverting the first output node O1, which is not limited by the embodiment of the present application. Similarly, it is determined whether the second adjustment mode includes inverting the first output nodes O2 and O3.

Assuming that the second adjustment manner determined by the method includes inverting the first output nodes O1 and O2, the difference between the third sub-graph and the first sub-graph determined according to the second adjustment manner is: the first output node O1 and the third output node O1 are different in polarity, and the first output node O2 and the third output node O2 are different in polarity.

In some embodiments, the semi-canonical rule may include a plurality of input negation rules, input permutation rules, or output negation rules. For example, when the semi-normalized rule includes an input inversion rule and an input arrangement rule, the second adjustment manner is used to instruct to adjust the polarity of at least one first input node and the arrangement order of at least two first input nodes in the N first input nodes in the first sub-graph. Or when the semi-normalized rule includes an input inversion rule and an output inversion rule, the second adjustment mode is used for indicating to adjust the polarity of at least one first input node of the N first input nodes and the polarity of at least one first output node of the M first output nodes in the first sub-graph. Or when the semi-normalization rule comprises an input arrangement rule and an output negation rule, the second adjustment mode is used for indicating and adjusting the arrangement sequence of at least two first input nodes in N first input nodes and the polarity of at least one first output node in M first output nodes in the first subgraph. Or when the semi-normalization rule comprises an input inversion rule, an input arrangement rule and an output inversion rule, the second adjustment mode is used for indicating and adjusting the polarity of at least one first input node in the N first input nodes, the arrangement sequence of at least two first input nodes and the polarity of at least one first output node in the M first output nodes in the first sub-graph.

Optionally, the computing device may obtain the semi-normalized rule before determining the second adjustment manner. The computing device may determine the semi-normalized rule itself or may obtain the semi-normalized rule through other devices connected to the computing device, which embodiments of the application are not limited in this regard.

Optionally, the computing device may store the second adjustment after determining the second adjustment.

Optionally, the computing device may determine the second subgraph from the third subgraph. The second sub-graph is logically equivalent to the third sub-graph. That is, when the value of the nth third input point in the N third input nodes of the third sub-graph is the same as the value of the nth second input node in the N second input nodes of the second sub-graph, the value of the mth third output node in the M third output nodes of the third sub-graph is the same as the value of the mth second output node in the M second output nodes of the second sub-graph, where n∈n, m∈m. N third input nodes in the third sub-graph are in one-to-one correspondence with N second input nodes in the second sub-graph, and M third output nodes in the third sub-graph are in one-to-one correspondence with M second output nodes in the second sub-graph. Alternatively, the truth table of the third sub-graph matches the truth table of the second sub-graph.

It should be understood that the third sub-graph includes P third intermediate nodes, the second sub-graph includes Q second intermediate nodes, and the values of P and Q may be the same or different, which is not limited by the embodiment of the present application.

In some embodiments, the computing device may determine a truth table for the third sub-graph and compare with the truth tables for each of the optimal sub-graphs included in the set of optimal sub-graphs to determine a truth table that matches the truth table for the third sub-graph and take the optimal sub-graph corresponding to the truth table as the second sub-graph.

In some embodiments, if the optimal sub-graph set does not include an optimal sub-graph logically equivalent to the third sub-graph, the computing device may store the third sub-graph in the optimal sub-graph set.

And S230, optimizing the first subgraph according to the second subgraph.

After determining a second sub-graph logically equivalent to the first sub-graph, the computing device may optimize the first sub-graph based on the second sub-graph.

It should be understood that, although the second sub-graph is logically equivalent to the first sub-graph, the polarities of the N second input nodes of the second sub-graph and the polarities of the N first input nodes of the first sub-graph may be completely identical, or may be partially identical, or may be completely different, which is not limited by the embodiment of the present application. Similarly, the arrangement order of the N second input nodes of the second sub-graph and the arrangement order of the N first input nodes of the first sub-graph may be completely the same, or may be partially the same, or may be completely different, which is not limited by the embodiment of the present application. The polarities of the M second output nodes of the second sub-graph and the polarities of the M first output nodes of the first sub-graph may be completely the same, may be partially the same, or may be completely different, which is not limited by the embodiment of the present application.

Optionally, the computing device may compare the number of nodes included in the first sub-graph with the second sub-graph after determining the second sub-graph. If the number of nodes in the second sub-graph is less than the number of nodes in the first sub-graph, the computing device may replace the first sub-graph based on the second sub-graph. If the number of nodes in the second sub-graph is greater than the number of nodes in the first sub-graph, the computing device may replace the second sub-graph in the optimal sub-graph set with the first sub-graph.

In the case where the number of nodes in the second sub-graph is less than the number of nodes in the first sub-graph, the computing device may determine a first correspondence between N second input nodes of the second sub-graph and N first input nodes of the first sub-graph, and a second correspondence between M second output nodes of the second sub-graph and M second output nodes of the first sub-graph. The computing device may adjust the polarity and/or the arrangement order of some or all of the N first input nodes of the second sub-graph according to the first correspondence; and/or the computing device may adjust the polarity of some or all of the M second output nodes of the second sub-graph according to the second correspondence. The computing device may replace the first sub-graph with a second sub-graph that is adjusted according to the first correspondence and/or the second correspondence. The computing device adjusts the second sub-graph according to the first corresponding relation and/or the second corresponding relation, so that the adjusted second sub-graph is equivalent to the first sub-graph, namely, the fact that other parts except the first sub-graph in the logic network table graph are not affected after the first sub-graph is replaced is guaranteed.

Optionally, after determining the second sub-graph from the third sub-graph, the computing device may compare the third sub-graph to the number of nodes included in the second sub-graph. If the number of nodes in the second sub-graph is less than the number of nodes in the third sub-graph, the computing device may replace the first sub-graph based on the second sub-graph. If the number of nodes in the second sub-graph is greater than the number of nodes in the third sub-graph, the computing device may replace the second sub-graph in the optimal sub-graph set with the third sub-graph.

In the case that the number of nodes in the second sub-graph is smaller than the number of nodes in the third sub-graph, the computing device may adjust the second sub-graph according to the first adjustment manner, and obtain an adjusted second sub-graph. The first adjustment mode is the inverse of the second adjustment mode. The computing device may also replace the first sub-graph with the adjusted second sub-graph. The computing device adjusts the second sub-graph according to the first adjustment mode, so that the adjusted second sub-graph is equivalent to the first sub-graph, namely, the fact that other parts except the first sub-graph in the logic network table graph are not affected after the first sub-graph is replaced is guaranteed.

In the case that the second adjustment manner is used to indicate that at least one of the N first input nodes in the first sub-graph is inverted, the computing device may adjust a polarity of at least one of the N second input nodes in the second sub-graph according to the first adjustment manner, to obtain an adjusted second sub-graph. The at least one second input node corresponds to the at least one first input node one by one, and the polarity of each second input node in the at least one second input node is opposite to the polarity of the corresponding first input node.

For example, assume that the first sub-graph is as shown in fig. 3, i.e., the polarities of the first input nodes I1 and I2 in the first sub-graph are positive. If the second adjustment method includes inverting the first input nodes I1 and I2, the polarities of the third input nodes I1 and I2 in the third sub-graph are inverted. The third input node I1 corresponds to the first input node I1, and the third input node I2 corresponds to the first input node I2. Assume that the polarities of the second input nodes I1 and I2 in the second sub-graph are inverted, and that the second input node I1 corresponds to the third input node I1, and the second input node I2 corresponds to the third input node I2. Since the second adjustment includes inverting the first input nodes I1 and I2, the first adjustment is inverting the second input nodes I1 and I2. The polarities of the second input nodes I1 and I2 in the adjusted second sub-graph obtained according to the first adjustment mode are positive. Or assuming that the polarities of the second input nodes I1 and I2 in the second sub-graph are positive, and the second input node I1 corresponds to the third input node I1, and the second input node I2 corresponds to the third input node I2. The polarities of the second input nodes I1 and I2 in the adjusted second sub-graph obtained according to the first adjustment mode are inverted.

In the case that the second adjustment manner is used to indicate an adjustment order for at least two first input nodes of the N first input nodes in the first sub-graph, the computing device may adjust an arrangement order of at least two second input nodes of the N second input nodes in the second sub-graph according to the first adjustment manner, to obtain an adjusted second sub-graph. The at least two second input nodes are in one-to-one correspondence with the at least two first input nodes, and the arrangement sequence of the at least two second input nodes is different from the arrangement sequence of the corresponding first input nodes.

For example, assume that the first sub-graph is shown in fig. 3, that is, the arrangement order of 5 first input nodes in the first sub-graph is I1, I2, I3, I4, I5. If the second adjustment method includes adjusting the arrangement order of the first input nodes I1 and I2, the arrangement order of the third input nodes in the third sub-graph is I2, I1, I3, I4, I5. And, the third input nodes I1 to I5 are respectively in one-to-one correspondence with the first input nodes I1 to I5. Assume that the arrangement order of the second input nodes in the second sub-graph is I2, I1, I3, I4, I5, and the second input node I1 corresponds to the third input node I1, the second input node I2 corresponds to the third input node I2, the second input node I3 corresponds to the third input node I3, the second input node I4 corresponds to the third input node I4, and the second input node I5 corresponds to the third input node I5. Since the second adjustment method includes adjusting the arrangement order of the first input nodes I1 and I2, the first adjustment method is to adjust the arrangement order of the second input nodes I1 and I2. The arrangement sequence of the second input nodes in the adjusted second subgraph obtained according to the first adjustment mode is I1, I2, I3, I4 and I5. Or the arrangement order of the second input nodes in the second sub-graph is assumed to be I1, I2, I3, I4 and I5, and the second input node I1 corresponds to the third input node I2, the second input node I2 corresponds to the third input node I1, the second input node I3 corresponds to the third input node I3, the second input node I4 corresponds to the third input node I4, and the second input node I5 corresponds to the third input node I5. The arrangement sequence of the second input nodes in the adjusted second subgraph obtained according to the first adjustment mode is I2, I1, I3, I4 and I5.

In the case that the second adjustment manner is used for indicating to invert at least one of the M first output nodes in the first sub-graph, the computing device may adjust the polarity of at least one of the M second output nodes in the second sub-graph according to the first adjustment manner, to obtain an adjusted second sub-graph. The at least one second output node corresponds to the at least one first output node one by one, and the polarity of each second output node in the at least one second output node is opposite to the polarity of the corresponding first output node.

For example, assume that the first sub-graph is as shown in fig. 3, i.e., the polarities of the first output nodes O1 and O2 in the first sub-graph are positive. If the second adjustment method includes inverting the first output nodes O1 and O2, the polarities of the third input nodes O1 and O2 in the third sub-graph are inverted. The first output node O1 corresponds to the third output node O1, and the first output node O2 corresponds to the third output node O2. Assume that the polarities of the second output nodes O1 and O2 in the second sub-graph are inverted, and that the second output node O1 corresponds to the third output node O1, and the second output node O2 corresponds to the third output node O2. Since the second adjustment includes inverting the first output nodes O1 and O2, the first adjustment is inverting the second output nodes O1 and O2. The polarities of the second output nodes O1 and O2 in the adjusted second sub-graph obtained according to the first adjustment mode are positive. Or assuming that the polarities of the second output nodes O1 and O2 in the second sub-graph are positive, and the second output node O1 corresponds to the third output node O1, and the second output node O2 corresponds to the third output node O2. The polarities of the second output nodes O1 and O2 in the adjusted second sub-graph obtained according to the first adjustment mode are opposite.

When the second adjustment is used to indicate any of the following: the computing device may perform adjustment on the second sub-graph according to the first adjustment manner, and obtain an adjusted second sub-graph.

For example, when the second adjustment manner is used to indicate that at least one of the N first input nodes in the first sub-graph is inverted and an order of adjustment is performed on at least two of the N first input nodes in the first sub-graph, the computing device may adjust a polarity of at least one of the N second input nodes in the second sub-graph and an order of arrangement of at least two of the N second input nodes in the second sub-graph according to the first adjustment manner, to obtain an adjusted second sub-graph.

For example, when the second adjustment manner is used to indicate inverting at least one of the N first input nodes in the first sub-graph and inverting at least one of the M first output nodes in the first sub-graph, the computing device may adjust the polarity of at least one of the N second input nodes in the second sub-graph and the polarity of at least one of the M second output nodes in the second sub-graph according to the first adjustment manner to obtain the adjusted second sub-graph.

For example, when the second adjustment manner is used to indicate an adjustment order of at least two first input nodes of the N first input nodes in the first sub-graph and an inverse of at least one first output node of the M first output nodes in the first sub-graph, the computing device may adjust an arrangement order of at least two second input nodes of the N second input nodes in the second sub-graph and a polarity of at least one second output node of the M second output nodes in the second sub-graph according to the first adjustment manner, to obtain an adjusted second sub-graph.

For example, when the second adjustment manner is used to instruct inverting at least one first input node of the N first input nodes in the first sub-graph, adjusting an order of at least two first input nodes of the N first input nodes in the first sub-graph, and inverting at least one first output node of the M first output nodes in the first sub-graph, the computing device may adjust a polarity of at least one second input node of the N second input nodes in the second sub-graph, an order of arrangement of at least two second input nodes, and a polarity of at least one second output node of the M second output nodes in the second sub-graph according to the first adjustment manner, to obtain an adjusted second sub-graph.

Optionally, since the number of input nodes included in the first sub-graph is the same as the number of output nodes included in the adjusted second sub-graph, and the first sub-graph is equivalent to the adjusted second sub-graph, the computing device may directly replace the first sub-graph in the logical network table graph with the adjusted second sub-graph.

The computing device may start searching from at least one input node, determine a first sub-graph that includes at least one output node and at least one intermediate node, and may cause all output-corresponding nodes of each intermediate node in the first sub-graph to belong to the first sub-graph, i.e., all intermediate nodes in the first sub-graph are replaceable nodes. The computing device may also determine an equivalent second sub-graph from the first sub-graph, thereby logically optimizing the first sub-graph. Because all the intermediate nodes included in the first sub-graph are replaceable nodes, the number of replaceable nodes is large when the logic optimization is carried out on the first sub-graph, so that the number of nodes in the optimized logic netlist is small, and the optimization rate is improved.

FIG. 4 is a schematic flow chart of a logic optimization method provided by an embodiment of the present application, where the method of FIG. 4 may be performed by the logic optimization system 100 of FIG. 1. The method of fig. 4 includes the following steps.

S410, determining P first intermediate nodes according to N first input nodes.

Optionally, before step S410, the computing device may determine N first input nodes, N being a positive integer greater than or equal to 1.

The computing device may search the logical mesh table graph according to the N first input nodes, thereby determining P first intermediate nodes. P is a positive integer greater than or equal to 1. The N first input nodes and the P first intermediate nodes belong to the logic network table diagram. The P-th first intermediate node in the P first intermediate nodes comprises n ₁ outputs, the node corresponding to n ₁ outputs of the P-th first intermediate node belongs to a first subgraph, P epsilon P, and n ₁ is a positive integer greater than or equal to 1. And, the P first intermediate node in the P first intermediate nodes includes n ₂ inputs, the node corresponding to n ₂ inputs of the P first intermediate node belongs to the first subgraph, and n ₂ is a positive integer greater than or equal to 1. The specific implementation manner of determining the P first intermediate nodes may be referred to the description in step S210, which is not repeated herein.

S420, determining M first output nodes according to the P first intermediate nodes, and obtaining a first sub-graph.

The computing device may determine M first output nodes from the P first intermediate nodes, M being a positive integer greater than or equal to 1. The M first output nodes are connected with N first input nodes through the P first intermediate nodes. The M first output nodes in the M first output nodes comprise M ₁ outputs, at least one node corresponding to at least one output in M ₁ outputs of the M first output nodes does not belong to the first subgraph, M epsilon M, and M ₁ is a positive integer greater than or equal to 1. The specific implementation manner of determining the M first output nodes may be referred to the description in step S210, which is not repeated herein.

The computing device may obtain the first subgraph after determining the N first input nodes, the P first intermediate nodes, and the M first output nodes. The logic net list graph comprises at least one sub-graph, and the first sub-graph belongs to the logic net list graph.

And S430, determining a second adjustment mode according to the semi-normalization rule and the first subgraph, and obtaining a third subgraph.

Optionally, prior to step S430, the computing device may determine a semi-normalization rule. The computing device may determine the semi-canonical rule itself or may determine the semi-canonical rule by other devices connected to the computing device, as embodiments of the application are not limited in this respect.

Optionally, the semi-normalized rule includes at least one of the following: an input negation rule, an input permutation rule, or an output negation rule. The specific rule can be described in step S220.

The computing device may determine, according to the semi-normalization rule, an adjustment that needs to be made to the first sub-graph, i.e., determine a second adjustment manner. The computing device may also adjust the first sub-graph in accordance with the second adjustment to determine a third sub-graph. The third sub-graph includes N third input nodes, M third output nodes, and P third intermediate nodes. The first sub-graph is different from at least one of the following in the third sub-graph: the polarity of at least one input node, the order of arrangement of at least two input nodes, or the polarity of at least one output node. The determination of the second adjustment means and the specific implementation of the third sub-graph may be referred to the description in step S220.

Optionally, the computing device may also record the second adjustment.

S440, determining whether a second sub-graph logically equivalent to the third sub-graph exists in the optimal sub-graph set.

Alternatively, the computing device may determine an optimal sub-graph set prior to step S440. The optimal sub-graph set comprises at least one optimal sub-graph, and each optimal sub-graph is the sub-graph with the least number of nodes contained in the logical equivalence class to which the sub-graph belongs. All sub-graphs contained in a logical equivalence class are logically equivalent to each other. The logical equivalence class may be an N equivalence class, an NP equivalence class, or an NPN equivalence class.

The computing device may determine, according to the truth table of the third sub-graph, whether a truth table matching the truth table of the third sub-graph exists in the optimal sub-graph set, and use an optimal sub-graph corresponding to the truth table as the second sub-graph. The second sub-graph comprises N second input nodes, M second output nodes and Q second intermediate nodes, wherein Q is a positive integer greater than or equal to 1. In other words, the computing device may determine whether a truth table of one optimal sub-graph in the set of optimal sub-graphs matches a truth table of a third sub-graph. If the truth table of an optimal sub-graph is matched with the truth table of a third sub-graph, the optimal sub-graph is logically equivalent to the third sub-graph, namely the optimal sub-graph is the second sub-graph. The specific implementation may be described in step S220.

If the computing device determines that there is no second sub-graph in the optimal sub-graph set that is logically equivalent to the third sub-graph, the computing device may perform step S450.

If the computing device determines that there is a second sub-graph in the optimal sub-graph set that is logically equivalent to the third sub-graph, the computing device may perform step S460.

S450, storing the third sub-graph into the optimal sub-graph set.

When there is no optimal sub-graph logically equivalent to the third sub-graph in the optimal sub-graph set, the computing device may store the third sub-graph in the optimal sub-graph set, thereby facilitating the logical optimization of other sub-graphs except for the first sub-graph. In other words, the computing device may maintain the optimal sub-graph set, and the optimal sub-graphs stored in the optimal sub-graph set are all optimal sub-graphs (e.g., third sub-graphs) adjusted according to the semi-canonical rule.

After performing step S450, the computing device has completed the logic optimization for the first sub-graph. The computing device may also repeatedly perform steps S410 to S490 on other sub-graphs in the logical network table graph except for the first sub-graph until all sub-graphs in the logical network table graph complete the logical optimization.

S460, determining whether the number of nodes of the second sub-graph is less than the number of nodes of the third sub-graph.

The computing device may further compare the number of nodes of the second sub-graph with the number of nodes of the third sub-graph when there is a second sub-graph in the optimal sub-graph set that is logically equivalent to the third sub-graph.

If the number of nodes of the second sub-graph is greater than the number of nodes of the third sub-graph, it indicates that the second sub-graph is not the optimal sub-graph in the logical equivalence class to which the second sub-graph belongs, and step S470 may be performed.

If the number of nodes of the second sub-graph is smaller than the number of nodes of the third sub-graph, it means that the first sub-graph can be replaced according to the second sub-graph, and step S480 can be performed.

And S470, updating the second sub-graph in the optimal sub-graph set into a third sub-graph.

When the number of nodes of the second sub-graph is greater than the number of nodes of the third sub-graph, the computing device may update the second sub-graph in the optimal sub-graph set to the third sub-graph, thereby ensuring that the optimal sub-graph set stores the sub-graph with the least number of nodes included in one logical equivalence class.

After performing step S470, the computing device has completed the logical optimization of the first sub-graph. The computing device may also repeatedly perform steps S410 to S490 on other sub-graphs in the logical network table graph except for the first sub-graph until all sub-graphs in the logical network table graph complete the logical optimization.

And S480, adjusting the second sub-graph according to the first adjustment mode to obtain an adjusted second sub-graph.

When the number of nodes of the second sub-graph is smaller than the number of nodes of the third sub-graph, the computing device may adjust the second sub-graph according to the first adjustment mode, to obtain an adjusted second sub-graph. The first adjustment method is the inverse of the second adjustment method in step S430. The computing device adjusts the second sub-graph according to the first adjustment mode, so that the adjusted second sub-graph is equivalent to the first sub-graph, namely, the fact that other parts except the first sub-graph in the logic network table graph are not affected after the first sub-graph is replaced is guaranteed. The specific implementation may be described in step S230.

And S490, replacing the first sub-graph with the adjusted second sub-graph.

After determining the adjusted second sub-graph, the computing device may directly replace the first sub-graph with the adjusted second sub-graph in the logic netlist diagram, thereby completing the logic optimization of the first sub-graph.

After executing step S490, the computing device may repeatedly execute steps S410 to S490 on the other subgraphs in the logical network table graph except for the first subgraph until all subgraphs in the logical network table graph complete the logical optimization.

The computing device may start searching from at least one input node, determine a first sub-graph that includes at least one output node and at least one intermediate node, and may cause all output-corresponding nodes of each intermediate node in the first sub-graph to belong to the first sub-graph, i.e., all intermediate nodes in the first sub-graph are replaceable nodes. Because all the intermediate nodes included in the first sub-graph are replaceable nodes, the number of replaceable nodes is large when the logic optimization is carried out on the first sub-graph, so that the number of nodes in the optimized logic netlist is small, and the optimization rate is improved. The computing device may also determine a third sub-graph based on the semi-canonical rule and the first sub-graph, thereby determining a second sub-graph that is logically equivalent to the first sub-graph. The method for determining the second sub-graph of the logic equivalence by the semi-standardized rule greatly reduces the calculated amount when judging the logic equivalence class and improves the operation efficiency of the method.

Having described a logic optimization method according to an embodiment of the present application, a computing device and computing apparatus according to embodiments of the present application are described below in conjunction with fig. 5 and 6.

FIG. 5 is a schematic diagram of a computing device according to one embodiment of the application. The computing device 500 includes a determination module 510 and an optimization module 520.

The determining module 510 is configured to search the logic netlist diagram according to the N first input nodes in the logic netlist diagram, and determine a first subgraph. The first sub-graph belongs to a logical net-list graph. The first subgraph comprises M first output nodes, P first intermediate nodes and N first input nodes, wherein the N first input nodes are connected with the M first output nodes through the P first intermediate nodes. The P-th first intermediate node in the P-th first intermediate nodes comprises n ₁ outputs, the node corresponding to the n ₁ outputs of the P-th first intermediate node belongs to a first subgraph, P epsilon P and N, M, P, n ₁ are positive integers which are larger than or equal to 1. The determining module 510 is further configured to determine a second sub-graph equivalent to the first sub-graph. The second sub-graph comprises N second input nodes, M second output nodes and Q second intermediate nodes, wherein Q is a positive integer greater than or equal to 1. The determination module 510 may perform steps S210, S220 in the method of fig. 2, steps S410 to S440 in the method of fig. 4.

The optimization module 520 is configured to optimize the first sub-graph according to the second sub-graph. The optimization module 520 may perform step S230 in the method of fig. 2, and steps S450 to S490 in the method of fig. 4.

FIG. 6 is a block diagram of a computing device provided in accordance with an embodiment of the present application. The computing device 600 shown in fig. 6 includes: processor 601, memory 602, and communication interface 603, processor 601, memory 602, and communication interface 603 communicate via bus 604.

The method disclosed in the above embodiment of the present invention may be applied to the processor 601 or implemented by the processor 601. The processor 601 may be a central processing unit (central processing unit, CPU), but may also be other general purpose processors, digital signal processors (DIGITAL SIGNAL processors, DSP), ASIC, FPGA or other programmable logic device, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or any conventional processor or the like. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in the processor 601 or instructions in the form of software. Processor 601 may implement or perform the methods, steps and logic blocks disclosed in embodiments of the present invention. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present invention may be embodied directly in the execution of a hardware decoding processor, or in the execution of a combination of hardware and software modules in a decoding processor. The software modules may be located in the memory 602. The processor 601 reads the instructions in the memory 602 and, in combination with its hardware, performs the steps of the method described above.

The memory 602 may store instructions for performing the methods performed by the computing device in the embodiments described above. The memory 602 may be volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The nonvolatile memory may be a read-only memory (ROM), a Programmable ROM (PROM), an erasable programmable ROM (erasable PROM), an electrically erasable programmable EPROM (EEPROM), or a flash memory. The volatile memory may be random access memory (random access memory, RAM) which acts as external cache memory. By way of example, and not limitation, many forms of RAM are available, such as static random access memory (STATIC RAM, SRAM), dynamic Random Access Memory (DRAM), synchronous Dynamic Random Access Memory (SDRAM), double data rate synchronous dynamic random access memory (double DATA DATE SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (ENHANCED SDRAM, ESDRAM), synchronous link dynamic random access memory (SYNCHLINK DRAM, SLDRAM), and direct memory bus random access memory (direct rambus RAM, DR RAM). It should be noted that the memory of the systems and methods described herein is intended to comprise, without being limited to, these and any other suitable types of memory. The processor 601 may execute instructions stored in the memory 602 and perform the steps of the computing device of the above embodiments in combination with other hardware, and reference may be made to the description of the above embodiments for specific working procedures and advantages.

The bus 604 may include a power bus, a control bus, a status signal bus, and the like in addition to a data bus. But for clarity of illustration, the various buses are labeled as bus 604 in the figures.

The embodiment of the application also provides a computer storage medium, and the computer storage medium stores program instructions, and the program can include part or all of the steps of the logic optimization method in the corresponding embodiment of fig. 2 or fig. 4 when being executed.

Embodiments of the present application also provide a chip system including a logic circuit for coupling with an input/output interface through which data is transmitted to perform the steps included in fig. 2 or 4 in the above embodiments.

According to a method provided by an embodiment of the present application, the present application also provides a computer program product, including: computer program code which, when run on a computer, causes the computer to perform the steps of the above embodiments.

According to the method provided by the embodiment of the present application, the present application further provides a computer readable medium storing a program code, which when run on a computer, causes the computer to perform the steps in the above-described embodiments.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.

In the several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a ROM, a RAM, a magnetic disk, or an optical disk, etc.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (14)

1. A logic optimization method, comprising:

Searching a logic network table graph according to N first input nodes in the logic network table graph, determining a first sub graph, wherein the first sub graph belongs to the logic network table graph, the first sub graph comprises M first output nodes, P first intermediate nodes and N first input nodes, the N first input nodes are connected with the M first output nodes through the P first intermediate nodes, the P first intermediate nodes in the P first intermediate nodes comprise N ₁ outputs, the node corresponding to the N ₁ outputs of the P first intermediate nodes belongs to the first sub graph, P epsilon P, and N, M, P, N ₁ is a positive integer greater than or equal to 1;

Determining a second sub-graph logically equivalent to the first sub-graph, wherein the second sub-graph comprises N second input nodes, M second output nodes and Q second intermediate nodes, and Q is a positive integer greater than or equal to 1;

and optimizing the first subgraph according to the second subgraph.

2. The method of claim 1, wherein the searching the logical network table graph according to the N first input nodes in the logical network table graph to determine the first sub-graph includes:

According to the N first input nodes, determining the P first intermediate nodes, wherein the P first intermediate nodes in the P first intermediate nodes comprise N ₂ inputs, nodes corresponding to the N ₂ inputs of the P first intermediate nodes belong to the first subgraph, and N ₂ is a positive integer greater than or equal to 1;

According to the P first intermediate nodes, determining M first output nodes, wherein an mth first output node in the M first output nodes comprises M ₁ outputs, a node corresponding to at least one output in M ₁ outputs of the mth first output node does not belong to the first subgraph, and M epsilon M and M ₁ are positive integers which are larger than or equal to 1.

3. The method according to claim 1 or 2, wherein said determining a second sub-graph equivalent to said first sub-graph comprises:

Determining a third sub-graph according to the first sub-graph, wherein the third sub-graph comprises N third input nodes, M third output nodes and P third intermediate nodes, and the first sub-graph is different from at least one of the following in the third sub-graph: polarity of at least one input node, arrangement order of at least two input nodes, or polarity of at least one output node;

And determining the second subgraph according to the third subgraph, wherein when the value of an nth third input point in the N third input nodes is the same as the value of an nth second input node in the N second input nodes, the value of an mth third output node in the M third output nodes is the same as the value of an mth second output node in the M second output nodes, and N is N and M is M.

4. The method of claim 3, wherein optimizing the first sub-graph based on the second sub-graph comprises:

the second sub-graph is adjusted according to a first adjusting mode, the adjusted second sub-graph is obtained, the first adjusting mode is an inverse mode of the second adjusting mode, the second adjusting mode is used for adjusting the first sub-graph into the third sub-graph, and P is larger than Q;

And replacing the first sub-graph with the adjusted second sub-graph.

5. The method of claim 4, wherein adjusting the second sub-graph according to the first adjustment mode to obtain an adjusted second sub-graph comprises:

according to the first adjustment mode, the polarity of at least one second input node in the N second input nodes in the second subgraph is adjusted, and the adjusted second subgraph is obtained; and/or the number of the groups of groups,

According to the first adjustment mode, adjusting the arrangement sequence of at least two second input nodes in the N second input nodes in the second subgraph to obtain an adjusted second subgraph; and/or the number of the groups of groups,

And according to the first adjustment mode, adjusting the polarity of at least one second output node in the M second output nodes in the second subgraph to obtain the adjusted second subgraph.

6. A method according to claim 3, characterized in that the method further comprises:

And when the P is smaller than the Q, replacing the second sub-graph with the third sub-graph in an optimal sub-graph set, wherein the optimal sub-graph set comprises at least one optimal sub-graph, and the second sub-graph belongs to the optimal sub-graph set.

7. A computing device, comprising:

The determining module is used for searching the logic network table graph according to N first input nodes in the logic network table graph to determine a first sub graph, wherein the first sub graph belongs to the logic network table graph, the first sub graph comprises M first output nodes, P first intermediate nodes and the N first input nodes, the N first input nodes are connected with the M first output nodes through the P first intermediate nodes, the P first intermediate nodes in the P first intermediate nodes comprise N ₁ outputs, the node corresponding to the N ₁ outputs of the P first intermediate nodes belongs to the first sub graph, and P E P, N, M, P, N ₁ are positive integers greater than or equal to 1;

The determining module is further configured to determine a second sub-graph equivalent to the first sub-graph, where the second sub-graph includes N second input nodes, M second output nodes, and Q second intermediate nodes, and Q is a positive integer greater than or equal to 1;

and the optimizing module is used for optimizing the first subgraph according to the second subgraph.

8. The apparatus of claim 7, wherein the determining module is specifically configured to:

According to the N first input nodes, determining the P first intermediate nodes, wherein the P first intermediate nodes in the P first intermediate nodes comprise N ₂ inputs, nodes corresponding to the N ₂ inputs of the P first intermediate nodes belong to the first subgraph, and N ₂ is a positive integer greater than or equal to 1;

According to the P first intermediate nodes, determining M first output nodes, wherein an mth first output node in the M first output nodes comprises M ₁ outputs, a node corresponding to at least one output in M ₁ outputs of the mth first output node does not belong to the first subgraph, and M epsilon M and M ₁ are positive integers which are larger than or equal to 1.

9. The apparatus according to claim 7 or 8, wherein the determining module is specifically configured to:

Determining a third sub-graph according to the first sub-graph, wherein the third sub-graph comprises N third input nodes, M third output nodes and P third intermediate nodes, and the first sub-graph is different from at least one of the following in the third sub-graph: polarity of at least one input node, arrangement order of at least two input nodes, or polarity of at least one output node;

And determining the second subgraph according to the third subgraph, wherein when the value of an nth third input point in the N third input nodes is the same as the value of an nth second input node in the N second input nodes, the value of an mth third output node in the M third output nodes is the same as the value of an mth second output node in the M second output nodes, and N is N and M is M.

10. The apparatus according to claim 9, wherein the optimization module is specifically configured to:

the second sub-graph is adjusted according to a first adjusting mode, the adjusted second sub-graph is obtained, the first adjusting mode is an inverse mode of the second adjusting mode, the second adjusting mode is used for adjusting the first sub-graph into the third sub-graph, and P is larger than Q;

And replacing the first sub-graph with the adjusted second sub-graph.

11. The apparatus according to claim 10, wherein the optimization module is specifically configured to:

according to the first adjustment mode, the polarity of at least one second input node in the N second input nodes in the second subgraph is adjusted, and the adjusted second subgraph is obtained; and/or the number of the groups of groups,

According to the first adjustment mode, adjusting the arrangement sequence of at least two second input nodes in the N second input nodes in the second subgraph to obtain an adjusted second subgraph; and/or the number of the groups of groups,

And according to the first adjustment mode, adjusting the polarity of at least one second output node in the M second output nodes in the second subgraph to obtain the adjusted second subgraph.

12. The apparatus of claim 9, wherein the optimization module is further configured to replace the second sub-graph with the third sub-graph in an optimal sub-graph set when the P is less than the Q, the optimal sub-graph set including at least one optimal sub-graph, the second sub-graph belonging to the optimal sub-graph set.

13. A computer device, comprising: a processor for coupling with a memory, reading and executing instructions and/or program code in the memory to perform the method according to any of claims 1-6.

14. A computer readable medium, characterized in that the computer readable medium stores a program code which, when run on a computer, causes the computer to perform the method according to any of claims 1-6.