CN117971764A

CN117971764A - CPU interconnection compatible method, device, equipment and medium

Info

Publication number: CN117971764A
Application number: CN202410048091.XA
Authority: CN
Inventors: 齐红玉; 黄美红; 许泗强
Original assignee: Inspur Computer Technology Co Ltd
Current assignee: Inspur Computer Technology Co Ltd
Priority date: 2024-01-11
Filing date: 2024-01-11
Publication date: 2024-05-03

Abstract

The application discloses a method, a device, equipment and a medium for interconnection compatibility of a central processing unit, and relates to the technical field of computers. The method is applied to the server motherboard, and comprises the following steps: identifying a current application scene and judging whether the interconnection mode between the first CPU and the second CPU is required to be switched currently or not; if the current need of switching the interconnection mode into single-side interconnection is judged, connecting the functional interfaces on the first CPU and the second CPU in a mode of connecting based on a preset printed circuit board wiring; if the current need of switching the interconnection mode into bilateral interconnection is judged, connecting the functional interfaces on the first CPU and the second CPU by using a cable assembly connector in a mode of connecting based on a preset cable; when the first CPU and the second CPU monitor that the interconnection mode is switched, the firmware of the first CPU and the second CPU is switched to the preset target firmware corresponding to the current interconnection mode. Through the technical scheme of the application, two CPU interconnection switching logics can be compatible.

Description

CPU interconnection compatible method, device, equipment and medium

Technical Field

The present invention relates to the field of computer technologies, and in particular, to a method, an apparatus, a device, and a medium for interconnection compatibility of a central processing unit.

Background

High performance server designs typically install 2 or more CPUs (Central Processing Unit, central processing units) to improve the performance of the operation, so CPU interconnection is important. Currently, there are various types of CPU products for the CPU platform No. 4, and the CPU interconnection is different due to different CPU internal designs. Therefore, for the No. 4 CPU platform of the sea light, different CPU interconnection modes need to be realized by using different types of CPU products. This results in increased design costs of the server motherboard and the manner of interconnection between CPUs is also limited by different application scenarios.

Therefore, how to provide a solution to the above technical problem is a problem that a person skilled in the art needs to solve at present.

Disclosure of Invention

In view of the above, the present invention aims to provide a method, an apparatus, a device and a medium for CPU interconnect compatibility, which can be compatible with two CPU interconnect switching logics, and can cover more application scenarios while saving cost. The specific scheme is as follows:

The application discloses a method for interconnecting and compatible central processing units, which is applied to a server main board, wherein the server main board comprises a first central processing unit chip, a second central processing unit chip, a scene judging module and a cable assembly connector; wherein the method comprises the following steps:

identifying a current application scene through the scene judging module, and judging whether the interconnection mode between the first CPU chip and the second CPU chip is required to be switched currently or not by utilizing the identified current application scene;

If the interconnection mode is judged to be switched to unilateral interconnection currently, connecting the functional interfaces on the first CPU chip and the second CPU chip in a mode of connection based on a preset printed circuit board wiring;

If the fact that the interconnection mode is required to be switched to bilateral interconnection is judged, the functional interfaces on the first central processing unit chip and the second central processing unit chip are connected through the cable assembly connector in a mode of connection based on a preset cable;

and after the first CPU chip and the second CPU chip monitor that the interconnection mode is switched, switching the firmware of the first CPU chip and the second CPU chip to a preset target firmware corresponding to the current interconnection mode.

Optionally, before the identifying, by the scene determining module, the current application scene and determining whether the interconnection mode between the first central processing unit chip and the second central processing unit chip needs to be switched currently according to the identified current application scene, the method further includes:

presetting two general input/output port signals for providing the judging index of the interconnection mode for the basic input/output system;

Setting up and down pull combinations for the general input/output signals respectively, and determining different general input/output signal state combinations according to the up and down pull combinations;

determining a first general input/output signal state combination matched with the single-side interconnection and a second general input/output signal state combination matched with the double-side interconnection from the general input/output signal state combinations;

configuring an interconnection mode corresponding to the first general input/output port signal state combination as the single-side interconnection, and configuring an interconnection mode corresponding to the second general input/output port signal state combination as the double-side interconnection;

correspondingly, the judging whether the interconnection mode between the first central processing unit chip and the second central processing unit chip needs to be switched currently by using the identified current application scene includes:

and matching the identified current application scene with the general input/output port signal state combination to judge whether the interconnection mode between the first CPU chip and the second CPU chip is required to be switched currently.

Optionally, the matching with the identified current application scenario and the general input/output signal state combination is performed to determine whether the interconnection mode between the first cpu chip and the second cpu chip needs to be switched currently, including:

If the identified current application scene corresponds to a scene requiring unilateral interconnection, and the general input/output signal state combination is the first general input/output signal state combination, judging that the interconnection mode between the first central processing unit chip and the second central processing unit chip does not need to be switched currently;

if the identified current application scene corresponds to a scene requiring unilateral interconnection, and the general input/output signal state combination is the second general input/output signal state combination, judging that the interconnection mode between the first central processing unit chip and the second central processing unit chip is required to be switched currently;

If the identified current application scene corresponds to a scene requiring bilateral interconnection, and the general input/output signal state combination is the first general input/output signal state combination, judging that the interconnection mode between the first central processing unit chip and the second central processing unit chip is required to be switched currently;

And if the identified current application scene corresponds to a scene requiring bilateral interconnection, and the general input/output signal state combination is the second general input/output signal state combination, judging that the interconnection mode between the first CPU chip and the second CPU chip does not need to be switched currently.

Optionally, if it is determined that the interconnection mode needs to be switched to bilateral interconnection, the connecting the functional interfaces on the first cpu chip and the second cpu chip by using the cable assembly connector in a mode of connection based on a preset cable includes:

and if the fact that the interconnection mode is required to be switched to bilateral interconnection is judged, connecting the functional interfaces on the first central processing unit chip and the second central processing unit chip by utilizing a mini cold-side input/output connector in a mode of connecting based on a preset cable.

if the interconnection mode is judged to be switched to bilateral interconnection currently, determining a target function interface for connecting the first CPU chip and the second CPU chip;

and connecting the target function interfaces by using the cable assembly connector in a mode of connecting based on a preset cable, and configuring other function interfaces except the target function interfaces on the first CPU chip and the second CPU chip into PCI-E signals so as to externally connect a PCI-E external plug-in card.

if it is determined that the interconnection mode is currently required to be switched to bilateral interconnection, connecting the first central processing unit chip of the sea light No. 748X series and the functional interface on the second central processing unit chip of the sea light No. 748X series by using the cable assembly connector in a mode of connection based on a preset cable;

Or, the first central processing unit chip of the sea light series No. 746X and the functional interface on the second central processing unit chip of the sea light series No. 746X are connected by using the cable assembly connector in a manner of connection based on a preset cable.

Optionally, the method for interconnection compatibility of the central processing units further includes:

And carrying out signal integrity evaluation on the unilateral interconnection and the bilateral interconnection, and adjusting the position of a PCIE connector connected with the server main board to improve the quality of the signal integrity when a signal quality risk early warning event occurs on the unilateral interconnection or the bilateral interconnection.

The application discloses a CPU interconnection compatible device, which is applied to a server main board, wherein the server main board comprises a first CPU chip, a second CPU chip, a scene judging module and a cable assembly connector; wherein the device comprises:

the scene judging module is used for identifying the current application scene through the scene judging module;

the switching judging module is used for judging whether the interconnection mode between the first CPU chip and the second CPU chip is required to be switched currently or not by utilizing the identified current application scene;

The unilateral interconnection mode module is used for connecting the functional interfaces on the first central processing unit chip and the second central processing unit chip in a mode of connecting based on a preset printed circuit board wiring if the interconnection mode is judged to be currently required to be switched to unilateral interconnection;

The bilateral interconnection mode module is used for connecting the functional interfaces on the first central processing unit chip and the second central processing unit chip by utilizing the cable assembly connector in a mode of connecting based on a preset cable if the interconnection mode is judged to be switched to bilateral interconnection currently;

In a third aspect, the present application discloses a server, the server comprising a processor, a memory and a server motherboard as described above; wherein the memory is configured to store a computer program that is loaded and executed by the processor to implement the CPU interconnect compatibility method as described above.

In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein the computer program when executed by a processor implements a cpu interconnect compatible method as described above.

The application provides a CPU interconnection compatible method which is applied to a server main board, wherein the server main board comprises a first CPU chip, a second CPU chip, a scene judging module and a cable assembly connector; wherein the method comprises the following steps: identifying a current application scene through the scene judging module, and judging whether the interconnection mode between the first CPU chip and the second CPU chip is required to be switched currently or not by utilizing the identified current application scene; if the interconnection mode is judged to be switched to unilateral interconnection currently, connecting the functional interfaces on the first CPU chip and the second CPU chip in a mode of connection based on a preset printed circuit board wiring; if the fact that the interconnection mode is required to be switched to bilateral interconnection is judged, the functional interfaces on the first central processing unit chip and the second central processing unit chip are connected through the cable assembly connector in a mode of connection based on a preset cable; and after the first CPU chip and the second CPU chip monitor that the interconnection mode is switched, switching the firmware of the first CPU chip and the second CPU chip to a preset target firmware corresponding to the current interconnection mode.

The beneficial technical effects of the application are as follows: and realizing the design of the interconnection switching logic of the server main board compatible with the two CPU chips according to the current identified application scene. If the interconnection mode corresponding to the current application scene is unilateral interconnection, the unilateral interconnection between the first central processing unit chip and the second central processing unit chip is realized by presetting a mode of connecting wiring of the printed circuit board, so that the cost of the printed circuit board is saved to the greatest extent, and resources are fully utilized; if the interconnection mode corresponding to the current application scene is bilateral interconnection, the bilateral interconnection between the first central processing unit chip and the second central processing unit chip is realized by using a cable assembly connector in a mode of connecting a preset cable. Therefore, the design that the server main board is compatible with two kinds of CPU chip interconnection switching logic is realized, and more application scenes are covered while the cost is saved. In addition, the application also realizes the corresponding firmware switching and system topology switching of the CPU chip corresponding to the interconnection mode switching of the CPU chip, and covers more application scenes.

In addition, the device and the storage medium for interconnecting and compatible central processing units provided by the application correspond to the method for interconnecting and compatible central processing units, and have the same effects.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a conventional single-sided interconnect scheme according to the present disclosure;

FIG. 2 is a schematic diagram of a prior art dual-sided interconnect scheme according to the present disclosure;

FIG. 3 is a flow chart of a CPU interconnect compatible method of the present application;

FIG. 4 is a schematic diagram illustrating CPU interconnect compatibility according to the present disclosure;

FIG. 5 is a flowchart of a specific CPU interconnect compatible method of the present disclosure;

FIG. 6 is a schematic diagram of an interconnection compatible device for a CPU according to the present application;

fig. 7 is a block diagram of an electronic device according to the present disclosure.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Currently, a No. 4 CPU platform for sea light has various types of CPU products, and different CPU interconnection modes are supported due to different internal designs of the CPU. The marine light No. 4 CPU platform supports two CPU interconnection modes, as shown in FIG. 1 and FIG. 2 respectively. The option1 (option 1) interconnection mode in fig. 1 is a single-sided interconnection mode, and the option2 interconnection mode in fig. 2 is a double-sided interconnection mode. Wherein, the 749x series CPU products only have 1 IO die (kernel), and the single-side and double-side interconnection modes of the CPU have the same effect; the 748x and 746x serial CPU products have 2 IO die inside, and the bilateral interconnection mode is more friendly to CPU performance. Meanwhile, the unilateral interconnection mode of the CPU is more friendly to the design of the main board, and the requirements on the number of laminated layers of the main board and the length of the main board are lower. Therefore, when matching with CPUs of different models, the same server motherboard can be designed in a compatible manner with different CPU interconnection modes under the condition of considering the cost, and is an important point of motherboard design.

Therefore, the application provides a CPU interconnection compatible scheme which can be compatible with two CPU interconnection switching logics, and can cover more application scenes while saving cost.

The embodiment of the invention discloses a method for interconnecting and compatible central processing units, which is applied to a server main board, wherein the server main board comprises a first central processing unit chip, a second central processing unit chip, a scene judging module and a cable assembly connector; referring to fig. 3, the method includes:

step S11: and identifying a current application scene through the scene judging module, and judging whether the interconnection mode between the first CPU chip and the second CPU chip is required to be switched currently or not by utilizing the identified current application scene.

In the embodiment of the application, the design of the server main board is compatible with two modes of unilateral interconnection and bilateral interconnection. The two CPU interconnection modes are mutually exclusive, do not exist at the same time, and respectively select different interconnection modes in different application scenes.

According to the embodiment of the application, the design that the server main board based on the marine light No. four platform is compatible with two CPU interconnection switching logics can be realized through cable switching. Firstly, a current application scene is identified through a scene judging module so as to judge whether cable switching is needed currently. It can be understood that if the current corresponding application scene is a scene requiring unilateral interconnection, the interconnection mode is correspondingly switched to unilateral interconnection; and if the current corresponding application scene is a scene needing bilateral interconnection, correspondingly switching the interconnection mode into bilateral interconnection.

Step S12: and if the fact that the interconnection mode is required to be switched to single-side interconnection is judged, connecting the functional interfaces on the first CPU chip and the second CPU chip in a mode of connecting based on a preset printed circuit board wiring.

In the embodiment of the application, for the application scene of unilateral interconnection, the connection is performed by a mode based on the routing of a preset printed circuit board (Printed Circuit Board, PCB). As shown in fig. 4, the manner in the illustration corresponds to the interconnection topology in a single-sided interconnection scenario. The unilateral interconnection of the CPU can save the cost of the PCB to the greatest extent through the way of PCB wiring, and PCIE (Peripheral Component Interconnect Express) resources are fully utilized.

Step S13: and if the fact that the interconnection mode is required to be switched to bilateral interconnection is judged, connecting the functional interfaces on the first CPU chip and the second CPU chip by using the cable assembly connector in a mode of connecting based on a preset cable.

In the embodiment of the application, for the application scene of bilateral interconnection, the bilateral interconnection of the CPU is realized by matching a mode of connection based on a preset cable. As shown in fig. 4, the second mode in the illustration corresponds to the interconnection topology in the bilateral interconnection scenario. Under the bilateral interconnection scene, BIOS configures PCIE resources of G0, G2, G4 and G5 interfaces (ports) on two CPUs into XHMI (paths between interconnection) of CPU interconnection, so as to realize bilateral interconnection of the CPUs. The G0 and G2 interfaces are interfaces that must be connected to each other, whether they are single-sided or double-sided.

It should be noted that, if it is determined that the interconnection mode is currently required to be switched to the dual-side interconnection, a Mini Cool Edge input/output connector (MCIO) is used to connect the functional interfaces on the first cpu chip and the second cpu chip in a mode of connection based on a preset cable.

In the embodiment of the application, when the server main body compatible with the design supports a CPU bilateral interconnection mode, PCIE resources which can be externally connected with PCIE external cards are reduced, so that the resource reduction of the external cards can be supported, and a scene that the use of 748x and 746x series CPU products requires bilateral interconnection is designated. IO die is a part of CPU, and compared with the area of a computing chip of the CPU, the CPU has the functions of data input and output, and is integrated with the DDR4 (Double Data Rate Fourth Generation Synchronous Dynamic Random Access Memory, fourth generation synchronous dynamic random access memory) memory controller, the PCIE 4.0 controller, the USB (Universal Serial Bus ) and the SATA (SERIAL ATA, serial ATA) controller and other IO interfaces. The 748x and 746x serial CPU products have 2 IO die inside, and the bilateral interconnection mode is more friendly to CPU performance.

Specifically, if it is determined that the interconnection mode is currently required to be switched to bilateral interconnection, the cable assembly connector is used to connect the functional interfaces on the first central processing unit chip of the sea light type 748X series and the second central processing unit chip of the sea light type 748X series; or, the first central processing unit chip of the sea light series No. 746X and the functional interface on the second central processing unit chip of the sea light series No. 746X are connected by using the cable assembly connector in a manner of connection based on a preset cable.

It can be understood that when the design of compatible two kinds of CPU interconnection switching logic of the main board based on the marine light No. four platform is realized for cable switching, the firmware and the system topology are correspondingly switched. Therefore, when the first central processing unit chip and the second central processing unit chip monitor that the interconnection mode is switched, the firmware of the first central processing unit chip and the second central processing unit chip is switched to the preset target firmware corresponding to the current interconnection mode. Therefore, the application can realize the design that the mainboard is compatible with two CPU interconnection switching logics on the sea light platform, and can cover more application scenes while saving cost.

In one specific embodiment, a description is given of a functional interface configuration of a bilateral interconnection scenario. If it is determined that the interconnection mode is currently required to be switched to bilateral interconnection, connecting the functional interfaces on the first central processing unit chip and the second central processing unit chip by using the cable assembly connector in a mode of connection based on a preset cable, including:

In the embodiment of the application, when the CPUs of the server main board need to be connected in a bilateral interconnection mode, the BIOS configures PCIE resources of G0, G2, G4 and G5 interfaces on the two CPUs into XHMI for CPU interconnection to realize bilateral interconnection of the CPUs. For the other ports, the ports are configured into PCIE signals for connecting to the outgoing PCIE extrapolation card. Similarly, as described above, when the compatible design of the server motherboard supports the bilateral interconnection mode of the CPU, PCIE resources that can externally connect to PCIE add-on cards are reduced, so that resource reduction of add-on cards can be supported, and a scenario that uses 748x and 746x series CPU products to require bilateral interconnection is specified.

In one specific embodiment, SI (SIGNAL INTEGRALITY, signal integrity) evaluation is required, so the cpu interconnect compatible method further includes:

Signal integrity refers to the quality of a signal on a transmission path. In digital circuits, a string of binary signal streams is represented by a waveform of voltage (or current). However, signals in nature are analog in nature and not digital, and all are subject to noise, distortion and losses. Therefore, in the embodiment of the application, the signal quality risks of the single-side interconnection of the CPU realized by the PCB and the double-side interconnection of the CPU realized by the cable are fully evaluated. If there is a high risk in some way, the SI quality of PCIE signals and XHMI signals can be guaranteed by adjusting the location of the outgoing PCIE connector. It can be understood that, generally, different manufacturers have respective loss value standards, and whether the signal quality risk early warning event occurs in the single-side interconnection or the double-side interconnection can be judged by comparing the loss value standards according to the layout wiring.

The embodiment of the application discloses a specific CPU interconnection compatibility method, which is shown in FIG. 5 and comprises the following steps:

Step S21: presetting two general input/output port signals for providing the judging index of the interconnection mode for the basic input/output system; and setting corresponding pull-up and pull-down combinations for the general input/output signals respectively, and determining different general input/output signal state combinations according to the pull-up and pull-down combinations.

In the embodiment of the present application, two GPIO (General-purpose input/output interface) signals are first specified to provide a judging index of an interconnection mode for a BIOS (Basic Input Output System, basic input/output system). Different configuration modes of PCIE resources in the BIOS are corresponding through the pull-up and pull-down combination of the two GPIO signals. When the corresponding GPIO signals are changed after the interconnected cables are inserted, the BIOS can detect the state change of the GPIO, and the GPIO signals are identified according to the GPIO combination designed in advance, so that the CPU of the server main board is considered to be connected in a unilateral interconnection mode or a bilateral interconnection mode.

Step S22: and determining a first general input/output signal state combination matched with the single-side interconnection and a second general input/output signal state combination matched with the double-side interconnection from the general input/output signal state combinations.

Step S23: and configuring the interconnection mode corresponding to the first general input/output port signal state combination as the single-side interconnection, and configuring the interconnection mode corresponding to the second general input/output port signal state combination as the double-side interconnection.

In the embodiment of the application, the pull-up and pull-down combinations of the two GPIO signals correspond to four different types, corresponding single-double-sided interconnection scenes are matched for the four types in advance, and then the corresponding state combinations are configured into the corresponding single-double-sided interconnection scenes.

Step S24: and identifying a current application scene through the scene judging module, and matching by utilizing the identified current application scene and the general input/output port signal state combination so as to judge whether the interconnection mode between the first CPU chip and the second CPU chip is required to be switched currently.

In the embodiment of the application, the condition for judging whether the cable is required to be switched is that the current application scene corresponds to a unilateral interconnection scene or a bilateral interconnection scene. In a first specific embodiment, if the identified current application scenario corresponds to a scenario requiring unilateral interconnection, and the combination of the general input/output signal states is the first general input/output signal state combination, it is determined that the interconnection mode between the first cpu chip and the second cpu chip does not need to be switched currently. When the corresponding GPIO signals change after the interconnected cables are inserted, the BIOS detects the change of the states of the GPIOs, and if the current GPIO signals correspond to a unilateral interconnection scene and the detection determines that the combination of the GPIO signals designed in advance also corresponds to the unilateral interconnection, the interconnection mode does not need to be switched.

In a second specific embodiment, if the identified current application scenario corresponds to a scenario requiring unilateral interconnection, and the general input/output signal state combination is the second general input/output signal state combination, it is determined that the interconnection mode between the first cpu chip and the second cpu chip needs to be switched currently. When the corresponding GPIO signals change after the interconnected cables are inserted, the BIOS detects the GPIO state change, and if the current corresponding unilateral interconnection scene but the detection determines that the GPIO signal combination designed in advance corresponds to bilateral interconnection, the interconnection mode needs to be switched, and the interconnection mode corresponding to the GPIO signal combination is switched to bilateral interconnection.

In a third specific embodiment, if the identified current application scenario corresponds to a scenario requiring bilateral interconnection, and the combination of the general input/output signal states is the first general input/output signal state combination, it is determined that the interconnection mode between the first cpu chip and the second cpu chip needs to be switched currently. When the corresponding GPIO signals change after the interconnected cables are inserted, the BIOS detects the GPIO state change, and if the current corresponding bilateral interconnection scene but the detection determines that the gpIO signal combination designed in advance corresponds to the unilateral interconnection, the interconnection mode needs to be switched, and the interconnection mode corresponding to the GPIO signal combination is switched to the unilateral interconnection.

In a fourth specific embodiment, if the identified current application scenario corresponds to a scenario requiring bilateral interconnection, and the general input/output signal state combination is the second general input/output signal state combination, it is determined that the interconnection mode between the first cpu chip and the second cpu chip does not need to be switched currently. When the corresponding GPIO signals change after the interconnected cables are inserted, the BIOS detects the change of the states of the GPIOs, and if the current corresponding bilateral interconnection scene and the detection determines that the GPIO signal combination designed in advance also corresponds to bilateral interconnection, the interconnection mode does not need to be switched.

Step S25: and if the fact that the interconnection mode is required to be switched to single-side interconnection is judged, connecting the functional interfaces on the first CPU chip and the second CPU chip in a mode of connecting based on a preset printed circuit board wiring.

Step S26: and if the fact that the interconnection mode is required to be switched to bilateral interconnection is judged, connecting the functional interfaces on the first CPU chip and the second CPU chip by using the cable assembly connector in a mode of connecting based on a preset cable.

For more specific processing procedures in the above step S25 and step S26, reference may be made to the corresponding contents disclosed in the foregoing embodiments, and no detailed description is given here.

Correspondingly, the embodiment of the application also discloses a CPU interconnection compatible device which is applied to a server main board, wherein the server main board comprises a first CPU chip, a second CPU chip, a scene judging module and a cable assembly connector; referring to fig. 6, the apparatus includes:

A scene determination module 11, configured to identify a current application scene through the scene determination module;

The switching judging module 12 is configured to judge whether the interconnection mode between the first central processing unit chip and the second central processing unit chip needs to be switched currently by using the identified current application scenario;

a single-side interconnection mode module 13, configured to connect the functional interfaces on the first central processing unit chip and the second central processing unit chip by a connection mode based on a preset printed circuit board wiring if it is determined that the interconnection mode is currently required to be switched to single-side interconnection;

A bilateral interconnection mode module 14, configured to connect the functional interfaces on the first cpu chip and the second cpu chip by using the cable assembly connector in a manner of connection based on a preset cable if it is determined that the interconnection mode is currently required to be switched to bilateral interconnection;

For more specific working procedures of the above modules, reference may be made to the corresponding contents disclosed in the foregoing embodiments, and no further description is given here.

Therefore, through the scheme of the embodiment, the method is applied to a server main board, wherein the server main board comprises a first central processing unit chip, a second central processing unit chip, a scene judging module and a cable assembly connector; wherein the device comprises: identifying a current application scene through the scene judging module, and judging whether the interconnection mode between the first CPU chip and the second CPU chip is required to be switched currently or not by utilizing the identified current application scene; if the interconnection mode is judged to be switched to unilateral interconnection currently, connecting the functional interfaces on the first CPU chip and the second CPU chip in a mode of connection based on a preset printed circuit board wiring; if the fact that the interconnection mode is required to be switched to bilateral interconnection is judged, the functional interfaces on the first central processing unit chip and the second central processing unit chip are connected through the cable assembly connector in a mode of connection based on a preset cable; and after the first CPU chip and the second CPU chip monitor that the interconnection mode is switched, switching the firmware of the first CPU chip and the second CPU chip to a preset target firmware corresponding to the current interconnection mode.

Further, the embodiment of the present application further discloses an electronic device, and fig. 7 is a block diagram of an electronic device 20 according to an exemplary embodiment, where the content of the figure is not to be considered as any limitation on the scope of use of the present application.

Fig. 7 is a schematic structural diagram of an electronic device 20 according to an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input output interface 25, and a communication bus 26. The memory 22 is configured to store a computer program that is loaded and executed by the processor 21 to implement relevant steps in the cpu interconnect compatible method disclosed in any of the foregoing embodiments.

In this embodiment, the power supply 23 is configured to provide an operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and an external device, and the communication protocol to be followed is any communication protocol applicable to the technical solution of the present application, which is not specifically limited herein; the input/output interface 25 is used for acquiring external input data or outputting external output data, and the specific interface type thereof may be selected according to the specific application requirement, which is not limited herein.

The memory 22 may be a carrier for storing resources, such as a read-only memory, a random access memory, a magnetic disk, or an optical disk, and the resources stored thereon may include an operating system 221, a computer program 222, data 223, and the like, and the data 223 may include various data. The storage means may be a temporary storage or a permanent storage.

The operating system 221 is used for managing and controlling various hardware devices on the electronic device 20 and the computer program 222, which may be Windows Server, netware, unix, linux, etc. The computer program 222 may further include a computer program that can be used to perform other specific tasks in addition to the computer program that can be used to perform the cpu interconnect compatible method performed by the electronic device 20 as disclosed in any of the previous embodiments.

Further, embodiments of the present application also disclose a computer readable storage medium, where the computer readable storage medium includes random access Memory (Random Access Memory, RAM), memory, read-Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, magnetic disk, or optical disk, or any other form of storage medium known in the art. The computer program, when executed by the processor, implements the aforementioned CPU interconnect compatibility method. For specific steps of the method, reference may be made to the corresponding contents disclosed in the foregoing embodiments, and no further description is given here.

In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, so that the same or similar parts between the embodiments are referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.

The steps of a central processing unit interconnect compatible method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software modules may be disposed in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The foregoing has described in detail the method, apparatus, device and medium for interconnection compatibility of central processing units provided by the present invention, and specific examples have been applied to illustrate the principles and embodiments of the present invention, and the above description of the examples is only for helping to understand the method and core idea of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.

Claims

1. The interconnection compatibility method of the central processing unit is characterized by being applied to a server main board, wherein the server main board comprises a first central processing unit chip, a second central processing unit chip, a scene judging module and a cable assembly connector; wherein the method comprises the following steps:

2. The method of claim 1, wherein before the identifying, by the scene determining module, a current application scene and determining whether the interconnection manner between the first cpu chip and the second cpu chip needs to be switched currently according to the identified current application scene, the method further comprises:

3. The method of claim 2, wherein the matching the identified current application scenario with the universal i/o signal state combination to determine whether the interconnection manner between the first cpu chip and the second cpu chip is currently required to be switched, comprises:

4. The method according to claim 1, wherein if it is determined that the interconnection mode is currently required to be switched to the dual-sided interconnection, connecting the functional interfaces on the first cpu chip and the second cpu chip by using the cable assembly connector in a mode of connection based on a preset cable, comprises:

and if the fact that the interconnection mode is required to be switched to single-side interconnection is judged, connecting the functional interfaces on the first central processing unit chip and the second central processing unit chip by utilizing a mini cold-side input/output connector in a mode of connecting based on a preset cable.

5. The method according to claim 1, wherein if it is determined that the interconnection mode is currently required to be switched to the dual-sided interconnection, connecting the functional interfaces on the first cpu chip and the second cpu chip by using the cable assembly connector in a mode of connection based on a preset cable, comprises:

6. The method according to claim 1, wherein if it is determined that the interconnection mode is currently required to be switched to the dual-sided interconnection, connecting the functional interfaces on the first cpu chip and the second cpu chip by using the cable assembly connector in a mode of connection based on a preset cable, comprises:

7. The cpu interconnect compatible method of any of claims 1 to 6, further comprising:

8. The interconnection compatible device of the central processing unit is characterized by being applied to a server main board, wherein the server main board comprises a first central processing unit chip, a second central processing unit chip, a scene judging module and a cable assembly connector; wherein the device comprises:

And when the first CPU chip and the second CPU chip monitor that the interconnection mode is switched, the firmware of the first CPU chip and the second CPU chip is switched to a preset target firmware corresponding to the current interconnection mode.

9. A server, characterized in that it comprises a processor, a memory and a server motherboard according to any of claims 1 to 7; wherein the memory is for storing a computer program to be loaded and executed by the processor to implement the cpu interconnect compatible method of any of claims 1 to 7.

10. A computer-readable storage medium storing a computer program; wherein the computer program when executed by a processor implements the cpu interconnect compatible method of any of claims 1 to 7.