CN117971722A - Execution method and device for fetch instruction - Google Patents
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Abstract
The application provides a method and a device for executing a fetch instruction, and relates to the technical field of processors. The method comprises the following steps: acquiring a first fetch result of a first fetch instruction; determining whether the first fetch result is a virtual address of a second fetch instruction, wherein the second fetch instruction is a subsequent fetch instruction of the first fetch instruction; and accessing the data cache based on the first fetch result to acquire the second fetch result of the second fetch instruction under the condition that the first fetch result is the virtual address of the second fetch instruction. Therefore, under the condition that the first fetch result is the virtual address of the second fetch instruction, the data cache can be directly accessed based on the first fetch result to acquire the second fetch result of the second fetch instruction, and the processes of launching, reading a register file, calculating the virtual address and the like related to the second fetch instruction are optimized, so that the fetch instruction delay of a main pipeline of the processor is greatly reduced.
Description
Technical Field
The present application relates to the field of processor technologies, and in particular, to a method and an apparatus for executing a fetch instruction.
Background
The development of the memory access speed of the processor is far from the development of the operation speed of the processor, the further development of the performance of the processor is severely restricted by the increasingly serious problem of the memory access speed, and the reduction of the access instruction use delay (load-to-use latency) of the main pipeline of the processor is the key for improving the memory access performance of the processor.
For accesses to data structures such as pointers, linked lists, etc., the memory address itself appears discontinuous or irregular in physical storage. Because of the irregular access mode of the pointer and the linked list, the access is difficult to optimize.
And accessing data structures such as pointers, linked lists and the like, wherein the result obtained by the former fetch instruction is the address of the latter fetch instruction. That is, the previous fetch instruction is written back to the value in the destination register, and the value is exactly the virtual address of the fetch instruction calculated by the address calculation unit. There is a correlation between these two instructions and the following instruction must wait for the results of the preceding instruction to write back to be able to issue execution.
Disclosure of Invention
The present application aims to solve at least one of the technical problems in the related art to some extent.
Therefore, an object of the present application is to provide a method for executing an access instruction, which utilizes the address characteristics of the last access instruction as a result of the previous access instruction in a data structure such as a pointer and a linked list, so as to reduce the use delay of the access instruction in a pipeline of a processor.
A second object of the present application is to provide an execution apparatus for fetching an instruction.
A third object of the present application is to propose an electronic device.
A fourth object of the present application is to propose a non-transitory computer readable storage medium.
A fifth object of the application is to propose a computer programme product.
To achieve the above object, an embodiment of a first aspect of the present application provides a method for executing a fetch instruction, including: acquiring a first fetch result of a first fetch instruction; determining whether the first fetch result is a virtual address of a second fetch instruction, wherein the second fetch instruction is a subsequent fetch instruction of the first fetch instruction; and accessing a data cache based on the first fetch result to acquire a second fetch result of the second fetch instruction under the condition that the first fetch result is a virtual address of the second fetch instruction.
According to one embodiment of the present application, the determining whether the first fetch result is a virtual address of a second fetch instruction includes: under the condition that the first access instruction carries a preset identifier, determining that the first access result is a virtual address of the second access instruction; or under the condition that the first fetch instruction does not carry the preset identifier, determining that the first fetch result is not the virtual address of the second fetch instruction.
According to one embodiment of the present application, further comprising: and in a program compiling stage, if the first fetch instruction is determined to be the fetch instruction for fetching the address of the second fetch instruction, adding the preset identifier into the first fetch instruction.
According to one embodiment of the present application, the determining whether the first fetch result is a virtual address of a second fetch instruction includes: determining that the first fetch result is a virtual address of the second fetch instruction under the condition that a program counter of the first fetch instruction is the same as any program counter in a history table; or under the condition that the program counter of the first fetch instruction is different from each program counter in the history table, determining that the first fetch result is not the virtual address of the second fetch instruction; the history table stores a program counter of a first history access instruction, the access result of the first history access instruction is a virtual address of a second history access instruction, and the second history access instruction is a subsequent access instruction of the first history access instruction.
According to one embodiment of the present application, before the determining whether the first fetch result is the virtual address of the second fetch instruction, the method further includes: and under the condition that the fetch result of the first historical fetch instruction is the virtual address of the second historical fetch instruction, recording a program counter of the first historical fetch instruction to generate the history table.
According to one embodiment of the present application, a memory access system of a processor includes a prediction unit, the prediction unit is located after the data cache, and the determining whether the first fetch result is a virtual address of a second fetch instruction includes:
The prediction unit predicts that the first fetch result is a virtual address of the second fetch instruction when it is determined that the program counter of the first fetch instruction is the same as any program counter in the history table; or the prediction unit predicts that the first fetch result is not the virtual address of the second fetch instruction when it is determined that the program counter of the first fetch instruction is different from each program counter in the history table.
According to one embodiment of the present application, the obtaining the first fetch result of the first fetch instruction includes: the access instruction transmitting queue transmits the first fetch instruction; the fixed point register file and the floating point register file provide source operands required by the first fetch instruction; the address generating part calculates and obtains the virtual address of the first fetch instruction according to the source operand; a data translation backup buffer memory translates a virtual address of the first fetch instruction into a first physical address corresponding to the first fetch instruction; extracting a first to-be-compared tag corresponding to the first fetch instruction from the first physical address; the tag comparison part compares the first tag to be compared with the tag corresponding to each path of cache in the data cache, and determines first hit path information corresponding to the first fetch instruction; and reading the first fetch result from a data storage array of a data cache based on the first hit way information.
According to one embodiment of the present application, the accessing the data cache based on the first fetch result to obtain the second fetch result of the second fetch instruction includes: the data translation backup buffer memory translates the first fetch result into a second physical address corresponding to the second fetch instruction; extracting a second label to be compared corresponding to the second fetch instruction from the second physical address; the tag comparison part compares the second tag to be compared with the tag corresponding to each path of cache in the data cache, and determines second hit path information corresponding to the second fetch instruction; and reading the second fetch result from the data storage array of the data cache based on the second hit way information.
To achieve the above object, according to a second aspect of the present application, an execution apparatus for a fetch instruction is provided, including: the first acquisition module is used for acquiring a first fetch result of the first fetch instruction; the determining module is used for determining whether the first fetch result is a virtual address of a second fetch instruction, wherein the second fetch instruction is a subsequent fetch instruction of the first fetch instruction; and the second acquisition module is used for accessing the data cache based on the first access result to acquire the second access result of the second access instruction under the condition that the first access result is the virtual address of the second access instruction.
According to one embodiment of the application, the determining module is configured to: under the condition that the first access instruction carries a preset identifier, determining that the first access result is a virtual address of the second access instruction; or under the condition that the first fetch instruction does not carry the preset identifier, determining that the first fetch result is not the virtual address of the second fetch instruction.
According to one embodiment of the application, the system further comprises an identification module for: and in a program compiling stage, if the first fetch instruction is determined to be the fetch instruction for fetching the address of the second fetch instruction, adding the preset identifier into the first fetch instruction.
According to one embodiment of the application, the determining module is configured to: determining that the first fetch result is a virtual address of the second fetch instruction under the condition that a program counter of the first fetch instruction is the same as any program counter in a history table; or under the condition that the program counter of the first fetch instruction is different from each program counter in the history table, determining that the first fetch result is not the virtual address of the second fetch instruction; the history table stores a program counter of a first history access instruction, the access result of the first history access instruction is a virtual address of a second history access instruction, and the second history access instruction is a subsequent access instruction of the first history access instruction.
According to one embodiment of the present application, the method further includes a generating module, configured to record a program counter of the first history fetch instruction to generate the history table, where the fetch result of the first history fetch instruction is a virtual address of the second history fetch instruction.
According to one embodiment of the present application, a memory access system of a processor includes a prediction unit, where the prediction unit is located after the data cache, and predicts that the first fetch result is a virtual address of the second fetch instruction if it is determined that a program counter of the first fetch instruction is identical to any program counter in the history table; or the prediction unit predicts that the first fetch result is not the virtual address of the second fetch instruction when it is determined that the program counter of the first fetch instruction is different from each program counter in the history table.
According to one embodiment of the application, a first acquisition module is configured to: the access instruction transmitting queue transmits the first fetch instruction; the fixed point register file and the floating point register file provide source operands required by the first fetch instruction; the address generating part calculates and obtains the virtual address of the first fetch instruction according to the source operand; a data translation backup buffer memory translates a virtual address of the first fetch instruction into a first physical address corresponding to the first fetch instruction; extracting a first to-be-compared tag corresponding to the first fetch instruction from the first physical address; the tag comparison part compares the first tag to be compared with the tag corresponding to each path of cache in the data cache, and determines first hit path information corresponding to the first fetch instruction; and reading the first fetch result from a data storage array of a data cache based on the first hit way information.
According to one embodiment of the application, the second acquisition module is configured to: the data translation backup buffer memory translates the first fetch result into a second physical address corresponding to the second fetch instruction; extracting a second label to be compared corresponding to the second fetch instruction from the second physical address; the tag comparison part compares the second tag to be compared with the tag corresponding to each path of cache in the data cache, and determines second hit path information corresponding to the second fetch instruction; and reading the second fetch result from the data storage array of the data cache based on the second hit way information.
To achieve the above object, an embodiment of a third aspect of the present application provides an electronic device, including: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executable by the at least one processor to implement the method of executing the fetch instruction according to the embodiment of the first aspect of the present application.
To achieve the above object, an embodiment of a fourth aspect of the present application provides a non-transitory computer readable storage medium storing computer instructions for implementing a method for executing an access instruction according to an embodiment of the first aspect of the present application.
To achieve the above object, an embodiment of a fifth aspect of the present application provides a computer program product, including a computer program, which when executed by a processor implements a method for executing an fetch instruction according to an embodiment of the first aspect of the present application.
The application at least realizes the following beneficial effects: and under the condition that the first fetch result is the virtual address of the second fetch instruction, the data cache can be accessed directly based on the first fetch result to acquire the second fetch result of the second fetch instruction, and the processes of launching, reading a register file, calculating the virtual address and the like related to the second fetch instruction are optimized, so that the use delay of the fetch instruction of a main pipeline of the processor is greatly reduced.
Drawings
The foregoing and/or additional aspects and advantages of the application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a diagram illustrating a pointer data type correspondence;
FIG. 2 is a schematic diagram corresponding to a linked list data type;
FIG. 3 is a schematic diagram illustrating a command format;
FIG. 4 is a schematic diagram illustrating another instruction format;
FIG. 5 is a schematic diagram illustrating another instruction format;
FIG. 6 is a schematic diagram illustrating another instruction format;
FIG. 7 is a schematic diagram illustrating another instruction format;
FIG. 8 is a schematic diagram illustrating another instruction format;
FIG. 9 is a schematic diagram illustrating another instruction format;
FIG. 10 is a diagram of a memory access system architecture of a processor;
FIG. 11 is a schematic diagram illustrating an exemplary implementation of a method of executing a fetch instruction, in accordance with an embodiment of the present application;
FIG. 12 is a diagram of an architecture of a memory access system of another processor according to an embodiment of the present application;
FIG. 13 is a schematic diagram of an execution device of a fetch instruction according to an embodiment of the present application;
Fig. 14 is a schematic diagram of an electronic device according to an embodiment of the application.
Detailed Description
Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present application and should not be construed as limiting the application.
And accessing data structures such as pointers, linked lists and the like, wherein the result obtained by the former fetch instruction is the address of the latter fetch instruction.
Fig. 1 is a schematic diagram corresponding to a pointer data type, as shown in fig. 1, 0x80a000 is an address of a pointer variable p, and 0x80ab0c is an address of a variable i. The pointer variable holds the address of the variable i, i.e. the value of the pointer variable. P=0x80ab0c, =p=5, & p=0x80a000. p is the pointer variable, and the address is stored.
Fig. 2 is a schematic diagram corresponding to a linked list data type, and as shown in fig. 2, the linked list stores the address of the next element while storing its own content. The field storing the data element is called the data field and the field storing the directly subsequent position is called the pointer field. The information stored in the pointer field is called a pointer or a chain.
In order to clearly describe the method provided by the embodiment of the invention, the following description is provided for fetching instructions. The formats of fetch instructions of different instruction sets are not identical, and the general instruction set fetch instructions comprise four types of fetch bytes (lb), fetch halfwords (lh), fetch words (lw) and fetch doublewords (ld). The following describes a fetch instruction using RISC-V (fifth generation reduced instruction set) as an example, but is not limited to the following instructions.
Lb rd, offset (rs 1), x [ rd ] = sext (M [ x [ rs1] +sext (offset) ] [7:0 ]), and the corresponding instruction format is shown in fig. 3. Where rd and rs1 are the identifiers of the base address registers, and offset is the offset. The instruction refers to a Byte Load (Load Byte), i.e., a Byte is read from address x [ rs1] + sign-extend (offset), and written to x [ rd ] after sign bit expansion.
Lbu rd, offset (rs 1), x [ rd ] =m [ x [ rs1] +sext (offset) ] [7:0], the corresponding instruction format is shown in fig. 4. The instruction refers to Unsigned Byte loading (Load Byte, unsigned), i.e., one Byte is read from address x [ rs1] + sign-extend (offset), written to x [ rd ] after zero extension.
Ld rd, offset (rs 1), x [ rd ] =M [ x [ rs1] +sext (offset) ] [63:0], the corresponding instruction format of which is shown in FIG. 5. The instruction refers to a double word load (Load Doubleword), i.e., eight bytes are read from address x [ rs1] + sign-extend (offset), and x [ rd ] is written.
Lh rd, offset (rs 1), x [ rd ] = sext (M [ x [ rs1] +sext (offset) ] [15:0 ]), the corresponding instruction format is shown in fig. 6. The instruction refers to half word loading (Load Halfword), i.e. two bytes are read from address x [ rs1] + sign-extend (offset), and x [ rd ] is written after sign bit expansion.
Lhu rd, offset (rs 1), x [ rd ] =m [ x [ rs1] +sext (offset) ] [15:0], the corresponding instruction format of which is shown in fig. 7. The instruction refers to Unsigned Halfword (Unsigned) loading, i.e., two bytes are read from address x [ rs1] + sign-extend (offset), zero extended and written to x [ rd ].
Lwrd, offset (rs 1), x [ rd ] =sext (M [ x [ rs1] +sext (offset) ] [31:0 ]), and the corresponding instruction format is shown in fig. 8. The instruction refers to a Word Load (Load Word), i.e., four bytes are read from address x [ rs1] + sign-extend (offset), and x [ rd ] is written.
Lwu rd, offset (rs 1), x [ rd ] =m [ x [ rs1] +sext (offset) ] [31:0], the corresponding instruction format of which is shown in fig. 9. The instruction refers to Unsigned Word loading (Load Word, unsigned), i.e., four bytes are read from address x [ rs1] + sign-extend (offset), written to x [ rd ] after zero extension.
FIG. 10 is a diagram of a memory access system architecture of a processor; as shown in FIG. 10, modern processors all implement out-of-order execution of accesses. The memory access instruction transmitting queue is responsible for transmitting memory access instructions ready for execution, wherein the memory access instructions comprise access instructions and memory instructions; the fixed-point register file and the floating-point register file are responsible for providing source operands required by instructions and storing written-back fixed-point and floating-point destination operands; the memory access generating part is responsible for calculating the address of the memory access instruction; a data translation look-aside buffer memory (Translation Lookaside Buffer, TLB) responsible for translating virtual addresses of access instructions into physical addresses; a TAG (DCACHE TAG) of the data Cache, a TAG (TAG) of the primary data Cache is stored; the TAG comparison part performs multi-way TAG comparison (TAG complex) to obtain hit path information; a Data Cache Data storage array (DCACHE DATA) stores Data (Data) of the Data Cache; the memory re-order queue stores and manages memory instructions, is responsible for maintaining the sequence relation of the memory instructions, and is responsible for intercepting the subsequent data Cache refilling (Refill) result and executing write-back operation when the data Cache access fails (CACHE MISS).
FIG. 11 is a schematic diagram of an exemplary embodiment of a method for executing an access instruction according to the present application, as shown in FIG. 11, comprising the steps of:
S1101, obtaining a first fetch result of the first fetch instruction.
In some embodiments, based on the memory access system architecture diagram shown in fig. 10, the specific steps of obtaining the first fetch result of the first fetch instruction are: (1) the memory access instruction issue queue sends a first fetch instruction; (2) The fixed-point register file and the floating-point register file provide source operands required by the first fetch instruction; (3) The address generating part calculates and obtains the virtual address of the first fetch instruction according to the source operand; (4) The data translation backup buffer memory translates the virtual address of the first fetch instruction into a first physical address corresponding to the first fetch instruction; (5) Extracting a first label to be compared corresponding to a first fetch instruction from a first physical address; (6) The tag comparison part compares a first tag to be compared with the tag corresponding to each path of cache in the data cache, and determines first hit path information corresponding to a first fetch instruction; (7) The first fetch result is read from the data storage array of the data cache based on the first hit way information.
S1102, determining whether the first fetch result is a virtual address of a second fetch instruction, wherein the second fetch instruction is a subsequent fetch instruction to the first fetch instruction.
In the embodiment of the disclosure, determining whether the first fetch result is the virtual address of the second fetch instruction may be implemented by software or hardware.
In some embodiments, the method implemented by software is: under the condition that the first access instruction carries a preset identifier, determining that the first access result is a virtual address of the second access instruction; or under the condition that the first fetch instruction does not carry the preset identification, determining that the first fetch result is not the virtual address of the second fetch instruction. Therefore, whether the first fetch instruction is an instruction for fetching the virtual address of the second fetch instruction can be accurately determined by identifying whether the first fetch instruction carries a preset identifier.
Optionally, in the program compiling stage, if it is determined that the first fetch instruction is a fetch instruction for fetching an address of the second fetch instruction, the preset identifier is added to the first fetch instruction. Thus, the preset mark is carried to the memory system along with the fetch instruction through each pipeline stage. Therefore, whether the fetch instruction is an instruction of a virtual address of a next fetch instruction can be accurately identified through the preset identification.
In some embodiments, in the case that a Program Counter (PC) of the first fetch instruction is the same as any Program Counter in the history table, determining that the first fetch result is a virtual address of the second fetch instruction; or under the condition that the program counter of the first fetch instruction is different from each program counter in the history table, determining that the first fetch result is not the virtual address of the second fetch instruction. The program counter stores a first history access instruction in the history table, the access result of the first history access instruction is a virtual address of a second history access instruction, and the second history access instruction is a subsequent access instruction of the first history access instruction. Thus, whether the first fetch instruction is an instruction of a virtual address of the second fetch instruction can be accurately predicted according to the stored history access information in the history table.
It should be noted that, each instruction has a corresponding program counter, that is, the instruction address of each instruction, and the program counter of the fetch instruction is brought into the memory access system through each pipeline stage along with the fetch instruction. Thus, the program counter of the fetch instruction can be used for predicting whether the fetch instruction is an instruction of a virtual address of a next fetch instruction.
Optionally, in the case that the fetch result of the first history fetch instruction is the virtual address of the second history fetch instruction, the program counter of the first history fetch instruction is recorded to generate the history table.
In some embodiments, the method implemented by hardware is: the prediction unit is arranged behind the data storage array of the data cache in the memory access system of the processor, i.e. the memory access system of the processor comprises the prediction unit, and the prediction unit is located behind the data cache. The prediction component predicts that the first fetch result is the virtual address of the second fetch instruction under the condition that the program counter of the first fetch instruction is the same as any program counter in the history table; or the prediction unit predicts that the first fetch result is not the virtual address of the second fetch instruction in the case that the program counter of the first fetch instruction is determined to be different from each program counter in the history table.
Fig. 12 is a schematic diagram of another access system of a processor according to an embodiment of the present disclosure, where, as shown in fig. 12, the access system of the processor includes a prediction unit, and the prediction unit is located after the data cache data storage array, and after the first access result is obtained from the data cache data storage array, the prediction unit predicts whether the first access result is a virtual address of the second access instruction according to the history table, and in case that the first access result is predicted to be a virtual address of the second access instruction, the prediction unit may directly access the data cache based on the first access result to obtain the second access result of the second access instruction.
S1103, accessing the data cache based on the first fetch result to obtain a second fetch result of the second fetch instruction if the first fetch result is the virtual address of the second fetch instruction.
In this embodiment of the present disclosure, after determining that the first access result is the virtual address of the second access instruction, the second access result of the second access instruction may be directly obtained based on the first access result, which specifically includes: (1) A data translation backup buffer memory for translating the first fetch result into a second physical address corresponding to the second fetch instruction; (2) Extracting a second label to be compared corresponding to a second fetch instruction from a second physical address; (3) The tag comparison part compares a second tag to be compared with the tag corresponding to each path of cache in the data cache, and determines second hit path information corresponding to a second fetch instruction; (4) And reading a second fetch result from the data storage array of the data cache based on the second hit way information.
Therefore, after the first access result is obtained, the second access result of the second access instruction can be read directly based on the virtual address of the first access result, the process that the access instruction transmitting queue transmits the second access instruction, the fixed-point register file and the floating-point register file provide source operands required by the second access instruction is skipped, the address generating part calculates and obtains the virtual address of the second access instruction according to the source operands corresponding to the second access instruction, the process of directly entering a read data cache tag and performing virtual-to-real address conversion through the TLB, the process of comparing the cache tag, reading the data cache data storage array and writing back data is performed, and the access instruction use delay of the instruction for fetching data by using the pointer address after the pointer and the linked list data type is greatly reduced.
In the disclosed embodiment, a first fetch result of a first fetch instruction is obtained first, then it is determined whether the first fetch result is a virtual address of a second fetch instruction, where the second fetch instruction is a subsequent fetch instruction of the first fetch instruction, and finally, in case that the first fetch result is the virtual address of the second fetch instruction, the data cache is accessed based on the first fetch result to obtain a second fetch result of the second fetch instruction. Therefore, under the condition that the first fetch result is the virtual address of the second fetch instruction, the data cache can be directly accessed based on the first fetch result to acquire the second fetch result of the second fetch instruction, and the processes of launching, reading a register file, calculating the virtual address and the like related to the second fetch instruction are optimized, so that the use delay of the fetch instruction of a main pipeline of the processor is greatly reduced.
Fig. 13 is a schematic diagram of an execution apparatus of an fetch instruction, as shown in fig. 13, and the execution apparatus 1300 of the fetch instruction includes:
a first obtaining module 1301, configured to obtain a first fetch result of the first fetch instruction;
A determining module 1302, configured to determine whether the first fetch result is a virtual address of a second fetch instruction, where the second fetch instruction is a subsequent fetch instruction of the first fetch instruction;
The second obtaining module 1303 is configured to access the data cache based on the first fetch result to obtain a second fetch result of the second fetch instruction if the first fetch result is a virtual address of the second fetch instruction.
Further, a determining module 1302 is configured to: under the condition that the first access instruction carries a preset identifier, determining that the first access result is a virtual address of the second access instruction; or under the condition that the first fetch instruction does not carry the preset identification, determining that the first fetch result is not the virtual address of the second fetch instruction.
Further, the device also comprises an identification module for: in the program compiling stage, if the first fetch instruction is determined to be the fetch instruction for fetching the address of the second fetch instruction, the preset identifier is added to the first fetch instruction.
Further, a determining module 1302 is configured to: under the condition that the program counter of the first fetch instruction is the same as any program counter in the history table, determining that the first fetch result is the virtual address of the second fetch instruction; or under the condition that the program counter of the first fetch instruction is different from each program counter in the history table, determining that the first fetch result is not the virtual address of the second fetch instruction; the program counter stores a first history access instruction in the history table, the access result of the first history access instruction is a virtual address of a second history access instruction, and the second history access instruction is a subsequent access instruction of the first history access instruction.
Further, the method also comprises a generation module for recording a program counter of the first history fetch instruction to generate a history table when the fetch result of the first history fetch instruction is the virtual address of the second history fetch instruction.
Further, the access system of the processor comprises a prediction component, the prediction component is positioned behind the data cache, and the prediction component predicts that the first fetch result is the virtual address of the second fetch instruction under the condition that the program counter of the first fetch instruction is identical to any program counter in the history table; or the prediction unit predicts that the first fetch result is not the virtual address of the second fetch instruction in the case that the program counter of the first fetch instruction is determined to be different from each program counter in the history table.
Further, a first obtaining module 1301 is configured to: the access instruction transmitting queue transmits a first access instruction; the fixed-point register file and the floating-point register file provide source operands required by the first fetch instruction; the address generating part calculates and obtains the virtual address of the first fetch instruction according to the source operand; the data translation backup buffer memory translates the virtual address of the first fetch instruction into a first physical address corresponding to the first fetch instruction; extracting a first label to be compared corresponding to a first fetch instruction from a first physical address; the tag comparison part compares a first tag to be compared with the tag corresponding to each path of cache in the data cache, and determines first hit path information corresponding to a first fetch instruction; the first fetch result is read from the data storage array of the data cache based on the first hit way information.
Further, the second obtaining module 1303 is configured to: a data translation backup buffer memory for translating the first fetch result into a second physical address corresponding to the second fetch instruction; extracting a second label to be compared corresponding to a second fetch instruction from a second physical address; the tag comparison part compares a second tag to be compared with the tag corresponding to each path of cache in the data cache, and determines second hit path information corresponding to a second fetch instruction; and reading a second fetch result from the data storage array of the data cache based on the second hit way information.
In the embodiment of the disclosure, when the first fetch result is the virtual address of the second fetch instruction, the data cache can be directly accessed based on the first fetch result to obtain the second fetch result of the second fetch instruction, so that the processes of transmitting, reading the register file, calculating the virtual address and the like related to the second fetch instruction are optimized, and the use delay of the fetch instruction of the main pipeline of the processor is greatly reduced.
In order to implement the above embodiment, an electronic device 1400 is further provided according to an embodiment of the present application, as shown in fig. 14, the electronic device 1400 includes: the processor 1401 and the memory 1402 communicatively coupled to the processors, the memory 1402 storing instructions executable by at least one processor, the instructions being executed by the at least one processor 1401 to implement the method of executing the fetch instructions as shown in the above-described embodiments.
In order to achieve the above embodiments, the embodiments of the present application also provide a non-transitory computer-readable storage medium storing computer instructions for causing a computer to implement the execution method of the fetch instructions as shown in the above embodiments.
In order to implement the above embodiments, the embodiments of the present application further provide a computer program product, including a computer program, which when executed by a processor implements the execution method of the fetch instruction as shown in the above embodiments.
In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
While embodiments of the present application have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the application, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the application.
Claims (11)
1. A method of executing a fetch instruction, comprising:
acquiring a first fetch result of a first fetch instruction;
Determining whether the first fetch result is a virtual address of a second fetch instruction, wherein the second fetch instruction is a subsequent fetch instruction of the first fetch instruction;
And accessing a data cache based on the first fetch result to acquire a second fetch result of the second fetch instruction under the condition that the first fetch result is a virtual address of the second fetch instruction.
2. The method of claim 1, wherein the determining whether the first fetch result is a virtual address of a second fetch instruction comprises:
Under the condition that the first access instruction carries a preset identifier, determining that the first access result is a virtual address of the second access instruction; or alternatively
And under the condition that the first fetch instruction does not carry the preset identifier, determining that the first fetch result is not the virtual address of the second fetch instruction.
3. The method as recited in claim 2, further comprising:
and in a program compiling stage, if the first fetch instruction is determined to be the fetch instruction for fetching the address of the second fetch instruction, adding the preset identifier into the first fetch instruction.
4. The method of claim 1, wherein the determining whether the first fetch result is a virtual address of a second fetch instruction comprises:
Determining that the first fetch result is a virtual address of the second fetch instruction under the condition that a program counter of the first fetch instruction is the same as any program counter in a history table; or alternatively
Determining that the first fetch result is not a virtual address of the second fetch instruction if the program counter of the first fetch instruction is different from each program counter in the history table;
The history table stores a program counter of a first history access instruction, the access result of the first history access instruction is a virtual address of a second history access instruction, and the second history access instruction is a subsequent access instruction of the first history access instruction.
5. The method of claim 4, further comprising, prior to said determining whether said first fetch result is a virtual address of a second fetch instruction:
And under the condition that the fetch result of the first historical fetch instruction is the virtual address of the second historical fetch instruction, recording a program counter of the first historical fetch instruction to generate the history table.
6. The method of claim 5, wherein the memory access system of the processor includes a prediction component, the prediction component located after the data cache, the determining whether the first fetch result is a virtual address of a second fetch instruction, comprising:
The prediction unit predicts that the first fetch result is a virtual address of the second fetch instruction when it is determined that the program counter of the first fetch instruction is the same as any program counter in the history table; or alternatively
The prediction unit predicts that the first fetch result is not a virtual address of the second fetch instruction if it is determined that the program counter of the first fetch instruction is different from each program counter in the history table.
7. The method of claim 1, wherein the fetching the first fetch result of the first fetch instruction comprises:
the access instruction transmitting queue transmits the first fetch instruction;
the fixed point register file and the floating point register file provide source operands required by the first fetch instruction;
The address generating part calculates and obtains the virtual address of the first fetch instruction according to the source operand;
a data translation backup buffer memory translates a virtual address of the first fetch instruction into a first physical address corresponding to the first fetch instruction;
Extracting a first to-be-compared tag corresponding to the first fetch instruction from the first physical address;
The tag comparison part compares the first tag to be compared with the tag corresponding to each path of cache in the data cache, and determines first hit path information corresponding to the first fetch instruction;
And reading the first fetch result from a data storage array of a data cache based on the first hit way information.
8. The method of claim 7, wherein accessing a data cache based on the first fetch result to fetch a second fetch result of the second fetch instruction comprises:
the data translation backup buffer memory translates the first fetch result into a second physical address corresponding to the second fetch instruction;
Extracting a second label to be compared corresponding to the second fetch instruction from the second physical address;
the tag comparison part compares the second tag to be compared with the tag corresponding to each path of cache in the data cache, and determines second hit path information corresponding to the second fetch instruction;
and reading the second fetch result from the data storage array of the data cache based on the second hit way information.
9. An execution device for a fetch instruction, comprising:
the first acquisition module is used for acquiring a first fetch result of the first fetch instruction;
The determining module is used for determining whether the first fetch result is a virtual address of a second fetch instruction, wherein the second fetch instruction is a subsequent fetch instruction of the first fetch instruction;
And the second acquisition module is used for accessing the data cache based on the first access result to acquire the second access result of the second access instruction under the condition that the first access result is the virtual address of the second access instruction.
10. An electronic device, comprising:
At least one processor; and
A memory communicatively coupled to the at least one processor; wherein,
The memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-8.
11. A non-transitory computer readable storage medium storing computer instructions for causing the computer to perform the method of any one of claims 1-8.
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