CN117971718A - Cache replacement method and device for multi-core processor - Google Patents

Abstract

The application provides a cache replacement method and device for a multi-core processor, and relates to the technical field of processors. Sending a first access request to a first-level private cache contained in a multi-level cache system, and determining a first hit state of the first access request in the first-level private cache; if the first hit state indicates that the first access request is not hit in the first-level private cache, generating first replacement information corresponding to the first-level private cache, wherein the first replacement information comprises first path information and first address information corresponding to a first data block to be replaced in the first-level private cache; generating a second access request sent to the second-level shared cache based on the first replacement information; and sending the second access request to the second-level shared cache, acquiring the return data of the second-level shared cache, and completing the cache replacement of the first-level private cache based on the return data. The application increases the residence time of the first-level private cache block on the processor chip and improves the utilization rate of the on-chip storage capacity of the processor.

Description

Cache replacement method and device for multi-core processor

Technical Field

The present application relates to the field of processor technologies, and in particular, to a cache replacement method and apparatus for a multi-core processor.

Background

The rapid development of semiconductor technology has led to an increasing speed and integration of microprocessors, increasing numbers and types of transistor resources that Processor designers can utilize to implement chips, multi-Core processors (Multi-Core processors) being the direction of development of high performance Processor designs, and the trend being an increasing number of Processor cores integrated on-chip. Along with the rapid increase of the design scale and complexity of the processor, how to efficiently realize multi-core Cache consistency (Cache Coherence), and the Cache consistency is maintained, so that precious Cache resources on a chip can be more effectively used, the utilization rate of storage resources is improved, and the method is an important problem of general attention and research in the current academia and industry.

Disclosure of Invention

The present application aims to solve at least one of the technical problems in the related art to some extent.

To this end, an object of the present application is to propose a cache replacement method for a multi-core processor, comprising: sending a first access request to a first-level private cache contained in the multi-level cache system, and determining a first hit state of the first access request in the first-level private cache; responding to the first hit state to indicate that the first access request is not hit in the first-level private cache, and generating first replacement information corresponding to the first-level private cache, wherein the first replacement information comprises first path information and first address information corresponding to a first data block to be replaced in the first-level private cache; generating a second access request sent to a second-level shared cache based on the first replacement information, wherein the second-level shared cache is an adjacent lower-level cache of the first-level private cache; and sending the second access request to the second-level shared cache, acquiring the return data of the second-level shared cache, and completing the cache replacement of the first-level private cache based on the return data.

A second object of the present application is to provide a cache replacement apparatus for a multi-core processor.

A third object of the present application is to propose an electronic device.

A fourth object of the present application is to propose a non-transitory computer readable storage medium.

A fifth object of the application is to propose a computer programme product.

To achieve the above objective, an embodiment of a first aspect of the present application provides a cache replacement method for a multi-core processor, including: sending a first access request to a first-level private cache contained in the multi-level cache system, and determining a first hit state of the first access request in the first-level private cache; responding to the first hit state to indicate that the first access request is not hit in the first-level private cache, and generating first replacement information corresponding to the first-level private cache, wherein the first replacement information comprises first path information and first address information corresponding to a first data block to be replaced in the first-level private cache; generating a second access request sent to a second-level shared cache based on the first replacement information, wherein the second-level shared cache is an adjacent lower-level cache of the first-level private cache; and sending the second access request to the second-level shared cache, acquiring the return data of the second-level shared cache, and completing the cache replacement of the first-level private cache based on the return data.

According to one embodiment of the present application, generating first replacement information corresponding to a first-level private cache includes: and generating first replacement information corresponding to the first-level private cache based on a preset replacement strategy.

According to one embodiment of the application, determining a first hit status of a first access request in a first level private cache comprises: and determining that the first hit state of the first access request in the first-level private cache is an access miss in response to the first target data block to be accessed by the first access request not being present in the first-level private cache or the first target data block being in an invalid state.

According to one embodiment of the present application, sending a second access request to a secondary shared cache, obtaining return data of the secondary shared cache, includes: sending the second access request to the second-level shared cache, and determining a second hit state of the second access request in the second-level shared cache; and responding to the second hit state to indicate that the second access request accesses the second-level shared cache, and acquiring the returned data of the second-level shared cache.

According to one embodiment of the present application, the cache replacement method of the multi-core processor further includes: responding to the second hit state to indicate that the second access request is not hit in the second-level shared cache, and acquiring a plurality of candidate second replacement information corresponding to the second-level shared cache based on a preset replacement strategy; sending a third access request to the lower storage system and acquiring return data returned from the lower storage system; and combining the first replacement information and a plurality of candidate second replacement information to perform cache replacement on the second-level shared cache.

According to one embodiment of the present application, performing cache replacement on a secondary shared cache in combination with first replacement information and a plurality of candidate second replacement information includes: acquiring first address information contained in the first replacement information, and acquiring candidate second address information contained in each candidate second replacement information in the plurality of candidate second replacement information; comparing the first address information with each candidate second address information, and judging whether the candidate second address information which is the same as the first address information exists or not; if the candidate second address information which is the same as the first address information exists, carrying out cache replacement on a second data block corresponding to the same candidate second address information based on the returned data; and if the candidate second address information which is the same as the first address information does not exist, performing cache replacement on the second data block corresponding to one candidate second address information in the plurality of candidate second address information based on the returned data.

According to one embodiment of the present application, a cache replacement of a first-level private cache is completed based on returned data, including: recording first replacement information in a cache directory corresponding to the second-level shared cache; and carrying out cache replacement on the first data block corresponding to the first replacement information based on the returned data.

According to one embodiment of the present application, recording first replacement information in a cache directory corresponding to a second level shared cache includes: judging whether a directory entry empty path exists in the cache directory; if the cache directory has a directory entry empty path, recording first replacement information in the directory entry empty path; if the cache directory does not have a directory entry empty path, determining a directory entry to be replaced from the cache directory, and recording first replacement information in the directory entry to be replaced.

According to one embodiment of the application, determining a directory entry to be replaced from a cache directory includes: based on a preset replacement strategy, acquiring a plurality of candidate directory entry information corresponding to the cache directory; acquiring first address information contained in the first replacement information, and acquiring candidate directory entry address information contained in each of a plurality of candidate directory entry information; comparing the first address information with each candidate directory entry address information, and judging whether the candidate directory entry address information which is the same as the first address information exists or not; if the candidate directory entry address information which is the same as the first address information exists, determining that the directory entry corresponding to the same candidate directory entry address information is the directory entry to be replaced; if the candidate directory entry address information which is the same as the first address information does not exist, determining that the directory entry corresponding to one of the candidate directory entry address information in the plurality of candidate directory entry information is the directory entry to be replaced.

According to one embodiment of the application, determining a second hit status of a second access request in the second level shared cache includes: responding to the second target data block to be accessed by the second access request to exist in the second-level shared cache and the second target data block is in a valid state, and determining that a second hit state of the second access request in the second-level shared cache is an access hit; and determining that a second hit state of the second access request in the second-level shared cache is an access miss in response to the second target data block to be accessed by the second access request not being present in the second-level shared cache or the second target data block being in an invalid state.

According to one embodiment of the application, the preset replacement policies include, but are not limited to, random replacement policies, least recently used replacement policies, least frequently used replacement policies, and first in first out replacement policies.

To achieve the above object, an embodiment of a second aspect of the present application provides a cache replacement apparatus for a multi-core processor, including: the sending module is used for sending a first access request to a first-level private cache contained in the multi-level cache system and determining a first hit state of the first access request in the first-level private cache; the first generation module is used for responding to the first hit state to indicate that the first access request is in access miss in the first-level private cache, and generating first replacement information corresponding to the first-level private cache, wherein the first replacement information comprises first path information and first address information corresponding to a first data block to be replaced in the first-level private cache; the second generation module is used for generating a second access request sent to the second-level shared cache based on the first replacement information, wherein the second-level shared cache is an adjacent lower-layer cache of the first-level private cache; and the replacement module is used for sending the second access request to the second-level shared cache, acquiring the return data of the second-level shared cache, and completing the cache replacement of the first-level private cache based on the return data.

According to one embodiment of the application, the first generation module is further configured to: and generating first replacement information corresponding to the first-level private cache based on a preset replacement strategy.

According to one embodiment of the application, the transmitting module is further configured to: and determining that the first hit state of the first access request in the first-level private cache is an access miss in response to the first target data block to be accessed by the first access request not being present in the first-level private cache or the first target data block being in an invalid state.

According to one embodiment of the application, the replacement module is further configured to: sending the second access request to the second-level shared cache, and determining a second hit state of the second access request in the second-level shared cache; and responding to the second hit state to indicate that the second access request accesses the second-level shared cache, and acquiring the returned data of the second-level shared cache.

According to one embodiment of the application, the replacement module is further configured to: responding to the second hit state to indicate that the second access request is not hit in the second-level shared cache, and acquiring a plurality of candidate second replacement information corresponding to the second-level shared cache based on a preset replacement strategy; sending a third access request to the lower storage system and acquiring return data returned from the lower storage system; and combining the first replacement information and a plurality of candidate second replacement information to perform cache replacement on the second-level shared cache.

According to one embodiment of the application, the replacement module is further configured to: acquiring first address information contained in the first replacement information, and acquiring candidate second address information contained in each candidate second replacement information in the plurality of candidate second replacement information; comparing the first address information with each candidate second address information, and judging whether the candidate second address information which is the same as the first address information exists or not; if the candidate second address information which is the same as the first address information exists, carrying out cache replacement on a second data block corresponding to the same candidate second address information based on the returned data; and if the candidate second address information which is the same as the first address information does not exist, performing cache replacement on the second data block corresponding to one candidate second address information in the plurality of candidate second address information based on the returned data.

According to one embodiment of the application, the replacement module is further configured to: recording first replacement information in a cache directory corresponding to the second-level shared cache; and carrying out cache replacement on the first data block corresponding to the first replacement information based on the returned data.

According to one embodiment of the application, the replacement module is further configured to: judging whether a directory entry empty path exists in the cache directory; if the cache directory has a directory entry empty path, recording first replacement information in the directory entry empty path; if the cache directory does not have a directory entry empty path, determining a directory entry to be replaced from the cache directory, and recording first replacement information in the directory entry to be replaced.

According to one embodiment of the application, the replacement module is further configured to: based on a preset replacement strategy, acquiring a plurality of candidate directory entry information corresponding to the cache directory; acquiring first address information contained in the first replacement information, and acquiring candidate directory entry address information contained in each of a plurality of candidate directory entry information; comparing the first address information with each candidate directory entry address information, and judging whether the candidate directory entry address information which is the same as the first address information exists or not; if the candidate directory entry address information which is the same as the first address information exists, determining that the directory entry corresponding to the same candidate directory entry address information is the directory entry to be replaced; if the candidate directory entry address information which is the same as the first address information does not exist, determining that the directory entry corresponding to one of the candidate directory entry address information in the plurality of candidate directory entry information is the directory entry to be replaced.

According to one embodiment of the application, the replacement module is further configured to: responding to the second target data block to be accessed by the second access request to exist in the second-level shared cache and the second target data block is in a valid state, and determining that a second hit state of the second access request in the second-level shared cache is an access hit; and determining that a second hit state of the second access request in the second-level shared cache is an access miss in response to the second target data block to be accessed by the second access request not being present in the second-level shared cache or the second target data block being in an invalid state.

According to one embodiment of the application, the preset replacement policies include, but are not limited to, random replacement policies, least recently used replacement policies, least frequently used replacement policies, and first in first out replacement policies.

To achieve the above object, an embodiment of a third aspect of the present application provides an electronic device, including: at least one processor; and a memory communicatively coupled to the at least one processor; the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to implement a cache replacement method of a multi-core processor according to an embodiment of the first aspect of the present application.

To achieve the above object, an embodiment of a fourth aspect of the present application provides a non-transitory computer readable storage medium storing computer instructions for implementing a cache replacement method of a multi-core processor according to the embodiment of the first aspect of the present application.

To achieve the above object, an embodiment of a fifth aspect of the present application provides a computer program product, including a computer program, which when executed by a processor implements a cache replacement method of a multi-core processor according to the embodiment of the first aspect of the present application.

The application at least realizes the following beneficial effects: the application aims to reduce the occurrence of replacement of upper access failure, and the occurrence of the replacement of the first-level private cache in different ways (ways) for maintaining the inclusion relation of the directory or the second-level shared cache to the first-level private cache, so that the extra replacement of different ways of the same cache line is caused, thereby increasing the retention time of the first-level private cache block on a processor chip and improving the utilization rate of the storage capacity of the processor chip.

Drawings

The foregoing and/or additional aspects and advantages of the application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a schematic diagram illustrating an exemplary implementation of a cache replacement method for a multi-core processor, according to one embodiment of the present application.

FIG. 2 is a schematic diagram of a multi-level cache system according to one embodiment of the present application.

Fig. 3 is a schematic diagram of a TAG of a first level private cache, according to an embodiment of the present application.

FIG. 4 is a schematic diagram of a TAG of a secondary shared cache, according to one embodiment of the application.

FIG. 5 is a schematic diagram of a multi-way group connection directory according to one embodiment of the application.

FIG. 6 is a schematic diagram illustrating an exemplary implementation of a cache replacement method for a multi-core processor, according to one embodiment of the application.

FIG. 7 is a schematic diagram illustrating an exemplary implementation of a cache replacement method for a multi-core processor, according to one embodiment of the application.

FIG. 8 is a schematic diagram of a cache replacement apparatus for a multi-core processor according to one embodiment of the application.

Fig. 9 is a schematic diagram of an electronic device according to an embodiment of the application.

Detailed Description

Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present application and should not be construed as limiting the application.

It should be noted that, in the present disclosure, all the actions of obtaining information and rights and providing services are performed under the premise of conforming to the corresponding data protection rule policy of the location and obtaining the authorization given by the owner of the corresponding device, which all conform to the rules of the related laws and regulations and do not violate the public welfare.

In a multi-core processor architecture, snoop (Snoop) and Directory (Directory) protocols are two common implementations of cache coherency protocols. The directory coherence protocol has good expansibility and can be expanded to more processor cores, such as 64 cores, 128 cores, 256 cores and the like, so that the directory coherence protocol is a coherence protocol which is widely applied in the current multi-core processor. The directory controller is a core component of a directory coherency protocol, and maintains multi-core Cache coherency by distributing copies of directory record Cache (Cache) blocks among processor cores.

And the TAG directory is copied, and the TAG (TAG) domain of the upper level Cache (Cache) is copied to maintain consistency, so that consistency maintenance information needs to be broadcasted, bandwidth is consumed, and the expandability is poor. Sparse directories are the way in which independent directory structures are employed to record the distribution of copies of data among processor cores. From the aspect of expandability, a multi-core processor generally adopts a Sparse Directory (spark Directory), the Sparse Directory adopts a Directory structure of group association, and each Directory entry stores information of an upper-layer Cache. The sparse directory has inter-group conflict, directory information of some upper-layer Cache blocks which are originally used can be replaced, and correspondingly, the upper-layer Cache blocks corresponding to the replaced directory entries are required to be invalidated.

Inclusive (inclusive), non-Inclusive (Non-inclusive), and Exclusive (Non-inclusive) architecture caches are three ways of organizing the Cache storage hierarchy. The Inclusive Cache levels maintain inclusion relations among Cache levels, so that Cache block data of the upper storage level exist in the lower storage level, the Cache blocks in the upper storage level can be recorded in which caches of the upper storage level and states through the maintenance directory in the lower storage level, and when the lower storage level is replaced, the Cache blocks in the upper storage level also need to be replaced for maintaining the inclusion relations. The Cache hierarchy (Non-Inclusive and Exclusive) containing the relation is not maintained, the maintenance of the consistency of the upper-layer caches also needs to maintain a directory in the lower-layer caches, the directory records which Cache blocks exist and are in the state of the upper-layer caches, and when the empty items of the directory are not replaced enough, the Cache blocks recorded by the replacement directory items in the upper-layer storage system also need to be replaced for maintaining the directory.

Because the Cache block is replaced (replaced) due to the Cache access failure (CACHE MISS) of the upper-layer Cache, the replacement of the upper-layer Cache block caused by the replacement of the directory with the directory generated in the lower layer is the maintenance of the directory record item, or the replacement of the Cache block (replaced) due to the Cache access failure of the lower layer Inclusive Cache is the maintenance of the inclusion relationship, which is the process of distributed independent processing, the replacement of the upper-layer Cache CACHE MISS is caused, the replacement of the upper-layer Cache is caused for the maintenance of the directory or the inclusion relationship of the lower-layer Cache to the upper-layer Cache, and the replacement (replacement) is caused to drop one Cache block of the upper-layer Cache in different ways (ways) of the same Cache line of the upper-layer, so that the retention time of the upper-layer Cache block is reduced, and the Cache capacity is not utilized more effectively.

FIG. 1 is a schematic diagram of an exemplary embodiment of a cache replacement method for a multi-core processor according to the present application, as shown in FIG. 1, including the following steps:

S101, sending a first access request to a first-level private cache contained in the multi-level cache system, and determining a first hit state of the first access request in the first-level private cache.

FIG. 2 is a schematic diagram of a multi-level Cache system according to the present application, as shown in FIG. 2, where the multi-core processor includes 128 processor cores, a total of 64MB capacity of secondary Cache (L2 Cache), 256MB capacity of tertiary Cache (L3 Cache), 512 bits per Cache line, and 40 bits of physical address are taken as an example.

The architecture of the multi-level Cache system is shown in fig. 2, and as shown in fig. 2, the L2 Cache is an upper-level Cache, and the L3 Cache is a lower-level Cache, that is, the L2 Cache may be used as a first-level private Cache, and the L3 Cache may be used as a second-level shared Cache.

It should be noted that, in the present application, the first-level private Cache is not limited to the L2 Cache, and the second-level shared Cache is not limited to the L3 Cache. Optionally, the first-level private Cache may be any one of a first-level Cache (L1 Cache), a second-level Cache, and a last-level Cache (LLC, last Level Cache) up to the last-level Cache of the processor; the second-level shared Cache can be any one of a second-level Cache, a third-level Cache and a last-level Cache (LLC, last Level Cache) of the processor, and the second-level shared Cache is an adjacent lower-level Cache of the first-level private Cache.

Each level of Cache comprises a Cache TAG (TAG) and CACHE DATA (data).

In the application, when data is required to be acquired from the first-level private cache, a first access request needs to be sent to the first-level private cache contained in the multi-level cache system.

If the first target data block to be accessed by the first access request does not exist in the first-level private cache or the first target data block is in an invalid state, determining that the first hit state of the first access request in the first-level private cache is an access miss.

S102, responding to the first hit state to indicate that the first access request is not hit in the first-level private cache, and generating first replacement information corresponding to the first-level private cache, wherein the first replacement information comprises first path information and first address information corresponding to a first data block to be replaced in the first-level private cache.

First, the first level private cache will be described.

The first-level private cache is in an 8-way group connection structure, and comprises a first-level private cache TAG (TAG) and a first-level private cache Data (Data).

The TAG of the first level private cache is shown in fig. 3, and includes: an address Tag of the primary private cache, a valid bit (for indicating whether the Tag entry is valid), an identification bit (for recording whether the primary private cache block is written with data, i.e., dirty), and a status bit (indicating the status of the corresponding cache block in the primary private cache). The status bit is SHD, which indicates that the corresponding cache block is in a Shared (SHD) state in the first-level private cache, and the status bit is EXC, which indicates that the corresponding block is in an Exclusive (EXC) state in the first-level private cache.

In the application, if the first hit state indicates that the first access request is not hit in the first-level private cache, first replacement information corresponding to the first-level private cache is generated. The first replacement information comprises first path information and first address information corresponding to a first data block to be replaced in the first-level private cache.

Wherein, when generating the first replacement information, the first replacement information corresponding to the first private cache may be generated based on a preset replacement policy (the preset replacement policy includes, but is not limited to, a Random replacement policy (Random), a least recently Used replacement policy (LEAST RECENTLY Used, LRU), a least frequently Used replacement policy (Least Frequently Used, LFU), and a first-in first-Out replacement policy (FIRST IN FIRST Out, FIFO), any of which may be selected when generating the first replacement information.

And S103, generating a second access request sent to a second-level shared cache based on the first replacement information, wherein the second-level shared cache is an adjacent lower-layer cache of the first-level private cache.

The second level shared cache is first described below.

The secondary shared buffer is in an 8-way group connection structure, and comprises a secondary shared buffer Tag and a secondary shared buffer Data. The Tag of the second-level shared cache is shown in fig. 4, and includes an address Tag, a valid bit and an identification bit of the second-level shared cache. When the identification bit is 1, the Cache block is written with dirty data, and when replacement occurs, the Cache block needs to be written to an underlying storage system.

In the application, a second access request sent to a secondary shared cache is generated based on the first replacement information. The first replacement information comprises first path information and first address information corresponding to a first data block to be replaced in the first-level private cache.

S104, sending the second access request to the second-level shared cache, acquiring return data of the second-level shared cache, and completing cache replacement of the first-level private cache based on the return data.

The corresponding cache directory of the secondary shared cache is described below. Taking a multi-way group connected directory (e.g., an 8-way group connected) as an example. Cache consistency for Inclusive (inclusive), non-Inclusive (Non-inclusive), and Exclusive (Non-inclusive) relationships may be maintained with a directory.

Wherein each row of the directory contains directory information as shown in table 1, and a schematic diagram of the multiple-group connected directory is shown in fig. 5.

A valid bit for indicating whether the directory entry is valid.

The upper layer Cache block address represents the block address of the first-level private Cache of the directory entry record.

The upper layer Cache block status bit indicates the status of the corresponding Cache block in the first-level private Cache, and the local domain is Valid only when the Valid bit is Valid.

The directory bit vector indicates which level of private caches the corresponding Cache block exists in, and the local domain is Valid only when the Valid bit is Valid.

Table 1 directory information contained in each row of the directory

Wherein, the Valid bit is represented by 1 for Valid (Valid) and 0 for Invalid (INV).

The first level private-cache state bits include:

CLEAN (CLEAN): indicating that the corresponding block is in a Shared (SHD) state in the primary private cache.

DIRTY (DIRTY): indicating that the corresponding block is in an Exclusive (EXC) state in the primary private Cache, or in a coherency protocol supporting an MOESI (Modified, own, exclusive, shared, or invalid) state, there is an Owner in the primary private Cache that owns the latest data of the Cache block.

Directory bit vector: recording in which level one private caches the Cache block exists by means of a directory bit vector. Only if the state of the directory entry is Valid, the directory bit vector of the corresponding entry is meaningful. The directory bit vector records in which primary private caches have the backup of the block, and a corresponding bit of 1 for the directory bit vector generally indicates that the corresponding primary private cache has the backup of the block, and a corresponding bit of 0 indicates that the corresponding primary private cache does not have the backup of the block.

The directory bit vector can be recorded by adopting a coarse vector directory and a compressed directory, and also can be recorded by adopting an all-bit vector directory. For example, with an all-bit vector directory, … … 1111 indicates that the Cache block backup is owned in the primary private caches of processor cores No. 0, no.1, no.2, and No. 3.

Further comprises: the information used by the replacement algorithm when the directory lines are full, such as age information, frequency of use information, etc. used in the least recently used algorithm. Also included in the MOESI coherency protocol is an Owner node number that records which processor core's primary private cache is the Owner (own) of the block of data.

In the application, the condition that the first-level private Cache and the second-level shared Cache are in a maintenance containing relation is mainly introduced, if the first-level private Cache and the second-level shared Cache are in the maintenance containing relation, a second access request is sent to the second-level shared Cache, return data of the second-level shared Cache is obtained, and Cache replacement of the first-level private Cache and a Cache directory is completed based on the return data, so that if the replacement of the first-level private Cache and the replacement of a lower-level Cache directory entry or the block replacement of the first-level private Cache caused by the replacement of the second-level shared Cache are the same Cache line, the same line as a replacement path transferred by the first-level private Cache can be selected for replacement.

Further, a situation that the first-level private cache and the second-level shared cache are not in maintenance inclusion relationship may also occur, if the first-level private cache and the second-level shared cache are not in maintenance inclusion relationship, a second access request is sent to the second-level shared cache, return data of the second-level shared cache is obtained, and updating of the cache directory is completed based on the return data.

The embodiment of the application provides a cache replacement method of a multi-core processor, which comprises the following steps: sending a first access request to a first-level private cache contained in the multi-level cache system, and determining a first hit state of the first access request in the first-level private cache; responding to the first hit state to indicate that the first access request is not hit in the first-level private cache, and generating first replacement information corresponding to the first-level private cache, wherein the first replacement information comprises first path information and first address information corresponding to a first data block to be replaced in the first-level private cache; generating a second access request sent to a second-level shared cache based on the first replacement information, wherein the second-level shared cache is an adjacent lower-level cache of the first-level private cache; and sending the second access request to the second-level shared cache, acquiring the return data of the second-level shared cache, and completing the cache replacement of the first-level private cache based on the return data. The application aims to reduce the occurrence of replacement of upper access failure, and the occurrence of the replacement of the first-level private cache in different ways (ways) for maintaining the inclusion relation of the directory or the second-level shared cache to the first-level private cache, so that the extra replacement of different ways of the same cache line is caused, thereby increasing the retention time of the first-level private cache block on a processor chip and improving the utilization rate of the storage capacity of the processor chip.

Furthermore, in the present application, before the multi-level cache system starts to be used, the multi-level cache system needs to be initialized, that is, the valid positions of each line in the cache directory corresponding to the second-level shared cache need to be invalidated; and the valid bit of each line of labels in each path of private cache is invalid; and the valid bit of each line of labels in each path of the second-level shared cache is invalid, so that all cache data are ensured to be invalid when the system is started, and the existence of dirty data or error data is avoided. Therefore, a clean state can be established before the system normally operates, and the consistency of data is ensured.

FIG. 6 is a schematic diagram of an exemplary embodiment of a cache replacement method for a multi-core processor according to the present application, as shown in FIG. 6, including the following steps:

s601, a first access request is sent to a first-level private cache contained in the multi-level cache system, and a first hit state of the first access request in the first-level private cache is determined.

S602, if the first hit state indicates that the first access request is not hit in the first-level private cache, first replacement information corresponding to the first-level private cache is generated, wherein the first replacement information comprises first path information and first address information corresponding to a first data block to be replaced in the first-level private cache.

And S603, generating a second access request sent to the second-level shared cache based on the first replacement information, wherein the first-level private cache and the second-level shared cache are in maintenance containing relation, and the second-level shared cache is an adjacent lower-layer cache of the first-level private cache.

The specific description of steps S601 to S603 may refer to the specific description of the relevant parts in the above embodiments, and will not be repeated here.

S604, sending the second access request to the second-level shared cache, and determining a second hit state of the second access request in the second-level shared cache.

Specifically, if the second target data block to be accessed by the second access request exists in the second-level shared cache and the second target data block is in a valid state, determining that a second hit state of the second access request in the second-level shared cache is an access hit.

S605, responding to the second hit state to indicate that the second access request accesses the hit in the second-level shared cache, and acquiring the return data of the second-level shared cache.

S606, completing the buffer replacement of the first-level private buffer based on the returned data.

And recording the first replacement information in a cache directory corresponding to the second-level shared cache, and carrying out cache replacement on the first data block corresponding to the first replacement information based on the returned data.

Specifically, when the first replacement information is recorded in the cache directory corresponding to the second-level shared cache, it is first required to determine whether the cache directory has a directory entry empty path.

As a possible case, if the cache directory has a directory entry empty way, the first replacement information is directly recorded in the directory entry empty way.

As another possible case, if the cache directory does not have a directory entry empty way, determining a directory entry to be replaced from the cache directory, and recording the first replacement information in the directory entry to be replaced. Wherein determining the directory entry to be replaced from the cache directory comprises: based on a preset replacement strategy, acquiring a plurality of candidate directory entry information corresponding to the cache directory; acquiring first address information contained in the first replacement information, and acquiring candidate directory entry address information contained in each of a plurality of candidate directory entry information; comparing the first address information with each candidate directory entry address information, and judging whether the candidate directory entry address information which is the same as the first address information exists or not; if the candidate directory entry address information which is the same as the first address information exists, determining that the directory entry corresponding to the same candidate directory entry address information is the directory entry to be replaced; if the candidate directory entry address information which is the same as the first address information does not exist, determining that the directory entry corresponding to one of the candidate directory entry address information in the plurality of candidate directory entry information is the directory entry to be replaced.

Among them, the preset replacement policies include, but are not limited to, random replacement policies (Random), least recently Used replacement policies (LEAST RECENTLY Used, LRU), least frequently Used replacement policies (Least Frequently Used, LFU), and first-in first-Out replacement policies (FIRST IN FIRST Out, FIFO), where at least two of them may be selected.

It should be noted that the preset replacement strategy is only shown by way of example, and does not limit the scope of the present application.

The embodiment of the application mainly introduces the condition that the second access request is accessed to hit in the second-level shared cache so as to realize invalidating access of the first-level private cache. The multi-level cache system can be configured with caches of different levels according to needs and expanded according to the needs of the system, when the secondary shared cache is hit directly, return data of the secondary shared cache is obtained, directory record and cache replacement of the primary private cache are performed by directly comparing first replacement information, cache resources are effectively utilized, the cache hit rate is improved, the retention time of the primary private cache block on a processor chip is increased, the on-chip storage capacity utilization rate of the processor is improved, and better user experience is provided.

FIG. 7 is a schematic diagram of an exemplary embodiment of a cache replacement method for a multi-core processor according to the present application, as shown in FIG. 7, including the following steps:

s701, a first access request is sent to a first-level private cache contained in a multi-level cache system, and a first hit state of the first access request in the first-level private cache is determined.

S702, if the first hit state indicates that the first access request is not hit in the first-level private cache, first replacement information corresponding to the first-level private cache is generated, wherein the first replacement information comprises first path information and first address information corresponding to a first data block to be replaced in the first-level private cache.

S703, generating a second access request sent to the second-level shared cache based on the first replacement information, wherein the first-level private cache and the second-level shared cache are in maintenance containing relation, and the second-level shared cache is an adjacent lower-layer cache of the first-level private cache.

The specific description of steps S701 to S703 may refer to the specific description of the relevant parts in the above embodiments, and will not be repeated here.

S704, sending the second access request to the second-level shared cache, and determining a second hit state of the second access request in the second-level shared cache.

Specifically, if the second target data block to be accessed by the second access request does not exist in the second-level shared cache, or the second target data block is in an invalid state, determining that the second hit state of the second access request in the second-level shared cache is an access miss.

And S705, responding to the second hit state to indicate that the second access request is not hit in the second-level shared cache, and acquiring a plurality of candidate second replacement information corresponding to the second-level shared cache based on a preset replacement strategy.

Among them, the preset replacement policies include, but are not limited to, random replacement policies (Random), least recently Used replacement policies (LEAST RECENTLY Used, LRU), least frequently Used replacement policies (Least Frequently Used, LFU), and first-in first-Out replacement policies (FIRST IN FIRST Out, FIFO), where at least two of them may be selected.

S706, sending a third access request to the lower storage system, and acquiring return data returned from the lower storage system.

And S707, combining the first replacement information and the plurality of candidate second replacement information to perform cache replacement on the secondary shared cache.

First address information contained in the first replacement information is acquired, and candidate second address information contained in each of a plurality of candidate second replacement information is acquired.

And comparing the first address information with each candidate second address information, and judging whether the candidate second address information which is the same as the first address information exists.

And if the candidate second address information which is the same as the first address information exists, performing cache replacement on a second data block corresponding to the same candidate second address information based on the returned data.

And if the candidate second address information which is the same as the first address information does not exist, performing cache replacement on the second data block corresponding to one candidate second address information in the plurality of candidate second address information based on the returned data.

S708, completing the cache replacement of the first-level private cache based on the returned data.

And acquiring returned data after the second-level shared cache is subjected to cache replacement, recording first replacement information in a cache directory corresponding to the second-level shared cache, and carrying out cache replacement on a first data block corresponding to the first replacement information based on the returned data.

Specifically, when the first replacement information is recorded in the cache directory corresponding to the second-level shared cache, it is first required to determine whether the cache directory has a directory entry empty path.

As a possible case, if the cache directory has a directory entry empty way, the first replacement information is directly recorded in the directory entry empty way.

As another possible case, if the cache directory does not have a directory entry empty way, determining a directory entry to be replaced from the cache directory, and recording the first replacement information in the directory entry to be replaced. Wherein determining the directory entry to be replaced from the cache directory comprises: based on a preset replacement strategy, acquiring a plurality of candidate directory entry information corresponding to the cache directory; acquiring first address information contained in the first replacement information, and acquiring candidate directory entry address information contained in each of a plurality of candidate directory entry information; comparing the first address information with each candidate directory entry address information, and judging whether the candidate directory entry address information which is the same as the first address information exists or not; if the candidate directory entry address information which is the same as the first address information exists, determining that the directory entry corresponding to the same candidate directory entry address information is the directory entry to be replaced; if the candidate directory entry address information which is the same as the first address information does not exist, determining that the directory entry corresponding to one of the candidate directory entry address information in the plurality of candidate directory entry information is the directory entry to be replaced. Among them, the preset replacement policies include, but are not limited to, at least two of Random replacement policies (Random), least recently Used replacement policies (LEAST RECENTLY Used, LRU), least frequently Used replacement policies (Least Frequently Used, LFU), and first-in first-Out replacement policies (FIRST IN FIRST Out, FIFO).

The embodiment of the application mainly introduces the condition that the second access request is not hit in the second-level shared cache, so as to realize invalidating access of the first-level private cache. The multi-level cache system can be configured with caches of different levels according to the needs of the system and expanded according to the needs of the system, when the second-level shared cache needs to be subjected to cache replacement, the first address information can be directly compared, the second-level shared cache can be subjected to cache replacement, the number of times of main memory access can be reduced, and the system performance is improved.

Fig. 8 is a schematic diagram of a cache replacement apparatus for a multi-core processor, as shown in fig. 8, where the cache replacement apparatus 800 for a multi-core processor includes a sending module 801, a first generating module 802, a second generating module 803, and a replacing module 804, where:

The sending module 801 is configured to send a first access request to a first-level private cache included in the multi-level cache system, and determine a first hit state of the first access request in the first-level private cache.

The first generation module 802 is configured to generate first replacement information corresponding to the first private cache if the first access request indicates that the first access request does not hit in the first private cache in response to the first hit status, where the first replacement information includes first way information and first address information corresponding to a first data block to be replaced in the first private cache.

And a second generating module 803, configured to generate, based on the first replacement information, a second access request sent to a second level shared cache, where the second level shared cache is an adjacent lower level cache of the first level private cache.

And the replacing module 804 is configured to send a second access request to the second-level shared cache, obtain return data of the second-level shared cache, and complete cache replacement of the first-level private cache based on the return data.

The device aims to reduce the occurrence of replacement of upper access failure, and generate additional replacement of the first-level private cache in different ways (ways) for maintaining the containing relation of the directory or the second-level shared cache to the first-level private cache, so that the time for the first-level private cache block to stay on a processor chip is increased, and the utilization rate of the on-chip storage capacity of the processor is improved.

Further, the first generating module 802 is further configured to: and generating first replacement information corresponding to the first-level private cache based on a preset replacement strategy.

Further, the sending module 801 is further configured to: and determining that the first hit state of the first access request in the first-level private cache is an access miss in response to the first target data block to be accessed by the first access request not being present in the first-level private cache or the first target data block being in an invalid state.

Further, the replacing module 804 is further configured to: sending the second access request to the second-level shared cache, and determining a second hit state of the second access request in the second-level shared cache; and responding to the second hit state to indicate that the second access request accesses the second-level shared cache, and acquiring the returned data of the second-level shared cache.

Further, the replacing module 804 is further configured to: responding to the second hit state to indicate that the second access request is not hit in the second-level shared cache, and acquiring a plurality of candidate second replacement information corresponding to the second-level shared cache based on a preset replacement strategy; sending a third access request to the lower storage system and acquiring return data returned from the lower storage system; and combining the first replacement information and a plurality of candidate second replacement information to perform cache replacement on the second-level shared cache.

Further, the replacing module 804 is further configured to: acquiring first address information contained in the first replacement information, and acquiring candidate second address information contained in each candidate second replacement information in the plurality of candidate second replacement information; comparing the first address information with each candidate second address information, and judging whether the candidate second address information which is the same as the first address information exists or not; if the candidate second address information which is the same as the first address information exists, carrying out cache replacement on a second data block corresponding to the same candidate second address information based on the returned data; and if the candidate second address information which is the same as the first address information does not exist, performing cache replacement on the second data block corresponding to one candidate second address information in the plurality of candidate second address information based on the returned data.

Further, the replacing module 804 is further configured to: recording first replacement information in a cache directory corresponding to the second-level shared cache; and carrying out cache replacement on the first data block corresponding to the first replacement information based on the returned data.

Further, the replacing module 804 is further configured to: judging whether a directory entry empty path exists in the cache directory; if the cache directory has a directory entry empty path, recording first replacement information in the directory entry empty path; if the cache directory does not have a directory entry empty path, determining a directory entry to be replaced from the cache directory, and recording first replacement information in the directory entry to be replaced.

Further, the replacing module 804 is further configured to: based on a preset replacement strategy, acquiring a plurality of candidate directory entry information corresponding to the cache directory; acquiring first address information contained in the first replacement information, and acquiring candidate directory entry address information contained in each of a plurality of candidate directory entry information; comparing the first address information with each candidate directory entry address information, and judging whether the candidate directory entry address information which is the same as the first address information exists or not; if the candidate directory entry address information which is the same as the first address information exists, determining that the directory entry corresponding to the same candidate directory entry address information is the directory entry to be replaced; if the candidate directory entry address information which is the same as the first address information does not exist, determining that the directory entry corresponding to one of the candidate directory entry address information in the plurality of candidate directory entry information is the directory entry to be replaced.

Further, the replacing module 804 is further configured to: responding to the second target data block to be accessed by the second access request to exist in the second-level shared cache and the second target data block is in a valid state, and determining that a second hit state of the second access request in the second-level shared cache is an access hit; and determining that a second hit state of the second access request in the second-level shared cache is an access miss in response to the second target data block to be accessed by the second access request not being present in the second-level shared cache or the second target data block being in an invalid state.

Further, the preset replacement policies appearing in the above modules include, but are not limited to, random replacement policies, least recently used replacement policies, least frequently used replacement policies, and first-in first-out replacement policies.

In order to implement the foregoing embodiments, an embodiment of the present application further proposes an electronic device 900, as shown in fig. 9, where the electronic device 900 includes: the processor 901 and a memory 902 communicatively connected to the processors, the memory 902 storing instructions executable by at least one processor, the instructions being executed by the at least one processor 901 to implement a cache replacement method for a multi-core processor as shown in the above embodiments.

In order to achieve the above embodiments, the embodiments of the present application also provide a non-transitory computer-readable storage medium storing computer instructions for causing a computer to implement a cache replacement method of a multi-core processor as shown in the above embodiments.

In order to implement the above embodiments, the embodiments of the present application further provide a computer program product, including a computer program, which when executed by a processor implements a cache replacement method of a multi-core processor as shown in the above embodiments.

In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present application.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.

While embodiments of the present application have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the application, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the application.

Claims (14)

1. A cache replacement method for a multi-core processor, comprising:

Sending a first access request to a first-level private cache contained in a multi-level cache system, and determining a first hit state of the first access request in the first-level private cache;

responding to the first hit state to indicate that the first access request is not hit in the first-level private cache, and generating first replacement information corresponding to the first-level private cache, wherein the first replacement information comprises first path information and first address information corresponding to a first data block to be replaced in the first-level private cache;

generating a second access request sent to a second-level shared cache based on the first replacement information, wherein the second-level shared cache is an adjacent lower-level cache of the first-level private cache;

And sending the second access request to the second-level shared cache, acquiring return data of the second-level shared cache, and completing cache replacement of the first-level private cache based on the return data.

2. The method of claim 1, wherein the generating the first replacement information corresponding to the first-level private cache comprises:

And generating first replacement information corresponding to the first-level private cache based on a preset replacement strategy.

3. The method of claim 2, wherein the determining a first hit status of the first access request in the level one private cache comprises:

And determining that the first hit state of the first access request in the first-level private cache is an access miss in response to the first target data block to be accessed by the first access request not being present in the first-level private cache or the first target data block being in an invalid state.

4. A method according to claim 1 or 3, wherein said sending the second access request to the secondary shared cache, obtaining return data of the secondary shared cache, comprises:

sending the second access request to the second-level shared cache, and determining a second hit state of the second access request in the second-level shared cache;

and responding to the second hit state to indicate that the second access request accesses the second-level shared cache, and acquiring the returned data of the second-level shared cache.

5. The method according to claim 4, further comprising:

Responding to the second hit state to indicate that the second access request is not hit in the second-level shared cache, and acquiring a plurality of candidate second replacement information corresponding to the second-level shared cache based on a preset replacement strategy;

Sending a third access request to a lower storage system and acquiring return data returned from the lower storage system;

And combining the first replacement information and the plurality of candidate second replacement information to perform cache replacement on the secondary shared cache.

6. The method of claim 5, wherein the cache replacement of the secondary shared cache in combination with the first replacement information and the plurality of candidate second replacement information comprises:

acquiring first address information contained in the first replacement information, and acquiring candidate second address information contained in each candidate second replacement information in the plurality of candidate second replacement information;

Comparing the first address information with each candidate second address information, and judging whether the candidate second address information identical to the first address information exists or not;

If the candidate second address information which is the same as the first address information exists, performing cache replacement on a second data block corresponding to the same candidate second address information based on the return data;

And if the candidate second address information which is the same as the first address information does not exist, performing cache replacement on a second data block corresponding to one candidate second address information in the plurality of candidate second address information based on the return data.

7. The method of claim 6, wherein the completing the cache replacement of the primary private cache based on the return data comprises:

recording the first replacement information in a cache directory corresponding to the second-level shared cache;

and carrying out cache replacement on the first data block corresponding to the first replacement information based on the returned data.

8. The method of claim 7, wherein the recording the first replacement information in the cache directory corresponding to the second level shared cache comprises:

Judging whether a directory entry empty path exists in the cache directory;

If the cache directory has a directory entry empty path, recording the first replacement information in the directory entry empty path;

and if the cache directory does not have a directory entry empty path, determining a directory entry to be replaced from the cache directory, and recording the first replacement information in the directory entry to be replaced.

9. The method of claim 8, wherein the determining a directory entry to replace from the cache directory comprises:

Based on a preset replacement strategy, acquiring a plurality of candidate directory entry information corresponding to the cache directory;

acquiring first address information contained in the first replacement information, and acquiring candidate directory entry address information contained in each of the plurality of candidate directory entry information;

Comparing the first address information with each candidate directory entry address information, and judging whether the candidate directory entry address information identical to the first address information exists or not;

if the candidate directory entry address information which is the same as the first address information exists, determining that the directory entry corresponding to the same candidate directory entry address information is the directory entry to be replaced;

If the candidate directory entry address information which is the same as the first address information does not exist, determining that the directory entry corresponding to one of the candidate directory entry address information in the plurality of candidate directory entry information is the directory entry to be replaced.

10. The method of claim 4, wherein the determining a second hit status of the second access request in the second level shared cache comprises:

Determining that the second hit state of the second access request in the second-level shared cache is an access hit in response to the second target data block to be accessed by the second access request being present in the second-level shared cache and the second target data block being in a valid state;

And determining that the second hit state of the second access request in the second-level shared cache is an access miss in response to the second target data block to be accessed by the second access request not being present in the second-level shared cache or the second target data block being in an invalid state.

11. The method of any one of claims 2, 5 or 9, wherein the preset replacement policy includes, but is not limited to, a random replacement policy, a least recently used replacement policy, a least frequently used replacement policy, and a first-in first-out replacement policy.

12. A cache replacement apparatus for a multi-core processor, comprising:

The sending module is used for sending a first access request to a first-level private cache contained in the multi-level cache system and determining a first hit state of the first access request in the first-level private cache;

the first generation module is used for responding to the first hit state to indicate that the first access request is not hit in the first-level private cache, and generating first replacement information corresponding to the first-level private cache, wherein the first replacement information comprises first path information and first address information corresponding to a first data block to be replaced in the first-level private cache;

The second generation module is used for generating a second access request sent to a second-level shared cache based on the first replacement information, wherein the second-level shared cache is an adjacent lower-layer cache of the first-level private cache;

and the replacement module is used for sending the second access request to the second-level shared cache, acquiring return data of the second-level shared cache, and completing cache replacement of the first-level private cache based on the return data.

13. An electronic device, comprising:

At least one processor; and

A memory communicatively coupled to the at least one processor; wherein,

The memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-11.

14. A non-transitory computer readable storage medium storing computer instructions for causing the computer to perform the method of any one of claims 1-11.