CN117971707A - Access processing method of system-level chip, system-level chip and electronic equipment - Google Patents

Abstract

The disclosure provides a system-level chip access processing method, a system-level chip and electronic equipment, wherein the system-level chip comprises a cache system and a plurality of IP modules; the cache system comprises a routing module, a plurality of cache controllers and a plurality of cache modules; any cache controller is configured to store data in a target memory address range in a memory through at least one cache module for one target IP module, wherein the data in the target memory address range is access data of the target IP module; after receiving an access request, the routing module determines a target address of the access request, and respectively matches the target address with a target memory address range corresponding to each cache controller to obtain a target cache controller; forwarding the access request to a target cache controller; and the target cache controller processes the access request according to the hit condition of the access request in the cache module corresponding to the target cache controller.

Description

Access processing method of system-level chip, system-level chip and electronic equipment

Technical Field

The disclosure relates to the technical field of cache, and in particular relates to a system-on-chip access processing method, a system-on-chip and electronic equipment.

Background

A System On Chip (SOC) refers to a System in which a plurality of IP blocks are integrated on a Chip. In a system on a chip, each IP module typically has a need to access off-chip memory. In order to improve the access efficiency, most IP modules use caches, i.e. caches, to access the data in the off-chip memory.

In the prior art, a Cache hit rate is low and access efficiency is low due to the fact that each IP module on the system-in-chip accesses by using the Cache. Therefore, a new system-on-chip access processing method is needed.

Disclosure of Invention

The invention aims to provide a system-on-chip access processing method, a system-on-chip and electronic equipment.

According to a first aspect of the present disclosure, there is provided a system-on-chip access processing method applied to a system-on-chip, where the system-on-chip includes a cache system and a plurality of IP modules; the cache system comprises a routing module, a plurality of cache controllers and a plurality of cache modules; any cache controller is configured to store data in a target memory address range in a memory through at least one cache module for one target IP module, wherein the data in the target memory address range is access data of the target IP module, and target memory address ranges corresponding to different cache controllers are different;

After receiving an access request, the routing module determines a target address of the access request, and respectively matches the target address with a target memory address range corresponding to each cache controller to obtain a target cache controller; forwarding the access request to a target cache controller;

And the target cache controller processes the access request according to the hit condition of the access request in the cache module corresponding to the target cache controller.

In one embodiment, any cache controller corresponds to a set of configuration registers, where the configuration registers are used to configure configuration information of the cache controller; the configuration information includes: a target memory address range; the matching the target address with the memory address range corresponding to each cache controller to obtain the target cache controller includes:

Acquiring a target address from the access request, acquiring configuration information of each cache controller, and acquiring a target memory address range corresponding to each cache controller;

And matching the target address with a target memory address range corresponding to each cache controller, and determining the cache controller corresponding to the target memory address range containing the target address as a target cache controller.

In one embodiment, the system on chip further comprises a memory controller, the method further comprising:

And the routing module forwards the access request to the memory controller for processing under the condition that the target address is not in the target memory address range corresponding to any cache controller.

In one embodiment, the configuration information further includes: the identification of the target IP module corresponding to the cache controller and the accessible cache module;

The target cache controller processes the access request according to the hit condition of the access request in the cache module corresponding to the target cache controller, and the processing includes:

traversing the accessible cache modules by the target cache controller according to the local configuration information, and determining whether the target address of the access request hits any cache module;

under the condition of hitting any cache module, processing hit data in the cache module according to the access request;

Under the condition that any cache module is not hit, whether the IP module sending the access request is a target IP module corresponding to the target IP module identifier is further determined according to the identifier of the target IP module in the local configuration information;

if yes, distributing a cache line in a cache module aiming at the data corresponding to the access request, and caching the data corresponding to the access request to the cache line;

If not, the access request is sent to the memory controller for processing.

In one embodiment, the system on chip further comprises a control module, and the configuration information further comprises: a cache module refreshing identifier and a refreshing finishing identifier; the method further comprises the steps of:

The control module configures a cache module refreshing identifier of a first cache controller corresponding to any IP module as enabling under the condition that any IP module has no data access requirement;

the first cache controller refreshes data in a locally accessible cache module under the condition that the cache module refreshing identifier is detected to be configured as enabling;

After the completion of the refresh is determined, configuring a local refresh completion identifier as enabling;

And the control module adjusts the accessible cache module in the configuration information of the first cache controller and the target memory address range under the condition that the refresh completion identification is configured to be enabled, so that the first cache controller cannot store the data in the memory through any cache module.

In one embodiment, the method further comprises:

The control module adjusts the accessible cache module in the configuration information of any other cache controller except the first cache controller so as to adjust the cache module of which the first cache is refreshed to be the accessible cache module of any other cache controller.

In one embodiment, the method further comprises:

And in the process of refreshing the data in the locally accessible cache modules, if an access request is received, the access request hits any cache module corresponding to the first cache controller, and the data aimed at by the access request is not refreshed to the memory, the data hit in the cache module is processed according to the access request.

According to a second aspect of the present disclosure, there is provided a system-on-chip including a cache system and a number of IP blocks; the cache system comprises a routing module, a plurality of cache controllers and a plurality of cache modules; any cache controller is configured to store data in a target memory address range in a memory through at least one cache module for one target IP module, wherein the data in the target memory address range is access data of the target IP module, and target memory address ranges corresponding to different cache controllers are different;

The routing module is used for determining a target address of the access request after receiving the access request, and respectively matching the target address with a target memory address range corresponding to each cache controller to obtain a target cache controller; forwarding the access request to a target cache controller;

and the target cache controller is used for processing the access request according to the hit condition of the access request in the cache module corresponding to the target cache controller.

In one embodiment, any cache controller corresponds to a set of configuration registers, where the configuration registers are used to configure configuration information of the cache controller; the configuration information includes: a target memory address range;

the route is specifically configured to obtain a target address from an access request, obtain configuration information of each cache controller, and obtain a target memory address range corresponding to each cache controller;

And matching the target address with a target memory address range corresponding to each cache controller, and determining the cache controller corresponding to the target memory address range containing the target address as a target cache controller.

In one embodiment, the system on chip further comprises a memory controller; the routing module is further configured to forward the access request to a memory controller for processing if the target address is not in a target memory address range corresponding to any cache controller.

In one embodiment, the configuration information further includes: the identification of the target IP module corresponding to the cache controller and the accessible cache module;

The target cache controller is specifically used for traversing the accessible cache modules according to the local configuration information and determining whether the target address of the access request hits any cache module or not; under the condition of hitting any cache module, processing hit data in the cache module according to the access request; under the condition that any cache module is not hit, whether the IP module sending the access request is a target IP module corresponding to the target IP module identifier is further determined according to the identifier of the target IP module in the local configuration information; if yes, distributing a cache line in a cache module aiming at the data corresponding to the access request, and caching the data corresponding to the access request to the cache line; if not, the access request is sent to the memory controller for processing.

In one embodiment, the system on chip further comprises a control module, and the configuration information further comprises: a cache module refreshing identifier and a refreshing finishing identifier;

The control module is used for configuring a cache module refreshing identifier of a first cache controller corresponding to any IP module to be enabled under the condition that any IP module has no data access requirement;

The first cache controller is used for refreshing data in a locally accessible cache module under the condition that the cache module refreshing identifier is detected to be configured to be enabled; after the completion of the refresh is determined, configuring a local refresh completion identifier as enabling;

The control module is further configured to adjust the accessible cache module in the configuration information of the first cache controller and the target memory address range when the refresh completion flag is detected to be configured to be enabled, so that the first cache controller cannot store data in the memory through any cache module.

In one embodiment, the control module is further configured to adjust an accessible cache module in configuration information of any other cache controller except the first cache controller, so as to adjust the cache module that the first cache is refreshed to be an accessible cache module of the any other cache controller.

In one embodiment, in the process of refreshing the data in the locally accessible cache module, if an access request is received, the access request hits any cache module corresponding to the first cache controller, and the data targeted by the access request is not refreshed to the memory, the data hit in the cache module is processed according to the access request.

According to a third aspect of the present disclosure, there is provided an electronic device comprising a system-on-chip in any of the embodiments of the second aspect.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

FIG. 1 is a schematic diagram of a memory and cache set associative mapping according to one embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a system-on-chip according to one embodiment of the disclosure;

FIG. 3 is a schematic flow chart of a system-on-chip access processing method according to an embodiment of the disclosure;

FIG. 4 is a flowchart illustrating a method for executing a cache controller according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of configuration information in a cache controller according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of a cache system according to an embodiment of the disclosure;

FIG. 7 is a schematic diagram of a selection signal provided by an embodiment of the present disclosure;

Fig. 8 is a schematic structural diagram of a graphics processing system according to an embodiment of the present disclosure.

Detailed Description

Before describing embodiments of the present disclosure, it should be noted that:

Some embodiments of the disclosure are described as process flows, in which the various operational steps of the flows may be numbered sequentially, but may be performed in parallel, concurrently, or simultaneously.

The terms "first," "second," and the like may be used in embodiments of the present disclosure to describe various features, but these features should not be limited by these terms. These terms are only used to distinguish one feature from another.

The term "and/or," "and/or" may be used in embodiments of the present disclosure to include any and all combinations of one or more of the associated features listed.

It will be understood that when two elements are described in a connected or communicating relationship, unless a direct connection or direct communication between the two elements is explicitly stated, connection or communication between the two elements may be understood as direct connection or communication, as well as indirect connection or communication via intermediate elements.

In order to make the technical solutions and advantages of the embodiments of the present disclosure more apparent, the following detailed description of exemplary embodiments of the present disclosure is provided in conjunction with the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present disclosure, not all embodiments of which are exhaustive. It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be combined with each other.

At present, when each IP module on the system-level chip accesses by using the Cache, various mapping modes can be adopted to map the data stored in the memory into the Cache for storage, and common mapping modes comprise direct mapping, group association, full association and the like. Regardless of the mapping manner, since each IP module uses a piece of Cache to store data, access data of different IP modules may be mapped into one CACHE LINE, which may cause frequent replacement of data in the Cache due to access of multiple IP modules.

As shown in fig. 1, a schematic diagram of a group-associative mapping manner includes N ways (ways) in the group-associative mapping manner, and each way includes M groups (sets). Each set, i.e. each set, comprises N cache lines. As shown in fig. 1, there are two ways, namely way0 and way1, each having 8 lines, corresponding to 8 sets, of 2 cache lines in each set, e.g., CACHE LINE of way0 and CACHE LINE of way1 are one set.

Thus, any two data blocks 0, 8, 16, 24 … in the memory can be stored in both CACHE LINE in the cache. The data requirements of each IP module are often different on the system-level chip, if the data accessed by each IP module is mapped and mapped into CACHE LINE a 0, the data in CACHE LINE a is frequently replaced, for example, after the data a accessed by the IP module a is mapped into CACHE LINE a of way0, the IP module B also needs to access the memory, after the data B accessed by the mapping is mapped into CACHE LINE a of way0, the data a in CACHE LINE a of way0 needs to be replaced with data B, and the data a is written back into the memory, at this time, if the data a still has the requirement of accessing the data a, the access request of the IP module a may miss (miss) in the Cache, and then the data B in CACHE LINE a of way0 may also need to be replaced back with the data a. It will be appreciated that the greater the probability of a miss and replacement as there are more IP blocks on the system on chip. In the case of a miss, the data needs to be searched from the memory and processed, so that the access efficiency is low.

In order to solve the above-mentioned problems, the present disclosure proposes an access processing method of a system-on-chip, which is applied to the system-on-chip, as shown in fig. 2, and the system-on-chip includes a cache system 210, a plurality of IP modules 220, and a memory controller 230. The cache system includes a routing module 2101, a number of cache controllers 2102, and a number of cache modules 2103. Any cache controller is configured to store data in a target memory address range in a memory through at least one cache module for one target IP module, wherein the data in the target memory address range is access data of the target IP module, and target memory address ranges corresponding to different cache controllers are different. As shown in fig. 3, the method includes:

s301, after receiving an access request, a routing module determines a target address of the access request, and matches the target address with a target memory address range corresponding to each cache controller to obtain a target cache controller; forwarding the access request to the target cache controller;

S302, the target cache controller processes the access request according to the hit condition of the access request in the cache module corresponding to the target cache controller.

In the above manner, since each cache controller is configured to store, for one target IP module, data in a target memory address range through at least one cache module, where the data in the target memory address range is access data of the target IP module, the data in each cache module is data to be accessed by a certain target IP module, and at the same time, an access request of the same IP module is routed to one cache controller for processing. Because the repeatability of the same IP module on the data requirement is higher, the data of the cache module cannot be replaced frequently, so that the hit rate of the cache is improved, and the overall access efficiency is improved.

When the system-in-chip works, data used by various IP modules are usually stored in an off-chip memory in advance, and in the present disclosure, the data used by the IP modules are referred to as access data of the IP modules. Since the access data of the IP blocks are stored in the memory in advance, the storage address of the access data of each IP block can be recorded, and in this disclosure, the storage address of the access data of the IP block in the memory is referred to as a target memory address. It will be appreciated that when the access data of the IP module is stored in the memory continuously, the target memory address range of the IP module is 1 address range, and when the access data of the IP module is stored in the memory discontinuously, the target memory address range of the IP module is a plurality of address ranges. The present disclosure does not limit a storage manner of access data of the IP module in the memory.

For example, N IP blocks are shared on a system-on-a-chip, where X IP blocks have a requirement of accessing a memory by using a cache, an IP block having a requirement of accessing a memory by using a cache is referred to as a target IP block in the present disclosure, and 1 cache controller may be configured for each of the N target IP blocks, where each cache controller may store data in a target memory address range corresponding to the target IP block through 1 or more cache blocks.

In one embodiment, as shown in table 1, the corresponding relationship of each target IP module, the cache controller, the cache module, and the target memory address range may be recorded in a register in the routing module.

TABLE 1

As shown in table 1, the target memory address range corresponding to the cache controller 1 is 1 address range, addr_min_1-addr_max_1, the cache module accessible to the cache controller 1 is a, and the corresponding target IP module is a. Similarly, the N cache modules accessible by the cache controller, the corresponding target IP module, and the target memory address range may be recorded.

The access requests sent by the various IP blocks typically carry operations on the data, such as read or write operations, and the destination address of the data in memory.

In this embodiment, the step S301 may specifically be: after receiving the access request, the routing module can respectively match the target address with a target memory address range corresponding to each locally stored cache controller according to the target address of the access request, determine the cache controller corresponding to the target memory address range containing the target address as a target cache controller, and then send the cache controller to the target cache controller.

In another embodiment, a set of configuration registers may be further configured in each cache controller, that is, any cache controller corresponds to a set of configuration registers, where the configuration registers are used to configure configuration information of the cache controller. Wherein the configuration information includes: a target memory address range. In this embodiment, S301 may be: the routing module acquires a target address from the access request, acquires configuration information of each cache controller and acquires a target memory address range corresponding to each cache controller;

and matching the target address with a target memory address range corresponding to each cache controller, determining the cache controller corresponding to the target memory address range containing the target address as a target cache controller, and then sending the cache controller to the target cache controller.

It will be appreciated that the Cache in this disclosure does not allocate a Cache controller and a Cache module to a portion of the IP modules, since access requests are also made to various other IP modules in addition to the target IP module, and the portion of the IP modules does not actually use the Cache, i.e., the Cache. But the routing module also needs to process after receiving the access request sent by the IP module. Specifically, the routing module forwards the access request to the memory controller for processing when the target address of the access request is not in the target memory address range corresponding to any cache controller. That is, if the destination address of the received access request is not within the destination memory address range corresponding to any cache controller, it may be determined that the data to which the access request is directed is not access data of any destination IP module, but access data of other IP modules except the destination IP module, and this portion of the IP modules does not use the requirement of the cache, and it is not possible to store the data to which the access request is directed in each cache module currently, so that the access request may be directly forwarded to the memory controller, and the memory controller accesses the memory for the access request.

In S302, if the correspondence relationship between each target IP module, the cache controller, the cache module, and the target memory address range is recorded in the routing module in a register manner.

The target cache controller can inquire information recorded by a register in the routing module, determine a locally accessible cache module, further determine whether a target address of the access request hits any cache module, and process hit data in the cache module according to the access request under the condition that any cache module is hit; under the condition that any cache module is not hit, further determining the identification of a target IP module corresponding to the local according to the information recorded by a register in the routing module, and further determining whether the IP module sending the access request is the target IP module corresponding to the target IP module identification; if yes, distributing a cache line in a cache module aiming at the data corresponding to the access request, and caching the data corresponding to the access request to the cache line; if not, the access request is sent to the memory controller for processing.

If the cache controller records the identification of the locally corresponding target IP module and the accessible cache module in the configuration information in the locally corresponding configuration register, the target cache controller can traverse the accessible cache module according to the local configuration information and determine whether the target address of the access request hits any cache module; under the condition of hitting any cache module, processing hit data in the cache module according to the access request; under the condition that any cache module is not hit, whether the IP module sending the access request is a target IP module corresponding to the target IP module identifier is further determined according to the identifier of the target IP module in the local configuration information; if yes, distributing a cache line in a cache module aiming at the data corresponding to the access request, and caching the data corresponding to the access request to the cache line; if not, the access request is sent to the memory controller for processing.

As shown in fig. 4, no matter where the correspondence between the target IP module, the cache controller, the cache module, and the target memory address range is recorded, the operation performed by the target cache controller is the flow shown in fig. 4, that is, S401 is performed first, that is, it is determined whether the access request hits any cache module corresponding locally, if yes, S402 is performed, that is, the data in the hit cache module is processed according to the access request, for example, a read process or a write process is performed, and when the write process is performed, a write-through or write-back policy may be adopted, which is not limited in the disclosure. If not, S403 is executed to determine whether the IP module sending the access request is the target IP module, that is, although the data in the cache module accessed by the cache controller is the access data of the target IP module, other modules may have a need to access the data, so that a determination is made here to determine whether it is the access request sent by the target IP module. If so, S404 is executed, that is, a cache line is allocated in the cache module for the data of the access request, and the data corresponding to the access request is cached in the allocated cache line, for example, the access request is a read operation, if not hit in the cache module, the cache line is allocated in the cache module according to a preset mapping mode, such as a group association mode, and the corresponding data in the memory is cached in the allocated cache line while the corresponding data in the memory is returned to the target IP module. For another example, if the access request is a write operation and does not hit in the cache module, a cache line is allocated in the cache module according to a preset mapping mode, such as a group association mode, and data carried by the access request is cached in the allocated cache line. It will be appreciated that the allocation of a cache and the allocation of a free cache line as described herein may be performed by replacing a certain cache line. When executing S403, if not, S405 is executed, that is, the access request is directly sent to the memory controller for processing. If the access request is not sent by the target IP module, the new or replaced cache line is not required to be distributed in the cache module according to the access request, and the data in the cache module is ensured to be the data actually accessed by the target IP module all the time.

In this way, for each target IP block, the corresponding cache block may share and use the data in the cache block, but the access operation of the other IP blocks may not cause the cache controller to newly allocate or replace the cache line in the cache block. Therefore, the data stored in the cache module corresponding to each certificate target IP module can be ensured to be the actual access data of the target IP module.

Considering that in an actual application scenario, the requirements of each target IP module on the buffer module may change, for example, if the system-on-chip is a GPU SOC (graphics processor system-on-chip), there are typically a video codec module and a display control module on the GPU SOC, where the video codec module only works when performing video codec, and the display control module only works when the image needs to be displayed, and the display control module does not work at other times. Therefore, the video codec module and the display control module also change the requirements of the buffer module at different times, i.e. only during operation and not during non-operation. Therefore, if the cache modules corresponding to the target IP modules can be redistributed according to the actual demands of the target IP modules, the resource waste of the cache modules can be avoided.

Based on the above conception, the disclosure proposes that the system-on-chip further includes a control module, and the configuration information of any cache controller further includes: and the cache module refreshes the mark and refreshes the mark after finishing.

The control module can configure a cache module refresh identifier of a cache controller (called a first cache controller in the disclosure) corresponding to any IP module to be enabled under the condition that the IP module has no data access requirement;

the first cache controller refreshes data in a locally accessible cache module under the condition that the cache module refreshing identification is detected to be configured as enabling;

After the completion of the refresh is determined, configuring a local refresh completion identifier as enabling;

And the control module adjusts the accessible cache module in the configuration information of the first cache controller and the target memory address range under the condition that the refresh completion identification is configured to be enabled, so that the first cache controller cannot store the data in the memory through any cache module.

The control module detects the working requirement of each target IP module, for example, the system-on-chip is a GPU SOC, when the control module detects that the video codec module is working, it determines that the video codec module does not need to use the buffer module, and can configure the buffer module refresh identifier of the buffer controller corresponding to the video codec module to be enabled, and when the buffer controller detects that the local buffer module refresh identifier is configured to be enabled, the buffer controller refreshes the data in the locally accessible buffer module, that is, the data of each buffer line in all the buffer modules accessible by the buffer controller is written back to the memory. After the completion of the refresh is determined, configuring a local refresh completion identifier as enabling; and the control module is used for adjusting the accessible cache module and the target memory address range in the configuration information of the cache controller under the condition that the control module detects that the refresh completion identification is configured as enabling, wherein the accessible cache module and the target memory address range can be cleared or configured as invalid, so that the cache controller corresponding to the video codec module cannot store data in a memory through any cache module. In other words, by the above manner, the cache module corresponding to the target IP module which does not need to use the cache can be dynamically released.

In the refreshing process, in order to enable the refreshed cache module to continue to serve the target IP module or other IP modules, if an access request is received and hits any cache module corresponding to the first cache controller in the process of refreshing the data in the locally accessible cache module, and the data aimed at by the access request is not refreshed to the memory, the first cache controller processes the hit data in the cache module according to the access request. For example, if the access request is a read operation, the data in the cache module is returned directly to the IP module that sent the access request. If the access request is a write operation, the data in the cache module is directly rewritten according to the access. In addition, in the refreshing process, if the received access request does not hit any cache module of the first cache controller, the first cache controller sends the access request to the memory controller after determining that the refreshing is finished.

In addition, in order to avoid resource waste of the cache module, the control module may further adjust the accessible cache module in the configuration information of any other cache controller except the first cache controller, so as to adjust the cache module that the first cache is refreshed to be the cache module accessible by any other cache controller.

Continuing the above example, if the corresponding buffer module of the video codec module is a and the corresponding buffer controller is 1, the control module may also adjust the accessible buffer module in the configuration information of any other buffer controller except the buffer controller 1, for example, adjust the buffer module in the configuration information of the buffer controller 2 corresponding to the display control module, specifically, increase the buffer module b, so that the display control module may access the buffer module b through the buffer controller 2. Therefore, after the buffer memory module of the original video encoding and decoding module is released, the buffer memory module is reassigned to the display control module for use. And the resource waste of the cache module is avoided. When the control module performs the reassignment of the cache modules, the control module may determine the cache requirement of each target IP module first, and dynamically reassign the released cache modules to the target IP module with the largest cache requirement.

In addition, in some scenes, when the system-in-chip is powered on, it is determined that a certain target IP module is not needed, for example, in a scene of cloud video editing codes, a cloud server only needs to perform video encoding and decoding, and video is not needed to be played, so after the GPU SOC in the cloud server is powered on, the control module can release the cache module of the display control module in the above manner and then distribute the cache module to the video editing code module.

Considering that the routing module and the plurality of cache controllers send access requests to the memory controller, and the memory controller may generally have only one set of interfaces, the cache system may further include an arbiter, and the multiple access requests sent by the routing module and the plurality of cache controllers are arbitrated before being sent to the memory controller, and the data returned from the memory controller is also distributed to the requesting party through the arbiter. The arbiter may arbitrate using polling or other arbitration schemes, which is not limited by this disclosure. In addition, an arbiter may be added to the memory controller instead of the cache system, for arbitrating the access requests sent by the routing module and the plurality of cache controllers.

In a specific embodiment, as shown in fig. 6, which is a schematic diagram of a cache system in this specific embodiment, parameters of the cache module are: CACHELINE SIZE (cache line size) is 1024bits/128 bytes, the mapping mode is group connected 16/64 groups, configured as read allocation/write allocation, and the write-back policy can be configured as write-back or write-through. Instantiating 4 cache modules, namely cache modules A/B/C/D, wherein each cache module corresponds to one SRAM array, each SRAM array comprises 16 SRAMs (corresponding to 16 paths), and each SRAM has a size of 1024 (data bit width)64 The SRAM array can be accessed by 4 cache controllers (depth), and the purpose of resource sharing is realized, namely, each cache controller can access 0-4 cache modules.

As shown in fig. 5, in this embodiment, the configuration information is stored in the cache controller.

The configuration information comprises four sections of target memory address ranges, namely addr_min_0-addr_max_0, addr_min_1-addr_max_1, addr_min_2-addr_max_2 and addr_min_3-addr_max_3, wherein each target memory address range is provided with a valid mark for marking whether the target memory address range is valid or not. Identification of the target IP module: master id, accessible cache module: sram_used, cache module refresh flag: flush, refresh finish identification: idle.

Each piece of configuration information is specifically used for: 1) The flush is configured by the control module, after the control module configures the flush as enabled, the flush register is polled, and after the flush register becomes 1, the flush operation is completed; 2) The master id is configured by the control module, indicating to which target IP module this cache controller is expected to be assigned for use; 3) The sram_used adopts a single thermal code, namely each bit corresponds to one SRAM, and if one bit is set to be 1, the corresponding SRAM array is used, and is mainly used for selecting input and output signals of the SRAM, and each SRAM array can only be used for one cache controller at the same time, namely the problem of access conflict does not exist; 4) The set_num represents the corresponding group number of the cache controller, if there is no merging operation, the value is 9' h40 (i.e. 64 groups), two cache resources can be merged, or four cache resources can be merged, the corresponding set_num is 9' h80 (128 groups) and 9' h100 (256 groups), respectively, because in the mapping mode of group association, the cache controller needs to map part of the content of the memory address to an Index signal to represent which group the accessed data is located, and when the set_num is about the number of groups, the bit width of the Index signal is larger. Thus, the cache controller may map the memory address according to the set_num.

In this particular embodiment, each cache controller has a set of SRAM interface signals, such as cs_n (chip select signal, active low), addr (address), rd (read enable), wr (write enable), wdata (data written to SRAM), rdata (data read from SRAM). If the cache module A/B/C/D is represented by SRAM A/B/C/D.

Then sram_used [0] =1 means using SRAM a; sram_used [1] =1, indicating the use of SRAM B; sram_used [2] =1 means using SRAM C; sram_used [3] =1, indicating the use of SRAM D.

The corresponding sram_used registers of the 4 cache controllers may be labeled sram_used_a/sram_used_b/sram_used_c/sram_used_d, using the different bits of these 4 registers, to generate the select signal for the SRAM mux.

sram_sel_a =

{sram_used_d[0],sram_used_c[0],sram_used_b[0],sram_used_a[0]}

sram_sel_b =

{sram_used_d[1],sram_used_c[1],sram_used_b[1],sram_used_a[1]}

sram_sel_c =

{sram_used_d[2],sram_used_c[2],sram_used_b[2],sram_used_a[2]}

sram_sel_d =

{sram_used_d[3],sram_used_c[3],sram_used_b[3],sram_used_a[3]}

Sram_sel_a-d are 4-bit signals, and each signal has 1bit at most.

FIG. 7 illustrates how inputs are selected, for example SRAM A, and for example wr, other inputs are similar; the a/b/c/d preceding wr in fig. 7 indicates from which cache controller, four ways of wr come in, followed by selection by sram_sel_a:

sram_sel_a [0] =1, then select a_wr to be given to wr of SRAM a;

sram_sel_a1=1, then select b_wr to be given to wr of SRAM a;

sram_sel_a2=1, then select cr_wr to SRAM a's wr;

sram_sel_a [3] =1, then select d_wr to give wr to SRAM a.

In this specific embodiment, the four target IP modules may be shared by using four cache controllers.

Based on the same inventive concept, the present disclosure also proposes a system-on-chip including a cache system and a plurality of IP modules; the cache system comprises a routing module, a plurality of cache controllers and a plurality of cache modules; any cache controller is configured to store data in a target memory address range in a memory through at least one cache module for one target IP module, wherein the data in the target memory address range is access data of the target IP module, and target memory address ranges corresponding to different cache controllers are different;

The routing module is used for determining a target address of the access request after receiving the access request, and respectively matching the target address with a target memory address range corresponding to each cache controller to obtain a target cache controller; forwarding the access request to a target cache controller;

and the target cache controller is used for processing the access request according to the hit condition of the access request in the cache module corresponding to the target cache controller.

In one embodiment, any cache controller corresponds to a set of configuration registers, where the configuration registers are used to configure configuration information of the cache controller; the configuration information includes: a target memory address range;

the route is specifically configured to obtain a target address from an access request, obtain configuration information of each cache controller, and obtain a target memory address range corresponding to each cache controller;

And matching the target address with a target memory address range corresponding to each cache controller, and determining the cache controller corresponding to the target memory address range containing the target address as a target cache controller.

In one embodiment, the system on chip further comprises a memory controller; the routing module is further configured to forward the access request to a memory controller for processing if the target address is not in a target memory address range corresponding to any cache controller.

In one embodiment, the configuration information further includes: the identification of the target IP module corresponding to the cache controller and the accessible cache module;

The target cache controller is specifically used for traversing the accessible cache modules according to the local configuration information and determining whether the target address of the access request hits any cache module or not; under the condition of hitting any cache module, processing the data in the hit cache module in the cache module according to the access request; under the condition that any cache module is not hit, whether the IP module sending the access request is a target IP module corresponding to the target IP module identifier is further determined according to the identifier of the target IP module in the local configuration information; if yes, distributing a cache line in a cache module aiming at the data corresponding to the access request, and caching the data corresponding to the access request to the cache line; if not, the access request is sent to the memory controller for processing.

In one embodiment, the system on chip further comprises a control module, and the configuration information further comprises: a cache module refreshing identifier and a refreshing finishing identifier;

The control module is used for configuring a cache module refreshing identifier of a first cache controller corresponding to any IP module to be enabled under the condition that any IP module has no data access requirement;

The first cache controller is used for refreshing data in a locally accessible cache module under the condition that the cache module refreshing identifier is detected to be configured to be enabled; after the completion of the refresh is determined, configuring a local refresh completion identifier as enabling;

The control module is further configured to adjust the accessible cache module in the configuration information of the first cache controller and the target memory address range when the refresh completion flag is detected to be configured to be enabled, so that the first cache controller cannot store data in the memory through any cache module.

In one embodiment, the control module is further configured to adjust an accessible cache module in configuration information of any other cache controller except the first cache controller, so as to adjust the cache module that the first cache is refreshed to be an accessible cache module of the any other cache controller.

In one embodiment, in the process of refreshing the data in the locally accessible cache module, if an access request is received, the access request hits any cache module corresponding to the first cache controller, and the data targeted by the access request is not refreshed to the memory, the data hit in the cache module is processed according to the access request.

Based on the same inventive concept, the present disclosure further proposes a graphics processing system, as shown in fig. 8, which at least includes:

GPU core, used for processing commands, such as the command of drawing, according to drawing command, carry out the Pipeline of the image rendering. The GPU core mainly comprises a computing unit and is used for executing commands compiled by the loader, belongs to a programmable module and consists of a large number of ALUs; the controller (not shown) further has various functional modules such as rasterization (a fixed stage of the 3D rendering pipeline), tilling (dicing a frame in the TBR and TBDR GPU architectures), clipping (a fixed stage of the 3D rendering pipeline, clipping out of view or primitives not shown on the back), post-processing (scaling, clipping, rotating the drawn image), etc.

A general DMA for performing data movement between the host memory and the GPU graphics card memory, for example, the vertex data for 3D drawing, and for moving the vertex data from the host memory to the GPU graphics card memory;

The network on chip is used for data exchange between each master and salve on the SOC; the data transmission between each IP module and the cache system, between the cache system and the memory controller can be carried out by adopting the network-on-chip;

And the PCIe controller is used for realizing PCIe protocol by the interface communicated with the host computer, so that the GPU display card is connected to the host computer through the PCIe interface. The host computer runs graphics API, driver of display card, etc.;

the memory controller is used for connecting memory equipment and storing data on the SOC;

a display controller for controlling the frame buffer in the memory to be output to the display by a display interface (HDMI, DP, etc.);

and the video decoder is used for decoding the coded video on the hard disk of the host into pictures which can be displayed.

And the video encoder is used for encoding the original video code stream on the hard disk of the host into a specified format and returning the encoded video code stream to the host.

Wherein, the above mentioned video encoder, video decoder, display controller, memory controller, PCIe controller, general DMA, GPU core, etc. can be understood as IP modules in the above.

The cache system is used for executing the access processing method of the system-level chip provided by the above in cooperation with the control module, and will not be described here again.

The control module is used for scheduling tasks of each module on the SOC, for example, the GPU is informed of the control module after rendering a frame of image, and the control module starts the display controller again to display the image drawn by the GPU on a screen; in addition, the control module is also used for executing the access processing method of the system-level chip in cooperation with the cache system. And will not be described in detail here.

The embodiment of the disclosure also provides electronic equipment, which comprises the system-on-chip. In some use scenarios, the product form of the electronic device is a portable electronic device, such as a smart phone, a tablet computer, a VR device, etc.; in some use cases, the electronic device is in the form of a personal computer, a game console, or the like.

While preferred embodiments of the present disclosure have been described above, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the appended claims be interpreted as including the preferred embodiments and all alterations and modifications that fall within the scope of this disclosure, and that those skilled in the art will recognize that the invention also includes the true scope of the embodiments of the disclosure without departing from the spirit and scope of the disclosure.

Claims (15)

1. The access processing method of the system-level chip is applied to the system-level chip, and the system-level chip comprises a cache system and a plurality of IP modules; the cache system comprises a routing module, a plurality of cache controllers and a plurality of cache modules; any cache controller is configured to store data in a target memory address range in a memory through at least one cache module for one target IP module, wherein the data in the target memory address range is access data of the target IP module, and target memory address ranges corresponding to different cache controllers are different;

After receiving an access request, the routing module determines a target address of the access request, and respectively matches the target address with a target memory address range corresponding to each cache controller to obtain a target cache controller; forwarding the access request to a target cache controller;

And the target cache controller processes the access request according to the hit condition of the access request in the cache module corresponding to the target cache controller.

2. The method of claim 1, wherein any cache controller corresponds to a set of configuration registers, wherein the configuration registers are configured to configure configuration information of the cache controller; the configuration information includes: a target memory address range; the matching the target address with the memory address range corresponding to each cache controller to obtain the target cache controller includes:

Acquiring a target address from the access request, acquiring configuration information of each cache controller, and acquiring a target memory address range corresponding to each cache controller;

And matching the target address with a target memory address range corresponding to each cache controller, and determining the cache controller corresponding to the target memory address range containing the target address as a target cache controller.

3. The method of claim 2, the system on a chip further comprising a memory controller, the method further comprising:

And the routing module forwards the access request to the memory controller for processing under the condition that the target address is not in the target memory address range corresponding to any cache controller.

4. The method of claim 2, the configuration information further comprising: the identification of the target IP module corresponding to the cache controller and the accessible cache module;

The target cache controller processes the access request according to the hit condition of the access request in the cache module corresponding to the target cache controller, and the processing includes:

traversing the accessible cache modules by the target cache controller according to the local configuration information, and determining whether the target address of the access request hits any cache module;

under the condition of hitting any cache module, processing hit data in the cache module according to the access request;

Under the condition that any cache module is not hit, whether the IP module sending the access request is a target IP module corresponding to the target IP module identifier is further determined according to the identifier of the target IP module in the local configuration information;

if yes, distributing a cache line in a cache module aiming at the data corresponding to the access request, and caching the data corresponding to the access request to the cache line;

If not, the access request is sent to the memory controller for processing.

5. The method of claim 4, the system on a chip further comprising a control module, the configuration information further comprising: a cache module refreshing identifier and a refreshing finishing identifier; the method further comprises the steps of:

The control module configures a cache module refreshing identifier of a first cache controller corresponding to any IP module as enabling under the condition that any IP module has no data access requirement;

the first cache controller refreshes data in a locally accessible cache module under the condition that the cache module refreshing identifier is detected to be configured as enabling;

After the completion of the refresh is determined, configuring a local refresh completion identifier as enabling;

And the control module adjusts the accessible cache module in the configuration information of the first cache controller and the target memory address range under the condition that the refresh completion identification is configured to be enabled, so that the first cache controller cannot store the data in the memory through any cache module.

6. The method of claim 5, further comprising:

The control module adjusts the accessible cache module in the configuration information of any other cache controller except the first cache controller so as to adjust the cache module of which the first cache is refreshed to be the accessible cache module of any other cache controller.

7. The method of claim 5, further comprising:

And in the process of refreshing the data in the locally accessible cache modules, if an access request is received, the access request hits any cache module corresponding to the first cache controller, and the data aimed at by the access request is not refreshed to the memory, the data hit in the cache module is processed according to the access request.

8. A system-in-chip comprising a cache system and a plurality of IP blocks; the cache system comprises a routing module, a plurality of cache controllers and a plurality of cache modules; any cache controller is configured to store data in a target memory address range in a memory through at least one cache module for one target IP module, wherein the data in the target memory address range is access data of the target IP module, and target memory address ranges corresponding to different cache controllers are different;

The routing module is used for determining a target address of the access request after receiving the access request, and respectively matching the target address with a target memory address range corresponding to each cache controller to obtain a target cache controller; forwarding the access request to a target cache controller;

and the target cache controller is used for processing the access request according to the hit condition of the access request in the cache module corresponding to the target cache controller.

9. The chip of claim 8, wherein any cache controller corresponds to a set of configuration registers, wherein the configuration registers are used for configuring configuration information of the cache controller; the configuration information includes: a target memory address range;

the route is specifically configured to obtain a target address from an access request, obtain configuration information of each cache controller, and obtain a target memory address range corresponding to each cache controller;

And matching the target address with a target memory address range corresponding to each cache controller, and determining the cache controller corresponding to the target memory address range containing the target address as a target cache controller.

10. The chip of claim 9, the system on chip further comprising a memory controller;

the routing module is further configured to forward the access request to a memory controller for processing if the target address is not in a target memory address range corresponding to any cache controller.

11. The chip of claim 9, the configuration information further comprising: the identification of the target IP module corresponding to the cache controller and the accessible cache module;

The target cache controller is specifically used for traversing the accessible cache modules according to the local configuration information and determining whether the target address of the access request hits any cache module or not; under the condition of hitting any cache module, processing hit data in the cache module according to the access request; under the condition that any cache module is not hit, whether the IP module sending the access request is a target IP module corresponding to the target IP module identifier is further determined according to the identifier of the target IP module in the local configuration information; if yes, distributing a cache line in a cache module aiming at the data corresponding to the access request, and caching the data corresponding to the access request to the cache line; if not, the access request is sent to the memory controller for processing.

12. The chip of claim 10, the system-on-chip further comprising a control module, the configuration information further comprising: a cache module refreshing identifier and a refreshing finishing identifier;

The control module is used for configuring a cache module refreshing identifier of a first cache controller corresponding to any IP module to be enabled under the condition that any IP module has no data access requirement;

The first cache controller is used for refreshing data in a locally accessible cache module under the condition that the cache module refreshing identifier is detected to be configured to be enabled; after the completion of the refresh is determined, configuring a local refresh completion identifier as enabling;

The control module is further configured to adjust the accessible cache module in the configuration information of the first cache controller and the target memory address range when the refresh completion flag is detected to be configured to be enabled, so that the first cache controller cannot store data in the memory through any cache module.

13. The chip according to claim 12,

The control module is further configured to adjust an accessible cache module in configuration information of any other cache controller except the first cache controller, so as to adjust the cache module in which the first cache is refreshed to be an accessible cache module of the any other cache controller.

14. The chip according to claim 12,

And the first cache controller processes the hit data in the cache module according to the access request if the access request is received and hits any cache module corresponding to the first cache controller and the data aimed at by the access request is not refreshed to the memory in the process of refreshing the data in the locally accessible cache module.

15. An electronic device comprising the system-on-chip of any one of claims 8-14.