CN117971538A

CN117971538A - Memory abnormality detection method and device, electronic equipment and storage medium

Info

Publication number: CN117971538A
Application number: CN202410117463.XA
Authority: CN
Inventors: 桑维光; 李永超; 魏冲洲
Original assignee: Xi'an Xunfei Super Brain Information Technology Co ltd
Current assignee: Xi'an Xunfei Super Brain Information Technology Co ltd
Priority date: 2024-01-26
Filing date: 2024-01-26
Publication date: 2024-05-03

Abstract

The application provides a memory abnormality detection method, a device, electronic equipment and a storage medium, wherein the memory abnormality detection method comprises the following steps: and obtaining a memory occupation amount statistical sequence of the target detection object in a set time period, carrying out sub-sequence division on the memory occupation amount statistical sequence according to the set sequence length, and determining whether the target detection object has memory leakage or not according to the memory change trend corresponding to each divided sub-sequence. The memory anomaly detection method provided by the application can observe the memory time sequence change of the target detection object, eliminate misjudgment on memory leakage detection caused by memory fluctuation, improve the detection accuracy, realize real-time automatic detection of memory leakage, reduce the labor cost and improve the detection efficiency.

Description

Memory abnormality detection method and device, electronic equipment and storage medium

Technical Field

The present application relates to the field of computer technologies, and in particular, to a method and apparatus for detecting a memory abnormality, an electronic device, and a storage medium.

Background

Due to negligence of developers in the development process or the influence of the technical level of the developers, various memory anomalies, such as memory leakage, memory boundary crossing access, memory repeated release, released memory revising and the like, are always unavoidable in the software development process, and particularly, the problem of memory anomalies in large and complex software systems is more remarkable. The memory leakage causes the program to consume a large amount of memory resources, and finally causes the problems of memory overflow, performance degradation, system breakdown and the like.

Currently, memory leak problems are typically detected using memory leak troubleshooting tools or manually. The memory leakage detection tool is slower in memory leakage detection speed, and memory leakage detection can be performed only after the process exits; the manual detection is usually to compare memory snapshots at two time points, manually analyze and search the difference between the two memory snapshots, determine a module with increased memory so as to reduce the investigation range, and the method cannot observe the time sequence change of the memory of each module, is easy to misjudge the module with fluctuation of the memory, has higher error rate of memory leakage detection and consumes a large amount of manpower and material resources.

Disclosure of Invention

In view of the above, embodiments of the present application are directed to providing a method, an apparatus, an electronic device, and a storage medium for detecting memory anomalies, which not only can implement real-time automatic detection of memory leakage, but also can eliminate erroneous judgment of memory leakage detection caused by memory fluctuation, and improve detection accuracy.

According to a first aspect of an embodiment of the present application, there is provided a method for detecting a memory exception, including:

acquiring a memory occupation amount statistical sequence of a target detection object in a set time period;

Performing sub-sequence division on the memory occupation amount statistical sequence according to a set sequence length;

and determining whether the target detection object has memory leakage or not according to the memory change trend corresponding to each divided sub-sequence.

Optionally, the determining whether the target detection object has memory leakage according to the memory change trend corresponding to each divided sub-sequence includes:

Detecting a first subsequence with the memory change trend being an ascending trend from the divided subsequences, wherein the memory change trend is that the last memory occupation amount sequence value of the first subsequence is larger than the first memory occupation amount sequence value;

and under the condition that the number of the detected first subsequences is larger than a set threshold value, determining that the target detection object has memory leakage.

Optionally, the method further comprises:

Updating attribute information of a target memory block in response to a first operation on the target memory block, wherein the first operation comprises a memory allocation operation and/or a memory release operation, and the attribute information comprises at least one of access prohibition attribute and release prohibition attribute;

And triggering a memory exception when a first operation request for the target memory block is received, wherein the first operation request comprises an operation request which is inconsistent with the attribute information.

Optionally, the first operation includes the memory allocation operation;

the responding to the first operation on the target memory block, updating the attribute information of the target memory block, including:

setting access prohibition attribute for a first memory area corresponding to a target memory block in response to memory allocation operation of the target memory block, wherein the first memory area is a preset area positioned at the boundary of the target memory block;

When receiving a first operation request to the target memory block, triggering a memory exception, including:

When an access request of a first function to a first memory area corresponding to the target memory block is received, triggering memory out-of-range access exception and controlling the first function to terminate operation.

Optionally, the first operation includes the memory release operation;

setting a release inhibition attribute for a target memory block in response to a memory release operation for the target memory block;

And triggering the repeated memory release exception when receiving a release request of the second function to the target memory block, and controlling the second function to stop running.

Optionally, the method further comprises:

Responding to the memory release operation of a target memory block, and placing the target memory block in a first waiting queue;

When a preset first queue cleaning strategy is met, removing the target memory block from the first waiting queue, and clearing the release inhibition attribute of the target memory block;

triggering the repeated memory release exception when a release request of the second function to the target memory block is received, and controlling the second function to terminate operation, wherein the method comprises the following steps:

And when a release request of the second function to the target memory block is received, triggering a repeated memory release exception if the target memory block is in the first waiting queue, and controlling the second function to stop running.

Optionally, the first operation includes the memory release operation;

setting access prohibition attribute for a target memory block in response to memory release operation of the target memory block;

And triggering the released memory to access the exception again when an access request of the third function to the target memory block is received, and controlling the third function to stop running.

Optionally, the method further comprises:

responding to the memory release operation of a target memory block, and placing the target memory block in a second waiting queue;

removing the target memory block from the second waiting queue and clearing the access prohibition attribute of the target memory block when a preset second queue clearing strategy is met;

When an access request of a third function to the target memory block is received, triggering the released memory to access the exception again, and controlling the third function to terminate operation, including:

And when an access request of a third function to the target memory block is received, triggering the released memory to access the exception again if the target memory block is in the second waiting queue, and controlling the third function to stop running.

According to a second aspect of an embodiment of the present application, there is provided a memory abnormality detection apparatus, including:

the first unit is used for acquiring a memory occupation amount statistical sequence of the target detection object in a set time period;

the second unit is used for carrying out sub-sequence division on the memory occupation amount statistical sequence according to the set sequence length;

And the third unit is used for determining whether the target detection object has memory leakage or not according to the memory change trend corresponding to each divided sub-sequence.

According to a third aspect of embodiments of the present application, there is provided an electronic device comprising a memory and a processor;

The memory is connected with the processor and used for storing programs;

The processor is configured to implement the memory abnormality detection method according to any one of the first aspect of the embodiments of the present application by running a program in the memory.

According to a fourth aspect of the embodiments of the present application, there is provided a storage medium having stored thereon a computer program which, when executed by a processor, implements the memory abnormality detection method according to any one of the first aspect of the embodiments of the present application.

According to the memory anomaly detection method provided by the application, firstly, a memory occupation amount statistical sequence of a target detection object in a set time period is obtained, then, subsequence division is carried out on the memory occupation amount statistical sequence according to the set sequence length, and finally, whether memory leakage occurs to the target detection object is determined according to the memory change trend corresponding to each subsequence of the division.

The memory anomaly detection method provided by the application can observe the memory time sequence change of the target detection object, eliminate misjudgment on memory leakage detection caused by memory fluctuation, improve the detection accuracy, realize real-time automatic detection of memory leakage, reduce the labor cost and improve the detection efficiency.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.

Fig. 1 is a flowchart of a method for detecting a memory abnormality according to an embodiment of the present application.

Fig. 2 is a schematic diagram of a process flow for determining whether a memory leak occurs in a target detection object according to an embodiment of the present application.

Fig. 3 is a flowchart of another method for detecting a memory exception according to an embodiment of the present application.

Fig. 4 is a schematic flowchart of a process for detecting a memory cross-boundary access exception according to an embodiment of the present application.

Fig. 5 is a schematic diagram of a processing flow for detecting a repeated release exception of a memory according to an embodiment of the present application.

Fig. 6 is a schematic diagram of a processing flow for detecting a released memory revisit exception according to an embodiment of the present application.

Fig. 7 is a schematic structural diagram of a memory abnormality detection device according to an embodiment of the present application.

Fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

The technical scheme of the embodiment of the application is suitable for being applied to various scenes for detecting memory anomalies, such as software development and debugging, system monitoring and operation and maintenance, security and vulnerability detection, data analysis, machine learning and other scenes. By adopting the technical scheme provided by the embodiment of the application, the real-time automatic detection of the memory leakage can be realized, and the misjudgment of the memory leakage detection caused by the memory fluctuation is eliminated.

The technical scheme of the embodiment of the application can be exemplarily applied to hardware equipment such as a processor, electronic equipment, a server (comprising a cloud server) and the like, or packaged into a software program to be operated, and when the hardware equipment executes the processing process of the technical scheme of the embodiment of the application, or the software program is operated, the aim of automatically splitting a target task and automatically calling an application program interface required by the task can be fulfilled, so that the target task is completed. The embodiment of the application only exemplary introduces the specific processing procedure of the technical scheme of the application, but does not limit the specific implementation form of the technical scheme of the application, and any technical implementation form capable of executing the processing procedure of the technical scheme of the application can be adopted by the embodiment of the application.

The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

Before describing the scheme of the application, the related technology is first described:

Due to negligence of developers in the development process or the influence of the technical level of the developers, various memory anomalies, such as memory leakage, memory boundary crossing access, memory repeated release, released memory revising and the like, are always unavoidable in the software development process, and particularly, the problem of memory anomalies in large and complex software systems is more remarkable.

The Memory Leak (Memory Leak) refers to a Memory of a heap that has been dynamically allocated in a program, and has the characteristics of concealment and accumulation, which is more difficult to detect than other Memory exceptions because the program is not released or cannot be released for some reason. The memory leakage can cause the program to consume a large amount of memory resources, and finally causes serious problems such as memory overflow, performance degradation, system breakdown and the like. In addition, memory leakage can also reduce the resource utilization and scalability of the system. For example, server application software, needs to run for a long time, processes requests sent from clients continuously, and if there is no effective memory management, there is a certain memory leak for each processing of request information. This not only affects the performance of the server, but may also cause a crash of the overall system.

In view of the above, embodiments of the present application are directed to providing a method, an apparatus, an electronic device, and a storage medium for detecting memory anomalies, which not only can implement real-time automatic detection of memory leakage, but also can eliminate erroneous judgment of memory leakage detection caused by memory fluctuation, and improve detection accuracy, and will be described in detail in the following embodiments.

Exemplary method

Fig. 1 is a flowchart of a method for detecting a memory exception according to an embodiment of the present application. As shown in fig. 1, the memory abnormality detection method provided in this embodiment includes steps S101 to S103:

S101, acquiring a memory occupation amount statistical sequence of the target detection object in a set time period.

The target detection object may be understood as a specific object that needs to perform memory exception detection, for example, may be an object of multiple types such as an application, a module, a function, and the like.

The set time period can be understood as a preset time range, and the memory occupation amount of the target detection object in the time range needs to be counted.

The memory occupation amount statistical sequence can be understood as a sequence of the memory occupation amount of the target detection object counted in a set time period, and the memory occupation amount statistical sequence can be a sequence formed by a series of memory occupation amounts at discrete time points or a continuous time sequence obtained after smoothing treatment.

Step S101 includes steps A1-A2:

A1, acquiring the memory occupation amount of each detection time point of the target detection object in the set time period.

The detection time point is a time point in a set time period determined according to a preset rule, and the memory occupation amount of the target detection object at the detection time point needs to be acquired every time the application program runs to the detection time point.

Optionally, the preset rule is that a fixed time interval exists between adjacent detection time points, that is, the memory occupation amount of the target detection object is periodically acquired according to the preset time interval in a set time period.

Alternatively, other preset rules may be adopted, for example, a time when the total memory occupation amount of the application to which the target detection object belongs reaches the preset total memory occupation amount threshold is determined as a monitoring time point, that is, the memory occupation amount of the target detection object is obtained each time the total memory occupation amount of the application to which the target detection object belongs reaches the total memory occupation amount threshold in a set time period.

The method for acquiring the memory occupation amount of the target detection object at a certain detection time point is determined according to the application scene and the platform, and the method is not limited to the method. For example, the memory snapshot function of the memory management library may be used to obtain the memory occupation amount of the target detection object, or other software tools for monitoring and recording the memory usage condition may be used to obtain the memory occupation amount of the target detection object.

And A2, counting the memory occupation amount of the target detection object at all detection time points of the set time period according to the time sequence, and generating a memory occupation amount counting sequence of the target detection object in the set time period.

Next, a specific implementation manner of step S101 will be exemplarily described in the case where the memory is managed by using Jemalloc memory management library and the target detection object is a function.

Jemalloc takes over the malloc and free, and increases the memory statistics of each function on the call stack each time memory is allocated for the function of the application program; when the total memory allocation amount of the application program reaches a preset allocation amount threshold value, generating a memory snapshot file at the current moment by utilizing a heap memory snapshot dump function of a Jemalloc memory management library, wherein the memory snapshot file records memory occupation information of each function of the application program at the current moment; analyzing the memory snapshot file by utilizing jeprof tools to generate a txt file recorded with the memory occupation condition of each function of the application program; according to the generated txt file, the memory occupation amount of the target detection object at the current moment can be determined; and counting the memory occupation amount data of the target detection object acquired in a preset time period according to a time sequence to obtain a memory occupation amount counting sequence of the target detection object in the set time period.

S102, sub-sequence division is carried out on the memory occupation amount statistical sequence according to the set sequence length.

The set sequence length may be understood as a length of each sub-sequence set in advance, and when dividing the memory occupation amount statistical sequence, the length is divided. The length of the set sequence can be fixed or dynamically set according to specific requirements.

The sub-sequence division is performed on the memory occupation amount statistical sequence according to the set sequence length, the whole memory occupation amount statistical sequence can be divided into a plurality of continuous sub-sequences, and each sub-sequence comprises memory occupation amount data with the set sequence length, namely memory occupation amount data at a series of time points.

As an optional implementation manner, the sub-sequence division is performed on the memory occupation amount statistical sequence by adopting a method of dividing according to a fixed step length, wherein the step length is the set sequence length. For example, if the sequence length is set to 10, the first 10 memory occupancy data in the memory occupancy statistics sequence is divided into a first sub-sequence, the next 10 memory occupancy data is divided into a second sub-sequence, and so on.

As an optional implementation manner, a sliding window dividing method is adopted to divide the subsequence of the memory occupation amount statistical sequence, wherein the size of the window is the set sequence length. For example, if the sequence length is set to be 10 and the sliding step length is set to be 1, the first 10 pieces of memory occupation amount data in the memory occupation amount statistics sequence are divided into a first subsequence, and the 2 nd to 11 th pieces of memory occupation amount data are divided into a second subsequence. By adopting the sliding window dividing method, the dynamic change of the memory occupation amount of the target detection object can be better captured, more details and changes can be captured, and the detection capability of abnormal behaviors can be improved.

It should be noted that, other related prior arts may be used to implement sub-sequence division of the memory occupation amount statistics sequence according to the set sequence length, which is not limited in the present application.

S103, determining whether the target detection object has memory leakage or not according to the memory change trend corresponding to each divided sub-sequence.

The memory change trend corresponding to a sub-sequence can be understood as the trend of the memory occupation amount in the sub-sequence changing with time. The memory change trend may include a trend of continuous increase, continuous decrease, overall increase, overall decrease, stability maintenance, etc., and the present application is not limited by comparison.

Specifically, after each divided sub-sequence is obtained, a preset first strategy is executed, each sub-sequence is analyzed independently, the memory change trend corresponding to each sub-sequence is determined, after the memory change trend corresponding to each sub-sequence is determined, a preset second strategy is executed, the memory change trend corresponding to each sub-sequence is analyzed comprehensively, and whether the memory leakage occurs to the target detection object is determined.

The first strategy can be understood as a preset processing method for determining the memory change trend of the subsequence. The first strategy may have a plurality of processing modes in actual operation, and may be specifically implemented with reference to related prior art, for example, data fitting is performed on memory occupation amount data in the subsequence, a memory occupation amount function of the subsequence is determined, and a memory change trend of the subsequence is determined through the memory occupation amount function.

The second policy may be understood as a preset processing method for determining whether the target detection object has memory leakage according to the memory change trend corresponding to each sub-sequence. The second policy may have multiple processing manners in actual operation, for example, the second policy may be to calculate a statistical feature of a memory variation trend of all the sub-sequences, and compare the statistical feature with an expected threshold to determine whether there is a memory leak, or determine whether there is a memory leak by using a time sequence analysis method or a machine learning method.

As an alternative implementation, as shown in fig. 2, step S103 may include steps S201-S202:

s201, detecting a first subsequence with the memory change trend being an ascending trend from the divided subsequences.

The memory change trend is an ascending trend, which indicates that the last memory occupation amount sequence value of the first subsequence is larger than the first memory occupation amount sequence value.

Specifically, after each divided sub-sequence is obtained, a preset first strategy is executed, the last memory occupation amount sequence value of each sub-sequence is compared with the first memory occupation amount sequence value of the sub-sequence, and the sub-sequence with the last memory occupation amount sequence value larger than the first memory occupation amount sequence value is determined as the first sub-sequence with the ascending trend.

And S202, determining that the target detection object suffers from memory leakage under the condition that the number of the detected first sub-sequences is larger than a set threshold value.

Optionally, the set threshold may be understood as a preset maximum threshold of the number of the first sub-sequences under the condition that no memory leak occurs, that is, when the number of the first sub-sequences is less than or equal to the preset threshold, the target detection object does not have memory leak, and when the number of the first sub-sequences is greater than the preset threshold, the target detection object has memory leak.

Alternatively, the set threshold may be understood as a preset maximum threshold of the ratio of the number of the first subsequences to the number of all the subsequences in the case that no memory leak occurs. The number of the first subsequences is larger than the set threshold, which is understood to mean that the ratio of the number of the first subsequences to the number of all the subsequences is larger than the set threshold.

As shown in fig. 3, the memory exception detection method provided in this embodiment further includes steps S301 to S302:

S301, in response to a first operation on a target memory block, updating attribute information of the target memory block, wherein the first operation comprises a memory allocation operation and/or a memory release operation, and the attribute information comprises an access prohibition attribute and/or a release prohibition attribute.

The first operation may be understood as an operation related to dynamically managing the target memory block during the running process of the application program, including a memory allocation operation and/or a memory release operation and/or other dynamically managed related operations, such as a memory reclamation operation.

The attribute information may be understood as a specific attribute of the target memory block, and at least includes an access prohibition attribute and/or a release prohibition attribute. And when the attribute information of the target memory block is the access prohibition attribute, indicating that the target memory block is prohibited from performing access operation currently. And when the attribute information of the target memory block is the release prohibition attribute, indicating that the target memory block is prohibited from performing release operation currently.

Specifically, a first mapping relation between a first operation and attribute information to be updated is pre-established, when the first operation is performed on the target memory block, the attribute information to be updated corresponding to the first operation is determined according to a preset first mapping relation in response to the first operation on the target memory block, and the attribute information of the target memory block is updated according to the attribute information to be updated.

S302, triggering a memory exception when a first operation request for the target memory block is received.

The first operation request includes an operation request that does not conform to the attribute information of the target memory block. For example, when the attribute information of the target memory block is the access prohibition attribute, the access request to the target memory block is the first operation request, and when the attribute information of the target memory block is the release prohibition attribute, the release request to the target memory block is the first operation request. The application does not limit the type of the first operation request, and specifically determines according to the actual situation or the attribute information of the target memory block.

Optionally, the memory anomalies include a memory out-of-range access anomaly, a memory repeated release anomaly, a released memory re-access anomaly, and other memory anomalies, which is not limited in the present application.

Specifically, when an operation request for a target memory block is received, whether the operation request accords with the attribute information of the target memory block is judged, and when the operation request does not accord with the attribute information of the target memory block, the memory exception is triggered.

Optionally, the triggering of the memory exception may be generating a prompt message of the memory exception to prompt the relevant staff to timely process the discovery and process the memory exception. The prompt information can be voice prompt, buzzing prompt, lamplight prompt, text prompt and the like.

Optionally, the triggering of the memory exception may be to terminate the operation of the object that initiates the first operation request, so as to achieve the effect that the object that initiates the first operation request crashes in the illegal operation site, and can help the staff to quickly locate the specific location where the memory exception occurs, so that the staff quickly locates and solves the memory exception, and the robustness of the application program and the reliability of the software system are improved. For example, when a first operation request of the application program for the target memory block is received, the application program is crashed in the illegal operation site, and the memory exception can be rapidly located by analyzing the core file generated when the application program crashes.

At present, a manual analysis method is generally adopted for detecting the memory abnormality, and after the memory abnormality causes program crash, a developer analyzes program codes, but because the program cannot crash immediately at the initial stage of the memory abnormality, the program can continue to execute until the influence of the memory error is accumulated to a critical point or crashes when a sensitive operation is triggered, the position of the program crash is caused to have high randomness, and the subsequent manual analysis is extremely difficult.

According to the memory abnormality detection method provided by the embodiment, the attribute information of the target memory block is updated in response to the first operation on the target memory block, and when a first operation request for the target memory block is received, the memory abnormality is triggered, wherein the first operation request comprises an operation request which is inconsistent with the attribute information. The memory abnormality detection method provided by the embodiment can trigger the memory abnormality in time when the memory error occurs, help developers to quickly locate the memory abnormality position, improve the memory abnormality detection efficiency, can be used for detecting various memory abnormalities, is simple to realize, and is easy to develop and deploy in practical application. In addition, the memory exception detection method provided by the embodiment does not need to recompile codes, and has small influence on program performance.

As an optional implementation manner, the first operation includes the memory allocation operation. In this implementation manner, the memory anomaly detection method provided in this embodiment may be used to detect a memory out-of-range access anomaly, as shown in fig. 4, where the detection of the memory out-of-range access anomaly includes steps S401 to S402:

S401, setting access prohibition attribute for a first memory area corresponding to a target memory block in response to memory allocation operation of the target memory block, wherein the first memory area is a preset area located at the boundary of the target memory block.

The first memory region may be configured to set a protection attribute, where the protection attribute includes at least a prohibited access attribute. When the first memory area is set as the access prohibition attribute, the first memory area is the access prohibition area, and the application program is not allowed to access the first memory area.

Optionally, before executing the memory abnormality detection method provided by the embodiment of the present application, the target memory block is divided into at least two areas in advance, that is, the target memory block includes at least a first memory area and a storage area. The storage area is used for storing instructions, variables, data structures and the like of programs, and can be accessed and operated on during operation. The first memory region is a reserved region which is located at a target memory block boundary and is different from the storage region, and the target memory block boundary can be a target memory block front end boundary and/or a target memory block rear end boundary. Preferably, the first memory areas of all the memory blocks are located at the same side boundary of the associated memory block.

Optionally, when the target memory block is allocated to the application program, a protection page is additionally reserved at the front end and/or the rear end of the target memory block, where the protection page is the first memory area located at the boundary of the target memory block.

Specifically, when memory allocation operation is performed on the target memory block, that is, the target memory block is allocated to the application program, according to a preset first mapping relationship, it is determined that attribute information to be updated corresponding to the memory allocation operation is a first memory area access prohibition attribute, and the access prohibition attribute is set for the first memory area corresponding to the target memory block.

Alternatively, setting the access prohibition attribute for the first memory area may be setting an inaccessible flag at the boundary of the first memory area.

Optionally, the protection attribute of the first memory region is set to the access-prohibited attribute using an mpprotect () function.

And S402, triggering memory out-of-range access exception and controlling the first function to terminate operation when an access request of the first function to a first memory area corresponding to the target memory block is received.

Memory out-of-bound access exceptions may be understood as applications that, when accessing a target memory block, are beyond the boundaries of the allocated memory block, meaning that the program attempts to read or write to memory locations that are outside of the effectively allocated memory block. Memory out-of-range errors can cause program crashes, data corruption, and even security vulnerabilities.

Specifically, when an access request of a first function of an application program to a first memory area corresponding to a target memory block is received, it can be determined that the application program tries to access an access forbidden area outside a normal memory area of the target memory block, and a memory out-of-range access behavior is generated.

As an optional implementation manner, the first operation includes the memory release operation. In this implementation manner, the memory exception detection method provided in this embodiment may detect a memory repeated release exception, as shown in fig. 5, where the detection of the memory repeated release exception includes steps S501 to S502:

S501, setting release inhibition attribute for a target memory block in response to memory release operation of the target memory block.

Specifically, when performing a memory release operation on a target memory block, determining attribute information to be updated corresponding to the memory release operation as a target memory block release inhibition attribute according to a preset first mapping relationship, and setting the release inhibition attribute for the target memory block.

Optionally, setting the release prohibition attribute for the target memory block may be setting a release prohibition flag in the target memory block. Alternatively, a release-prohibited flag may be set at the head position of the target memory block.

S502, triggering the repeated memory release exception when a release request of the second function to the target memory block is received, and controlling the second function to stop running.

A memory repeated release exception may be understood as an erroneous operation of releasing the same memory block multiple times in the application program, which means that the application program tries to perform the release operation again on the memory block that has been released. Repeated release of memory exceptions can disrupt the state of the memory management system, resulting in memory corruption or other unpredictable behavior.

Specifically, when the attribute information of the target memory block is the release prohibition attribute, it is indicated that the target memory block is released, in this state, when a release request of the second function of the application program to the target memory block is received, it can be determined that the second function of the application program tries to execute the release operation again on the target memory block, so that a memory repeated release behavior is generated, at the same time, the memory repeated release abnormality is triggered, and meanwhile, the second function is controlled to terminate operation, so that the application program crashes on the site of the memory repeated release, thereby helping a developer to quickly locate the position of the memory repeated release abnormality and improving the detection efficiency of the memory repeated release abnormality.

As an alternative implementation manner, the detection of the repeated release exception of the memory may further include steps B1-B2:

b1, responding to the memory release operation of the target memory block, and placing the target memory block in a first waiting queue.

And B2, removing the target memory block from the first waiting queue and clearing the release inhibition attribute of the target memory block when a preset first queue clearing strategy is met.

The first waiting queue may be understood as a data structure for storing memory blocks waiting to be released.

The first queue clean-up policy may be understood as a preset rule for determining when to remove a target memory block from the first waiting queue. The first queue cleaning policy may be determined based on different factors, such as queue length, queue storage time, etc. Optionally, the first queue cleaning policy is to remove a memory block that first enters the first waiting queue when the maximum queue length is reached, and satisfying the first queue cleaning policy may be understood that the target memory block is a memory block with the longest storage time in the first waiting queue, and the queue length of the first waiting queue reaches the maximum queue length.

Specifically, when the memory release operation is performed on the target memory block, the target memory block is not released immediately, but is placed in the first waiting queue, a release inhibition attribute is set for the target memory block, until the target memory block meets a preset first queue cleaning policy, the target memory block is moved out of the first waiting queue, the target memory block is released, and the release inhibition attribute of the target memory block is cleared.

In this implementation manner, step S502 "when receiving a release request of the second function for the target memory block, triggers a repeated memory release exception, and controls the second function to terminate operation", including:

As an alternative implementation manner, the first operation includes a memory release operation. In this implementation manner, the memory exception detection method provided in this embodiment may detect a released memory revisit exception, as shown in fig. 6, where the detection of the released memory revisit exception includes steps S601-S602:

S601, setting access prohibition attribute for a target memory block in response to memory release operation of the target memory block.

Specifically, when the memory release operation is performed on the target memory block, according to a preset first mapping relationship, determining that attribute information to be updated corresponding to the memory release operation is an access prohibition attribute of the target memory block, and setting the access prohibition attribute for the target memory block.

Optionally, the access prohibition attribute is set for the target memory block, which may be that a flag for prohibiting access is set in the target memory block.

Alternatively, the entire target memory block may be set to an inaccessible state using the mpprotect () function.

And S602, triggering the released memory to access the exception again when an access request of the third function to the target memory block is received, and controlling the third function to terminate operation.

A released memory re-access exception may be understood as a faulty operation of an application program to access a memory block that has been released by it, possibly resulting in data corruption or other unpredictable behavior.

Specifically, when the whole target memory block is in the access prohibition state and an access request of the third function of the application program to the target memory block is received, it can be determined that the third function of the application program tries to execute access operation to the target memory block, a released memory revisitation behavior is generated, at the moment, the released memory revisitation abnormality is triggered, and meanwhile, the third function is controlled to terminate operation, so that the application program crashes on the site of the released memory revisitation, a developer is helped to quickly locate the position of the released memory revisitation abnormality, and the detection efficiency of the released memory revisitation abnormality is improved.

As an alternative implementation, the detection of the released memory re-access exception may further include steps C1-C2:

c1, responding to the memory release operation of the target memory block, and placing the target memory block in a second waiting queue.

And C2, removing the target memory block from the second waiting queue and clearing the access prohibition attribute of the target memory block when a preset second queue clearing strategy is met.

The second waiting queue may be understood as a data structure for storing memory blocks that have been freed, the memory blocks in the queue being set to the access-prohibited attribute.

The second queue clean-up policy may be understood as a preset rule for determining when to remove a target memory block from the second wait queue. The second queue cleaning policy may be determined based on different factors, such as queue length, queue storage time, etc.

Specifically, after the target memory block is released, setting access prohibition attribute for the target memory block, and placing the target memory block in a second waiting queue until the target memory block meets a preset second queue cleaning policy, removing the target memory block from the second waiting queue, and simultaneously clearing the access prohibition attribute of the target memory block.

In this implementation, step S602 "when an access request of the third function to the target memory block is received, triggering the released memory access exception again, and controlling the third function to terminate operation" includes:

Exemplary apparatus

Corresponding to the memory abnormality detection method, the embodiment of the application also provides a memory abnormality detection device. Fig. 7 is a schematic structural diagram of a memory abnormality detection device according to an embodiment of the present application, where, as shown in fig. 7, the memory abnormality detection device according to an embodiment of the present application includes:

a first unit 701, configured to obtain a memory occupation amount statistics sequence of a target detection object in a set period of time;

A second unit 702, configured to perform sub-sequence division on the memory occupation amount statistics sequence according to a set sequence length;

and a third unit 703, configured to determine whether the target detection object has memory leakage according to the memory variation trend corresponding to each of the divided sub-sequences.

Optionally, the third unit 703 may be specifically configured to:

According to the memory anomaly detection device provided by the application, firstly, a first unit 701 is used for obtaining a memory occupation amount statistical sequence of a target detection object in a set time period, then a second unit 702 is used for carrying out sub-sequence division on the memory occupation amount statistical sequence according to a set sequence length, and finally a third unit 703 is used for determining whether the target detection object has memory leakage according to the memory change trend corresponding to each divided sub-sequence.

The memory anomaly detection device provided by the application can observe the memory time sequence change of the target detection object, eliminate misjudgment on memory leakage detection caused by memory fluctuation, improve the detection accuracy, realize real-time automatic detection of memory leakage, reduce the labor cost and improve the detection efficiency.

Optionally, the apparatus further includes:

A fourth unit, configured to update attribute information of a target memory block in response to a first operation on the target memory block, where the first operation includes a memory allocation operation and/or a memory release operation, and the attribute information includes at least one of an access prohibition attribute and a release prohibition attribute;

And a fifth unit, configured to trigger a memory exception when a first operation request for the target memory block is received, where the first operation request includes an operation request that does not conform to the attribute information.

Optionally, the first operation includes the memory allocation operation;

the fourth unit may be specifically configured to:

the fifth unit may be specifically configured to:

Optionally, the first operation includes the memory release operation;

the fourth unit may be specifically configured to:

the fifth unit may be specifically configured to:

Optionally, the apparatus further includes:

A sixth unit, configured to respond to a memory release operation on a target memory block, and place the target memory block in a first waiting queue; when a preset first queue cleaning strategy is met, removing the target memory block from the first waiting queue, and clearing the release inhibition attribute of the target memory block;

the fifth unit may be specifically configured to:

Optionally, the first operation includes the memory release operation;

the fourth unit may be specifically configured to:

the fifth unit may be specifically configured to:

Optionally, the apparatus further includes:

A seventh unit, configured to respond to a memory release operation on a target memory block, and place the target memory block in a second waiting queue; removing the target memory block from the second waiting queue and clearing the access prohibition attribute of the target memory block when a preset second queue clearing strategy is met;

the fifth unit may be specifically configured to:

The memory abnormality detection device provided in this embodiment belongs to the same application concept as the memory abnormality detection method provided in the foregoing embodiment of the present application, and may execute the memory abnormality detection method provided in any of the foregoing embodiments of the present application, and has a functional module and beneficial effects corresponding to executing the memory abnormality detection method. Technical details not described in detail in this embodiment may be referred to the specific processing content of the memory abnormality detection method provided in the foregoing embodiment of the present application, and will not be described herein.

The functions performed by the first unit 701, the second unit 702, and the third unit 703 may be implemented by the same or different processors, respectively, and embodiments of the present application are not limited.

It will be appreciated that the elements of the above apparatus may be implemented in the form of processor-invoked software. For example, the device includes a processor, where the processor is connected to a memory, and the memory stores instructions, and the processor invokes the instructions stored in the memory to implement any of the methods above or to implement functions of each unit of the device, where the processor may be a general-purpose processor, such as a CPU or a microprocessor, and the memory may be a memory within the device or a memory outside the device. Or the units in the device may be implemented in the form of hardware circuits, and the functions of some or all of the units may be implemented by designing a hardware circuit, where the hardware circuit may be understood as one or more processors; for example, in one implementation, the hardware circuit is an ASIC, and the functions of some or all of the above units are implemented by designing the logic relationships of the elements in the circuit; for another example, in another implementation, the hardware circuit may be implemented by a PLD, for example, an FPGA may include a large number of logic gates, and the connection relationship between the logic gates is configured by a configuration file, so as to implement the functions of some or all of the above units. All units of the above device may be realized in the form of processor calling software, or in the form of hardware circuits, or in part in the form of processor calling software, and in the rest in the form of hardware circuits.

In an embodiment of the present application, the processor is a circuit with signal processing capability, and in an implementation, the processor may be a circuit with instruction reading and running capability, such as a CPU, a microprocessor, a GPU, or a DSP, etc.; in another implementation, the processor may implement a function through a logical relationship of hardware circuitry that is fixed or reconfigurable, e.g., a hardware circuit implemented by the processor as an ASIC or PLD, such as an FPGA, or the like. In the reconfigurable hardware circuit, the processor loads the configuration document, and the process of implementing the configuration of the hardware circuit may be understood as a process of loading instructions by the processor to implement the functions of some or all of the above units. Furthermore, a hardware circuit designed for artificial intelligence may be provided, which may be understood as an ASIC, such as NPU, TPU, DPU, etc.

It will be seen that each of the units in the above apparatus may be one or more processors (or processing circuits) configured to implement the above method, for example: CPU, GPU, NPU, TPU, DPU, microprocessors, DSP, ASIC, FPGA, or a combination of at least two of these processor forms.

Furthermore, the units in the above apparatus may be integrated together in whole or in part, or may be implemented independently. In one implementation, these units are integrated together and implemented in the form of an SOC. The SOC may include at least one processor for implementing any of the methods above or for implementing the functions of the units of the apparatus, where the at least one processor may be of different types, including, for example, a CPU and an FPGA, a CPU and an artificial intelligence processor, a CPU and a GPU, and the like.

Exemplary electronic device

Another embodiment of the present application also proposes an electronic device, as shown in fig. 8, including:

a memory 200 and a processor 210;

Wherein the memory 200 is connected to the processor 210, and is used for storing a program;

The processor 210 is configured to implement the memory exception detection method disclosed in any one of the above embodiments by running the program stored in the memory 200.

Specifically, the electronic device may further include: a bus, a communication interface 220, an input device 230, and an output device 240.

The processor 210, the memory 200, the communication interface 220, the input device 230, and the output device 240 are interconnected by a bus. Wherein:

A bus may comprise a path that communicates information between components of a computer system.

Processor 210 may be a general-purpose processor, such as a general-purpose Central Processing Unit (CPU), microprocessor, etc., or may be an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of programs in accordance with aspects of the present invention. But may also be a Digital Signal Processor (DSP), application Specific Integrated Circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components.

Processor 210 may include a main processor, and may also include a baseband chip, modem, and the like.

The memory 200 stores programs for implementing the technical scheme of the present invention, and may also store an operating system and other key services. In particular, the program may include program code including computer-operating instructions. More specifically, memory 200 may include read-only memory (ROM), other types of static storage devices that may store static information and instructions, random access memory (random access memory, RAM), other types of dynamic storage devices that may store information and instructions, disk storage, flash, and the like.

The input device 230 may include means for receiving data and information entered by a user, such as a keyboard, mouse, camera, scanner, light pen, voice input device, touch screen, pedometer, or gravity sensor, among others.

Output device 240 may include means, such as a display screen, printer, speakers, etc., that allow information to be output to a user.

The communication interface 220 may include devices using any transceiver or the like for communicating with other devices or communication networks, such as ethernet, radio Access Network (RAN), wireless Local Area Network (WLAN), etc.

The processor 210 executes the program stored in the memory 200 and invokes other devices, which may be used to implement the steps of any of the memory anomaly detection methods provided in the above embodiments of the present application.

The embodiment of the application also provides a chip, which comprises a processor and a data interface, wherein the processor reads and runs a program stored in a memory through the data interface so as to execute the memory abnormality detection method introduced in any embodiment, and the specific processing process and the beneficial effects thereof can be introduced by referring to the embodiment of the memory abnormality detection method.

Exemplary computer program product and storage Medium

In addition to the methods and apparatus described above, embodiments of the application may also be a computer program product comprising computer program instructions which, when executed by a processor, cause the processor to perform the steps in a memory anomaly detection method according to various embodiments of the application described in any of the embodiments of the specification.

The computer program product may write program code for performing operations of embodiments of the present application in any combination of one or more programming languages, including an object oriented programming language such as Java, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server.

Furthermore, an embodiment of the present application may also be a storage medium having stored thereon a computer program that is executed by a processor to perform the steps in the memory abnormality detection method according to various embodiments of the present application described in any of the above embodiments of the present specification, and specifically may implement the steps of:

For the foregoing method embodiments, for simplicity of explanation, the methodologies are shown as a series of acts, but one of ordinary skill in the art will appreciate that the present application is not limited by the order of acts, as some steps may, in accordance with the present application, occur in other orders or concurrently. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily required for the present application.

It should be noted that, in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described as different from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other. For the apparatus class embodiments, the description is relatively simple as it is substantially similar to the method embodiments, and reference is made to the description of the method embodiments for relevant points.

The steps in the method of each embodiment of the application can be sequentially adjusted, combined and deleted according to actual needs, and the technical features described in each embodiment can be replaced or combined.

The modules and the submodules in the device and the terminal of the embodiments of the application can be combined, divided and deleted according to actual needs.

In the embodiments provided in the present application, it should be understood that the disclosed terminal, apparatus and method may be implemented in other manners. For example, the above-described terminal embodiments are merely illustrative, and for example, the division of modules or sub-modules is merely a logical function division, and there may be other manners of division in actual implementation, for example, multiple sub-modules or modules may be combined or integrated into another module, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or modules, which may be in electrical, mechanical, or other forms.

The modules or sub-modules illustrated as separate components may or may not be physically separate, and components that are modules or sub-modules may or may not be physical modules or sub-modules, i.e., may be located in one place, or may be distributed over multiple network modules or sub-modules. Some or all of the modules or sub-modules may be selected according to actual needs to achieve the purpose of the embodiment.

In addition, each functional module or sub-module in the embodiments of the present application may be integrated in one processing module, or each module or sub-module may exist alone physically, or two or more modules or sub-modules may be integrated in one module. The integrated modules or sub-modules may be implemented in hardware or in software functional modules or sub-modules.

Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software unit executed by a processor, or in a combination of the two. The software elements may be disposed in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. The memory abnormality detection method is characterized by comprising the following steps:

2. The method of claim 1, wherein determining whether the target detection object has a memory leak according to the memory change trend corresponding to each of the divided sub-sequences, comprises:

3. The method according to claim 1 or 2, characterized in that the method further comprises:

Updating attribute information of a target memory block in response to a first operation on the target memory block, wherein the first operation comprises a memory allocation operation and/or a memory release operation, and the attribute information at least comprises an access prohibition attribute and/or a release prohibition attribute;

4. The method of claim 3, wherein the first operation comprises the memory allocation operation;

5. The method of claim 3, wherein the first operation comprises the memory release operation;

6. The method of claim 5, wherein the method further comprises:

7. The method of claim 3, wherein the first operation comprises the memory release operation;

8. The method of claim 7, wherein the method further comprises:

9. A memory abnormality detection apparatus, comprising:

10. An electronic device comprising a memory and a processor;

The memory is connected with the processor and used for storing programs;

The processor is configured to implement the memory abnormality detection method according to any one of claims 1 to 8 by running a program in the memory.

11. A storage medium having a computer program stored thereon, which when executed by a processor, implements the memory anomaly detection method according to any one of claims 1 to 8.