CN117971157A - Carry logic circuit - Google Patents
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Abstract
The application discloses a carry logic circuit, and relates to the technical field of integrated circuits. Comprising the following steps: the first signal input end and the second signal input end of each carry logic processing module are used for inputting cascade input signals of corresponding levels, the third signal input end and the fourth signal input end are used for inputting cascade input signals of the previous levels, the carry input end is used for being connected with carry output ends of the previous two levels, and the arithmetic output ends and the carry output ends are respectively used for outputting arithmetic results and carry results of the corresponding levels. Each carry logic processing module can generate an arithmetic output signal and a carry output signal of a corresponding level based on cascade input signals of the corresponding level and the previous level and carry output signals of the previous two levels, so that carry delay is reduced in a cascade mode of a plurality of carry logic processing modules of a previous level, and the service performance of a carry logic circuit is improved.
Description
Technical Field
The present application relates to the field of integrated circuits, and in particular, to a carry logic circuit.
Background
With the rapid development of integrated circuits, a carry circuit is used as a key component of various high-performance computing modules or systems, and after logic operation processing is performed on input signals by using a plurality of carry devices, the carry signal can be transferred to a next-stage carry device of the carry circuit with smaller delay. However, after a plurality of carry devices are cascaded, the number of the carry devices in cascade is increased along with the increase of the operation digital width, so that the carry chain is too long, the carry delay introduced when the carry circuit processes the data of the operand is larger, and finally the data processing and the real-time performance of the carry circuit are not high.
Disclosure of Invention
The application provides a carry logic circuit, which comprises a plurality of cascade carry logic processing modules, wherein the plurality of carry logic processing modules are in one-to-one correspondence with cascade input signals of multiple stages, and each carry logic processing module is used for carrying out target logic operation on the cascade input signals of the corresponding stages of each carry logic processing module; each carry logic processing module comprises a carry input end, a carry output end, an arithmetic output end and a plurality of signal input ends, wherein the plurality of signal input ends at least comprise a first signal input end, a second signal input end, a third signal input end and a fourth signal input end; the first signal input end and the second signal input end of each carry logic processing module are used for inputting cascade input signals of a corresponding level of each carry logic processing module, the third signal input end and the fourth signal input end of each first logic processing module are respectively and correspondingly connected with the first signal input end and the second signal input end of a carry logic processing module of a previous level, the arithmetic output end of each carry logic processing module is used for outputting an arithmetic result of performing the target logic operation by the cascade input signals of the corresponding level of each carry logic processing module, and the first logic processing module is any carry logic processing module of any level except the carry logic processing module of the first level among the carry logic processing modules; the carry input end of each second logic processing module is used for being connected with the carry output ends of the carry logic processing modules of the previous two levels, the carry output end of each carry logic processing module is used for outputting a cascade input signal of the corresponding level of each carry logic processing module to carry out a carry result of the target logic operation, and the second logic processing module is any one level of carry logic processing module except the first level and the second level of carry logic processing modules in the plurality of carry logic processing modules.
The carry logic circuit provided by the embodiment of the application comprises a plurality of cascade carry logic processing modules, wherein each carry logic processing module is arranged to receive cascade input signals of corresponding stages and is connected with the signal input end of the carry logic processing module of the previous stage and the carry output ends of the carry logic processing modules of the previous two stages, and each carry logic processing module can generate arithmetic output signals and carry output signals of corresponding stages based on cascade input signals of the corresponding stages and the previous stages and carry output signals of the previous two stages. Based on the method, each carry logic processing module only needs to be cascaded with the carry logic processing module of the next level, and the carry logic processing module of the adjacent level of each carry logic processing module can be omitted from being cascaded in the carry chain, so that the length of the carry chain formed by the cascaded carry logic processing modules is reduced under the condition of increasing the operation digital width, the carry delay is further reduced, and the data processing and operation instantaneity of the carry logic circuit are improved; meanwhile, a carry chain is formed by cascading a plurality of carry logic processing modules at one level, so that the carry logic circuit completes data processing of each level of the carry logic circuit in a manner of forming two carry chains under the condition that the number of the carry logic processing modules used is unchanged, the carry delay of each carry chain is reduced, and the use performance of the carry logic circuit is improved.
These and other aspects of the application will be more readily apparent from the following description of the embodiments.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram illustrating a carry logic circuit according to an embodiment of the application.
Fig. 2 is a schematic diagram illustrating a structure of a carry logic processing module according to an embodiment of the application.
Fig. 3 is a schematic diagram illustrating a structure of a carry logic processing module according to another embodiment of the present application.
Fig. 4 is a schematic diagram illustrating a carry logic circuit according to another embodiment of the present application.
Fig. 5 is a schematic diagram illustrating a structure of a carry logic processing module according to another embodiment of the present application.
Detailed Description
In order to enable those skilled in the art to better understand the present application, a clear and complete description of the technical solution in the present embodiment will be provided below with reference to the accompanying drawings in the present embodiment. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The terms "first," "second," and the like in this disclosure are used for distinguishing between different objects and not for describing a particular sequential order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
Referring to fig. 1, fig. 1 is a schematic diagram illustrating a carry logic circuit 1 according to an embodiment of the application. The carry logic circuit 1 provided in the embodiment of the present application will be described in detail with reference to fig. 1. As shown in fig. 1, the carry logic circuit 1 of the present application includes a plurality of cascaded carry logic processing modules 10.
Optionally, the plurality of carry logic processing modules 10 are in one-to-one correspondence with the cascade input signals of the multiple stages, and each carry logic processing module 10 is configured to perform a target logic operation on the cascade input signal of the corresponding stage of each carry logic processing module 10. Each carry logic processing module 10 includes a Carry Input (CIN), a Carry Output (COUT), an arithmetic output (Z), and a plurality of signal inputs including at least a first signal input (I0), a second signal input (I1), a third signal input (I2), and a fourth signal input (I3).
In this embodiment, the first signal input end (I0) and the second signal input end (I1) of each carry logic processing module 10 are used for inputting cascade input signals of a corresponding level of each carry logic processing module 10, the third signal input end (I2) and the fourth signal input end (I3) of each first logic processing module are respectively connected with the first signal input end (I0) and the second signal input end (I1) of a previous level of carry logic processing module 10 correspondingly, the arithmetic output end (Z) of each carry logic processing module 10 is used for outputting an arithmetic result of a target logic operation by the cascade input signals of a corresponding level of each carry logic processing module 10, the first logic processing module is any level of carry logic processing modules 10 except for the carry logic processing module 10 of the first level, and the arithmetic output end (Z) of each carry logic processing module 10 at least comprises an arithmetic output signal. The carry logic circuit 1 of the present application may perform logic processing such as integer addition, integer subtraction, or digital comparison, and is not limited herein.
Specifically, each of the plurality of cascaded carry logic processing modules 10 is configured to receive the cascade input signal of its corresponding stage and the cascade input signal of its previous stage, except for the first stage of carry logic processing modules 10. For example, the carry logic processing module 10 of the second level is configured to receive the cascade input signal of the second level and the cascade input signal of the first level; the third-level carry logic processing module 10 is configured to receive the third-level cascade input signal and the second-level cascade input signal.
In this embodiment, the carry input terminal (CIN) of each second logic processing module is used to connect with the carry output terminal (COUT) of the carry logic processing module 10 of the previous two stages, the carry output terminal (COUT) of each carry logic processing module 10 is used to output the carry result of the target logic operation performed by the cascade input signal of the corresponding stage of each carry logic processing module 10, and the second logic processing module is any one stage of carry logic processing modules 10 except the first stage and the second stage of carry logic processing modules 10 of the plurality of carry logic processing modules 10. The carry result output by the carry output terminal (COUT) of each carry logic processing module 10 at least includes a carry output signal.
Specifically, in addition to the first-level and second-level carry logic processing modules 10 in the plurality of cascaded carry logic processing modules 10, the carry input terminal (CIN) of each odd-level carry logic processing module 10 is used for being connected with the carry output terminal (COUT) of the carry logic processing module 10 of the previous odd-level, and the carry input terminal (CIN) of each even-level carry logic processing module 10 is used for being connected with the carry output terminal (COUT) of the carry logic processing module 10 of the previous even-level. For example, the Carry Input (CIN) of the third level of carry logic processing module 10 is for connection with the Carry Output (COUT) of the first level of carry logic processing module 10, and the Carry Input (CIN) of the fourth level of carry logic processing module 10 is for connection with the Carry Output (COUT) of the second level of carry logic processing module 10.
In this embodiment, the cascade input signal includes a first cascade input signal and a second cascade input signal, the first signal input terminal (I0) is used for inputting the first input signal, the second signal input terminal (I1) is used for inputting the second input signal, the third signal input terminal (I2) is used for inputting the third input signal, and the fourth signal input terminal (I3) is used for inputting the fourth input signal; the first input signal and the third input signal are cascade input signals of adjacent levels in the first cascade input signal, the second input signal and the fourth input signal are cascade input signals of adjacent levels in the second cascade input signal, the first input signal corresponds to the level of the second input signal, and the third input signal corresponds to the level of the fourth input signal; each carry logic processing module 10 is configured to perform a target logic operation on the first cascade input signal and the second cascade input signal of the corresponding hierarchy, and generate a carry output signal and an arithmetic output signal of the corresponding hierarchy of each carry logic processing module 10.
It should be noted that the first signal input (I0) and the second signal input (I1) of the first-level carry logic processing module 10 are used for inputting the cascade input signal of the first level, and the Carry Input (CIN) of the first-level and the second-level carry logic processing module 10 are both used for receiving the initial carry input signal.
Based on the cascade connection, two carry chains are formed in the carry logic circuit 1 according to the embodiment of the present application, and each carry logic processing module 10 is capable of performing a target logic operation based on the cascade input signal of its corresponding level, the cascade input signal of its previous level, and the carry output signals of the carry logic processing modules 10 of its previous two levels, so as to generate a carry output signal and an arithmetic output signal of each carry logic processing module 10 of the corresponding level. Since each carry logic processing module 10 in each carry chain can implement the arithmetic operation and the carry operation of two adjacent levels, each carry logic processing module 10 can output the arithmetic output signal and the carry output signal of the corresponding level. In addition, when each carry logic processing module 10 in each carry chain completes carry operation, carry look-ahead is realized relative to the carry logic processing modules 10 of the previous two levels connected with the carry input end (CIN), and carry output of each carry logic processing module 10 is not directly dependent on the carry logic processing module 10 of the previous level, so that the effect of quick carry is realized. Therefore, compared with the conventional cascade connection mode of a plurality of 1-bit carry logic processors, the cascade connection mode of the plurality of carry logic processing modules 10 in the application forms two carry chains, and the carry chain length is halved under the condition that the number of the used carry logic processing modules 10 is unchanged, so that the carry delay is reduced. In addition, compared with the conventional cascade connection mode of 1-bit carry logic processors, each carry logic processing module 10 in the carry logic circuit 1 of the embodiment utilizes more ports, and improves the port utilization rate while reducing carry delay.
As an embodiment, the carry logic circuit 1 includes an odd carry chain including a cascade of a first-level carry logic processing module 10, a third-level carry logic processing module 10, a fifth-level carry logic processing module 10, a 2 n-1-th-level carry logic processing module 10, and an even carry chain including a cascade of a second-level carry logic processing module 10, a fourth-level carry logic processing module 10, a sixth-level carry logic processing module 10, a.i., a 2 n-th-level carry logic processing module 10, n being a positive integer.
Specifically, in the odd carry chain, the first-stage carry logic processing module 10 is configured to receive the cascade input signal and the initial carry input signal of the first stage, and generate the first-stage arithmetic output signal and the first-stage carry output signal output to the carry input terminal (CIN) of the third-stage carry logic processing module 10 through the target logic operation; the third-level carry logic processing module 10 is configured to receive the second-level cascade input signal, the third-level cascade input signal, and the first-level carry output signal, and generate a third-level arithmetic output signal and a third-level carry output signal output to a carry input terminal (CIN) of the fifth-level carry logic processing module 10 through the target logic operation; the logic operation manner of the other odd-level carry logic processing modules 10 can refer to the odd-level carry logic processing modules 10, and will not be described herein.
Specifically, in the even carry chain, the second-level carry logic processing module 10 is configured to receive the first-level cascade input signal, the second-level cascade input signal, and the initial carry input signal, and generate, through the target logic operation, the second-level arithmetic output signal and the second-level carry output signal output to the carry input terminal (CIN) of the fourth-level carry logic processing module 10; the fourth-level carry logic processing module 10 is configured to receive the third-level cascade input signal, the fourth-level cascade input signal, and the second-level carry output signal, and generate the fourth-level arithmetic output signal and the fourth-level carry output signal output to the carry input terminal (CIN) of the sixth-level carry logic processing module 10 through the target logic operation, and the logic operation manner of the remaining even-level carry logic processing modules 10 can refer to the foregoing even-level carry logic processing module 10, which is not described herein again.
In the embodiment of the present application, the carry logic circuit 1 includes a plurality of cascaded carry logic processing modules 10, and each carry logic processing module 10 is configured to receive the cascade input signals of its corresponding stage and is connected to the signal input terminal of the carry logic processing module 10 of its previous stage and the carry output terminals of the carry logic processing modules 10 of its previous two stages, and each carry logic processing module 10 is capable of generating the arithmetic output signals of its corresponding stage and the carry output signals based on the cascade input signals of its corresponding stage and the previous stage and the carry output signals of its previous two stages. Based on the above, each carry logic processing module 10 is only required to be cascaded with the carry logic processing module 10 of a level which is separated from the carry logic processing module 10, and the carry logic processing module 10 of the adjacent level of each carry logic processing module 10 can be omitted from being cascaded in the carry chain, so that the length of the carry chain formed by the cascaded carry logic processing modules 10 is reduced under the condition of increasing the operation digital width, the carry delay is further reduced, and the data processing and operation instantaneity of the carry logic circuit are improved; meanwhile, a carry chain is formed by cascading a plurality of carry logic processing modules 10 at one level, so that the carry logic circuit 1 completes data processing of each level of the carry logic circuit 1 by forming two carry chains under the condition that the number of the carry logic processing modules 10 used is unchanged, the carry delay of each carry chain is reduced, and the use performance of the carry logic circuit 1 is improved.
Referring to fig. 2, fig. 2 is a schematic diagram illustrating a carry logic processing module 10 according to an embodiment of the application. As shown in fig. 2, the carry logic processing module 10 of the present embodiment includes a carry logic operation unit 20 and an arithmetic logic operation unit 30.
In this embodiment, the carry logic operation unit 20 includes at least five input terminals and one output terminal, the five input terminals of the carry logic operation unit 20 are respectively connected to the first signal input terminal, the second signal input terminal, the third signal input terminal, the fourth signal input terminal and the carry input terminal, and the output terminal of the carry logic operation unit 20 is used for being connected to the carry output terminal. The carry logic operation unit 20 is configured to perform carry logic operation according to the first input signal, the second input signal, the third input signal, the fourth input signal, and the carry input signal, and generate a carry output signal for output.
Optionally, the arithmetic logic unit 30 includes at least five input terminals and one output terminal, the five input terminals of the arithmetic logic unit 30 are respectively connected to the first signal input terminal, the second signal input terminal, the third signal input terminal, the fourth signal input terminal and the carry input terminal, and the output terminal of the arithmetic logic unit 30 is configured to be connected to the arithmetic output terminal. The arithmetic logic unit 30 is configured to perform an arithmetic logic operation according to the first input signal, the second input signal, the third input signal, the fourth input signal, and the carry input signal, and generate an arithmetic output signal for output.
In the present embodiment, the carry logic operation unit 20 includes at least a first lookup table 21, a second lookup table 22, and a first selector 23. Each of the lookup tables used in the present application may be at least four-input, five-input, and six-input lookup tables, which are not limited herein.
Optionally, the first lookup table 21 includes a first output end and at least four first input ends, at least four first input ends of the first lookup table 21 are respectively connected to the first signal input end, the second signal input end, the third signal input end and the fourth signal input end, and the first lookup table 21 is configured to determine a carry transfer signal (Propagate) according to the first input signal, the second input signal, the third input signal and the fourth input signal by using a carry transfer operation strategy in the target logic operation. Wherein, when the carry logic circuit is applied to the addition logic operation, the boolean expression for implementing the first lookup table 21 is:
Propagate＝(Ai+1∧Bi+1)&(Ai∧Bi)；
Wherein a i and B i respectively represent the addend and the summand of the previous level of each carry logic processing module 10, i.e. the cascade input signal of the lower level; a i+1 and B i+1 respectively represent an addend and an summand of a corresponding level of each carry logic processing module 10, that is, a cascade input signal of a higher level; "≡" is exclusive or operator; "≡" is bit and operator.
Specifically, the exclusive or result of a i+1 and B i+1 is used to characterize the sum result of a i+1 and B i+1, which does not include a carry result, and thus corresponds to a carry-free addition result. That is, when only one of a i+1 and B i+1 is logic 1, the exclusive or result of a i+1 and B i+1 is logic 1; when A i+1 and B i+1 are both logic 0, the exclusive OR result of A i+1 and B i+1 is logic 0; when both a i+1 and B i+1 are logic 1, a i+1 and B i+1 are added to generate a carry, and the addition result without carry is 0, so that the exclusive-or result of a i+1 and B i+1 is logic 0, and the exclusive-or result of a i and B i is equivalent to the summation result of a i and B i.
Further, the bit and operation of (a i+1∧Bi+1) and (a i∧Bi) is used to determine whether the summation result of a i+1 and B i+1 and the summation result of a i and B i are both logic 1, and the addition of the summand and the summand of each of the two adjacent levels does not generate a carry, and the bit and result of (a i+1∧Bi+1) and (a i∧Bi) are logic 1. When the summand and the summand of any one of the two adjacent levels add to produce a carry, the bit sum result of (a i+1∧Bi+1) and (a i∧Bi) is a logic 0.
Optionally, the second lookup table 22 includes a second output end and at least four second input ends, where the at least four second input ends of the second lookup table 22 are connected to the first signal input end, the second signal input end, the third signal input end and the fourth signal input end, respectively, and the second lookup table 22 is configured to utilize a carry generation operation strategy in the target logic operation, and determine a carry generation signal (generation) according to the first input signal, the second input signal, the third input signal and the fourth input signal. Wherein, when the carry logic circuit is applied to the addition logic operation, the boolean expression for the second lookup table 22 is:
Generate＝Ai+1∧Bi+1?(Ai∧Bi?0:Bi):Bi+1；
Wherein, "? A conditional operator, for example, in a ∈ba: b, if the exclusive OR result of a and b is logic 1, then assign a to the output value; if the exclusive OR result of a and b is logic 1, then b is assigned to the output value.
Specifically, the conditional operation result of a i∧Bi?0:Bi is used to represent the carry results of a i and B i, that is, when both a i and B i are logic 0 or only one of a i and B i is logic 1, no carry is generated after the addition of a i and B i, and the conditional operation result of a i∧Bi?0:Bi is logic 0; when A i and B i are both logic 1, A i and B i are added to generate carry, and the conditional operation result of A i∧Bi?0:Bi is logic 1.
Further, the exclusive or result of a i+1∧Bi+1 is a logic 1, that is, when a i+1 and B i+1 in the upper bits are added to 1 but do not Generate a carry, the carry generation signal (generator) outputs the conditional operation result of a i∧Bi?0:Bi, that is, the carry result of a i and B i in the lower bits, and when a i and B i are added to Generate a carry, the carry generation signal (generator) outputs a logic 1. The exclusive OR result of A i+1∧Bi+1 is a logic 0, where A i+1 and B i+1 are both logic 0 or both logic 1, the carry generation signal (generator) outputs B i+1, and the carry generation signal (generator) outputs a logic 1 only when the higher order A i+1 and B i+1 add to Generate a carry.
Optionally, the first selector 23 comprises three inputs connected to the first output of the first look-up table 21, the second output of the second look-up table 22 and the carry input, respectively, and the first selector 23 is configured to determine the carry generation signal (generator) or the carry input signal (Cin i) as the carry output signal (Cout i+1) based on the carry transfer signal (Propagate). Wherein, when the carry logic circuit is applied to the addition logic operation, the boolean expression for the first selector 23 is implemented as:
Couti+1＝Ai+1∧Bi+1?Cini+1:Bi+1＝Ai+1∧Bi+1?Couti:Bi+1
＝Ai+1∧Bi+1?(Ai∧Bi?Cini:Bi):Bi+1
＝(Ai+1∧Bi+1)&(Ai∧Bi)?Cini:(Ai+1∧Bi+1?(Ai∧Bi?0:Bi):Bi+1)
The boolean expression for the first selector 23 to implement because Propagate＝(Ai+1∧Bi+1)&(Ai∧Bi);Generate＝Ai+1∧Bi+1?(Ai∧Bi?0:Bi):Bi+1, can be:
Couti+1＝PropagateCini:Generate；
Specifically, when the carry propagate signal (Propagate) is logic 1, neither a i+1 nor B i+1 nor a i nor B i add to Generate a carry, the carry Generate signal (generator) outputs logic 1 only when a i+1 is logic 0 and B i+1 is logic 1. But since the carry propagate signal (Propagate) is a logic 1, the first selector 23 determines the carry input signal (Cin i) as the carry output signal (Cout i+1). If the carry-in signal (Cin i) is logic 1, the carry-in signal (Cin i) is added with the lower bits of a i and B i to generate a carry, and the lower bit carry is added with the higher bits of a i+1 and B i+1 to generate a carry, so that the higher bit carry-out signal (Cout i+1) outputs logic 1; if the carry in signal (Cin i) is a logic 0, then the addition of the carry in signal (Cin i) to the lower bits a i and B i does not generate a carry, and the addition of a i+1 and B i+1 does not generate a carry, so that the higher bit carry out signal (Cout i+1) outputs a logic 0. In the above case, the carry-in signal (Cin i) is logic 0 or logic 1 will change the output logic of the high-order carry-out signal (Cout i+1), i.e., when the carry-in signal (Propagate) is logic 1 and the carry-in signal (Cin i) is logic 1 or logic 0, the output logic of the carry-out signal (Cout i+1) is the same as the output logic of the carry-in signal (Cin i), thereby outputting the carry-in signal (Cin i) as the carry-out signal (Cout i+1).
Specifically, when the carry propagate signal (Propagate) is logic 0, the first selector 23 determines the carry propagate signal (Propagate) as the carry output signal (Cout i+1). If the carry generation signal (generator) outputs a logic 1 when a i+1 and B i+1 in the upper bits are added to 1 but do not Generate a carry, it can be understood that a i and B i in the lower bits are added to a i+1 and B i+1 in the upper bits to Generate a carry and a Cout i+1 in the upper bits outputs a logic 1 only when a i and B i are added to Generate a carry; if the carry generation signal (generator) generates a carry when the higher order A i+1 and B i+1 are added to Generate a carry, the carry generation signal (generator) outputs a logic 1. And, if a i+1 and B i+1 are 1 and add to 1 but do not Generate a carry, both lower a i and B i are logic 0, and the carry generation signal (generation) is logic 0; if both the higher bits A i+1 and B i+1 are logic 0, the carry generation signal (generator) is logic 0. In the above case, no matter whether the carry in signal (Cin i) is logic 0 or logic 1, the output logic of the high-order carry out signal (Cout i+1) is not changed, i.e., when the carry propagate signal (Propagate) is logic 0 and the carry out signal (generator) is logic 1 or logic 0, the output logic of the carry out signal (Cout i+1) is the same as the output logic of the carry out signal (generator), so that the carry out signal (generator) is outputted as the carry out signal (Cout i+1).
Based on the above, the carry logic operation unit 20 can Generate the carry transfer signal (Propagate) through the first lookup table 21, generate the carry generation signal (generator) through the second lookup table 22, and perform the carry logic operation by using the first selector 23, so that the carry generation signal (generator) can be determined as the carry output signal (Cout i+1) in the case that the carry transfer signal (Propagate) is the first digital signal (logic 0), and can also be determined as the carry output signal (Cout i+1) in the case that the carry transfer signal (Propagate) is the second digital signal (logic 1), so that the carry logic operation unit 20 can perform the logic operation of generating the carry output signal of its corresponding stage from the cascade input signal of the previous stage of the carry logic processing module 10, the cascade input signal of its corresponding stage, and the carry input signal.
In the present embodiment, the arithmetic logic unit 30 includes at least a third lookup table 31, five input terminals of the third lookup table 31 are respectively connected to the first signal input terminal (I0), the second signal input terminal (I1), the third signal input terminal (I2), the fourth signal input terminal (I3) and the carry input terminal (CIN), and the third lookup table 31 is configured to determine an arithmetic output signal according to the first input signal, the second input signal, the third input signal, the fourth input signal and the carry input signal by using an arithmetic operation strategy in the target logic operation (S i+1). Wherein, when the carry logic circuit is applied to the addition logic operation, the boolean expression for implementing the third lookup table 31 is:
Si+1＝Ai+1∧Bi+1∧Cini+1＝Ai+1∧Bi+1∧(Ai∧Bi?Cini:Bi);
Specifically, a i∧Bi?Cini:Bi is the carry result of the carry-in signal (Cin i) and lower bits a i and B i, and a i+1∧Bi+1 is the carry-out addition result of higher bits a i+1 and B i+1. If only one of a i+1 and B i+1 is logic 1, the exclusive or result of a i+1 and B i+1 is logic 1: if the lower carry result is logic 1, the arithmetic output signal (S i+1) is logic 0, which means that the lower carry is added with the upper a i+1 and B i+1 to generate a carry, and the non-carry addition result is logic 0; if the lower carry result is logic 0, the arithmetic output signal (S i+1) is logic 1, which means that no carry is generated after the lower carry is added to the upper a i+1 and B i+1, and the result of the no carry addition is logic 1. If both A i+1 and B i+1 are logic 1 or logic 0, the exclusive OR result of A i+1 and B i+1 is logic 0: if the lower carry result is logic 1, the arithmetic output signal (S i+1) is logic 1, which means that no carry is generated after the lower carry is added with the higher a i+1 and B i+1, and the result of no carry addition is logic 1; if the lower carry result is logic 0, the arithmetic output signal (S i+1) is logic 0, which indicates that the addition result of the lower carry and the higher a i+1 and B i+1 is logic 0.
Based on the above manner, the arithmetic logic unit 30 is capable of performing an arithmetic logic operation of generating an arithmetic output signal of a corresponding level according to the cascade input signal of the previous level of the carry logic processing module 10, the cascade input signal of the corresponding level, and the carry input signal.
Optionally, under the condition of larger operation digital width, compared with the conventional carry logic circuit, the carry logic circuit in the application has shorter estimated clock period when carrying out carry operation, namely the operation speed is faster, so that the carry logic circuit can reduce carry delay and improve the instantaneity of operation.
In the present embodiment, by setting the carry logic operation unit 20 and the arithmetic logic operation unit 30 in the carry logic processing module 10, each level of carry logic processing module 10 can perform the target logic operation based on the input cascade input signal of its corresponding level, the cascade input signal of its previous level, and the carry output signals of its previous two levels of carry logic processing modules 10, and generate the carry output signal and the arithmetic output signal of the corresponding level of each carry logic processing module 10, so that the carry delay of the carry logic circuit can be reduced when the carry logic processing module 10 is used in the carry logic circuit, and the output of one arithmetic result can be realized.
Referring to fig. 3, fig. 3 is a schematic diagram illustrating a carry logic processing module 10 according to another embodiment of the application. As shown in fig. 3, the carry logic processing module 10 of the present embodiment includes a carry logic operation unit 20 and an arithmetic logic operation unit 30.
In the present embodiment, the carry logic operation unit 20 includes at least a first lookup table 21, a second lookup table 22, and a first selector 23. The first lookup table 21 is configured to determine a carry propagation signal according to the first input signal, the second input signal, the third input signal, and the fourth input signal by using a carry propagation strategy in the target logic operation; the second lookup table 22 is configured to determine a carry generation signal according to the first input signal, the second input signal, the third input signal, and the fourth input signal by using a carry generation operation strategy in the target logic operation; the first selector 23 is used for determining a carry generation signal or a carry input signal as a carry output signal from the carry transfer signal.
Optionally, the arithmetic logic unit 30 includes at least a third lookup table 31, where the third lookup table 31 is configured to determine an arithmetic output signal according to the first input signal, the second input signal, the third input signal, the fourth input signal, and the carry input signal by using an arithmetic operation strategy in the target logic operation.
Further, the arithmetic output terminal includes at least a first arithmetic output terminal and a second arithmetic output terminal, and the arithmetic logic unit 30 further includes a second selector 32 and a third selector 33, the first arithmetic output terminal is connected to an output terminal of the third lookup table 31, and the second arithmetic output terminal is connected to an output terminal of the third selector 33. Each carry logic processing module 10 further comprises a first control signal input for receiving a first control signal (I 1) and a second control signal input for receiving a second control signal (I 2).
In the present embodiment, the three input terminals of the second selector 32 are respectively connected to the first control signal input terminal, the output terminal of the first lookup table 21, and the output terminal of the second lookup table 22, the second selector 32 is configured to determine the carry generation signal (generator) or the carry transfer signal (Propagate) as the first output signal (O 1) according to the first control signal (I 1), and the boolean expression for implementing the second selector 32 is:
O1＝I1？Generate:Propagate；
Specifically, the second selector 32 is configured to determine the carry propagate signal (Propagate) as the first output signal (O 1) in the case where the first control signal (I 1) is the first digital signal (logic 0); the second selector 32 is configured to determine a carry generation signal (generator) as the first output signal (O 1) in case the first control signal (I 1) is the second digital signal (logic 1).
The three inputs of the third selector 33 are connected to the second control signal input, the output of the third look-up table 31 and the output of the second selector 32, respectively. The third selector 33 is configured to determine the arithmetic output signal (S i+1) or the first output signal (O 1) as the second output signal (O 2) according to the second control signal (I 2), and the boolean expression for implementing the third selector 33 is:
O2＝I2?Si+1:O1；
The third selector 33 is specifically configured to control whether the arithmetic output signal (S i+1) generated by the third lookup table 31 is output by the second arithmetic output terminal, and the third selector 33 is configured to output the arithmetic output signal (S i+1) as the second output signal (O 2) to the second arithmetic output terminal when the second control signal is the second digital signal (logic 1), so that the second arithmetic output terminal can output the arithmetic output signal when the second control signal is the second digital signal (logic 1) (S i+1).
Based on this, if the second control signal is the first digital signal (logic 0), only the first arithmetic output terminal is connected to the external logic circuit, and the arithmetic output signal (S i+1) generated by the third lookup table 31 is outputted; if the second control signal is a second digital signal (logic 1), only the second arithmetic output terminal is connected to an external logic circuit, and the arithmetic output signal (S i+1) generated by the third lookup table 31 is outputted, thereby realizing the selection of the arithmetic output terminal. In other embodiments, if the second control signal is a second digital signal (logic 1), the first and second operand outputs may be connected to external logic circuits to output the same operand output signal (S i+1).
Further, the arithmetic logic unit 30 further includes a multiplexer 34, two input terminals of the multiplexer 34 are respectively connected to the first control signal input terminal and the carry input terminal (CIN), an output terminal of the multiplexer 34 is connected to an input terminal of the third lookup table 31, and the multiplexer 34 is used for selecting the first control signal or the carry input signal to input into the third lookup table 31.
In the present embodiment, the setting of the carry logic operation unit 20 and the arithmetic logic operation unit 30 in the carry logic processing module 10 enables the carry logic processing module 10 to reduce the carry delay of the carry logic circuit and to realize the output of one arithmetic result when used in the carry logic circuit, and the second selector 32 and the third selector 33 additionally provided in the arithmetic logic operation unit 30 enable the selection of the arithmetic output terminal in the carry logic processing module 10 and expand the application range of the carry logic processing module 10.
Referring to fig. 4, fig. 4 is a schematic diagram illustrating a carry logic circuit 1 according to another embodiment of the application. As shown in fig. 4, the carry logic circuit 1 of the present application includes a plurality of cascaded carry logic processing modules 10.
In this embodiment, the plurality of carry logic processing modules 10 are in one-to-one correspondence with the cascade input signals of the carry-in stages, that is, each carry logic processing module is configured to receive the cascade input signals of two adjacent stages, perform the target logic operation on the cascade input signals of two stages, output the operation result of two stages corresponding to each carry logic processing module and the carry result of the corresponding carry-in stage, and output the carry-in result to the carry input end of the carry logic processing module 10 of the next stage.
Specifically, the first signal input terminal, the second signal input terminal, the third signal input terminal, and the fourth signal input terminal of each carry logic processing module 10 are respectively used for inputting the first input signal, the second input signal, the third input signal, and the fourth input signal. The cascade input signals of each carry logic processing module 10 include a first cascade input signal and a second cascade input signal, the first input signal and the third input signal are cascade input signals of adjacent levels in the first cascade input signal, the second input signal and the fourth input signal are cascade input signals of adjacent levels in the second cascade input signal, the first input signal corresponds to a level of the second input signal, and the third input signal corresponds to a level of the fourth input signal.
As one embodiment, the first-level carry logic processing module 10 is configured to input a first-level cascade input signal, a second-level cascade input signal, and an initial carry input signal, and output first-level and second-level arithmetic output signals and a second-level carry output signal; the second-level carry logic processing module 10 is configured to input a third-level cascade input signal, a fourth-level cascade input signal, and a second-level carry output signal output by the first-level carry logic processing module 10, and output third-level and fourth-level arithmetic output signals and a fourth-level carry output signal; the logic operation manner of the carry logic processing module 10 of the other levels can refer to the carry logic processing module 10 of the aforementioned level, and will not be described herein.
In some embodiments, the plurality of cascaded carry logic processing modules 10 in the carry logic circuit 1 provided in this disclosure may be the carry logic processing modules 10 described in the foregoing embodiments, that is, each carry logic processing module 10 includes a carry logic operation unit and an arithmetic logic operation unit, the carry logic operation unit is configured to output a carry result of a carry look-ahead stage corresponding to the carry logic module, and the arithmetic logic operation unit is configured to output an arithmetic result of one stage corresponding to the carry logic module.
Further, the carry logic circuit 1 provided in this embodiment further includes a plurality of first arithmetic logic processing modules, the plurality of cascaded carry logic processing modules 10 are in one-to-one correspondence with the plurality of first arithmetic logic processing modules, each first arithmetic logic processing module is configured to input two cascade input signals of adjacent levels, perform an arithmetic logic operation on the cascade input signals of the two levels, output an arithmetic result of another level corresponding to the carry logic processing module, and each first arithmetic logic processing module includes at least one lookup table.
Optionally, in the case of a larger operational digital width, compared with the conventional carry logic circuit, the carry logic circuit in fig. 4 of the present application has a shorter estimated clock period, i.e. a faster operation speed, when the carry operation is completed, so that the carry logic circuit in fig. 4 of the present application can reduce carry delay and improve the real-time performance of the operation. Compared with the carry logic circuit 1 in fig. 4, the carry logic circuit 1 in fig. 1 of the application has shorter estimated clock period when performing logic operation, and further increases operation speed, so that when the operation digital width is larger, the carry logic circuit 1 in fig. 1 of the application can further reduce carry delay and increase operation instantaneity compared with the carry logic circuit 1 in fig. 4.
In this embodiment, a carry logic processing module 10 and a first arithmetic logic processing module are disposed in each level of the carry logic circuit 1, a plurality of carry logic processing modules 10 are cascade-connected, and each first arithmetic logic processing module is connected to a corresponding carry logic processing module 10. Compared with the conventional cascade connection mode of a plurality of 1-bit carry logic processors, the carry chain in the application realizes carry-ahead operation through a plurality of cascade connection 2-bit carry logic processing modules 10, the number of the used carry logic processing modules 10 is halved, the length of the carry chain is halved, and the carry delay is reduced. In addition, the plurality of lookup tables provided in each carry logic processing module 10 in the carry logic circuit 1 of the present embodiment uses at least four input terminals, and the port utilization rate of each carry logic processing module 10 is improved compared with the conventional plurality of 1-bit carry logic processors.
In other embodiments, referring to fig. 5, fig. 5 is a schematic diagram illustrating a carry logic processing module 10 according to another embodiment of the present application. As shown in fig. 5, the carry logic processing module 10 of the present embodiment includes a carry logic operation unit 20, a first arithmetic logic operation unit 40, and a second arithmetic logic operation unit 50.
Optionally, each carry logic operation unit 20 is configured to input cascade input signals of two adjacent levels, and perform carry logic operation on the cascade input signals of two levels, so as to generate a carry result of the carry look-ahead level corresponding to the carry processing module. The first arithmetic logic unit 40 is configured to input a cascade input signal of a low-level stage, and perform an arithmetic logic operation on the cascade input signal of the low-level stage to generate a low-level arithmetic result corresponding to the carry processing module. The second arithmetic logic unit 50 is configured to input cascade input signals of two adjacent levels, perform arithmetic logic operation on the cascade input signals of two adjacent levels, and generate an arithmetic result of a high level corresponding to the carry processing module.
As an embodiment, each carry logic processing module 10 may include only one carry logic operation unit 20, and the first arithmetic logic operation unit 40 and the second arithmetic logic operation unit 50 are disposed outside the carry logic processing module 10. The carry logic processing module 10 of each hierarchy is connected to a first arithmetic logic unit 40 and a second arithmetic logic unit 50 corresponding to the carry logic processing module 10 of each hierarchy.
In this embodiment, the carry logic circuit implements carry-ahead operation by using a plurality of 2-bit carry logic processing modules 10 in cascade, so that the number of carry logic processing modules 10 used in the carry logic operation process is smaller, and the carry chain length is reduced, thereby reducing carry delay, and compared with a conventional 1-bit carry logic processor, the port utilization of each carry logic processing module 10 in the present application is improved.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the application has been described in detail with reference to the foregoing embodiments, it will be appreciated by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not drive the essence of the corresponding technical solutions to depart from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims (10)
1. The carry logic circuit is characterized by comprising a plurality of cascade carry logic processing modules, wherein the plurality of carry logic processing modules are in one-to-one correspondence with cascade input signals of multiple stages, and each carry logic processing module is used for carrying out target logic operation on the cascade input signals of the corresponding stages of each carry logic processing module;
Each carry logic processing module comprises a carry input end, a carry output end, an arithmetic output end and a plurality of signal input ends, wherein the plurality of signal input ends at least comprise a first signal input end, a second signal input end, a third signal input end and a fourth signal input end;
The first signal input end and the second signal input end of each carry logic processing module are used for inputting cascade input signals of a corresponding level of each carry logic processing module, the third signal input end and the fourth signal input end of each first logic processing module are respectively and correspondingly connected with the first signal input end and the second signal input end of a carry logic processing module of a previous level, the arithmetic output end of each carry logic processing module is used for outputting an arithmetic result of performing the target logic operation by the cascade input signals of the corresponding level of each carry logic processing module, and the first logic processing module is any carry logic processing module of any level except the carry logic processing module of the first level among the carry logic processing modules;
the carry input end of each second logic processing module is used for being connected with the carry output ends of the carry logic processing modules of the previous two levels, the carry output end of each carry logic processing module is used for outputting a cascade input signal of the corresponding level of each carry logic processing module to carry out a carry result of the target logic operation, and the second logic processing module is any one level of carry logic processing module except the first level and the second level of carry logic processing modules in the plurality of carry logic processing modules.
2. The carry logic circuit of claim 1, wherein the cascade input signals comprise a first cascade input signal and a second cascade input signal, the first signal input for inputting a first input signal, the second signal input for inputting a second input signal, the third signal input for inputting a third input signal, the fourth signal input for inputting a fourth input signal;
The first input signal and the third input signal are cascade input signals of adjacent levels in the first cascade input signal, the second input signal and the fourth input signal are cascade input signals of adjacent levels in the second cascade input signal, the first input signal corresponds to the level of the second input signal, and the third input signal corresponds to the level of the fourth input signal;
And each carry logic processing module is used for carrying out the target logic operation on the first cascade input signal and the second cascade input signal of the corresponding level, and generating a carry output signal and an arithmetic output signal of the corresponding level of each carry logic processing module.
3. The carry logic circuit of claim 2, wherein each of the carry logic processing modules comprises a carry logic operation unit and an arithmetic logic operation unit;
The carry logic operation unit is used for carrying out carry logic operation according to the first input signal, the second input signal, the third input signal, the fourth input signal and the carry input signal, and generating the carry output signal;
the arithmetic logic unit is used for performing arithmetic logic operation according to the first input signal, the second input signal, the third input signal, the fourth input signal and the carry input signal, and generating the arithmetic output signal.
4. A carry logic circuit according to claim 3, wherein the carry logic operation unit comprises a first look-up table, a second look-up table and a first selector;
The first lookup table comprises a first output end and at least four first input ends, the at least four first input ends are respectively connected to the first signal input end, the second signal input end, the third signal input end and the fourth signal input end, and the first lookup table is used for determining a carry transfer signal according to the first input signal, the second input signal, the third input signal and the fourth input signal by utilizing a carry transfer operation strategy in the target logic operation;
The second lookup table comprises a second output end and at least four second input ends, the at least four second input ends are respectively connected to the first signal input end, the second signal input end, the third signal input end and the fourth signal input end, and the second lookup table is used for generating an operation strategy by utilizing carry in the target logic operation and determining a carry generation signal according to the first input signal, the second input signal, the third input signal and the fourth input signal;
The first selector comprises three input ends which are respectively connected to the first output end of the first lookup table, the second output end of the second lookup table and the carry input end, and the first selector is used for determining the carry generation signal or the carry input signal as the carry output signal according to the carry transfer signal.
5. The carry logic circuit of claim 4, wherein the first selector is configured to determine the carry generation signal as the carry output signal if the carry propagate signal is a first digital signal;
the first selector is configured to determine the carry input signal as the carry output signal if the carry propagate signal is a second digital signal.
6. A carry logic circuit according to claim 3, wherein the arithmetic logic unit comprises a third look-up table;
Five input ends of the third lookup table are respectively connected to the first signal input end, the second signal input end, the third signal input end, the fourth signal input end and the carry input end, and the third lookup table is used for determining the arithmetic output signal according to the first input signal, the second input signal, the third input signal, the fourth input signal and the carry input signal by utilizing an arithmetic operation strategy in the target logic operation.
7. The carry logic circuit of claim 6, wherein the arithmetic output comprises at least a first and a second arithmetic output, the arithmetic logic unit further comprising a second and a third selector, the first arithmetic output being connected to an output of the third lookup table, the second arithmetic output being connected to an output of the third selector;
Each carry logic processing module further comprises a first control signal input end and a second control signal input end, wherein the first control signal input end is used for receiving a first control signal, and the second control signal input end is used for receiving a second control signal;
The three input ends of the second selector are respectively connected to the first control signal input end, the output end of the first lookup table and the output end of the second lookup table;
three input ends of the third selector are respectively connected to the second control signal input end, the output end of the third lookup table and the output end of the second selector.
8. The carry logic circuit of claim 7, wherein the second arithmetic output is configured to output the arithmetic output signal if the second control signal is a second digital signal.
9. The carry logic circuit of claim 7, wherein the arithmetic logic unit further comprises a multiplexer having two inputs connected to the first control signal input and the carry input, respectively, and an output connected to an input of the third look-up table, the multiplexer being configured to select the first control signal or the carry input signal for input to the third look-up table.
10. A carry logic circuit according to any one of claims 1 to 9, wherein the first signal input and the second signal input of the carry logic processing module of the first stage are arranged to input a cascade input signal of the first stage, the carry inputs of the carry logic processing modules of both the first stage and the second stage being arranged to receive an initial carry input signal.
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