CN117971031A - System-on-chip dormancy and awakening method - Google Patents
System-on-chip dormancy and awakening method Download PDFInfo
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- CN117971031A CN117971031A CN202311684688.5A CN202311684688A CN117971031A CN 117971031 A CN117971031 A CN 117971031A CN 202311684688 A CN202311684688 A CN 202311684688A CN 117971031 A CN117971031 A CN 117971031A
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- 238000000034 method Methods 0.000 title claims abstract description 56
- 230000005059 dormancy Effects 0.000 title claims abstract description 18
- 230000007958 sleep Effects 0.000 claims abstract description 81
- 238000012840 feeding operation Methods 0.000 claims description 16
- 230000002618 waking effect Effects 0.000 claims description 13
- 230000006266 hibernation Effects 0.000 claims 3
- 230000004044 response Effects 0.000 claims 1
- 238000012544 monitoring process Methods 0.000 description 4
- 230000005856 abnormality Effects 0.000 description 3
- 230000019371 dormancy process Effects 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000004590 computer program Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention provides a system-on-chip dormancy method, which is implemented in a power management unit of the system-on-chip and comprises the following steps: acquiring a sleep state of a central processing unit; when the central processing unit is in a dormant state, controlling a digital logic circuit corresponding to the central processing unit to enter the dormant state; and controlling the working state of a clock and/or a timer of the watchdog corresponding to the central processing unit according to the dormant state of the digital logic circuit. The dormancy and awakening method of the system on chip provided by the invention can effectively reduce the power consumption of the system on chip.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a method for hibernating and waking up a system on a chip.
Background
A system-on-chip is a product that encapsulates multiple chips together, often to independently perform specific functions, and includes a complete system with embedded software. In the case that the internal subsystem of the system on chip has no service, it is necessary to put it into a sleep state to reduce power consumption.
In existing systems on chip, a Watchdog (WDT) is required to monitor the system during system sleep. The monitoring mode needs the processor to wake up at regular time to perform the dog feeding operation in the sleeping process so as to achieve the purpose of monitoring the system stability. In this case, the processor wake-up timing is only used to perform the dog feeding operation, and no traffic is involved, so that the processor still requires a large wake-up power consumption in a state where it should be dormant.
Disclosure of Invention
The dormancy and awakening method of the system on chip provided by the invention can effectively reduce the power consumption of the system on chip.
In a first aspect, the present invention provides a system-on-chip sleep method, performed by a power management unit in the system-on-chip, the method comprising:
acquiring a sleep state of a central processing unit;
when the central processing unit is in a dormant state, controlling a digital logic circuit corresponding to the central processing unit to enter the dormant state;
and controlling the working state of a clock and/or a timer of the watchdog corresponding to the central processing unit according to the dormant state of the digital logic circuit.
Optionally, after the acquiring the sleep state of the central processor, the method further includes:
and when the central processing unit is in a non-dormant state, maintaining the non-dormant state of the digital logic circuit corresponding to the central processing unit.
Optionally, the controlling the working state of the clock and/or the timer of the watchdog corresponding to the central processing unit according to the sleep state of the digital logic circuit includes:
judging whether the dormancy flag bit of the digital logic circuit corresponding to the central processing unit is changed into a dormancy flag or not, or judging whether the digital logic circuit corresponding to the central processing unit sends out a dormant signal or not;
When the flag bit is not changed into a dormant flag or the logic circuit does not send out a dormant signal, the working states of the clock and the timer of the watchdog are maintained;
And when the flag bit is changed into a dormant flag or the logic circuit sends out a dormant signal, controlling a clock or a timer of the watchdog to stop working.
Optionally, the controlling the working state of the clock and/or the timer of the watchdog corresponding to the central processing unit according to the sleep state of the digital logic circuit includes:
acquiring a current time interval from when a signal for controlling a digital logic circuit corresponding to the central processing unit to enter a dormant state is sent out;
When the time interval is not smaller than a first preset time interval, controlling a clock or a timer of the watchdog to stop working;
and when the time interval is smaller than a first preset time interval, maintaining the working state of the clock and the timer of the watchdog.
Optionally, the controlling the working state of the clock and/or the timer of the watchdog corresponding to the central processing unit according to the sleep state of the digital logic circuit includes:
and when the digital logic circuit is in a dormant state, controlling at least one of a clock and a timer of a watchdog corresponding to the central processing unit to stop working.
In a second aspect, the present invention further provides a system on chip wake-up method, performed by a power management unit in the system on chip, the method comprising:
Starting a clock and/or a timer of a watchdog corresponding to a central processing unit and a digital logic circuit corresponding to the central processing unit according to the wake-up signal;
And controlling the wake-up state of the central processing unit according to the wake-up state of the digital logic circuit.
Optionally, starting the clock and/or timer of the watchdog corresponding to the central processing unit and the digital logic circuit corresponding to the central processing unit according to the wake-up signal includes:
Starting a clock and/or a timer of a watchdog corresponding to the central processor according to the wake-up signal;
and controlling the wake-up state of the digital logic circuit corresponding to the central processing unit according to the starting state of the clock and/or the timer.
Optionally, the controlling the wake-up state of the digital logic circuit corresponding to the central processing unit according to the start-up state of the clock and/or the timer includes:
Acquiring the starting states of the clock and the timer;
When the clock and the timer are in a starting state, waking up a digital logic circuit corresponding to the central processing unit;
and when one of the clock and the timer is in a non-starting state, maintaining the dormant state of the digital logic circuit corresponding to the central processing unit.
Optionally, the controlling the wake-up state of the central processing unit according to the wake-up state of the digital logic circuit includes:
judging whether the dormancy flag bit of the digital logic circuit corresponding to the central processing unit is changed into a wake-up state or not, or judging whether the digital logic circuit corresponding to the central processing unit sends out a wake-up signal or not;
when the flag bit is not changed into the wake-up state or the logic circuit does not send out the wake-up signal, the sleep state of the central processing unit is maintained;
and when the flag bit is changed into a wake-up state or the logic circuit sends out a wake-up signal, waking up the central processing unit.
Optionally, the controlling the wake-up state of the central processing unit according to the wake-up state of the digital logic circuit includes:
Acquiring a current time interval from when a signal for controlling a digital logic circuit corresponding to the central processing unit to enter an awake state is sent out;
when the time interval is not smaller than a second preset time interval, waking up the central processing unit;
and when the time interval is smaller than a second preset time interval, maintaining the sleep state of the central processing unit.
In a third aspect, the present invention also provides a method for dormancy and wakeup of a system on a chip, a central processing unit executed in the system on a chip, the method comprising:
determining that the current working state needs to enter a dormant state or an awake state according to the current working scene;
When the current working state needs to enter a dormant state, stopping executing the feeding operation of the watchdog;
When the current working state needs to enter the wake-up state, the execution of the feeding operation of the watchdog is started.
According to the sleep and wake-up method of the system on chip, provided by the embodiment of the invention, the clock or the timer of the watchdog can be stopped under the condition that the central processing unit and the digital logic circuit are in sleep, and the central processing unit is not required to perform the dog feeding operation, so that the power consumption in the sleep state is reduced. In addition, the watchdog does not need to count time under the state that the central processing unit and the digital logic circuit are dormant, so that the timing time of the watchdog is greatly shortened, the bit width requirement of the timer for timing by the watchdog is also greatly reduced, and the area occupied by the watchdog is reduced.
Drawings
FIG. 1 is a flow chart of a system-on-chip sleep method according to an embodiment of the invention;
FIG. 2 is a flowchart of a method for controlling a digital logic circuit to go to sleep in a system-on-chip sleep method according to another embodiment of the present invention;
FIG. 3 is a flow chart of a clock and/or timer for stopping a watchdog in a system-on-chip sleep method according to another embodiment of the present invention;
FIG. 4 is a flow chart of a clock and/or timer for stopping a watchdog in a system-on-chip sleep method according to another embodiment of the present invention;
FIG. 5 is a flowchart of a wake-up method of a system on chip according to another embodiment of the present invention;
FIG. 6 is a flow chart of a sequential start watchdog and digital logic circuit in a system on chip wake-up method according to another embodiment of the present invention;
FIG. 7 is a flowchart of a wake-up digital logic circuit in a system-on-chip wake-up method according to another embodiment of the present invention;
FIG. 8 is a flowchart of a wake-up CPU in a wake-up method of a system-on-chip according to another embodiment of the present invention;
FIG. 9 is a flowchart of a wake-up CPU in a wake-up method of a system-on-chip according to another embodiment of the present invention;
FIG. 10 is a flowchart of a system-on-chip sleep and method according to another embodiment of the present invention;
FIG. 11 is an exemplary flow chart of a system-on-chip sleep and method according to another embodiment of the invention;
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
An embodiment of the present invention provides a sleep method for a system on a chip, which is implemented in a power management unit in the system on a chip, as shown in fig. 1, and includes:
Step 110, obtaining the sleep state of a central processing unit;
In some embodiments, during the sleep process of the system on chip, the cpu is enabled to enter the sleep state when no task is performed, and therefore, in this embodiment, it is necessary to confirm the sleep state of the cpu first, so as to determine whether other circuits enter the sleep state. In a preferred embodiment, when the sleep state of the central processor is acquired, the sleep state of the central processor may be determined by an interrupt signal actively sent by the central processor, or may be determined by polling the sleep state of the central processor by the power management unit.
Step 120, when the central processing unit is in a sleep state, controlling a digital logic circuit corresponding to the central processing unit to enter the sleep state;
In some embodiments, after the cpu enters the sleep state, the corresponding digital logic circuit is no longer required to perform tasks, and at this time, the corresponding digital logic circuit may be controlled to perform the sleep state.
And 130, controlling the working state of a clock and/or a timer of the watchdog corresponding to the central processing unit according to the dormant state of the digital logic circuit.
In some embodiments, since the digital logic circuit requires a certain time to enter the sleep state, it is necessary to ensure that the watchdog clock and/or timer is disabled after the digital logic circuit enters the sleep state, and before the digital logic circuit enters the sleep state, it should be ensured that the watchdog clock and timer are in an active state. For a watchdog, one or both of the timer and the clock may be deactivated. When the timer stops working, it will no longer have a clock signal, at which point the watchdog timer will not continue to grow. When the timer stops working, the timer will not continue to grow, whether or not there is a clock signal, since the timer is not working.
As an alternative embodiment, as shown in fig. 2, in step 110, after the acquiring the sleep state of the central processing unit, the method further includes:
And 140, when the central processing unit is in a non-dormant state, maintaining the non-dormant state of the digital logic circuit corresponding to the central processing unit.
In some embodiments, the operation of the central processor needs to rely on the corresponding digital logic circuit when the central processor is in a non-sleep state, and thus, in order to ensure proper operation of the central processor, it is necessary to ensure that the corresponding digital logic circuit does not enter a sleep state.
As an optional implementation manner, as shown in fig. 3, in step 130, the controlling, according to the sleep state of the digital logic circuit, the working state of the watchdog clock and/or timer corresponding to the central processing unit includes:
step 131, judging whether the sleep flag bit of the digital logic circuit corresponding to the central processing unit is changed to a sleep flag or whether the digital logic circuit corresponding to the central processing unit sends out a signal that has been dormant;
In some embodiments, since the stop of the watchdog clock and/or the timer is required to be performed after all the digital logic circuits are dormant, it is required to determine whether all the digital logic circuits are dormant, and in the dormancy process of the digital logic circuits, after the last dormancy of the plurality of digital logic circuits that are dormant is sequentially performed, the last dormant digital logic circuit changes the corresponding flag bit, and when the flag bit is changed to the dormant state, it indicates that all the digital logic circuits have been dormant.
Step 132, when the flag bit is not changed into a sleep flag or the logic circuit does not send out a sleep signal, maintaining the working state of the clock and the timer of the watchdog;
In some embodiments, when there is digital logic in a non-sleep state, it is desirable to keep the watchdog's clock and timer active so that the watchdog monitors the entire system on chip.
And step 133, when the flag bit is changed to a dormant flag or the logic circuit sends out a dormant signal, controlling a clock or a timer of the watchdog to stop working.
In some embodiments, when the digital logic circuit has all entered the sleep state, most of the working logic of the system on a chip has stopped, and the probability of an abnormality is very small, so the clock or timer of the watchdog can be stopped at this time, avoiding the central processor from waking up for executing the watchdog feeding operation without task execution.
As an optional implementation manner, as shown in fig. 4, in step 130, the controlling, according to the sleep state of the digital logic circuit, the working state of the watchdog clock and/or timer corresponding to the central processing unit includes:
Step 134, obtaining a current time interval from when a signal for controlling the digital logic circuit corresponding to the central processing unit to enter a sleep state is sent out;
In some embodiments, since the digital logic circuit generally goes to sleep for a relatively fixed time period, a time interval may be set, and after the signal is sent, the digital logic circuit may be considered to have all gone to sleep after the set time interval.
Step 135, when the time interval is not less than a first preset time interval, controlling a clock or a timer of the watchdog to stop working;
In some embodiments, the first predetermined time interval may be set based on an empirical value, i.e., the time required for the digital logic circuit to enter a sleep state is collected and set based on the collected data. When the time interval exceeds the first preset time interval, the state of the digital logic circuit is determined to be a dormant state, at the moment, most of working logic of the system on a chip is stopped, and the probability of abnormality is extremely low, so that a clock or a timer of the watchdog can be stopped at the moment, and the CPU is prevented from waking up for executing the dog feeding operation under the condition of no task execution.
And 136, when the time interval is smaller than a first preset time interval, maintaining the working state of the clock and the timer of the watchdog.
In some embodiments, the state of the digital logic is determined to be an un-dormant state when the time interval does not exceed the first predetermined time interval, at which time a watchdog is still required to monitor the system on chip.
As an optional implementation manner, in step 130, the controlling the working state of the clock and/or the timer of the watchdog corresponding to the central processing unit according to the sleep state of the digital logic circuit includes:
and when the digital logic circuit is in a dormant state, controlling at least one of a clock and a timer of a watchdog corresponding to the central processing unit to stop working.
In some embodiments, neither the watchdog's clock nor the timer stops working, and thus the timer does not continue to grow, resulting in a restart of the system due to the growth of the timer.
The embodiment of the invention also provides a wake-up method of the system on chip, which is implemented in a power management unit of the system on chip, as shown in fig. 5, and comprises the following steps:
Step 210, starting a watchdog clock and/or a timer corresponding to a central processing unit and a digital logic circuit corresponding to the central processing unit according to a wake-up signal;
in some embodiments, in order to ensure stable operation of the system on chip, it is necessary to ensure that the watchdog is able to continuously monitor the system on chip during its operation, and the operation of the central processor depends on the corresponding digital logic circuit, so in this embodiment, the clock and/or timer of the watchdog and the corresponding digital logic circuit first need to be started. In the starting process, the clock and/or the timer of the watchdog and the corresponding digital logic circuit can be started at the same time, and in the starting mode, the starting time of the clock and/or the timer of the watchdog is generally smaller than the starting time of the digital logic circuit, and even if the starting time of the clock and/or the timer of the watchdog exceeds the starting time of the digital logic circuit, the clock and/or the timer of the watchdog only exceeds the starting time of the digital logic circuit, so that the clock and/or the timer of the watchdog can be monitored when the digital logic circuit enters the awakening state or within a very short time after the digital logic circuit enters the awakening state. In the starting process, the clock and/or the timer of the watchdog can be started first, and the corresponding digital logic circuit is started after the clock and/or the timer of the watchdog is started, so that the digital logic circuit is ensured to be necessarily monitored by the watchdog when entering the wake-up state. When the clock and/or timer of the watchdog is started, if the clock is stopped, the clock needs to be started; if the timer is stopped, the timer needs to be started; if both are stopped, both need to be started.
Step 220, controlling the wake-up state of the cpu according to the wake-up state of the digital logic circuit.
In some embodiments, the digital logic circuit has a steady-state operating condition after being in the wake-up state, at which point the central processor may wake-up.
As an alternative embodiment, as shown in fig. 6, in step 210, starting a clock and/or a timer of a watchdog corresponding to a central processing unit and a digital logic circuit corresponding to the central processing unit according to a wake-up signal includes:
step 211, starting a clock and/or a timer of a watchdog corresponding to the central processor according to the wake-up signal;
in some embodiments, since the digital logic circuit needs to be monitored by the watchdog during operation, it is necessary to ensure that the start-up time of the watchdog is earlier than the start-up time of the digital logic circuit. Therefore, in order to reduce the probability of errors occurring during operation of the digital logic circuit at start-up, in this embodiment, the clock and/or timer of the watchdog is first started.
Step 212, controlling the wake-up state of the digital logic circuit corresponding to the central processing unit according to the start-up state of the clock and/or the timer.
In some embodiments, after the watchdog's clock and timer are both started, the watchdog may already be able to monitor the operation of the system on beat, at which point the digital logic may be awakened.
As an alternative embodiment, as shown in fig. 7, in step 212, the controlling the wake-up state of the digital logic circuit corresponding to the cpu according to the start-up state of the clock and/or the timer includes:
Step 213, acquiring the starting states of the clock and the timer;
In some embodiments, since neither the clock nor the timer is in a non-enabled state, the watchdog is not able to stably monitor the operation of the system-on-chip, and therefore, in this embodiment, the enabled state of the clock and the timer needs to be obtained first.
Step 214, when the clock and the timer are both in the starting state, waking up the digital logic circuit corresponding to the central processing unit;
in some embodiments, the watchdog can stably monitor the operation of the system-on-chip when both the clock and the timer are in the enabled state, at which point the digital logic circuit may be awakened.
And step 215, when one of the clock and the timer is in a non-starting state, maintaining the sleep state of the digital logic circuit corresponding to the central processing unit.
In some embodiments, the watchdog is not able to wake up the digital logic circuit at this time, and is required to maintain the sleep state of the digital logic circuit, since neither the clock nor the timer is in a non-active state, which does not enable the watchdog to stably monitor the operation of the system on chip.
As an alternative embodiment, as shown in fig. 8, in step 220, the controlling the wake-up state of the central processing unit according to the wake-up state of the digital logic circuit includes:
Step 221, judging whether the sleep flag bit of the digital logic circuit corresponding to the central processing unit is changed to an awake state, or judging whether the digital logic circuit corresponding to the central processing unit sends out an awake signal;
In some embodiments, since the wake-up of the cpu needs to be performed after all the digital logic circuits are woken up, it is necessary to determine whether all the digital logic circuits are woken up first, and in the wake-up process of the digital logic circuits, after the last wake-up of the plurality of digital logic circuits that are woken up is performed sequentially, the last wake-up digital logic circuit changes the corresponding flag bit, and when the flag bit is changed to the wake-up state, it indicates that all the digital logic circuits have been woken up.
Step 222, when the flag bit is not changed to the wake-up state or the logic circuit does not send out the wake-up signal, maintaining the sleep state of the central processing unit;
in some embodiments, because the operation of the cpu depends on the digital logic, the cpu is not able to operate stably when the digital logic in the sleep state is present, and thus it is desirable to maintain the sleep state of the cpu.
Step 223, when the flag bit has been changed to a wake-up state or the logic circuit has sent out a wake-up signal, waking up the central processing unit.
In some embodiments, the central processor may wake up when the digital logic circuit in sleep state is not present, and the central processor already has a steady running condition.
As an alternative embodiment, as shown in fig. 9, in step 230, the controlling the wake-up state of the central processing unit according to the wake-up state of the digital logic circuit includes:
step 224, obtaining a current time interval from when a signal for controlling the digital logic circuit corresponding to the central processing unit to enter the wake-up state is sent out;
In some embodiments, since the process of entering the wake-up state of the digital logic circuit generally has a relatively fixed time range, a time interval may be set, and after the signal is sent, the digital logic circuit may be considered to have all entered the sleep state after the set time interval.
Step 225, when the time interval is not less than a second preset time interval, waking up the central processing unit;
In some embodiments, the second predetermined time interval may be set based on an empirical value, i.e., the time required for the digital logic circuit to enter the awake state is collected and set based on the collected data. And when the time interval exceeds the second preset time interval, determining the state of the digital logic circuit as a wake-up state, wherein the central processing unit has the condition of stable operation of the central processing unit, and waking up the central processing unit.
And step 226, maintaining the sleep state of the central processing unit when the time interval is smaller than a second preset time interval.
In some embodiments, when the time interval does not exceed the second predetermined time interval, it is determined that the state of the digital logic circuit is not a wake-up state, and at this time, the condition that the central processor operates stably is not satisfied, and the central processor is not woken up.
The embodiment of the invention also provides a sleep and wake-up method of the system on chip, which is implemented in a central processing unit of the system on chip, as shown in fig. 10, and the method comprises the following steps:
Step 310, determining that the current working state needs to enter a sleep state or an awake state according to the current working scene;
In some embodiments, the current working scenario refers to whether a task needs to be executed currently, when a task needs to be executed, the current working state should be in an awake state, and when no task needs to be executed, the current working state should be in a sleep state.
Step 320, terminating execution of the feeding operation of the watchdog when the current working state needs to enter the sleep state;
In some embodiments, when the current operating state requires a sleep state, the feeding operation to the watchdog is terminated, so that after entering the sleep state, no regular wake-up is required for feeding operation, thereby reducing power consumption in the sleep state.
Step 330, when the current working state needs to enter the wake-up state, starting execution of the feeding operation of the watchdog.
In some embodiments, when the current operational state requires an awake state, the watchdog monitors the operation of the system-on-chip, and thus, the watchdog feeding operation needs to be initiated.
As shown in fig. 11, a flow of a system on a chip adopting the technical solution of the embodiment of the present invention from a wake-up state to a sleep state and then from the sleep state to the wake-up state is exemplarily shown as follows:
The running state of the system on a chip is periodically updated by the CPU (namely, the watchdog feeding operation) when the system on a chip is not in dormancy, when the system on a chip enters into the dormancy process, the CPU enters into the dormancy state first, the digital logic circuit enters into the dormancy state one by one, and the clock of the watchdog is automatically stopped in the last step of the dormancy state of the digital logic circuit, so that the watchdog is ensured to be not required to wake up to update when the system is in dormancy. And in the wake-up process of the system on chip, the watchdog clock is started first, the digital logic circuits wake up one by one, the watchdog is ensured to continuously count time and continuously monitor whether the system is hung up or not, and finally the central processing unit is woken up again. In the T4 stage of the diagram, most of working logic of the system stops, and the occurrence probability of abnormality is small. By sacrificing the monitoring of this portion, unnecessary wake-up execution of the dog feeding operation is avoided in exchange for a reduction in average power consumption of the system sleep. Therefore, the average power consumption of the system in the dormant state can be greatly reduced while the stability monitoring of the system is considered, and abnormal protrusions of bottom current in the dormant process are eliminated.
Those skilled in the art will appreciate that implementing all or part of the above-described method embodiments may be accomplished by way of computer programs, which may be stored on a computer readable storage medium, which when executed may comprise the steps of the method embodiments described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a random-access Memory (Random Access Memory, RAM), or the like.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.
Claims (11)
1. A method of system-on-chip hibernation, characterized by a power management unit implemented in the system-on-chip, the method comprising:
acquiring a sleep state of a central processing unit;
when the central processing unit is in a dormant state, controlling a digital logic circuit corresponding to the central processing unit to enter the dormant state;
and controlling the working state of a clock and/or a timer of the watchdog corresponding to the central processing unit according to the dormant state of the digital logic circuit.
2. The system-on-chip hibernation method according to claim 1, wherein after the obtaining the hibernation state of the central processing unit, the method further comprises:
and when the central processing unit is in a non-dormant state, maintaining the non-dormant state of the digital logic circuit corresponding to the central processing unit.
3. The sleep method of claim 1, wherein controlling the working state of the watchdog clock and/or timer corresponding to the cpu according to the sleep state of the digital logic circuit comprises:
judging whether the dormancy flag bit of the digital logic circuit corresponding to the central processing unit is changed into a dormancy flag or not, or judging whether the digital logic circuit corresponding to the central processing unit sends out a dormant signal or not;
When the flag bit is not changed into a dormant flag or the logic circuit does not send out a dormant signal, the working states of the clock and the timer of the watchdog are maintained;
and when the flag bit is changed into a dormant flag or the logic circuit sends out a dormant signal, controlling a clock or a timer of the watchdog to stop working.
4. The on-chip sleep method as set forth in claim 1, wherein the controlling the working state of the watchdog clock and/or timer corresponding to the cpu according to the sleep state of the digital logic circuit includes:
acquiring a current time interval from when a signal for controlling a digital logic circuit corresponding to the central processing unit to enter a dormant state is sent out;
When the time interval is not smaller than a first preset time interval, controlling a clock or a timer of the watchdog to stop working;
and when the time interval is smaller than a first preset time interval, maintaining the working state of the clock and the timer of the watchdog.
5. The method according to claim 1, wherein controlling the working state of the clock and/or timer of the watchdog corresponding to the central processing unit according to the sleep state of the digital logic circuit comprises:
and when the digital logic circuit is in a dormant state, controlling at least one of a clock and a timer of a watchdog corresponding to the central processing unit to stop working.
6. A system-on-chip wake-up method, characterized by a power management unit implemented in the system-on-chip, the method comprising:
Starting a clock and/or a timer of a watchdog corresponding to a central processing unit and a digital logic circuit corresponding to the central processing unit according to the wake-up signal;
And controlling the wake-up state of the central processing unit according to the wake-up state of the digital logic circuit.
7. The method of claim 6, wherein starting a clock and/or timer of a watchdog corresponding to a central processor and a digital logic circuit corresponding to the central processor in response to a wake-up signal comprises:
Starting a clock and/or a timer of a watchdog corresponding to the central processor according to the wake-up signal;
and controlling the wake-up state of the digital logic circuit corresponding to the central processing unit according to the starting state of the clock and/or the timer.
8. The method according to claim 6, wherein controlling the wake-up state of the digital logic circuit corresponding to the cpu according to the start-up state of the clock and/or the timer comprises:
Acquiring the starting states of the clock and the timer;
When the clock and the timer are in a starting state, waking up a digital logic circuit corresponding to the central processing unit;
and when one of the clock and the timer is in a non-starting state, maintaining the dormant state of the digital logic circuit corresponding to the central processing unit.
9. The method of claim 6, wherein controlling the wake-up state of the central processing unit in accordance with the wake-up state of the digital logic circuit comprises:
judging whether the dormancy flag bit of the digital logic circuit corresponding to the central processing unit is changed into a wake-up state or not, or judging whether the digital logic circuit corresponding to the central processing unit sends out a wake-up signal or not;
when the flag bit is not changed into the wake-up state or the logic circuit does not send out the wake-up signal, the sleep state of the central processing unit is maintained;
and when the flag bit is changed into a wake-up state or the logic circuit sends out a wake-up signal, waking up the central processing unit.
10. The method of claim 6, wherein controlling the wake-up state of the central processing unit in accordance with the wake-up state of the digital logic circuit comprises:
Acquiring a current time interval from when a signal for controlling a digital logic circuit corresponding to the central processing unit to enter an awake state is sent out;
when the time interval is not smaller than a second preset time interval, waking up the central processing unit;
and when the time interval is smaller than a second preset time interval, maintaining the sleep state of the central processing unit.
11. A method of sleep and wake-up of a system on a chip, the method comprising a central processor executing in the system on a chip:
determining that the current working state needs to enter a dormant state or an awake state according to the current working scene;
When the current working state needs to enter a dormant state, stopping executing the feeding operation of the watchdog;
When the current working state needs to enter the wake-up state, the execution of the feeding operation of the watchdog is started.
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