CN117955587A - Frame synchronization method and device - Google Patents
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Abstract
The embodiment of the specification provides a frame synchronization method and device, wherein the frame synchronization method comprises the following steps: acquiring bit stream data, and caching the bit stream data based on splicing information and shift information to determine target cache data; judging whether target cache data are matched with a special synchronous code group or not, and determining a matching result; and performing frame synchronization based on the matching result, the splicing information and the shift information, and determining target frame data. Caching the bit stream data based on splicing information and shift information to determine target cache data by acquiring the bit stream data; judging whether target cache data are matched with a special synchronous code group or not, and determining a matching result; and carrying out frame synchronization based on the matching result, the splicing information and the shift information to determine target frame data, so that the frame synchronization can be completed only by a table look-up mode, the complexity is reduced, and the frame synchronization efficiency is improved.
Description
Technical Field
The embodiment of the specification relates to the technical field of digital signals, in particular to a frame synchronization method.
Background
In a digital time division multiplexing communication system, in order to correctly separate each time slot signal, a start flag of each frame must be provided at a transmitting end, and a process of detecting and acquiring the flag at a receiving end is called frame synchronization. The whole system needs to be able to enter frame synchronization quickly after starting up, or to recover frame synchronization quickly once the frame is out of sync. Frame synchronization implementations include a "start-stop synchronization method", an "insert special synchronization code group method", and an "optimistic frame lock method".
The frame synchronization function of the signal receiver is usually implemented on a special chip, such as an FPGA, logic codes are written, the frame synchronization operation is completed by using the efficient processing capability of the special chip to the special function, and then the synchronized data frame is sent to other modules, and the other modules complete subsequent work. However, with the development of the general chip, the requirements for transferring part of the functions of the special chip to the general chip to realize the same become more and more, including the above demodulation, decoding, carrier synchronization, bit synchronization, frame synchronization, etc., and since the frame synchronization needs to be operated according to bits, there are a great number of shift operations, and the situations of lower frame synchronization efficiency and higher resource consumption occur in the conventional bit operation manner, which results in failing to meet the situations of higher time requirement and situations of higher communication code rate. Thus, a better solution is needed.
Disclosure of Invention
In view of this, the present embodiment provides a frame synchronization method. One or more embodiments of the present specification relate to a frame synchronization apparatus, a computing device, a computer-readable storage medium, and a computer program that solve the technical drawbacks of the prior art.
According to a first aspect of embodiments of the present disclosure, there is provided a frame synchronization method, including:
Acquiring bit stream data, and caching the bit stream data based on splicing information and shift information to determine target cache data;
judging whether target cache data are matched with a special synchronous code group or not, and determining a matching result;
And performing frame synchronization based on the matching result, the splicing information and the shift information, and determining target frame data.
In one possible implementation manner, obtaining the bit stream data, caching the bit stream data based on the splicing information and the shift information to determine target cache data includes:
acquiring bit stream data, caching the bit stream data into a first cache, and determining a byte data stream;
moving the byte data stream to a first position of a second buffer memory based on the splicing information, and determining residual bit data;
And moving the residual bit data to a second position of the second buffer memory based on the shift information, and determining target buffer memory data.
In one possible implementation, determining whether the target cache data matches a special synchronization code group, determining a matching result, includes:
determining a target synchronous code group and acquiring a head synchronous code group of target cache data;
under the condition that the target synchronous code group is the same as the head synchronous code group, the matching result is matched;
and under the condition that the target synchronous code group and the head synchronous code group are not identical, the matching result is unmatched.
In one possible implementation, frame synchronization is performed based on the matching result, the splicing information, and the shift information, and determining the target frame data includes:
If the matching result is unmatched, moving preset bits for the target cache data, and determining target bits;
Performing special synchronous code group matching based on the length of the target bit and the bit length threshold of the special synchronous code group;
and under the condition that the matching result is matched, performing frame synchronization based on the splicing information and the shift information, and determining target frame data.
In one possible implementation, performing special synchronization code group matching based on the length of the target bit and a bit length threshold of the special synchronization code group includes:
comparing the length of the target bit with a bit length threshold of a special synchronous code group;
under the condition that the length of the target bit is greater than or equal to the bit length threshold, determining whether a special synchronous code group is matched based on the target cache data, and determining a matching result until the matching result is matched;
in the case that the length of the target bit is smaller than the bit length threshold, acquiring the bit stream data is performed until the matching result is matched.
In one possible implementation, frame synchronization is performed based on the splicing information and the shift information, and determining the target frame data includes:
acquiring updated bit stream data, caching the updated bit stream data into a first cache, and determining an updated byte data stream;
moving the updated byte data stream to a first position of the second buffer based on the splicing information, and determining updated residual bit data;
Based on the shift information, moving the updated remaining bit data to a second position of the second cache, and determining updated cache data;
and determining target frame data based on the length of the updated cache data and a frame length bit threshold of a preset data frame length.
In one possible implementation, determining the target frame data based on updating the length of the buffered data and a frame length bit threshold of a preset data frame length includes:
comparing the length of the updated cache data with a frame length bit threshold value of a preset data frame length;
determining target frame data under the condition that the length of the updated cache data is greater than or equal to a frame length bit threshold value;
And under the condition that the length of the update cache data is smaller than the frame length bit threshold value, acquiring the update bit stream data until the target frame data is determined.
According to a second aspect of embodiments of the present specification, there is provided a frame synchronization apparatus comprising:
the data acquisition module is configured to acquire bit stream data, and buffer the bit stream data based on splicing information and shift information to determine target buffer data;
the code group synchronization module is configured to judge whether the target cache data is matched with a special synchronous code group or not, and determine a matching result;
And the data synchronization module is configured to perform frame synchronization based on the matching result, the splicing information and the shift information and determine target frame data.
According to a third aspect of embodiments of the present specification, there is provided a computing device comprising:
a memory and a processor;
The memory is configured to store computer-executable instructions that, when executed by the processor, perform the steps of the frame synchronization method described above.
According to a fourth aspect of embodiments of the present specification, there is provided a computer readable storage medium storing computer executable instructions which, when executed by a processor, implement the steps of the frame synchronization method described above.
According to a fifth aspect of embodiments of the present specification, there is provided a computer program, wherein the computer program, when executed in a computer, causes the computer to perform the steps of the frame synchronization method described above.
The embodiment of the specification provides a frame synchronization method and a device, wherein the frame synchronization method comprises the following steps: acquiring bit stream data, and caching the bit stream data based on splicing information and shift information to determine target cache data; judging whether target cache data are matched with a special synchronous code group or not, and determining a matching result; and performing frame synchronization based on the matching result, the splicing information and the shift information, and determining target frame data. Caching the bit stream data based on splicing information and shift information to determine target cache data by acquiring the bit stream data; judging whether target cache data are matched with a special synchronous code group or not, and determining a matching result; and carrying out frame synchronization based on the matching result, the splicing information and the shift information to determine target frame data, so that the frame synchronization can be completed only by a table look-up mode, the complexity is reduced, and the frame synchronization efficiency is improved.
Drawings
Fig. 1 is a schematic view of a frame synchronization method according to an embodiment of the present disclosure;
FIG. 2 is a flow chart of a method of frame synchronization provided in one embodiment of the present disclosure;
fig. 3 is a schematic diagram of a splicing process of a frame synchronization method according to an embodiment of the present disclosure;
FIG. 4 is a splice table generation code diagram of a frame synchronization method according to one embodiment of the present disclosure;
fig. 5 is a schematic diagram of a shift process of a frame synchronization method according to an embodiment of the present disclosure
FIG. 6 is a shift table generation code diagram of a frame synchronization method according to one embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of a frame synchronization device according to an embodiment of the present disclosure;
FIG. 8 is a block diagram of a computing device provided in one embodiment of the present description.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present description. This description may be embodied in many other forms than described herein and similarly generalized by those skilled in the art to whom this disclosure pertains without departing from the spirit of the disclosure and, therefore, this disclosure is not limited by the specific implementations disclosed below.
The terminology used in the one or more embodiments of the specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the one or more embodiments of the specification. As used in this specification, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used in one or more embodiments of the present specification refers to and encompasses any or all possible combinations of one or more of the associated listed items.
It should be understood that, although the terms first, second, etc. may be used in one or more embodiments of this specification to describe various information, these information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, a first may also be referred to as a second, and similarly, a second may also be referred to as a first, without departing from the scope of one or more embodiments of the present description. The word "if" as used herein may be interpreted as "at … …" or "at … …" or "in response to a determination" depending on the context.
In the present specification, a frame synchronization method is provided, and the present specification relates to a frame synchronization apparatus, a computing device, and a computer-readable storage medium, which are described in detail in the following embodiments one by one.
Referring to fig. 1, fig. 1 is a schematic view of a frame synchronization method according to an embodiment of the present disclosure.
In the application scenario of fig. 1, the computing device 101 may obtain the bitstream data, and cache the bitstream data based on the splicing information and the shift information 102 to determine the target cache data 103. The computing device 101 may then determine whether the target cache data 103 matches a particular set of sync codes, determining a match result 104. Thereafter, the computing device 101 may determine the target frame data 105 based on the matching result 104, the stitching information, and the shift information 102 for frame synchronization.
The computing device 101 may be hardware or software. When the computing device 101 is hardware, it may be implemented as a distributed cluster of multiple servers or terminal devices, or as a single server or single terminal device. When the computing device 101 is embodied as software, it may be installed in the hardware devices listed above. It may be implemented as a plurality of software or software modules, for example, for providing distributed services, or as a single software or software module. The present invention is not particularly limited herein.
Referring to fig. 2, fig. 2 shows a flowchart of a frame synchronization method according to an embodiment of the present disclosure, which specifically includes the following steps.
Step 201: and acquiring bit stream data, and caching the bit stream data based on the splicing information and the shift information to determine target cache data.
The splicing information may be information for splicing the bit stream data, for example, presented in a table form, which may be referred to as a splicing table, and the shift information may be information for shifting the position of the bit stream data, for example, presented in a table form, which may be referred to as a shift table.
In practical application, the invention is only aimed at the frame synchronization in the mode of 'inserting special synchronous code group method'. The communication data transmission means that data is transmitted from one position (transmitter) to another position (receiver), the data content can be video, image, voice, text and the like, in order to ensure that the data can be effectively transmitted, the data is required to be split into a plurality of frames with fixed length, if the data is less than one frame, the frames are required to be filled to the designated length according to a set rule, then the transmitter sequentially transmits the frames, the receiver receives and assembles the data frame by frame, a frame synchronization method is required to be provided between the receiving and transmitting devices, a special synchronization code group method is required to be inserted, namely, the transmitter inserts a group of fixed information at the head or tail of each frame as a synchronization mark for marking the beginning or end position of the data frame, the receiver continuously detects the synchronization mark after receiving the data, and then the frame synchronization can be completed according to the frame length acquisition information, and the complete effective data frame is obtained.
The input data stream of the frame synchronization is the output data stream after the bit synchronization, and the data after the bit synchronization is bit stream data, so that the frame synchronization needs to be carried out according to the bits in the bit stream data, and a large amount of data with the following bits are spliced into the prior bit data in the frame synchronization process. The minimum alignment mode of the C language is byte alignment (1 byte=8 bits), so that the bit operation is low in efficiency and complex in logic, and the bit operation is converted into byte operation by a direct value-taking mode. The direct value-taking mode is realized by looking up a table, and two look-up tables, a 3-dimensional splicing table and a 2-dimensional shift table are involved.
Specifically, the splicing table is used for splicing the high-order (0-7) part of one byte (called a source byte) to the low-order (0-7) part of the other byte (called a target byte) so as to realize the inter-byte shift. The table is a 3-dimensional table, such as unsigned CHAR SPLICING [8] [256] [256], wherein the 1 st dimension is the valid bit number of the target byte, and from the high order, 0-7 valid data bits can be contained in the target byte, and when the high order valid data of the target byte can not be modified in splicing, only the high order part in the source byte can be spliced to the low order invalid byte part of the target byte; the 2 nd dimension is a value before target byte splicing, and the whole value range of the single byte value is covered, wherein the value range can be 0-255; the 3 rd dimension is the value before the source byte is spliced, and covers the whole value range of the single byte value, which can be 0-255. Taking the example of splicing the upper 3 bits of the source byte to the lower 3 bits of the target byte, the splicing process is as shown in fig. 3, and one value-taking operation completes the inter-byte bitwise splicing: the size and content of the splice table is fixed, the total size of the table is 8x256x 256= 8388608, and the table content can be generated by a fixed code, see fig. 4.
Further, the shift table is used for sequentially shifting the effective part of the lower bits (0-7) of a certain byte to the upper bits, and freeing the lower bit part to realize the shift in the byte. The table is a 2-dimensional table, such as unsigned CHAR SHIFTING [8] [256], wherein the 1 st dimension is the invalid bit number in the byte, and from the high bit, there can be 0-7 invalid bit numbers in the byte, which indicates how many bits need to be moved from the low bit to the high bit, and the low bit vacated after the movement is filled with 0; the 2 nd dimension is the value of the byte to be moved, and covers the whole value range of the single byte value, which can be 0-255. Taking the left shift of the original byte by 3 bits as an example, the shift process is as shown in fig. 5, one value-taking operation completes the shift in the byte, the low 3 bits of the byte value of the result after the shift are invalid, and the default 0 is filled: the size and content of the shift table is fixed, the total size of the table is 8x256=2048, and the table content can be generated by a fixed code, see fig. 6.
In the above embodiment, the shift table and the splice table are generated using the C language as an example, and the shift table and the splice table may be generated using another computer programming language, which is not limited in the embodiment of the present specification.
In one possible implementation manner, obtaining the bit stream data, caching the bit stream data based on the splicing information and the shift information to determine target cache data includes: acquiring bit stream data, caching the bit stream data into a first cache, and determining a byte data stream; moving the byte data stream to a first position of a second buffer memory based on the splicing information, and determining residual bit data; and moving the residual bit data to a second position of the second buffer memory based on the shift information, and determining target buffer memory data.
The bit stream data may be bit stream data after bit synchronization acquired from the receiver. The first buffer may be a received bitstream data buffer for receiving bit-synchronized bitstream data, and the second buffer may be a data frame buffer for storing splice-shifted frame data. The target buffer data may be buffer data in a data frame buffer.
Specifically, a group of bit stream data after bit synchronization is obtained from a receiver and stored in a received bit stream data buffer, a first byte is marked as a current byte, the current byte of the received bit stream data buffer is spliced to a last byte of a data frame buffer by utilizing a splicing table, the rest bit bits after the current byte splicing of the received bit stream data buffer are moved to a next byte of the last byte of the data frame buffer by utilizing a shifting table, the byte is taken as the last byte of the data frame buffer, and then the next byte of the received bit stream data buffer is taken as the current byte.
It should be noted that, the above-mentioned process of receiving the bitstream data and storing the bitstream data into the received bitstream data buffer, and then storing the received bitstream data buffer into the data frame buffer by using the splicing table and the shifting table is a cyclic process in frame synchronization, that is, after the data in the received bitstream data buffer is processed, a set of bitstream data after bit synchronization is acquired from the receiver and stored into the received bitstream data buffer.
In the embodiment of the specification, the concatenation between two bytes does not need to make complex left-right movement, high-low conversion, logical AND or operation, and can be completed only by a simple value-taking mode, and the time complexity of value (query) from the concatenation table reaches the minimum O (1). The shifting of the single byte can be completed only by a simple value-taking mode, and the time complexity of the value (inquiry) from the shifting table reaches the minimum O (1).
Step 202: and judging whether the target cache data is matched with a special synchronous code group or not, and determining a matching result.
In one possible implementation, determining whether the target cache data matches a special synchronization code group, determining a matching result, includes: determining a target synchronous code group and acquiring a head synchronous code group of target cache data; under the condition that the target synchronous code group is the same as the head synchronous code group, the matching result is matched; and under the condition that the target synchronous code group and the head synchronous code group are not identical, the matching result is unmatched.
In practical application, the codeword is specified as: 0011011. the frame synchronization is to search and identify the synchronization code word from the received data stream, and take the time slot as the head of a frame to make the frame structure of the receiving end and the transmitting end completely consistent, thereby ensuring the synchronous work of the two exchangers, and realizing the correct receiving and exchanging of the digital information.
Step 203: and performing frame synchronization based on the matching result, the splicing information and the shift information, and determining target frame data.
In one possible implementation, frame synchronization is performed based on the matching result, the splicing information, and the shift information, and determining the target frame data includes: if the matching result is unmatched, moving preset bits for the target cache data, and determining target bits; performing special synchronous code group matching based on the length of the target bit and the bit length threshold of the special synchronous code group; and under the condition that the matching result is matched, performing frame synchronization based on the splicing information and the shift information, and determining target frame data.
In practical application, it is determined whether the data frame buffer header matches a special synchronization code group, if not, the whole data frame buffer needs to be shifted to the left by 1 bit, and in the process of shifting to the left, the operation is performed by using the above-mentioned splicing table and shift table, and detailed processes are not repeated.
In the embodiment of the specification, besides the received bit stream data cache for storing bit stream data and the data frame cache for storing the synchronized data frames, no extra storage space is required to be opened in the synchronization process, so that the application and recovery cost of memory resources are greatly reduced.
In one possible implementation, performing special synchronization code group matching based on the length of the target bit and a bit length threshold of the special synchronization code group includes: comparing the length of the target bit with a bit length threshold of a special synchronous code group; under the condition that the length of the target bit is greater than or equal to the bit length threshold, determining whether a special synchronous code group is matched based on the target cache data, and determining a matching result until the matching result is matched; in the case that the length of the target bit is smaller than the bit length threshold, acquiring the bit stream data is performed until the matching result is matched.
Further, after the left shift is completed, checking whether the remaining effective bit length of the data frame buffer is greater than or equal to the bit length of the special synchronous code group, if not, indicating that the matching operation cannot be executed, and continuing to splice one byte from the received bit stream data buffer to the data frame buffer; otherwise, continuing to judge whether the data frame buffer head matches the special synchronous code group. And marking the matching state of the special synchronous code group as matched until the complete special synchronous code group is matched.
In one possible implementation, frame synchronization is performed based on the splicing information and the shift information, and determining the target frame data includes: acquiring updated bit stream data, caching the updated bit stream data into a first cache, and determining an updated byte data stream; moving the updated byte data stream to a first position of the second buffer based on the splicing information, and determining updated residual bit data; based on the shift information, moving the updated remaining bit data to a second position of the second cache, and determining updated cache data; and determining target frame data based on the length of the updated cache data and a frame length bit threshold of a preset data frame length.
In practical application, after the synchronous code group matching state is matched, the receiving of the residual data can be carried out, and the complete frame data is spliced.
Specifically, starting from the current byte of the received bit stream data buffer, splicing the current byte of the received bit stream data buffer to the last byte of the data frame buffer by using a splicing table, moving the rest bits after splicing the current byte of the received bit stream data buffer to the next byte of the last byte of the data frame buffer by using a shifting table, taking the byte as the last byte of the data frame buffer, and then taking the next byte of the received bit stream data buffer as the current byte. After each splicing of a section of data, judging whether the current effective bit length of the data frame buffer is greater than or equal to the designated data frame length, thereby determining whether to splice a complete frame of data.
In one possible implementation, determining the target frame data based on updating the length of the buffered data and a frame length bit threshold of a preset data frame length includes: comparing the length of the updated cache data with a frame length bit threshold value of a preset data frame length; determining target frame data under the condition that the length of the updated cache data is greater than or equal to a frame length bit threshold value; and under the condition that the length of the update cache data is smaller than the frame length bit threshold value, acquiring the update bit stream data until the target frame data is determined.
If the frame length of the whole data frame is not enough, continuing splicing from the current byte of the received bit stream data buffer, otherwise, indicating that the frame is synchronized to a whole data frame, taking out bits with the designated frame length from the data frame buffer head as a whole data frame, and moving the rest bits in the data frame buffer to the data frame buffer head by utilizing a splicing table and a shifting table.
In the embodiment of the present disclosure, only 1 memory copy is required from the received bitstream data buffer to the data frame buffer during the whole process of searching the special synchronization code group and obtaining the complete data frame. The efficiency of data operation is improved.
Further, after the data frame is obtained, the matching state is marked as unmatched, whether the frame synchronization operation needs to be continuously executed is judged, if so, the frame synchronization of the next round is continuously executed from the current byte of the received bit stream data buffer until the frame synchronization request is detected to be stopped or no bit stream data is input.
The embodiment of the specification provides a frame synchronization method and a device, wherein the frame synchronization method comprises the following steps: acquiring bit stream data, and caching the bit stream data based on splicing information and shift information to determine target cache data; judging whether target cache data are matched with a special synchronous code group or not, and determining a matching result; and performing frame synchronization based on the matching result, the splicing information and the shift information, and determining target frame data. Caching the bit stream data based on splicing information and shift information to determine target cache data by acquiring the bit stream data; judging whether target cache data are matched with a special synchronous code group or not, and determining a matching result; and carrying out frame synchronization based on the matching result, the splicing information and the shift information to determine target frame data, so that the frame synchronization can be completed only by a table look-up mode, the complexity is reduced, and the frame synchronization efficiency is improved.
Corresponding to the above method embodiments, the present disclosure further provides an embodiment of a frame synchronization device, and fig. 7 shows a schematic structural diagram of a frame synchronization device according to one embodiment of the present disclosure. As shown in fig. 7, the apparatus includes:
A data acquisition module 701 configured to acquire bitstream data, cache the bitstream data based on the splicing information and the shift information to determine target cache data;
The code group synchronization module 702 is configured to determine whether the target cache data is matched with a special synchronization code group, and determine a matching result;
the data synchronization module 703 is configured to perform frame synchronization based on the matching result, the splicing information and the shift information, and determine target frame data.
In one possible implementation, the data acquisition module 701 is further configured to:
acquiring bit stream data, caching the bit stream data into a first cache, and determining a byte data stream;
moving the byte data stream to a first position of a second buffer memory based on the splicing information, and determining residual bit data;
And moving the residual bit data to a second position of the second buffer memory based on the shift information, and determining target buffer memory data.
In one possible implementation, the code group synchronization module 702 is further configured to:
determining a target synchronous code group and acquiring a head synchronous code group of target cache data;
under the condition that the target synchronous code group is the same as the head synchronous code group, the matching result is matched;
and under the condition that the target synchronous code group and the head synchronous code group are not identical, the matching result is unmatched.
In one possible implementation, the data synchronization module 703 is further configured to:
If the matching result is unmatched, moving preset bits for the target cache data, and determining target bits;
Performing special synchronous code group matching based on the length of the target bit and the bit length threshold of the special synchronous code group;
and under the condition that the matching result is matched, performing frame synchronization based on the splicing information and the shift information, and determining target frame data.
In one possible implementation, the data synchronization module 703 is further configured to:
comparing the length of the target bit with a bit length threshold of a special synchronous code group;
under the condition that the length of the target bit is greater than or equal to the bit length threshold, determining whether a special synchronous code group is matched based on the target cache data, and determining a matching result until the matching result is matched;
in the case that the length of the target bit is smaller than the bit length threshold, acquiring the bit stream data is performed until the matching result is matched.
In one possible implementation, the data synchronization module 703 is further configured to:
acquiring updated bit stream data, caching the updated bit stream data into a first cache, and determining an updated byte data stream;
moving the updated byte data stream to a first position of the second buffer based on the splicing information, and determining updated residual bit data;
Based on the shift information, moving the updated remaining bit data to a second position of the second cache, and determining updated cache data;
and determining target frame data based on the length of the updated cache data and a frame length bit threshold of a preset data frame length.
In one possible implementation, the data synchronization module 703 is further configured to:
comparing the length of the updated cache data with a frame length bit threshold value of a preset data frame length;
determining target frame data under the condition that the length of the updated cache data is greater than or equal to a frame length bit threshold value;
And under the condition that the length of the update cache data is smaller than the frame length bit threshold value, acquiring the update bit stream data until the target frame data is determined.
The embodiment of the specification provides a frame synchronization method and device, wherein the frame synchronization device comprises: acquiring bit stream data, and caching the bit stream data based on splicing information and shift information to determine target cache data; judging whether target cache data are matched with a special synchronous code group or not, and determining a matching result; and performing frame synchronization based on the matching result, the splicing information and the shift information, and determining target frame data. Caching the bit stream data based on splicing information and shift information to determine target cache data by acquiring the bit stream data; judging whether target cache data are matched with a special synchronous code group or not, and determining a matching result; and carrying out frame synchronization based on the matching result, the splicing information and the shift information to determine target frame data, so that the frame synchronization can be completed only by a table look-up mode, the complexity is reduced, and the frame synchronization efficiency is improved.
The above is an exemplary scheme of a frame synchronization device of the present embodiment. It should be noted that, the technical solution of the frame synchronization device and the technical solution of the frame synchronization method belong to the same concept, and details of the technical solution of the frame synchronization device, which are not described in detail, can be referred to the description of the technical solution of the frame synchronization method.
Fig. 8 illustrates a block diagram of a computing device 800 provided in accordance with one embodiment of the present description. The components of computing device 800 include, but are not limited to, memory 810 and processor 820. Processor 820 is coupled to memory 810 through bus 830 and database 850 is used to hold data.
Computing device 800 also includes access device 840, access device 840 enabling computing device 800 to communicate via one or more networks 860. Examples of such networks include public switched telephone networks (PSTN, public Switched Telephone Network), local area networks (LAN, local Area Network), wide area networks (WAN, wide Area Network), personal area networks (PAN, personal Area Network), or combinations of communication networks such as the internet. The access device 840 may include one or more of any type of network interface, wired or wireless, such as a network interface card (NIC, network interface controller), such as an IEEE802.11 wireless local area network (WLAN, wireless Local Area Network) wireless interface, a worldwide interoperability for microwave access (Wi-MAX, worldwide Interoperability for Microwave Access) interface, an ethernet interface, a universal serial bus (USB, universal Serial Bus) interface, a cellular network interface, a bluetooth interface, near Field Communication (NFC).
In one embodiment of the present description, the above-described components of computing device 800, as well as other components not shown in FIG. 8, may also be connected to each other, such as by a bus. It should be understood that the block diagram of the computing device illustrated in FIG. 8 is for exemplary purposes only and is not intended to limit the scope of the present description. Those skilled in the art may add or replace other components as desired.
Computing device 800 may be any type of stationary or mobile computing device including a mobile computer or mobile computing device (e.g., tablet, personal digital assistant, laptop, notebook, netbook, etc.), mobile phone (e.g., smart phone), wearable computing device (e.g., smart watch, smart glasses, etc.), or other type of mobile device, or a stationary computing device such as a desktop computer or personal computer (PC, personal Computer). Computing device 800 may also be a mobile or stationary server.
Wherein the processor 820 is configured to execute computer-executable instructions that, when executed by the processor, perform the steps of the frame synchronization method described above. The foregoing is a schematic illustration of a computing device of this embodiment. It should be noted that, the technical solution of the computing device and the technical solution of the frame synchronization method belong to the same concept, and details of the technical solution of the computing device, which are not described in detail, can be referred to the description of the technical solution of the frame synchronization method.
An embodiment of the present disclosure also provides a computer-readable storage medium storing computer-executable instructions that, when executed by a processor, implement the steps of the frame synchronization method described above.
The above is an exemplary version of a computer-readable storage medium of the present embodiment. It should be noted that, the technical solution of the storage medium and the technical solution of the frame synchronization method described above belong to the same concept, and details of the technical solution of the storage medium not described in detail may be referred to the description of the technical solution of the frame synchronization method described above.
An embodiment of the present specification also provides a computer program, wherein the computer program, when executed in a computer, causes the computer to perform the steps of the frame synchronization method described above.
The above is an exemplary version of a computer program of the present embodiment. It should be noted that, the technical solution of the computer program and the technical solution of the frame synchronization method belong to the same concept, and details of the technical solution of the computer program, which are not described in detail, can be referred to the description of the technical solution of the frame synchronization method.
The foregoing describes specific embodiments of the present disclosure. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
The computer instructions include computer program code that may be in source code form, object code form, executable file or some intermediate form, etc. The computer readable medium may include: any entity or device capable of carrying the computer program code, a recording medium, a U disk, a removable hard disk, a magnetic disk, an optical disk, a computer Memory, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), an electrical carrier signal, a telecommunications signal, a software distribution medium, and so forth. It should be noted that the computer readable medium contains content that can be appropriately scaled according to the requirements of jurisdictions in which such content is subject to legislation and patent practice, such as in certain jurisdictions in which such content is subject to legislation and patent practice, the computer readable medium does not include electrical carrier signals and telecommunication signals.
It should be noted that, for simplicity of description, the foregoing method embodiments are all expressed as a series of combinations of actions, but it should be understood by those skilled in the art that the embodiments are not limited by the order of actions described, as some steps may be performed in other order or simultaneously according to the embodiments of the present disclosure. Further, those skilled in the art will appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily all required for the embodiments described in the specification.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments.
The preferred embodiments of the present specification disclosed above are merely used to help clarify the present specification. Alternative embodiments are not intended to be exhaustive or to limit the invention to the precise form disclosed. Obviously, many modifications and variations are possible in light of the teaching of the embodiments. The embodiments were chosen and described in order to best explain the principles of the embodiments and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. This specification is to be limited only by the claims and the full scope and equivalents thereof.
Claims (10)
1. A method of frame synchronization, comprising:
Acquiring bit stream data, and caching the bit stream data based on splicing information and shift information to determine target cache data;
Judging whether the target cache data is matched with a special synchronous code group or not, and determining a matching result;
And performing frame synchronization based on the matching result, the splicing information and the shift information, and determining target frame data.
2. The method of claim 1, wherein the obtaining the bitstream data, buffering the bitstream data based on the splice information and the shift information to determine the target buffered data, comprises:
Acquiring bit stream data, caching the bit stream data into a first cache, and determining a byte data stream;
Moving the byte data stream to a first position of a second buffer memory based on splicing information, and determining residual bit data;
And moving the residual bit data to a second position of the second cache based on the shift information, and determining target cache data.
3. The method of claim 1, wherein said determining whether the target cache data matches a particular set of synchronization codes, determining a match result, comprises:
Determining a target synchronous code group and acquiring a head synchronous code group of the target cache data;
the matching result is matched under the condition that the target synchronous code group and the head synchronous code group are the same;
and under the condition that the target synchronous code group and the head synchronous code group are not identical, the matching result is unmatched.
4. The method of claim 2, wherein the determining target frame data based on the matching result, the stitching information, and the shift information for frame synchronization comprises:
If the matching result is unmatched, moving the target cache data by a preset bit, and determining a target bit;
Performing special synchronous code group matching based on the length of the target bit and the bit length threshold of the special synchronous code group;
and under the condition that the matching result is matched, carrying out frame synchronization based on the splicing information and the shift information, and determining target frame data.
5. The method of claim 4, wherein said performing special synchronization code group matching based on the length of the target bit and a bit length threshold of the special synchronization code group comprises:
Comparing the length of the target bit with a bit length threshold of the special synchronous code group;
executing the step of determining whether to match a special synchronous code group based on the target cache data under the condition that the length of the target bit is greater than or equal to the bit length threshold value, and determining a matching result until the matching result is matched;
and executing the obtained bit stream data until the matching result is matched under the condition that the length of the target bit is smaller than the bit length threshold value.
6. The method of claim 4, wherein said determining target frame data based on frame synchronization of said splice information and said shift information comprises:
Acquiring updated bit stream data, caching the updated bit stream data into the first cache, and determining an updated byte data stream;
Based on the splicing information, moving the updated byte data stream to a first position of a second buffer memory, and determining updated residual bit data;
Determining updated cache data based on the shift information moving the updated remaining bit data to a second location of the second cache;
and determining target frame data based on the length of the updated cache data and a frame length bit threshold of a preset data frame length.
7. The method of claim 6, wherein the determining the target frame data based on the length of the update buffer data and a frame length bit threshold of a preset data frame length comprises:
comparing the length of the updated cache data with a frame length bit threshold of the preset data frame length;
Determining target frame data under the condition that the length of the updated cache data is greater than or equal to the frame length bit threshold value;
And under the condition that the length of the update cache data is smaller than the frame length bit threshold value, executing the acquisition of the update bit stream data until the target frame data is determined.
8. A frame synchronization device, comprising:
the data acquisition module is configured to acquire bit stream data, and buffer the bit stream data based on splicing information and shift information to determine target buffer data;
the code group synchronization module is configured to judge whether the target cache data is matched with a special synchronous code group or not, and determine a matching result;
And the data synchronization module is configured to perform frame synchronization based on the matching result, the splicing information and the shift information, and determine target frame data.
9. A computing device, comprising:
a memory and a processor;
The memory is configured to store computer executable instructions, and the processor is configured to execute the computer executable instructions, which when executed by the processor, implement the steps of the frame synchronization method of any one of claims 1 to 7.
10. A computer readable storage medium storing computer executable instructions which when executed by a processor perform the steps of the frame synchronization method of any one of claims 1 to 7.
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