CN117954395A - Semiconductor structure and manufacturing method thereof - Google Patents

Semiconductor structure and manufacturing method thereof Download PDF

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Publication number
CN117954395A
CN117954395A CN202211296206.4A CN202211296206A CN117954395A CN 117954395 A CN117954395 A CN 117954395A CN 202211296206 A CN202211296206 A CN 202211296206A CN 117954395 A CN117954395 A CN 117954395A
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China
Prior art keywords
contact pad
semiconductor structure
chip
connection portion
conductive layer
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CN202211296206.4A
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Chinese (zh)
Inventor
吕开敏
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Priority to CN202211296206.4A priority Critical patent/CN117954395A/en
Priority to PCT/CN2023/075977 priority patent/WO2024082495A1/en
Publication of CN117954395A publication Critical patent/CN117954395A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The embodiment of the disclosure relates to the field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure comprises: the chip is provided with a first surface, the first surface comprises an electric connection area and a non-electric connection area, and at least part of the non-electric connection area is positioned at the edge of the first surface; a plurality of first contact pads, wherein the first contact pads are positioned in the non-electric connection area; a plurality of second contact pads, the second contact pads being located in the electrical connection region; the connecting part is at least positioned between part of the first contact pads, and the top surface of the connecting part is lower than the top surface of the first contact pads, so that the problem of chip warpage can be solved.

Description

Semiconductor structure and manufacturing method thereof
Technical Field
The embodiment of the disclosure relates to the field of semiconductors, in particular to a semiconductor structure and a manufacturing method thereof.
Background
A chip is an integrated circuit that is made up of a large number of transistors. Different chips have different integration scales, up to hundreds of millions; as small as tens, hundreds of transistors. The transistor has two states, on and off, denoted by 1, 0. A plurality of 1 and 0 signals generated by a plurality of transistors are set to specific functions (i.e., instructions and data) to represent or process letters, numbers, colors, graphics, etc. After the chip is powered up, a starting instruction is firstly generated to start the chip, and new instructions and data are continuously received to complete the functions.
With the development of electronic technology, miniaturized and light-weight electronic products have become a trend. Accordingly, the chip and the substrate are continuously thinned, and the chip warpage is increasingly obvious and unacceptable due to the thinning of the chip and the substrate.
There is a need for a semiconductor structure that improves the warpage of a chip.
Disclosure of Invention
The embodiment of the disclosure provides a semiconductor structure and a manufacturing method thereof, which can at least improve the problem of chip warpage.
According to some embodiments of the present disclosure, an aspect of the embodiments of the present disclosure provides a semiconductor structure, including a chip, the chip having a first surface, and the first surface including an electrical connection region and a non-electrical connection region, wherein at least a portion of the non-electrical connection region is located at an edge of the first surface; a plurality of first contact pads, wherein the first contact pads are positioned in the non-electric connection area; a plurality of second contact pads, wherein the second contact pads are positioned in the electrical connection area; and the connecting part is positioned at least between part of the first contact pads, and the top surface of the connecting part is lower than the top surface of the first contact pads.
In some embodiments, the plurality of first contact pads are arranged in an array, and the plurality of first contact pads and the plurality of connection portions form a grid structure, and the grid structure includes: square grid, diamond grid, trapezoidal grid or cross grid.
In some embodiments, the connection is further located between two of the first contact pads in a diagonal position in the grid structure.
In some embodiments, a plurality of the first contact pads are arranged in an array, and the connection portion is located between two of the first contact pads in a diagonal position.
In some embodiments, the thickness of the connection portion is less than the thickness of the first contact pad in a direction perpendicular to the first face.
In some embodiments, the thickness of the connection portion is 1/5 to 1/3 of the thickness of the first contact pad.
In some embodiments, the first contact pad is of unitary construction with the adjacent connection.
In some embodiments, the first contact pad comprises: a first conductive layer and a second conductive layer which are laminated in sequence; the first conductive layer and the adjacent connecting part are of an integral structure.
In some embodiments, all of the non-electrical connection regions are provided with the connection portion; or the non-electric connection area comprises a corner part, and the connection part is only positioned at the corner part.
In some embodiments, further comprising: a support portion located on the first contact pad surface; and the electric connection part is positioned on the surface of the second contact pad.
In some embodiments, a plurality of the chips are stacked, and the support portion is configured to support adjacent ones of the chips, and the electrical connection portion is configured to electrically connect adjacent ones of the chips.
In some embodiments, the chip further has a second face disposed opposite the first face, the first contact pad being further located on the second face; the semiconductor structure further includes a solder structure located on a top surface of the first contact pad of the second face.
According to some embodiments of the present disclosure, another aspect of embodiments of the present disclosure further provides a method for manufacturing a semiconductor structure, including: providing a chip, wherein the chip is provided with a first surface, the first surface comprises a non-electric connection area and an electric connection area, and at least part of the non-electric connection area is positioned at the edge of the first surface; and forming a first contact pad, a second contact pad and a connecting part, wherein the first contact pad is positioned in the non-electric connection area, the second contact pad is positioned in the electric connection area, the connecting part is positioned between at least part of the first contact pads, and the top surface of the connecting part is lower than the top surface of the first contact pad.
In some embodiments, the method of forming the connection comprises: forming a seed layer, wherein the seed layer is positioned on the surface of the chip; forming a first mask layer, wherein the first mask layer is positioned on the surface of the seed layer, the first mask layer is provided with a target pattern, and the target pattern exposes part of the surface of the seed layer; and forming a connecting part, wherein the connecting part is positioned in the target graph.
In some embodiments, the first contact pad comprises: the method for forming the first contact pad comprises the following steps of: after the connecting part is formed, a second mask layer is formed on the surface of the connecting part, and the second mask layer is spaced from the first mask layer; and forming a second conductive layer, wherein the second conductive layer is positioned between the first mask layer and the second mask layer, the part of the connecting part in contact connection with the second conductive layer is used as the first conductive layer, and the first conductive layer and the second conductive layer are used as the first contact pad.
In some embodiments, after forming the first contact pad, further comprising: removing the first mask layer and the second mask layer; and etching the seed layer by taking the first contact pad as a mask to form the spaced seed layers.
In some embodiments, a method of forming the connection and the first contact pad includes: forming an initial conductive layer, wherein the initial conductive layer is positioned on the surface of the chip; the initial conductive layer is etched to form the connection portion and the first contact pad.
The technical scheme provided by the embodiment of the disclosure has at least the following advantages: the connecting parts are arranged between the first contact pads of the non-electric connection areas of the chips, so that the situation of mismatching of stress between different materials on the chips can be resisted, the edge warpage of the chips can be reduced by increasing the coverage area of the connecting parts on the first surfaces of the chips, and the welding effect can be improved in the subsequent chip welding process.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, which are not to be construed as limiting the embodiments unless specifically indicated otherwise; in order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the conventional technology, the drawings required for the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.
FIG. 1 is a cross-sectional view of a semiconductor structure according to one embodiment of the present disclosure;
Fig. 2 is a top view of a semiconductor structure according to an embodiment of the present disclosure;
FIG. 3 is a top view of another semiconductor structure provided in an embodiment of the present disclosure;
FIG. 4 is a schematic view of a partial structure according to an embodiment of the present disclosure;
fig. 5 is a cross-sectional view of another semiconductor structure provided in an embodiment of the present disclosure;
fig. 6 is a cross-sectional view of yet another semiconductor structure provided in an embodiment of the present disclosure;
fig. 7 to 13 are schematic structural diagrams corresponding to steps of a method for fabricating a semiconductor structure according to an embodiment of the disclosure;
fig. 14 to 16 are schematic structural diagrams corresponding to steps of a method for fabricating a semiconductor structure according to another embodiment of the present disclosure.
Detailed Description
As known from the background art, in the process of stacking and packaging chips, since various materials are used in the process of stacking and packaging, such as substrate materials, passivation layer materials, metal materials and the like of the chips, stress mismatch between the different materials causes the chips to bend, and compared with the middle part, the bending degree of the edges of the chips is larger, and the warpage of the chips can greatly affect the subsequent process, and along with continuous thinning of the chips, the warpage of the chips has a larger effect on the subsequent process.
The implementation of the present disclosure provides a semiconductor structure, which is characterized in that at least part of non-electric connection areas of a chip are arranged at the edge of a first surface of the chip, a plurality of first contact pads are arranged in the non-electric connection areas, connection parts are arranged between at least part of the first contact pads, and different first contact pads are connected through the connection parts, so that the stress resistance of the edge of the chip is improved, the stress effect of passivation layer materials on the chip is reduced, and the warpage of the chip is improved.
Embodiments of the present disclosure will be described in detail below with reference to the attached drawings. However, those of ordinary skill in the art will understand that in the various embodiments of the present disclosure, numerous technical details have been set forth in order to provide a better understanding of the present disclosure. The technical solutions claimed in the present disclosure can be implemented without these technical details and with various changes and modifications based on the following embodiments.
Referring to fig. 1 to 6, wherein fig. 1 is a cross-sectional view of a semiconductor structure provided in an embodiment of the present disclosure, fig. 2 is a top view of a semiconductor structure provided in an embodiment of the present disclosure, fig. 3 is a top view of another semiconductor structure provided in an embodiment of the present disclosure, fig. 4 is a partial schematic view of a semiconductor structure provided in an embodiment of the present disclosure, fig. 5 is a cross-sectional view along a dotted line direction of fig. 4, and fig. 6 is another cross-sectional view along a dotted line direction of fig. 4.
Specifically, the semiconductor structure includes: the chip 100, the chip 100 has a first surface 101, and the first surface 101 includes an electrical connection area 102 and a non-electrical connection area 103, wherein at least a portion of the non-electrical connection area 103 is located at an edge of the first surface 101; a plurality of first contact pads 110, wherein the first contact pads 110 are located in the non-electrical connection region 103; a plurality of second contact pads 120, wherein the second contact pads 120 are located in the electrical connection region 102; the connection part 130, the connection part 130 is at least between part of the first contact pads 110, and the top surface of the connection part 130 is lower than the top surface of the first contact pad 110.
The electrical performance of the chip 100 can not be affected by arranging the connecting portion 130 in the non-electrical connection region 103 of the chip, and the warpage of the chip 100 can be improved by arranging at least part of the non-electrical connection region 103 at the edge of the chip 100 and arranging the connecting portion 130 in the non-electrical connection region 103, and the warpage of the chip 100 can be reduced by increasing the stress resistance of the first surface of the chip 100.
It is understood that the warpage is the degree of bending of the chip after the chip is deformed, compared with a chip with a flat surface.
In some embodiments, the chip 100 may be a functional structure, that is, the chip 100 may have various circuit structures, such as transistors, wiring layers, word lines, bit lines, capacitors, and the like, within the chip.
In some embodiments, the first side of the chip 100 may refer to the back side of the chip, that is, the first contact pad 110, the second contact pad 120, and the connection portion 130 may be disposed on the back side of the chip.
In some embodiments, the electrical connection region 102 refers to a region with a functional structure, such as: in the area where data information needs to be input or data information needs to be read, the second contact pads 120 of the electrical connection area 102 are spaced apart from each other, and each second contact pad 120 may be in contact connection with only one structure in the electrical connection area 102 of the chip 100, for example, one second contact pad 120 is in contact connection with only one bit line in the electrical connection area 102, data information is provided to only the bit line through the second contact pad 120, data information is provided to only one word line in the electrical connection area 102 through the second contact pad 120, and since the word line and the bit line in the electrical connection area 102 cannot be in direct contact connection, different second contact pads 120 respectively in electrical connection with the word line and the bit line are also spaced apart from each other.
In some embodiments, the non-electrical connection region 103 refers to a region without a functional structure, that is, the structure in the non-electrical connection region 103 does not affect the specific function of the chip 100, and the non-electrical connection region 103 can be disposed at the edge of the chip 100, so as to protect the electrical connection region 102, because the non-electrical connection region 103 does not affect the function of the chip 100, even if the non-electrical connection region 103 is damaged to some extent, the non-electrical connection region 103 will not affect the chip 100 greatly.
In some embodiments, the first contact pad 110 may be a pad structure, and the first contact pad 110 located in the non-electrical connection region 103 may be located only on the surface of the chip 100, that is, the first contact pad 110 may not contact the structure within the chip 100.
In some embodiments, the chip 100 further has a second side 104, the second side 104 is disposed opposite to the first side 101, and the first contact pad 110 is further located on the second side 104; the semiconductor structure further includes a solder structure 140, the solder structure 140 being located on a top surface of the first contact pad 110 of the second side 104. It will be appreciated that in some embodiments, the bonding between the chips 100 may be performed by soldering the soldering structure 140 of the second side 104 of one chip 100 to the first contact pad 110 of the first side 101 of another chip 100, so that the connection between the chips 100 is achieved, and the first contact pad 110 is located in the non-electrical connection region 103 of the chip, and the function of the electrical connection region 102 in the chip 100 may be prevented from being affected by the bonding performed by the first contact pad 110 of the non-electrical connection region 103.
In some embodiments, the second contact pad 120 may include a pad structure and a conductive via penetrating through the chip 100, and the pad structure is communicated with a structure in the chip through the conductive via, so that signal data may be input to a circuit structure in the chip 100 or data information in the chip 100 may be read out through the pad structure of the second contact pad 120.
In some embodiments, the second contact pad 120 may further include a pad structure on the second side 104, that is, the second contact pad 120 includes a pad structure on the first side 101, a conductive via penetrating the chip 100, and a pad structure on the second side 104.
In some embodiments, the connection portion 130 is used to connect two first contact pads 110, so that the stress resistance of the first contact pads 110 can be increased, and by providing the connection portion 130, the contact area between the subsequent packaging material or passivation layer material and the substrate material of the chip 100 can be reduced, so that the surface area where the stress mismatch phenomenon between different materials occurs can be reduced, so that the warpage of the chip 100 can be reduced, and by providing at least part of the connection portion 130 with a non-electrical connection region located at the edge of the chip 100, the weight of the edge of the chip 100 can be increased, so that the warpage of the edge of the chip can be further balanced.
By providing the top surface of the connection portion 130 lower than the top surface of the first contact pad 110, it is possible to avoid solder overflowing to the top surface of the connection portion 130 when the chip 100 is connected to each other and to avoid affecting the soldering effect of the chip 100. Taking solder as an example, by setting the top surface of the connection portion 130 lower than the top surface of the first contact pad 110, a phenomenon of creeping tin can be avoided, and the reliability of soldering of the chip 100 can be improved.
In some embodiments, the plurality of first contact pads 110 are arranged in an array, and the plurality of first contact pads 110 and the plurality of connection portions 130 form a grid structure, and the grid structure includes: square grid, diamond grid, trapezoidal grid or cross grid. Referring to fig. 2 to 4, it may be understood that the grid structure herein refers to a shape of orthographic projection on the surface of the chip 100 after the plurality of first contact pads 110 are connected with the plurality of connection portions 130, and the square grid, the diamond grid, the trapezoid grid or the cross grid is a description of the orthographic projection shape, for example, referring to fig. 2, the grid structure shown in fig. 2 presents a trapezoid structure, which may be referred to as a trapezoid grid. By arranging the plurality of first contact pads 110 and the plurality of connecting portions 130 to form a grid structure, the plurality of first contact pads 110 can be connected into a whole, so that the stress resistance of the first contact pads 110 can be increased, the warpage of the chip 100 can be reduced, and the yield of the subsequent process steps can be improved.
In some embodiments, the connection 130 is also located between two first contact pads 110 in a diagonal position in the grid structure. Taking fig. 2 as an example, as shown in the drawing, the first contact pads 110 in the non-electrical connection area 103 have four rows and nine columns, which define a first row, a second row, a third row and a fourth row of the first contact pads 110 from top to bottom, and from left to right, and from first row to ninth row of the first contact pads 110 respectively, where the connection portion 130 is further located between two first contact pads 110 in a diagonal position in the grid structure, which means that the connection portion 130 is located between the first contact pads 110 in the first row and the first contact pads 110 in the second row, or the connection portion 130 is located between the first contact pads 110 in the first row and the first contact pads 110 in the third row, and so on, that is, a part of the extension direction of the connection portion 130 forms a certain included angle with the arrangement direction of the first contact pads 110, and a part of the extension direction of the connection portion 130 is the same as the arrangement direction of the first contact pads 110.
The terms top-to-bottom and left-to-right in the above description refer to top-to-bottom and left-to-right in the schematic structural diagram shown in fig. 2, and do not correspond to the actual structure.
In some embodiments, the plurality of first contact pads 110 are arranged in an array, and the connection portion 130 is located between two first contact pads 110 in a diagonal position. Referring to fig. 3, the extending direction of the connection portion 130 and the arrangement direction of the first contact pads 110 form a certain included angle, and the warpage of the chip 100 can be improved by arranging a plurality of first contact pads 110 in an array arrangement, and the connection portion 130 is located between two first contact pads 110 located at diagonal positions.
In some embodiments, all of the non-electrical connection regions 103 are provided with connection portions 130; or the non-electrical connection region 103 includes a corner portion, and the connection portion 130 is only located at the corner portion. Referring to fig. 2, it can be understood that, in the semiconductor structure shown in fig. 2, all the non-electrical connection regions 103 are provided with the connection portions 130, that is, the first contact pads 110 located in the non-electrical connection regions 103 are connected to the connection portions 130; referring to fig. 3, the semiconductor structure shown in fig. 3 is that the non-electrical connection region 103 includes a corner portion, the connection portion 130 is only located at the corner portion, the corner portion of the chip 100 is generally the portion with the largest warpage of the chip 100, and by disposing the connection portion 130 at the corner portion of the chip 100, the cost of the whole semiconductor structure can be reduced while the warpage of the chip 100 is improved to a certain extent.
In some embodiments, the thickness of the connection portion 130 is smaller than the thickness of the first contact pad 110 in a direction perpendicular to the first face 101, and reliability during soldering of the chip 100 may be improved by providing the thickness of the connection portion 130 to be smaller than the thickness of the first contact pad 110.
In some embodiments, the thickness of the connection portion 130 is 1/5 to 1/3 of the thickness of the first contact pad 110, it is understood that the thicker the thickness of the connection portion 130, the stronger the capability of improving the warpage of the chip 100, however, the thicker the thickness of the connection portion 130, the more likely the chip 100 is abnormal when being connected to each other, so by setting the thickness of the connection portion to be 1/5 to 1/3 of the thickness of the first contact pad 110, the connection portion 130 has a certain reliability while improving the warpage of the chip 100.
In some embodiments, the thickness of the connection portion 130 may be 2-4 μm, for example, 3 μm or 4 μm, etc., it is understood that when the thickness of the connection portion 130 is less than 2 μm, the ability of the connection portion 130 to improve the warpage of the chip 100 is not strong, and when the thickness of the connection portion 130 is greater than 4 μm, the thickness of the connection portion 130 is too thick, which may affect the soldering of the subsequent chip 100, so that by setting the thickness of the connection portion 130 to be 2-4 μm, the connection portion 130 may have a certain improving ability while avoiding affecting the soldering of the subsequent chip 100.
It is understood that the thickness herein refers to the dimension of the connection 130 in a direction perpendicular to the surface of the chip 100.
In some embodiments, the first contact pad 110 and the adjacent connection portion 130 are integrally formed, and the reliability of the connection between the first contact pad 110 and the adjacent connection portion 130 can be improved by providing the first contact pad 110 and the adjacent connection portion 130 as an integrally formed structure, so as to avoid abnormal connection between the connection portion 130 and the first contact pad 110.
The first contact pad 110 is integrally formed with the adjacent connection portion 130, that is, by forming the first contact pad 110 and the connection portion 130 in the same process step when forming the first contact pad 110 and the connection portion 130, it is possible to reduce the abnormality of the connection between the first contact pad 110 and the connection portion 130.
In other embodiments, the first contact pad 110 and the adjacent connection portion 130 may have two different structures, that is, the first contact pad 110 and the connection portion 130 are formed when the first contact pad 110 and the connection portion 130 are formed, and the arrangement of the connection portion 130 may be flexibly adjusted according to the actual requirement by arranging the first contact pad 110 and the adjacent connection portion 130.
In some embodiments, the material of the connection portion 130 is the same as that of the first contact pad 110, so that the abnormality caused by the difference of materials between the connection portion 130 and the first contact pad 110 can be avoided by providing that the material of the connection portion 130 is the same as that of the first contact pad 110, and the interface state between the connection portion 130 and the first contact pad 110 can be reduced, thereby improving the reliability of the semiconductor structure.
In some embodiments, the material of the connection portion 130 may be a metal material such as copper, silver or gold, the material of the first contact pad 110 may be a metal material such as copper, silver or gold, the material of the second contact pad 120 may be a metal material such as copper, silver or gold, and the materials of the connection portion 130, the first contact pad 110 and the second contact pad 120 may be selected according to practical requirements.
In some embodiments, the width of the connection portion 130 is 0.1 μm to 2 μm, it is understood that the wider the width of the connection portion 130, the greater the capability of improving the warpage of the chip 100, the wider the width of the connection portion 130, and the material of the connection portion 130 will expand with heat and contract with cold in the subsequent process, so that the wider the width of the connection portion 130, the gap reserved between different connection portions 130 will be reduced, resulting in the connection portions 130 being squeezed with each other, and therefore, when the width of the connection portion 130 is less than 0.1 μm, the capability of the connection portion 130 of improving the warpage of the chip 100 is weaker, and when the width of the connection portion 130 is greater than 2 μm, the reliability of the connection portion 130 may be affected.
In some embodiments, referring to fig. 6, the first contact pad 110 includes: a first conductive layer 111 and a second conductive layer 112 stacked in this order; the first conductive layer 111 and the adjacent connection portion 130 are integrally formed, and it is understood that the first contact pad 110 and the connection portion 130 can be formed by forming the first conductive layer 111 and the adjacent connection portion 130 and then forming the second conductive layer, and the reliability of the connection between the first conductive layer 111 and the connection portion 130 can be increased by providing the first conductive layer 111 and the adjacent connection portion 130 as an integral structure.
In some embodiments, the materials of the first conductive layer 111 and the second conductive layer 112 may be the same, for example, metal materials such as copper, silver, or gold; in other embodiments, the materials of the first conductive layer 111 and the second conductive layer 112 may be different.
In some embodiments may further comprise: the connection layer 180, the connection layer 180 is located on the top surface of the first contact pad 110, the connection layer 180 can facilitate the interconnection between the chips 100, and the connection tightness of the chips 100 can be improved.
In some embodiments, the semiconductor structure may further include: a supporting part, which is positioned on the surface of the first contact pad 110; the electrical connection portion is located on the surface of the second contact pad 120, and it can be understood that the electrical connection portion is located on the surface of the first contact pad 110 by providing a supporting portion, and the electrical connection portion is located on the surface of the second contact pad 120, so that the chips can be connected with each other by the supporting portion and the electrical connection portion, and the subsequent chips 100 can be conveniently welded by providing the supporting portion and the electrical connection portion.
In some embodiments, a semiconductor structure includes: the plurality of chips 100 are stacked, and the supporting portion is used for supporting the adjacent chips 100, and the electrical connection portion is used for electrically connecting the adjacent chips, it can be understood that connection and signal transmission between different chips 100 can be achieved by providing the supporting portion and the electrical connection portion.
In some embodiments, the material of the support portion may be a harder material to provide support, and the material of the electrical connection portion may be a conductive material to provide signal transmission between the stacked chips 100.
According to the embodiment of the disclosure, the chip 100 is provided with the non-electric connection region 103, at least part of the non-electric connection region 103 is arranged at the edge of the first surface 101 of the chip 100, a plurality of first contact pads 110 are arranged in the non-electric connection region 103, the connection parts 130 are arranged between at least part of the first contact pads 110, and different first contact pads 110 are connected through the connection parts 130, so that the stress resistance of the chip 100 is improved, the stress effect of other materials on the chip 100 is reduced, and the warpage of the chip 100 is improved.
Another embodiment of the present disclosure further provides a method for manufacturing a semiconductor structure, which may be used to form the semiconductor structure described above, and hereinafter, description will be given of the method for manufacturing a semiconductor structure according to another embodiment of the present disclosure with reference to the accompanying drawings, and the same or corresponding parts as those of the foregoing embodiments may be referred to the corresponding description of the foregoing embodiments, which will not be repeated herein.
Referring to fig. 7 to 13 and fig. 2, fig. 7 to 13 are schematic structural diagrams corresponding to each step of a method for manufacturing a semiconductor structure according to an embodiment of the disclosure.
Specifically, the method for manufacturing the semiconductor structure comprises the following steps: providing a chip 100, wherein the chip 100 has a first surface 101, and the first surface 101 includes a non-electrical connection region 103 and an electrical connection region 102, wherein at least a portion of the non-electrical connection region 103 is located at an edge of the first surface 101; the first contact pads 110, the second contact pads 120 and the connection portion 130 are formed, the first contact pads 110 are located in the non-electrical connection region 103, the second contact pads 120 are located in the electrical connection region 102, the connection portion 130 is located at least between part of the first contact pads 110, and the top surface of the connection portion 130 is lower than the top surface of the first contact pads 110.
The first contact pad 110 located in the non-electrical connection region 103 may be used to connect different chips 100, the second contact pad 120 located in the electrical connection region 102 may be used to transmit signals between different chips 100, the connection portion 130 located at least in part of the first contact pad 110 may be used to improve warpage of the chips 100, increase stress resistance of edges of the chips 100, and prevent solder from overflowing to the top surface of the connection portion 130 during soldering to cause poor chip connection by forming the top surface of the connection portion 130 lower than the top surface of the first contact pad 110, thereby improving reliability of the semiconductor structure manufacturing method.
In some embodiments, fig. 7-9, a method of forming the connection 130 includes: forming a seed layer 150, wherein the seed layer 150 is positioned on the surface of the chip 100; forming a first mask layer 160, wherein the first mask layer 160 is positioned on the surface of the seed layer 150, the first mask layer 160 has a target pattern, and the target pattern exposes a part of the surface of the seed layer 150; the connection part 130 is formed, and the connection part 130 is located in the target pattern. The subsequent formation of the connection portion 130 may be facilitated by forming the seed layer 150, and the morphology of the formed connection portion 130 may be improved, the position and morphology of the connection portion 130 may be defined by forming the first mask layer 160 having the target pattern, and the warpage of the chip 100 may be improved by forming the connection portion 130.
Referring to fig. 7, the seed layer 150 is formed, and in some embodiments, the seed layer 150 may be formed by UBM (Under Bump Metallurgy) sputtering, and the surface smoothness of the seed layer 150 may be improved by using UBM sputtering.
In some embodiments, the seed layer 150 may be formed by sputtering titanium and/or copper.
Referring to fig. 8, the first mask layer 160 is formed, and in some embodiments, the first mask layer 160 may be formed by first forming a first initial mask layer (not shown), and performing steps such as exposing and developing the first initial mask layer to form the first mask layer 160 having a target pattern.
In some embodiments, the material of the first mask layer 160 may be a photoresist, where the photoresist may be a positive photoresist and a negative photoresist, where the positive photoresist is decomposed in an illuminated portion and a non-illuminated portion is remained under the irradiation of an exposure source such as ultraviolet, the negative photoresist is decomposed in an illuminated portion and a non-illuminated portion under the irradiation of an exposure source such as ultraviolet, the resolution of the positive photoresist is better than that of the negative photoresist, and the negative photoresist has high heat resistance, and the corresponding material may be selected according to actual needs.
Referring to fig. 9, the connection 130 is formed, and in some embodiments, the material of the connection 130 may be copper, and the connection 130 may be formed by directly plating copper.
Referring to fig. 10 and 11, in some embodiments, the first contact pad 110 includes: the method for forming the first contact pad 110 includes the steps of: after the connection portion 130 is formed, a second mask layer 170 is formed on the surface of the connection portion 130, and the second mask layer 170 is spaced apart from the first mask layer 160; the second conductive layer 112 is formed, the second conductive layer 112 is located between the first mask layer 160 and the second mask layer 170, the portion of the connection portion 130 contacting and connected with the second conductive layer 112 is used as the first conductive layer 111, and the first conductive layer 111 and the second conductive layer 112 are used as the first contact pad 110. By forming the second mask layer 170, defining the shape of the second conductive layer 112 through the second mask layer 170 and the first mask layer 160, forming the second conductive layer 112 to form the first contact pad 110 with the top surface higher than the connection portion 130, and by using the connection portion 130, which is in contact connection with the second conductive layer 112, as the first conductive layer 111, the reliability of the connection between the connection portion 130 and the first contact pad 110 can be improved, and the interface state between the connection portion 130 and the first contact pad 110 can be reduced.
Referring to fig. 10, the second mask layer 170 is formed, and the material of the second mask layer 170 may be the same as that of the first mask layer 160, for example, may be a photoresist layer, and the material of the second mask layer 170 may also be other insulating materials, for example, silicon nitride, etc.
In some embodiments, the top surface of the second mask layer 170 may be flush with the top surface of the first mask layer 160.
It should be noted that, the level herein means that the top surface of the second mask layer 170 is completely level with the top surface of the first mask layer 160, or that the difference in height between the top surface of the second mask layer 170 and the top surface of the first mask layer 160 is within the allowable range of error, and that the difference in height between the top surface of the second mask layer 170 and the top surface of the first mask layer 160 is also considered to be level with the top surface of the first mask layer 160.
Referring to fig. 11, a second conductive layer 112 is formed, in some embodiments, a top surface of the formed second conductive layer 112 may be lower than a top surface of the second mask layer 170, in some embodiments, a connection layer may be further formed on the top surface of the second conductive layer 112, and a space may be reserved for a subsequent formation of the connection layer by forming the top surface of the second conductive layer 112 lower than the top surface of the second mask layer 170; in other embodiments, the top surface of the second conductive layer formed may also be flush with the top surface of the second mask layer 170.
Referring to fig. 12 and 13, after forming the first contact pad 110, it further includes: removing the first mask layer 160 and the second mask layer 170; the seed layer 150 is etched using the first contact pad 110 as a mask to form the spaced seed layer 150. The seed layer 150 is etched by using the first contact pad 110 as a mask to form a spaced seed layer.
Referring to fig. 12, the connection layer 180 is formed, and the connection between the chips 100 may be facilitated by forming the connection layer 180, and the connection tightness of the chips 100 may be improved.
Referring to fig. 13, the first mask layer 160 and the second mask layer 170 are removed, and the seed layer 150 is etched.
The method for manufacturing a semiconductor structure according to the embodiments of the present disclosure forms the first contact pad 110 and the connection portion 130 by forming the first conductive layer 111 and the connection portion 130 and then forming the second conductive layer 112, so that the reliability of connection between the first contact pad 110 and the connection portion 130 can be improved, the material of the second conductive layer 112 can be flexibly set, the reliability of connection between the first contact pad 110 and the chip 100 can be improved,
Another embodiment of the present disclosure further provides another method for manufacturing a semiconductor structure, which is substantially the same as the above embodiment, and the main differences include: the method for forming the connection portion and the first contact pad are different, and a method for manufacturing another semiconductor structure according to another embodiment of the present disclosure will be described with reference to the drawings.
Referring to fig. 14 to 16, fig. 14 to 16 are schematic structural views corresponding to steps of another method for fabricating a semiconductor structure according to another embodiment of the present disclosure.
Specifically, the method for forming the connection portion 230 and the first contact pad 210 includes: forming an initial conductive layer 270, the initial conductive layer 270 being located on the surface of the chip 200; the initial conductive layer 270 is etched to form the connection portion 230 and the first contact pad 210. That is, the connection portion 230 and the first contact pad 210 are formed in the same step, and the connection portion 230 and the first contact pad 210 are integrally formed.
In some embodiments, the method of etching the initial conductive layer 270 may be by forming the mask layer 260 having the target pattern, and etching the initial conductive layer 270 using the mask layer 260 as a mask.
In some embodiments, the initial conductive layer 270 is formed further comprising: a seed layer 250 is formed.
In the embodiment of the disclosure, the connection portion 230 and the first contact pad 210 are formed in the same step, so that the process steps of the manufacturing method of the semiconductor structure can be reduced, and the process duration of the manufacturing method of the whole semiconductor structure can be reduced.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of implementing the disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the embodiments of the disclosure. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the embodiments of the disclosure, and the scope of the embodiments of the disclosure should be assessed accordingly to that of the appended claims.

Claims (17)

1. A semiconductor structure, comprising:
The chip is provided with a first surface, the first surface comprises an electric connection area and a non-electric connection area, and at least part of the non-electric connection area is positioned at the edge of the first surface;
A plurality of first contact pads, wherein the first contact pads are positioned in the non-electric connection area;
a plurality of second contact pads, wherein the second contact pads are positioned in the electrical connection area;
And the connecting part is positioned at least between part of the first contact pads, and the top surface of the connecting part is lower than the top surface of the first contact pads.
2. The semiconductor structure of claim 1, wherein a plurality of the first contact pads are arranged in an array, and the plurality of first contact pads and the plurality of connection portions form a grid structure, and the grid structure comprises: square grid, diamond grid, trapezoidal grid or cross grid.
3. The semiconductor structure of claim 2, wherein the connection is further located between two of the first contact pads in a diagonal position in the grid structure.
4. The semiconductor structure of claim 1, wherein a plurality of the first contact pads are arranged in an array, and the connection portion is located between two of the first contact pads that are located at diagonal positions.
5. The semiconductor structure of claim 1, wherein a thickness of the connection portion is less than a thickness of the first contact pad in a direction perpendicular to the first face.
6. The semiconductor structure of claim 1 or 5, wherein the thickness of the connection portion is 1/5 to 1/3 of the thickness of the first contact pad.
7. The semiconductor structure of claim 1, wherein the first contact pad is integral with the adjacent connection.
8. The semiconductor structure of claim 1, wherein the first contact pad comprises: a first conductive layer and a second conductive layer which are laminated in sequence; the first conductive layer and the adjacent connecting part are of an integral structure.
9. The semiconductor structure of claim 1, wherein all of the non-electrical connection regions are provided with the connection portion; or the non-electric connection area comprises a corner part, and the connection part is only positioned at the corner part.
10. The semiconductor structure of claim 1, further comprising: a support portion located on the first contact pad surface; and the electric connection part is positioned on the surface of the second contact pad.
11. The semiconductor structure according to claim 10, comprising a plurality of the chips arranged in a stacked manner, wherein the supporting portion is configured to support the adjacent chips, and wherein the electrical connection portion is configured to electrically connect the adjacent chips.
12. The semiconductor structure of claim 1, wherein the die further has a second face disposed opposite the first face, the first contact pad further being located on the second face; the semiconductor structure further includes a solder structure located on a top surface of the first contact pad of the second face.
13. A method of fabricating a semiconductor structure, comprising:
Providing a chip, wherein the chip is provided with a first surface, the first surface comprises a non-electric connection area and an electric connection area, and at least part of the non-electric connection area is positioned at the edge of the first surface;
And forming a first contact pad, a second contact pad and a connecting part, wherein the first contact pad is positioned in the non-electric connection area, the second contact pad is positioned in the electric connection area, the connecting part is positioned between at least part of the first contact pads, and the top surface of the connecting part is lower than the top surface of the first contact pad.
14. The method of fabricating a semiconductor structure of claim 13, wherein the method of forming the connection portion comprises:
Forming a seed layer, wherein the seed layer is positioned on the surface of the chip;
Forming a first mask layer, wherein the first mask layer is positioned on the surface of the seed layer, the first mask layer is provided with a target pattern, and the target pattern exposes part of the surface of the seed layer;
And forming a connecting part, wherein the connecting part is positioned in the target graph.
15. The method of fabricating a semiconductor structure of claim 14, wherein the first contact pad comprises: the method for forming the first contact pad comprises the following steps of:
After the connecting part is formed, a second mask layer is formed on the surface of the connecting part, and the second mask layer is spaced from the first mask layer;
And forming a second conductive layer, wherein the second conductive layer is positioned between the first mask layer and the second mask layer, the part of the connecting part in contact connection with the second conductive layer is used as the first conductive layer, and the first conductive layer and the second conductive layer are used as the first contact pad.
16. The method of fabricating a semiconductor structure of claim 15, further comprising, after forming the first contact pad:
Removing the first mask layer and the second mask layer;
and etching the seed layer by taking the first contact pad as a mask to form the spaced seed layers.
17. The method of claim 15, wherein forming the connection portion and the first contact pad comprises:
forming an initial conductive layer, wherein the initial conductive layer is positioned on the surface of the chip;
The initial conductive layer is etched to form the connection portion and the first contact pad.
CN202211296206.4A 2022-10-21 2022-10-21 Semiconductor structure and manufacturing method thereof Pending CN117954395A (en)

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