CN117954386A - Metal filling method for reducing resistance of through hole - Google Patents
Metal filling method for reducing resistance of through hole Download PDFInfo
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- CN117954386A CN117954386A CN202410115254.1A CN202410115254A CN117954386A CN 117954386 A CN117954386 A CN 117954386A CN 202410115254 A CN202410115254 A CN 202410115254A CN 117954386 A CN117954386 A CN 117954386A
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- 239000002184 metal Substances 0.000 title claims abstract description 74
- 238000000034 method Methods 0.000 title claims abstract description 52
- 238000011049 filling Methods 0.000 title claims abstract description 22
- 239000010410 layer Substances 0.000 claims abstract description 124
- 238000005530 etching Methods 0.000 claims abstract description 30
- 239000011229 interlayer Substances 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 238000002955 isolation Methods 0.000 claims abstract description 24
- 230000008569 process Effects 0.000 claims abstract description 24
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 230000008021 deposition Effects 0.000 claims abstract description 9
- 238000000227 grinding Methods 0.000 claims abstract description 3
- 239000000463 material Substances 0.000 claims description 15
- 239000003989 dielectric material Substances 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 10
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 10
- 229910052721 tungsten Inorganic materials 0.000 claims description 10
- 239000010937 tungsten Substances 0.000 claims description 10
- 238000005498 polishing Methods 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 4
- 229910052715 tantalum Inorganic materials 0.000 claims description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 4
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 5
- 239000004020 conductor Substances 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
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- 238000010586 diagram Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 description 3
- 239000010941 cobalt Substances 0.000 description 3
- 229910017052 cobalt Inorganic materials 0.000 description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
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- 238000005240 physical vapour deposition Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
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- 229920000052 poly(p-xylylene) Polymers 0.000 description 1
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- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
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Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a metal filling method for reducing the resistance value of a through hole, which comprises the steps of providing a substrate, and forming an integrated circuit device on the substrate; forming an interconnect structure on a semiconductor substrate, wherein the interconnect structure includes a plurality of conductive features connected to the integrated circuit device; forming an etching stop layer covering the interconnection structure, and forming a first interlayer dielectric layer on the etching stop layer; forming an opening pattern on the first interlayer dielectric layer to define a forming region of the first through hole; forming an isolation layer on the through hole, removing the isolation layer outside the side wall of the opening pattern, and etching to remove the etching stop layer at the bottom of the opening pattern so as to expose the conductive part below the etching stop layer; a first metal layer covering the exposed conductive features is formed by a selective growth process, followed by a second metal layer filling the pattern of openings by deposition, grinding. The invention improves the reliability and stability of the device.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a metal filling method for reducing the resistance value of a through hole.
Background
With the shrinking of the process, the process dimension of the middle section is smaller and smaller. In the technical node before the deep micro-nano semiconductor process, the size and the characteristics of the CMOS device have the greatest influence on the electrical performance of the device, and along with the miniaturization of the size, the influence of the contact resistance of the middle and rear section and the self resistance of the metal wire on the performance of the device is larger and larger. In order to reduce the influence on the electrical property, the Co connection process is further added in the middle section from the initial Al connection process to the Cu connection process at the rear end, so that the resistance of the metal wire is lower and lower, and the influence of the metal wire on the performance of the device is reduced. However, with the change of the metal connection process and the miniaturization of the size, the manufacturing process is more and more complex, the difficulty is higher and the yield is more and more difficult to improve.
To reduce the mid-section connection resistance, TSMC (taiwan integrated circuit manufacturing company, inc.) introduced a selective growth tungsten process at the zeroth layer ViA (ViA) of 7nm, eliminating TiN as an insulating layer and bonding layer necessary for metal filling. Since TiN is a high-resistance material, the resistance of the through holes can be reduced by about 50% without existence of TiN, and the device performance is obviously improved. But the growth process difficulty is greater due to the selective growth of tungsten and the interface bonding between W and oxide is poor due to the absence of TiN. Therefore, in the W CMP (chemical mechanical planarization polishing), the polishing liquid easily infiltrates along the interface between W and the oxide layer, and damages the underlying metal. The solution of TSMC is to apply pressure by adding multiple IMP (ion implantation) layers and form a bowl-shaped opening structure on the bottom metal by wet etching, so that the damage of the bottom metal is reduced, but the damage of the front Co metal cannot be completely avoided by the method. In addition, the growth efficiency of the selectively grown tungsten process is poor, and it often occurs that CVD W (chemical vapor deposited tungsten) and TiN fill into holes where the selectively grown tungsten is not completely grown.
In order to solve the above problems, a new metal filling method for reducing the resistance of the through hole is needed.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a metal filling method for reducing the resistance of a through hole, which is used for solving the problems that in the prior art, the difficulty of a growth process of a selective growth metal process is high, and the interface combination between a metal layer and an oxide layer is poor due to no existence of an isolation layer, so that the metal at the bottom layer of the through hole is easy to be damaged.
To achieve the above and other related objects, the present invention provides a metal filling method for reducing a via resistance, comprising:
Step one, providing a substrate, and forming an integrated circuit device on the substrate;
forming an interconnect structure on the semiconductor substrate, wherein the interconnect structure includes a plurality of conductive features connected to the integrated circuit device;
forming an etching stop layer covering the interconnection structure, and forming a first interlayer dielectric layer on the etching stop layer;
forming an opening pattern on the first interlayer dielectric layer to define a forming area of the first through hole;
Forming an isolation layer on the through hole, removing the isolation layer outside the side wall of the opening pattern, and etching to remove the etching stop layer at the bottom of the opening pattern so that the conductive part below the etching stop layer is exposed;
and fifthly, forming a first metal layer which covers and exposes the conductive component by utilizing a selective growth process, and then forming a second metal layer which fills the opening pattern by utilizing deposition and grinding.
Preferably, the substrate in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate.
Preferably, the conductive member in the first step includes a second interlayer dielectric layer to separate and isolate the various conductive members.
Preferably, the conductive member in the first step includes a contact; a metal wire; and at least one of the second through holes.
Preferably, the material of the etching stop layer in the second step is silicon nitride.
Preferably, the first interlayer dielectric layer in the second step includes at least one of a dielectric material of silicon oxide and a low-k dielectric material.
Preferably, the material of the isolation layer in the fourth step includes at least one of tantalum, tantalum nitride, titanium and titanium nitride.
Preferably, in the fifth step, the material of the first and second metal layers is tungsten.
Preferably, in the fifth step, the second metal layer is formed by using a chemical vapor deposition method.
Preferably, the polishing method in the fifth step is chemical mechanical planarization polishing.
As described above, the metal filling method for reducing the resistance of the through hole of the present invention has the following beneficial effects:
the invention utilizes the advantage that the bottom of the selectively grown metal layer is not provided with the isolation layer with high resistance, and the isolation layer is reserved at the middle upper part of the through hole for the adhesion layer of the contact between the metal layer and the interlayer dielectric layer, so that the reliability and the stability of the device are improved.
Drawings
FIG. 1 is a schematic illustration of the process flow of the present invention;
FIG. 2 is a schematic illustration of the formation of an interconnect structure in accordance with the present invention;
FIG. 3 is a schematic diagram of forming an etch stop layer and a first interlayer dielectric layer according to the present invention;
FIG. 4 is a schematic view of forming an opening pattern according to the present invention;
FIG. 5 is a schematic view of the formation of an isolation layer according to the present invention;
FIG. 6 is a schematic diagram of an etch stop layer according to the present invention;
FIG. 7 is a schematic diagram of an etch stop layer with etch bare according to the present invention;
FIG. 8 is a schematic view of forming a first metal layer according to the present invention;
FIG. 9 is a schematic diagram of forming a second metal layer according to the present invention;
FIG. 10 is a schematic view of a polished second metal layer according to the present invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Referring to fig. 1, the present invention provides a metal filling method for reducing a via resistance, comprising:
step one, providing a substrate 101, and forming an integrated circuit device 102 on the substrate 101;
forming an interconnect structure on a semiconductor substrate 101, wherein the interconnect structure includes a plurality of conductive features 103 connected to an integrated circuit device 102, forming a structure as shown in fig. 2;
The semiconductor substrate 101 also includes various doped features such as n-type doped wells, p-type doped wells, source and drain, other doped features, or combinations thereof configured to form various devices or components of devices. The semiconductor structure includes various IC devices formed on a semiconductor substrate 101. The IC devices include fin field effect transistors (finfets), diodes, bipolar transistors, imaging sensors, resistors, capacitors, inductors, memory cells, or combinations thereof.
The interconnect structure includes various conductive features 103 to connect various IC devices into an integrated circuit. The interconnect structure also includes a second interlayer dielectric layer 104 to separate and isolate the various conductive features 103. For example, the interconnect structure includes contacts; a metal wire; and a second through hole. The metal lines are distributed in a plurality of metal layers. For example, the metal lines may include copper, aluminum copper alloy, other suitable conductive materials, or combinations thereof. The second via may comprise copper, aluminum copper alloy, other suitable conductive material, or a combination thereof. The contacts may comprise tungsten, silicide, nickel, cobalt, copper, other suitable conductive materials, or combinations thereof. In some examples, the various conductive features 103 may further include barrier layers such as tantalum and tantalum nitride, titanium and titanium nitride.
In this embodiment, the top metal line comprises cobalt.
The second interlayer dielectric layer 104 includes one or more dielectric materials to provide isolation functions to various device components (such as gates) and various conductive features 103 (such as metal lines, contacts, and second vias). The second interlayer dielectric layer 104 comprises a dielectric material such as silicon oxide, a low-k dielectric material, other suitable dielectric material, or a combination thereof. In some examples, the low-k dielectric material includes Fluorinated Silicon Glass (FSG), carbon doped silicon oxide, xerogel, aerogel, amorphous carbon fluoride, parylene, BCB (bisbenzocyclobutene), polyimide, and/or other suitable dielectric materials having a dielectric constant substantially less than that of thermal silicon oxide. For example, the formation of the second interlayer dielectric layer 104 includes deposition and CMP. Deposition may include spin coating, CVD, other suitable deposition techniques, or combinations thereof. The second interlayer dielectric layer 104 may include a plurality of layers and be formed in common with the various conductive features 103 in an appropriate procedure, such as a damascene process.
In some embodiments, the interconnect structure or portions thereof are formed by deposition and patterning. For example, metals (or metal alloys) such as aluminum copper are deposited by Physical Vapor Deposition (PVD) and then patterned by photolithographic processes and etching. The second interlayer dielectric layer 104 is then provided by deposition (and CMP). In some embodiments, the interconnect structure uses a damascene process to form the metal lines. In a damascene process, a second interlayer dielectric layer 104 is deposited, the second interlayer dielectric layer 104 is further planarized by CMP, and then patterned by photolithography and etching to form trenches. One or more conductive materials are deposited to fill the trenches and another CMP process is applied to remove excess conductive material and planarize the top surface, thereby forming conductive features 103. A damascene process may be used to form metal lines, second vias, and contacts. A dual damascene process may be applied to form a layer of metal lines and second vias adjacent to the metal lines. In this case, the second interlayer dielectric layer 104 is deposited and patterned twice to form a trench and a second via, respectively. Metal is then deposited to fill both the trench and the second via to form a metal line and a second via.
In some embodiments, the substrate 101 in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulator layer under a thin semiconductor layer that is an active layer of the SOI substrate. The semiconductor and bulk semiconductor of the active layer typically comprise crystalline semiconductor material silicon, but may also comprise one or more other semiconductor materials such as germanium, silicon germanium alloys, compound semiconductors (e.g., gaAs, alAs, inAs, gaN, alN, etc.) or alloys thereof (e.g., gaxAl1-xAs, gaxAl1-xN, inxGa1-xAs, etc.), oxide semiconductors (e.g., znO, snO2, tiO2, ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or hybrid orientation substrates.
Step two, forming an etching stop layer 105 covering the interconnection structure, and forming a first interlayer dielectric layer 106 (the first and the second are only distinguished and not represented in number) on the etching stop layer 105 to form the structure shown in fig. 3;
in some embodiments, the material of the etch stop layer 105 in step two is silicon nitride.
In some embodiments, the first interlayer dielectric layer 106 in step two comprises at least one of a dielectric material of silicon oxide, a low-k dielectric material. The material of the first interlayer dielectric layer 106 is similar to that of the second interlayer dielectric layer 104, and will not be described here.
Step three, forming an opening pattern on the first interlayer dielectric layer 106 to define a formation region of the first through holes (the first through holes and the second through holes are only distinguished and not represented in number), and forming a structure as shown in fig. 4, namely, stopping etching the first interlayer dielectric layer 106 on the etching stop layer 105;
Step four, forming an isolation layer 107 on the through hole, forming a structure shown in fig. 5, removing the isolation layer 107 outside the side wall of the opening pattern, forming a structure shown in fig. 6, etching to remove the etching stop layer 105 at the bottom of the opening pattern, and exposing the conductive component 103 below the etching stop layer to form a structure shown in fig. 7;
Specifically, the dry etching method is used to improve the etching directionality and selectivity, only the isolation layer 107 on the bottom and the surface is removed and opened, and only the isolation layer 107 on the side wall of the etched opening pattern is left as a protection layer for the subsequent deposition of the second metal layer 109 because the shape of the opening pattern is relatively straight. After etching to remove the etching stop layer 105 at the bottom of the opening pattern, the isolation layer 107 is still on the sidewall of the upper half of the opening pattern, and the bottom etching stop layer 105 is not on the sidewall.
In some embodiments, the material of isolation layer 107 in step four comprises at least one of tantalum, tantalum nitride, titanium nitride. In this embodiment, the material of the isolation layer 107 is titanium nitride, which is formed by an atomic layer deposition method.
Step five, a first metal layer 108 covering the exposed conductive part 103 is formed by a selective growth process to form a structure as shown in fig. 8, and then a second metal layer 109 filling the opening pattern is formed by deposition and polishing (sequentially shown in fig. 9 and 10). The invention utilizes the advantage that the bottom of the selectively grown metal layer is not provided with the isolation layer 107 with high resistance, and the isolation layer 107 is reserved at the middle upper part of the through hole for the adhesion layer of the contact between the metal layer and the interlayer dielectric layer, so that the reliability and the stability of the device are improved.
In this embodiment, wet cleaning with an organic cleaning solution and water is also typically required prior to depositing the metal layer.
In some embodiments, the material of the first and second metal layers in the fifth step is tungsten. The first metal layer 108 does not need to be grown to a high height and can cover the bottom cobalt metal.
In some embodiments, the second metal layer 109 is formed in the fifth step by using a chemical vapor deposition method. Tungsten deposited by chemical vapor deposition can be well connected with the surface of the wafer, and the peeling phenomenon is prevented.
In some embodiments, the polishing in step five is chemical mechanical planarization polishing.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
In summary, the invention utilizes the advantage that the bottom of the selectively grown metal layer is not provided with the isolation layer with high resistance, and the isolation layer is reserved at the middle upper part of the through hole for the adhesion layer of the contact between the metal layer and the interlayer dielectric layer, so that the reliability and the stability of the device are improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. A metal filling method for reducing the resistance of a through hole is characterized by at least comprising the following steps:
Step one, providing a substrate, and forming an integrated circuit device on the substrate;
forming an interconnect structure on the semiconductor substrate, wherein the interconnect structure includes a plurality of conductive features connected to the integrated circuit device;
forming an etching stop layer covering the interconnection structure, and forming a first interlayer dielectric layer on the etching stop layer;
forming an opening pattern on the first interlayer dielectric layer to define a forming area of the first through hole;
Forming an isolation layer on the through hole, removing the isolation layer outside the side wall of the opening pattern, and etching to remove the etching stop layer at the bottom of the opening pattern so that the conductive part below the etching stop layer is exposed;
and fifthly, forming a first metal layer which covers and exposes the conductive component by utilizing a selective growth process, and then forming a second metal layer which fills the opening pattern by utilizing deposition and grinding.
2. The metal filling method for reducing a via resistance according to claim 1, wherein: the substrate in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate.
3. The metal filling method for reducing a via resistance according to claim 1, wherein: the conductive features in step one include a second interlayer dielectric layer to separate and isolate the various conductive features.
4. The metal filling method for reducing a via resistance according to claim 1, wherein: the conductive member in step one includes a contact; a metal wire; and at least one of the second through holes.
5. The metal filling method for reducing a via resistance according to claim 1, wherein: and step two, the material of the etching stop layer is silicon nitride.
6. The metal filling method for reducing a via resistance according to claim 1, wherein: the first interlayer dielectric layer in the second step comprises at least one of a dielectric material of silicon oxide and a low-k dielectric material.
7. The metal filling method for reducing a via resistance according to claim 1, wherein: and in the fourth step, the material of the isolation layer comprises at least one of tantalum, tantalum nitride, titanium and titanium nitride.
8. The metal filling method for reducing a via resistance according to claim 1, wherein: and in the fifth step, the materials of the first metal layer and the second metal layer are tungsten.
9. The metal filling method for reducing a via resistance according to claim 8, wherein: and step five, forming the second metal layer by using a chemical vapor deposition method.
10. The metal filling method for reducing a via resistance according to claim 1, wherein: the polishing method in the fifth step is chemical mechanical planarization polishing.
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| CN202410115254.1A CN117954386A (en) | 2024-01-26 | 2024-01-26 | Metal filling method for reducing resistance of through hole |
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