CN117954383A - Semiconductor structure and preparation method thereof - Google Patents

Semiconductor structure and preparation method thereof Download PDF

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Publication number
CN117954383A
CN117954383A CN202211297910.1A CN202211297910A CN117954383A CN 117954383 A CN117954383 A CN 117954383A CN 202211297910 A CN202211297910 A CN 202211297910A CN 117954383 A CN117954383 A CN 117954383A
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China
Prior art keywords
dielectric layer
interlayer dielectric
layer
groove
conductive
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唐中迪
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN202211297910.1A priority Critical patent/CN117954383A/en
Priority to PCT/CN2023/094697 priority patent/WO2024082626A1/en
Publication of CN117954383A publication Critical patent/CN117954383A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The application relates to a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor structure comprises the steps of providing a substrate; forming a plurality of conducting layers and first interlayer dielectric layers which are horizontally arranged at intervals on a substrate; the first interlayer dielectric layer covers the conductive layers and fills gaps between adjacent conductive layers; forming a groove in the first interlayer dielectric layer; the grooves are positioned between the adjacent conductive layers; forming a second interlayer dielectric layer at least in the groove; the second interlayer dielectric layer is deposited at a lower rate at the bottom of the recess than at the upper portion of the recess sidewall, such that an air gap is formed in the second interlayer dielectric layer within the recess. The preparation method of the semiconductor structure can be used for reducing parasitic capacitance between adjacent conductive layers, improving RC delay between the conductive layers and the second interlayer dielectric layer, and further improving the speed and performance of the device.

Description

Semiconductor structure and preparation method thereof
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a preparation method thereof.
Background
Semiconductor devices in the field of semiconductor fabrication typically include a number of metal lines disposed on a surface of the device, which may be separated from each other by insulating layers of dielectric material (also referred to as interlevel dielectric layers, abbreviated as ILD).
However, as semiconductor device dimensions continue to shrink, device performance is increasingly limited by interlayer dielectric capacitance. For example, interlayer dielectrics cause parasitic capacitance to exist before adjacent metal lines, resulting in resistance-capacitance delays (RC delays), which in turn affect the speed of the device.
Therefore, how to reduce the RC delay between adjacent metal lines is a current problem that needs to be solved.
Disclosure of Invention
Based on this, it is necessary to provide a semiconductor structure and a method for manufacturing the same, which address the shortcomings in the prior art.
In one aspect, the present application provides a method for fabricating a semiconductor structure, comprising:
providing a substrate;
forming a plurality of conducting layers and first interlayer dielectric layers which are horizontally arranged at intervals on the substrate; the first interlayer dielectric layer covers the conductive layers and fills gaps between adjacent conductive layers;
forming a groove in the first interlayer dielectric layer; the grooves are positioned between adjacent conductive layers;
Forming a second interlayer dielectric layer at least in the groove; the second interlayer dielectric layer is deposited at a rate at least less in the lower region of the recess than in the upper region of the recess, and an air gap is formed in the second interlayer dielectric layer within the recess.
In some embodiments, the groove lower region comprises the groove bottom, or comprises the groove bottom and the groove sidewall lower portion;
the recess upper region includes the recess sidewall upper portion.
In some embodiments, the depth of the recess is less than the thickness of the first interlayer dielectric layer;
Forming a groove in the first interlayer dielectric layer comprises the following steps:
forming an initial groove in the first interlayer dielectric layer; the depth of the initial groove is smaller than that of the groove;
performing plasma treatment on the side wall and the bottom of the initial groove to form a plasma treatment area on the side wall and the bottom of the initial groove;
continuing to etch the first interlayer dielectric layer based on the initial groove to form the groove; the upper part of the side wall of the groove comprises the plasma treatment area, and the deposition rate of the second interlayer dielectric layer in the plasma treatment area is higher than that in the lower part of the side wall of the groove and the bottom of the groove.
In some embodiments, the plasma treating the sidewall and the bottom of the initial recess includes:
Performing plasma treatment on the side wall and the bottom of the initial groove by using argon plasma and helium plasma; the gas flow of the argon plasma is 50 sccm-150 sccm, the gas flow of the helium plasma is 200 sccm-800 sccm, and the radio frequency power in the plasma treatment process is 300W-1000W.
In some embodiments, before forming the plurality of conductive layers and the first interlayer dielectric layer arranged at intervals horizontally on the substrate, the method further includes:
forming a covering dielectric layer on the upper surface of the substrate;
forming a plurality of conductive plugs in the covering dielectric layer; the first interlayer dielectric layer and the conductive layer are both formed on the upper surface of the covering dielectric layer; the conductive layer is in contact with the conductive plug.
In some embodiments, the forming a capping dielectric layer on the upper surface of the substrate includes:
Taking silane and nitric oxide gas as reaction gases, and adopting a plasma enhanced chemical vapor deposition process to deposit an oxide layer on the upper surface of the substrate as the covering medium layer; the deposition rate of the covering dielectric layer is 10 nm/s-30 nm/s;
the forming a first interlayer dielectric layer on the substrate comprises the following steps:
Oxygen and tetraethoxysilane are used as reactants, and a plasma enhanced chemical vapor deposition process is adopted to deposit an oxide layer on the substrate to be used as the first interlayer dielectric layer; the deposition rate of the first interlayer dielectric layer is 1 nm/s-20 nm/s;
forming a second interlayer dielectric layer in at least the groove, including:
Ozone and tetraethoxysilane are used as reactants, and a low-pressure chemical vapor deposition process is adopted to form a deposition oxide layer in at least the groove to be used as the second interlayer dielectric layer; the deposition temperature of the second interlayer dielectric layer is 400-500 ℃; in the low-pressure chemical vapor deposition process, the molar ratio of ozone to tetraethoxysilane is 3-15.
In some embodiments, before forming the plurality of conductive layers and the first interlayer dielectric layer arranged at intervals horizontally on the substrate, the method further includes:
forming a covering dielectric layer on the upper surface of the substrate;
forming a plurality of conductive plugs in the covering dielectric layer; the first interlayer dielectric layer and the conductive layer are formed on the covering dielectric layer; the conductive layer is in contact with the conductive plug.
In some embodiments, before forming the plurality of conductive layers and the first interlayer dielectric layer arranged at intervals horizontally on the substrate, the method further includes:
forming a covering dielectric layer on the upper surface of the substrate;
Forming a plurality of conductive plugs in the covering dielectric layer; the first interlayer dielectric layer and the conductive layer are formed on the covering dielectric layer; the conductive layer is in contact with the conductive plug;
Wherein, the first interlayer dielectric layer and the conductive layer are both formed on the covering dielectric layer; the groove penetrates through the first interlayer dielectric layer along the thickness direction so as to expose the covering dielectric layer; the deposition rate of the second interlayer dielectric layer on the surface of the covering dielectric layer is smaller than that of the first interlayer dielectric layer.
In some embodiments, after the forming a plurality of conductive layers arranged at horizontal intervals on the substrate, before forming the first interlayer dielectric layer, the method further includes:
Forming an isolation layer on the upper surface of the covering dielectric layer and the upper surface of the conductive layer; the first interlayer dielectric layer is positioned on the upper surface of the isolation layer; the groove penetrates through the first interlayer dielectric layer along the thickness direction so as to expose the isolation layer; the deposition rate of the second interlayer dielectric layer on the surface of the isolation layer is smaller than that of the first interlayer dielectric layer.
In some embodiments, the forming a capping dielectric layer on the upper surface of the substrate includes:
oxygen and tetraethoxysilane are used as reactants, and a plasma enhanced chemical vapor deposition process is adopted to deposit an oxide layer on the substrate to be used as the covering medium layer; the deposition rate of the first interlayer dielectric layer is 1 nm/s-20 nm/s;
the forming a first interlayer dielectric layer on the substrate comprises the following steps:
Taking silane and nitric oxide gas as reaction gases, and adopting a plasma enhanced chemical vapor deposition process to deposit an oxide layer on the upper surface of the substrate to serve as the first interlayer dielectric layer; the deposition rate of the first interlayer dielectric layer is 10 nm/s-30 nm/s;
forming a second interlayer dielectric layer in at least the groove, including:
Ozone and tetraethoxysilane are used as reactants, and a low-pressure chemical vapor deposition process is adopted to form a deposition oxide layer in at least the groove to be used as the second interlayer dielectric layer; the deposition temperature of the second interlayer dielectric layer is 400-500 ℃, and the molar ratio of ozone to tetraethoxysilane in the low-pressure chemical vapor deposition process is 3-15.
In some embodiments, the forming an isolation layer on the upper surface of the capping dielectric layer and the upper surface of the conductive layer includes:
forming an oxide layer on the surface of the covering dielectric layer and the upper surface of the conductive layer by adopting a thermal oxidation process to serve as the isolation layer; the temperature of the thermal oxidation process is 300-500 ℃.
In some embodiments, the second interlayer dielectric layer is further located on an upper surface of the first interlayer dielectric layer.
In some embodiments, the second interlayer dielectric layer located on the upper surface of the first interlayer dielectric layer has a thickness of 30nm to 200nm.
In another aspect, the present application also provides, according to some embodiments, a semiconductor structure, including:
A substrate;
A plurality of parallel conductive layers arranged at intervals and positioned on the substrate;
the first interlayer dielectric layer covers the conductive layers and fills gaps between adjacent conductive layers; the first interlayer dielectric layer is internally provided with a groove, and the groove is positioned between adjacent conductive layers;
The second interlayer dielectric layer is at least positioned in the groove, the deposition rate of the second interlayer dielectric layer in the lower area of the groove is at least smaller than that of the upper area of the groove, and an air gap is formed in the second interlayer dielectric layer in the groove.
In some embodiments, the groove lower region comprises the groove bottom, or comprises the groove bottom and the groove sidewall lower portion;
the recess upper region includes the recess sidewall upper portion.
In some embodiments, the depth of the recess is less than the thickness of the first interlayer dielectric layer; the upper part of the side wall of the groove is provided with a plasma treatment area, and the deposition rate of the second interlayer dielectric layer in the plasma treatment area is larger than that of the lower part of the side wall of the groove and the bottom of the groove.
In some embodiments, the semiconductor structure further comprises:
The dielectric layer is covered and positioned on the upper surface of the substrate;
A conductive plug in the dielectric layer; the first interlayer dielectric layer and the conductive layer are formed on the covering dielectric layer; the conductive layer is in contact with the conductive plug.
In some embodiments, the semiconductor structure further comprises:
The dielectric layer is covered and positioned on the upper surface of the substrate;
A conductive plug in the dielectric layer; the first interlayer dielectric layer and the conductive layer are formed on the covering dielectric layer; the conductive layer is in contact with the conductive plug;
The first interlayer dielectric layer and the conductive layer are formed on the upper surface of the covering dielectric layer; the groove penetrates through the first interlayer dielectric layer along the thickness direction so as to expose the covering dielectric layer; the deposition rate of the second interlayer dielectric layer on the surface of the covering dielectric layer is smaller than that of the first interlayer dielectric layer.
In some embodiments, the semiconductor structure further comprises:
The isolation layer is positioned on the upper surface of the covering dielectric layer and the upper surface of the conductive layer;
The first interlayer dielectric layer is positioned on the upper surface of the isolation layer; the groove penetrates through the first interlayer dielectric layer along the thickness direction so as to expose the covering dielectric layer; the deposition rate of the second interlayer dielectric layer on the surface of the covering dielectric layer is smaller than that of the first interlayer dielectric layer.
In some embodiments, the second interlayer dielectric layer is further located on the upper surface of the first interlayer dielectric layer; the thickness of the second interlayer dielectric layer positioned on the upper surface of the first interlayer dielectric layer is 30 nm-200 nm.
The semiconductor structure and the preparation method thereof provided by the application have at least the following beneficial effects:
According to the preparation method of the semiconductor structure, the air gap with the low dielectric constant (the dielectric constant of the air gap is close to 1) is introduced between the adjacent conductive layers through forming the air gap in the second interlayer dielectric layer, so that the overall dielectric constant of the second interlayer dielectric layer is reduced, parasitic capacitance between the adjacent conductive layers is reduced, RC delay between the conductive layers and the second interlayer dielectric layer is improved, and the speed and performance of the device are further improved. In addition, the deposition rate of the second interlayer dielectric layer in the lower area of the groove is at least smaller than that in the upper area of the groove, so that an air gap with a moderate size can be formed in the second interlayer dielectric layer, the formed position of the air gap is also lower, gaps are prevented from being introduced in subsequent processing due to unsuitable size or position of the air gap, and the problem of damage to the conductive layer caused by the fact that moisture passes through the gaps in the subsequent processing is avoided.
According to the semiconductor structure provided by the application, the air gap is formed in the second interlayer dielectric layer, the air gap with a low dielectric constant (the dielectric constant of the air gap is close to 1) is introduced between the adjacent conductive layers, the integral dielectric constant of the second interlayer dielectric layer is reduced, so that the parasitic capacitance between the adjacent conductive layers is reduced, the RC delay between the conductive layers and the second interlayer dielectric layer is improved, and the speed and the performance of the device are further improved. In addition, the deposition rate of the second interlayer dielectric layer in the lower area of the groove is at least smaller than that in the upper area of the groove, so that an air gap with a moderate size can be formed in the second interlayer dielectric layer, the formed position of the air gap is also lower, gaps are prevented from being introduced in subsequent processing due to unsuitable size or position of the air gap, and the problem of damage to the conductive layer caused by the fact that moisture passes through the gaps in the subsequent processing is avoided.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments or the conventional techniques of the present application, the drawings required for the descriptions of the embodiments or the conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
Fig. 1 is a flow chart illustrating a method for manufacturing a semiconductor structure according to some embodiments of the present application;
Fig. 2 is a schematic flow chart of step S300 in a method for manufacturing a semiconductor structure according to some embodiments of the present application;
Fig. 3 and fig. 4 are schematic flow diagrams illustrating steps before forming a plurality of conductive layers and a first interlayer dielectric layer arranged horizontally and at intervals on a substrate in a method for manufacturing a semiconductor structure according to some embodiments of the present application;
fig. 5 to fig. 9 are schematic cross-sectional views of structures obtained in each step in a method for manufacturing a semiconductor structure according to some embodiments of the present application; fig. 9 is a schematic cross-sectional view of a semiconductor structure according to some embodiments of the present application;
fig. 10 to 12 are schematic cross-sectional views of structures obtained by steps in the method for manufacturing a semiconductor structure according to other embodiments of the present application;
Fig. 13 to 16 are schematic cross-sectional views of structures obtained in various steps in a method for fabricating a semiconductor structure according to still other embodiments of the present application; fig. 16 is a schematic cross-sectional view of a semiconductor structure according to still other embodiments of the present application.
Reference numerals illustrate:
100. A substrate; 200. a conductive layer; 300. a first interlayer dielectric layer; 410. an initial groove; 420. a groove; 430. patterning the photoresist layer; 500. a second interlayer dielectric layer; 600. an air gap; 700. covering a dielectric layer; 710. a conductive plug; 800. an isolation layer.
Detailed Description
In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on …" or "adjacent …" another element or layer, it can be directly on or adjacent the other element or layer or intervening elements or layers may be present. It will be understood that, although the terms first and second may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application; for example, the first interlayer dielectric layer may be referred to as a second interlayer dielectric layer, and similarly, the second interlayer dielectric layer may be referred to as a first interlayer dielectric layer; the first interlayer dielectric layer and the second interlayer dielectric layer are different interlayer dielectric layers.
Spatially relative terms, such as "lower," "upper," and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is flipped, features described as "lower" would be oriented "upper". Thus, the exemplary term "lower" may include both upper and lower orientations. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application, such that variations of the illustrated shapes due to, for example, manufacturing techniques and/or tolerances are to be expected. Embodiments of the present application should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing techniques. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the application.
In view of the foregoing deficiencies in the prior art, the present application provides a semiconductor structure and a method for fabricating the same, the details of which will be described in the following examples.
Semiconductor devices in the field of semiconductor fabrication typically include a number of metal lines disposed on a surface of the device, which may be separated from each other by an interlayer dielectric layer.
However, as semiconductor device dimensions continue to shrink, device performance is increasingly limited by interlayer dielectric capacitance. For example, interlayer dielectrics cause parasitic capacitance before adjacent metal lines, resulting in RC delay, which in turn affects the speed of the device.
Therefore, how to reduce the RC delay between adjacent metal lines is a current problem that needs to be solved.
Based on this, the present application provides, according to some embodiments, a method of fabricating a semiconductor structure.
Referring to fig. 1, in some embodiments, the preparation method may include the steps of:
S100: a substrate is provided.
S200: forming a plurality of conducting layers and first interlayer dielectric layers which are horizontally arranged at intervals on a substrate; the first interlayer dielectric layer covers the conductive layers and fills gaps between adjacent conductive layers.
S300: forming a groove in the first interlayer dielectric layer; the grooves are located between adjacent conductive layers.
S400: forming a second interlayer dielectric layer at least in the groove; the second interlayer dielectric layer is deposited at a rate at least less in the lower region of the recess than in the upper region of the recess, and an air gap is formed in the second interlayer dielectric layer within the recess.
According to the preparation method of the semiconductor structure, the air gap with the low dielectric constant (the dielectric constant of the air gap is close to 1) is introduced between the adjacent conductive layers by forming the air gap in the second interlayer dielectric layer, so that the overall dielectric constant of the second interlayer dielectric layer is reduced, parasitic capacitance between the adjacent conductive layers is reduced, RC delay between the conductive layers and the second interlayer dielectric layer is improved, and the speed and performance of the device are further improved. In addition, the deposition rate of the second interlayer dielectric layer in the lower area of the groove is at least smaller than that in the upper area of the groove, so that an air gap with a moderate size can be formed in the second interlayer dielectric layer, the formed position of the air gap is also lower, gaps are prevented from being introduced in subsequent processing due to unsuitable size or position of the air gap, and the problem of damage to the conductive layer caused by the fact that moisture passes through the gaps in the subsequent processing is avoided.
In some embodiments, the lower region of the groove comprises a groove bottom, or comprises a groove bottom and a groove sidewall lower portion; the groove upper region includes a groove sidewall upper portion.
In some embodiments, the depth of the recess is less than the thickness of the first interlayer dielectric layer.
Referring to fig. 2, in some embodiments, forming a recess in the first interlayer dielectric layer in step S300 may include the following steps:
S310: forming an initial groove in the first interlayer dielectric layer; the depth of the initial groove is less than the depth of the groove.
S320: and performing plasma treatment on the side wall and the bottom of the initial groove to form a plasma treatment area on the side wall and the bottom of the initial groove.
S330: continuing to etch the first interlayer dielectric layer based on the initial groove to form a groove; the upper part of the side wall of the groove comprises a plasma treatment area, and the deposition rate of the second interlayer dielectric layer in the plasma treatment area is higher than that in the lower part of the side wall of the groove and the bottom of the groove.
In some embodiments, the plasma treatment of the sidewall and the bottom of the initial recess in step S320 may include the following steps:
Performing plasma treatment on the side wall of the initial groove by using argon plasma and helium plasma; the gas flow of the argon plasma is 50 sccm-150 sccm, the gas flow of the helium plasma is 200 sccm-800 sccm, and the radio frequency power in the plasma treatment process is 300W-1000W.
Referring to fig. 3, in some embodiments, before forming the plurality of conductive layers and the first interlayer dielectric layer arranged horizontally at intervals on the substrate in step S200, the preparation method may further include the following steps:
s510: and forming a covering dielectric layer on the upper surface of the substrate.
S511: forming a plurality of conductive plugs in the dielectric layer; the first interlayer dielectric layer and the conductive layer are both formed on the upper surface of the covering dielectric layer; the conductive layer is in contact with the conductive plug.
In some embodiments, step S510 of forming a capping dielectric layer on the upper surface of the substrate may include the following steps:
Taking silane and nitric oxide gas as reaction gases, and adopting a plasma enhanced chemical vapor deposition process to deposit an oxide layer on the upper surface of the substrate as a covering dielectric layer; the deposition rate of the covering dielectric layer is 10 nm/s-30 nm/s.
In step S200, forming a first interlayer dielectric layer on a substrate may include the following steps:
Oxygen and tetraethoxysilane are used as reactants, and a plasma enhanced chemical vapor deposition process is adopted to deposit an oxide layer on a substrate to be used as a first interlayer dielectric layer; the deposition rate of the first interlayer dielectric layer is 1 nm/s-20 nm/s.
Step S400, at least, forming a second interlayer dielectric layer in the recess, may include the following steps:
Ozone and tetraethoxysilane are used as reactants, and a deposited oxide layer is formed at least in the groove by adopting a low-pressure chemical vapor deposition process and used as a second interlayer dielectric layer; the deposition temperature of the second interlayer dielectric layer is 400-500 ℃; in the low-pressure chemical vapor deposition process, the molar ratio of ozone to tetraethoxysilane is 3-15.
Referring to fig. 4, in some embodiments, before forming the plurality of conductive layers and the first interlayer dielectric layer arranged horizontally at intervals on the substrate in step S200, the preparation method may further include the following steps:
s520: and forming a covering dielectric layer on the upper surface of the substrate.
S521: forming a plurality of conductive plugs in the dielectric layer; the first interlayer dielectric layer and the conductive layer are both formed on the covering dielectric layer; the conductive layer is in contact with the conductive plug.
In some embodiments, the first interlayer dielectric layer and the conductive layer are both formed on the capping dielectric layer; the groove penetrates through the first interlayer dielectric layer along the thickness direction so as to expose the covering dielectric layer; the deposition rate of the second interlayer dielectric layer on the surface of the covering dielectric layer is smaller than that of the first interlayer dielectric layer.
In some embodiments, after forming the plurality of conductive layers horizontally arranged at intervals on the substrate in step S200, before forming the first interlayer dielectric layer, the method may further include the following steps:
Forming an isolation layer on the upper surface of the covering dielectric layer and the upper surface of the conducting layer; the first interlayer dielectric layer is positioned on the upper surface of the isolation layer; the groove penetrates through the first interlayer dielectric layer along the thickness direction so as to expose the isolation layer; the deposition rate of the second interlayer dielectric layer on the surface of the isolation layer is smaller than that of the first interlayer dielectric layer.
In some embodiments, step S520 of forming a capping dielectric layer on the upper surface of the substrate may include the following steps:
Oxygen and tetraethoxysilane are used as reactants, and a plasma enhanced chemical vapor deposition process is adopted to deposit an oxide layer on a substrate as a covering dielectric layer; the deposition rate of the first interlayer dielectric layer is 1 nm/s-20 nm/s.
In step S200, forming a first interlayer dielectric layer on a substrate may include the following steps:
Taking silane and nitric oxide gas as reaction gases, and adopting a plasma enhanced chemical vapor deposition process to deposit an oxide layer on the upper surface of the substrate as a first interlayer dielectric layer; the deposition rate of the first interlayer dielectric layer is 10 nm/s-30 nm/s.
Step S400, at least, forming a second interlayer dielectric layer in the recess, may include the following steps:
Ozone and tetraethoxysilane are used as reactants, and a deposited oxide layer is formed at least in the groove by adopting a low-pressure chemical vapor deposition process and used as a second interlayer dielectric layer; the deposition temperature of the second interlayer dielectric layer is 400-500 ℃, and the mol ratio of ozone to tetraethoxysilane is 3-15 in the low-pressure chemical vapor deposition process.
In some embodiments, the forming the isolation layer on the upper surface of the dielectric layer and the upper surface of the conductive layer may include the following steps:
Forming an oxide layer on the surface of the covering dielectric layer and the upper surface of the conductive layer by adopting a thermal oxidation process to serve as an isolation layer; the temperature of the thermal oxidation process is 300-500 ℃.
In some embodiments, the second interlayer dielectric layer is further located on an upper surface of the first interlayer dielectric layer.
In some embodiments, the second interlayer dielectric layer located on the upper surface of the first interlayer dielectric layer has a thickness of 30nm to 200nm.
In order to more clearly illustrate the preparation methods in some of the above embodiments, some embodiments of the present application are understood below with reference to fig. 5 to 16.
Referring to fig. 5, in step S100, a substrate 100 is provided.
The material of the substrate 100 is not particularly limited in the present application. As an example, the substrate 100 may include, but is not limited to, silicon (Si), sapphire, glass, silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), or the like, or a combination thereof.
With continued reference to fig. 5, in some embodiments, before forming the plurality of conductive layers 200 and the first interlayer dielectric layer 300 on the substrate 100 at the step S200, the preparation method may further include the following steps S510 to S511.
In step S510, a capping dielectric layer 700 is formed on the upper surface of the substrate 100.
In step S511, a plurality of conductive plugs 710 are formed in the capping dielectric layer 700; the first interlayer dielectric layer 300 and the conductive layer 200 are both formed on the upper surface of the capping dielectric layer 700; the conductive layer 200 is in contact with the conductive plugs 710.
Referring to fig. 5, in step S200, a plurality of conductive layers 200 and a first interlayer dielectric layer 300 are formed on a substrate 100 at intervals. The first interlayer dielectric layer 300 covers the conductive layers 200 and fills the gaps between the adjacent conductive layers 200.
The material of the conductive layer 200 is not particularly limited in the present application. As an example, the material of the conductive layer 200 may include, but is not limited to, a material capable of performing a conductive function such as aluminum (Al), tungsten (W), copper (Cu), ruthenium (Ru), titanium nitride (TiN), or tantalum nitride (TaN).
In some embodiments, the conductive layer 200 is made of aluminum.
Referring to fig. 6 to 8, in step S300, a recess 420 is formed in the first interlayer dielectric layer 300; the grooves 420 are located between adjacent conductive layers 200.
The manner of forming the recess 420 in the first interlayer dielectric layer 300 is not particularly limited in the present application. As an example, the recess 420 may be formed in the first interlayer dielectric layer 300 by, but not limited to, dry etching (Dry etching).
In some embodiments, step S300 may be embodied as steps S310-S330 as follows.
In step S310, as shown in fig. 6, an initial recess 410 is formed in the first interlayer dielectric layer 300.
It should be noted that, the depth of the initial groove 410 is smaller than the depth of the groove 420 formed in step S300.
The manner of forming the initial recess 410 in the first interlayer dielectric layer 300 in step S310 is not particularly limited in the present application. As an example, as shown in fig. 6, an initial recess 410 may be formed in the first interlayer dielectric layer 300 in the following manner, such as:
forming a patterned mask layer 430 on the upper surface of the first interlayer dielectric layer 300; patterned masking layer 430 has openings that define the location and shape of initial recesses 410. The first interlayer dielectric layer 300 is etched based on the patterned mask layer 430 to form an initial recess 410 in the first interlayer dielectric layer 300.
The material of the patterned mask layer 430 in the above steps is not particularly limited. By way of example, patterned masking layer 430 may include, but is not limited to, a patterned photoresist layer.
In step S320, as shown in fig. 7, plasma processing (PLASMA TREATMENT) is performed on the sidewalls and bottom of the initial recess 410 to form plasma processing regions on the sidewalls and bottom of the initial recess 410.
The kind of the reaction gas used for the plasma treatment of the sidewall and bottom of the preliminary groove 410 in step S320 is not particularly limited. As an example, the step S320 may perform plasma treatment on the sidewalls and bottom of the initial recess 410 using, but not limited to, a reactive gas such as an argon plasma and a helium (He) plasma.
In some embodiments, the sidewalls and bottom of the initial recess 410 are plasma-treated using argon plasma and helium plasma in step S320.
The gas flow rates of the argon plasma and the helium plasma in step S320 are not particularly limited.
As an example, the gas flow rate of the argon plasma in step S320 may be 50sccm to 150sccm; for example, the gas flow rate of the argon plasma in step S320 may be 50 seem, 75 seem, 100 seem, 125 seem, 150 seem, or the like. As an example, the gas flow rate of the helium plasma in step S320 may be 200sccm to 800sccm; for example, the gas flow rate of the helium gas plasma in step S320 may be 200 seem, 300 seem, 500 seem, 700 seem, 800 seem, or the like.
The magnitude of the RF power (Radio frequency power, RF power for short) during plasma processing is not particularly limited in the present application. As an example, the rf power during plasma processing may be 300W to 1000W; for example, the RF power during plasma processing may be 300W, 500W, 700W, 900W, 1000W, etc.
In step S330, as shown in fig. 8, the etching of the first interlayer dielectric layer 300 is continued based on the initial recess 410 to form a recess 420. The sidewall upper portion of the recess 420 includes a plasma processing region where the second interlayer dielectric layer 500 is deposited at a greater rate than the deposition rate at the sidewall lower portion of the recess 420 and the bottom of the recess 420.
The depth of the initial groove 410 is not particularly limited in the present application. As an example, the depth of the initial groove 410 may be 1/5 to 1/2 of the depth of the groove 420 formed in step S300; for example, the depth of the initial recess 410 may be 1/2, 1/3, 1/4, 1/5, etc. of the depth of the recess 420 formed in step S300.
In some embodiments, the first interlayer dielectric layer 300 may be etched a plurality of times based on the initial recess 410 to form the recess 420. The number of times of etching the first interlayer dielectric layer 300 to form the recess 420 based on the initial recess 410 is not particularly limited in the present application. As an example, the first interlayer dielectric layer 300 may be etched 1 to 4 times based on the initial groove 410 to form the groove 420; for example, the first interlayer dielectric layer 300 may be etched 1,2, 3, or 4 times based on the initial recesses 410 to form the recesses 420.
In some embodiments, the depth of the initial recess 410 may be 1/2 of the depth of the recess 420 formed in step S300, and the first interlayer dielectric layer 300 is etched once based on the initial recess 410 to form the recess 420. In other embodiments, the depth of the initial recess 410 may be 1/3 of the depth of the recess 420 formed in step S300, and the first interlayer dielectric layer 300 is etched twice based on the initial recess 410 to form the recess 420; in the two etches, each etch depth may be 1/3 of the depth of the recess 420.
Referring to fig. 9, in step S400, a second interlayer dielectric layer 500 is formed at least in the recess 420. The second interlayer dielectric layer 500 is deposited at a rate at least less in a lower region (shown at a) of the recess 420 than in an upper region (shown at b) of the recess 420, and an air gap 600 is formed in the second interlayer dielectric layer 500 within the recess 420.
It should be noted that, in the embodiment of the present application, the lower region of the groove 420 may include the bottom of the groove 420, or may include the bottom of the groove 420 and the lower portion of the sidewall of the groove 420. It should also be noted that in embodiments of the present application, the upper region of the recess 420 may include an upper portion of the sidewall of the recess 420.
The material of the second interlayer dielectric layer 500 is not particularly limited in the present application. As an example, the material of the second interlayer dielectric layer 500 may include, but is not limited to, tetraethoxysilane stearate (SATEOS).
As an example, in step S400, the second interlayer dielectric layer 500 may be formed in the recess 420 by the following method, for example:
Ozone (O 3) and tetraethyl orthosilicate (TEOS) are used as reactants, and a low-pressure chemical vapor deposition process is used to form a deposited oxide layer in at least the recess 420 as the second interlayer dielectric layer 500.
The deposition temperature of the second interlayer dielectric layer 500 is not particularly limited in the present application. As an example, the deposition temperature of the second interlayer dielectric layer 500 may be 400 to 500 ℃; for example, the second interlayer dielectric layer 500 may be deposited at a temperature of 400 ℃, 425 ℃, 450 ℃, 475 ℃, 500 ℃, or the like.
The application is not limited in the molar ratio of ozone to ethyl orthosilicate in the low-pressure chemical vapor deposition process. As an example, the molar ratio of ozone to ethyl orthosilicate in the low pressure chemical vapor deposition process may be 3 to 15; for example, the molar ratio of ozone to ethyl orthosilicate may be 3, 7, 11 or 15, etc.
With continued reference to fig. 9, in some embodiments, the second interlayer dielectric layer 500 is further disposed on the upper surface of the first interlayer dielectric layer 300.
The thickness of the second interlayer dielectric layer 500 on the upper surface of the first interlayer dielectric layer 300 is not particularly limited in the present application. As an example, the thickness of the second interlayer dielectric layer 500 located on the upper surface of the first interlayer dielectric layer 300 may be 30nm to 200nm; for example, the thickness of the second interlayer dielectric layer 500 located on the upper surface of the first interlayer dielectric layer 300 may be 30nm, 50nm, 100nm, 150nm, 200nm, or the like.
The material of the capping dielectric layer 700 and the material of the first interlayer dielectric layer 300 are not particularly limited in the present application.
In some embodiments, the material of the capping dielectric layer 700 is different from the material of the first interlayer dielectric layer 300.
With continued reference to fig. 5, in some embodiments, the material of the capping dielectric layer 700 may include an oxide of silane (SiH 4), and the material of the first interlayer dielectric layer 300 may include an oxide of tetraethyl orthosilicate for plasma enhancement (PLASMA ENHANCED Tetraethylorthosilicate, PETEOS).
As an example, the capping dielectric layer 700 may be formed on the upper surface of the substrate 100 by a method such as:
With silane and nitric oxide (N 2 O) gases as reactive gases, an oxide layer is deposited on the upper surface of the substrate 100 as a capping dielectric layer 700 by a Plasma Enhanced Chemical Vapor Deposition (PECVD) process. Alternatively, the deposition rate of the capping dielectric layer 700 may be 10nm/s to 30nm/s; for example, the deposition rate of the capping dielectric layer 700 may be 10nm/s, 15nm/s, 20nm/s, 25nm/s, 30nm/s, or the like.
As an example, the first interlayer dielectric layer 300 may be formed on the substrate 100 by a method such as:
Oxygen (O 2) and ethyl orthosilicate are used as reactants, and a plasma enhanced chemical vapor deposition process is used to deposit an oxide layer on the substrate 100 as the first interlayer dielectric layer 300. Alternatively, the deposition rate of the first interlayer dielectric layer 300 may be 1nm/s to 20nm/s; for example, the deposition rate of the first interlayer dielectric layer 300 may be 1nm/s, 5nm/s, 10nm/s, 15nm/s, 20nm/s, or the like.
Referring to fig. 10, in other embodiments, the material of the capping dielectric layer 700 may include an oxide of ethyl orthosilicate for plasma enhancement, and the first interlayer dielectric layer 300 may include an oxide of silane. Referring to fig. 11 to 12, the subsequent steps of the preparation method in the embodiment can be referred to the previous descriptions of fig. 6 to 9, and will not be repeated here.
As an example, the capping dielectric layer 700 may be formed on the upper surface of the substrate 100 by a method including:
Oxygen and ethyl orthosilicate are used as reactants, and a plasma enhanced chemical vapor deposition process is used to deposit an oxide layer on the substrate 100 as the capping dielectric layer 700. Alternatively, the deposition rate of the first interlayer dielectric layer 300 may be 1nm/s to 20nm/s; ; for example, the deposition rate of the capping dielectric layer 700 may be 1nm/s, 5nm/s, 10nm/s, 15nm/s, 20nm/s, or the like.
As an example, the first interlayer dielectric layer 300 may be formed on the substrate 100 by a method such as:
An oxide layer is deposited on the upper surface of the substrate 100 as the first interlayer dielectric layer 300 by a plasma enhanced chemical vapor deposition process using silane and nitric oxide gas as reactive gases. Alternatively, the deposition rate of the first interlayer dielectric layer 300 may be 10nm/s to 30nm/s; for example, the deposition rate of the first interlayer dielectric layer 300 may be 10nm/s, 15nm/s, 20nm/s, 25nm/s, 30nm/s, or the like.
It should be noted that, the material of the capping dielectric layer 700, the material of the first interlayer dielectric layer 300, and the type of the reaction gas are only examples, and the materials and the manner for preparing the capping dielectric layer 700 and the first interlayer dielectric layer 300 in the practical embodiment are not limited to the examples described above.
With continued reference to fig. 11, in some embodiments, a first interlayer dielectric layer 300 and a conductive layer 200 are both formed on a capping dielectric layer 700; the groove 420 penetrates through the first interlayer dielectric layer 300 in the thickness direction to expose the capping dielectric layer 700; the deposition rate of the second interlayer dielectric layer 500 on the surface of the capping dielectric layer 700 is less than the deposition rate of the first interlayer dielectric layer 300.
In the method for manufacturing a semiconductor structure provided in the foregoing embodiment, the deposition rate of the second interlayer dielectric layer 500 on the surface of the capping dielectric layer 700 is smaller than the deposition rate of the second interlayer dielectric layer 500 on the surface of the first interlayer dielectric layer 300, so that the air gap 600 with a moderate size can be formed in the second interlayer dielectric layer 500 by utilizing the difference of the deposition rates of the second interlayer dielectric layer 500 on the surfaces of different structures.
Referring to fig. 13, in some embodiments, before forming the plurality of conductive layers 200 and the first interlayer dielectric layer 300 on the substrate 100 at the step S200 at intervals, the preparation method may further include the following steps S520 to S521.
In step S520, as shown in fig. 13, a capping dielectric layer 700 is formed on the upper surface of the substrate 100.
In step S521, a plurality of conductive plugs 710 are formed in the capping dielectric layer 700; the first interlayer dielectric layer 300 and the conductive layer 200 are both formed on the capping dielectric layer 700; the conductive layer 200 is in contact with the conductive plugs 710.
With continued reference to fig. 13, in some embodiments, after forming the plurality of conductive layers 200 on the substrate 100 at the step S200 and before forming the first interlayer dielectric layer 300, the preparation method may further include the following steps:
an isolation layer 800 is formed to cover the upper surface of the dielectric layer 700 and the upper surface of the conductive layer 200.
In the above embodiment, the structure obtained by forming the first interlayer dielectric layer 300 in step S200 is shown in fig. 14, where the first interlayer dielectric layer 300 is located on the upper surface of the isolation layer 800.
In the above embodiment, the structure of forming the recess 420 in step S300 is shown in fig. 15, where the recess 420 penetrates through the first interlayer dielectric layer 300 in the thickness direction to expose the isolation layer 800.
In the above embodiment, the structure of the second interlayer dielectric layer 500 formed in step S400 is shown in fig. 16, and the deposition rate of the second interlayer dielectric layer 500 on the surface of the isolation layer 800 is smaller than that of the first interlayer dielectric layer 300.
The present application is not limited to a specific manner of forming the isolation layer 800 on the upper surface of the capping dielectric layer 700 and the upper surface of the conductive layer 200. As an example, the isolation layer 800 may be formed on the upper surface of the capping dielectric layer 700 and the upper surface of the conductive layer 200 by the following method, for example:
an oxide layer is formed as the isolation layer 800 on the surface of the capping dielectric layer 700 and the upper surface of the conductive layer 200 by a thermal oxidation process.
The temperature of the thermal oxidation process is not particularly limited in the present application. As an example, the temperature of the thermal oxidation process may be 300 ℃ to 500 ℃; for example, the temperature of the thermal oxidation process may be 300 ℃, 350 ℃, 400 ℃, 450 ℃, 500 ℃, or the like.
It should be understood that, although the steps in the flowcharts of fig. 1 to 4 are sequentially shown as indicated by arrows, these steps are not necessarily sequentially performed in the order indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps of fig. 1-4 may include steps or stages that are not necessarily performed at the same time, but may be performed at different times, nor does the order in which the steps or stages are performed necessarily occur sequentially, but may be performed alternately or alternately with other steps or at least a portion of the steps or stages in other steps.
The present application, in accordance with some embodiments, provides a semiconductor structure,
With continued reference to fig. 9, in some embodiments, the semiconductor structure may include a substrate 100, a plurality of conductive layers 200 arranged in parallel and spaced apart, a first interlayer dielectric layer 300, and a second interlayer dielectric layer 500.
As shown in fig. 9, a plurality of conductive layers 200 arranged in parallel and at intervals are located on the substrate 100; the first interlayer dielectric layer 300 covers the conductive layers 200 and fills the gaps between the adjacent conductive layers 200, and the first interlayer dielectric layer 300 has grooves 420 (not shown in fig. 9) therein, the grooves 420 being located between the adjacent conductive layers 200; the second interlayer dielectric layer 500 is at least located in the recess 420, and the deposition rate of the second interlayer dielectric layer 500 in the lower region of the recess 420 is at least smaller than that in the upper region of the recess 420, and the air gap 600 is formed in the second interlayer dielectric layer 500 in the recess 420.
In the semiconductor structure provided in the above embodiment, the air gap 600 is formed in the second interlayer dielectric layer 500, and the air gap 600 with a low dielectric constant (the dielectric constant of the air gap 600 is close to 1) is introduced between the adjacent conductive layers 200, so as to reduce the overall dielectric constant of the second interlayer dielectric layer 500, thereby reducing the parasitic capacitance between the adjacent conductive layers 200, improving the RC delay between the conductive layers 200 and the second interlayer dielectric layer 500, and further improving the speed and performance of the device. In addition, since the deposition rate of the second interlayer dielectric layer 500 in the lower region of the recess 420 is at least smaller than that in the upper region of the recess 420, the air gap 600 with a moderate size can be formed in the second interlayer dielectric layer 500, and the position of the air gap 600 is also lower, so that the problem of damage to the conductive layer 200 caused by the fact that moisture passes through the gap in the subsequent process due to the fact that the air gap 600 is not appropriate in size or position is avoided.
With continued reference to fig. 9, in some embodiments, the second interlayer dielectric layer 500 is further disposed on the upper surface of the first interlayer dielectric layer 300.
With continued reference to fig. 9, in some embodiments, the depth of the recess 420 may be less than the thickness of the first interlayer dielectric layer 300.
In some embodiments, an upper portion of the sidewall of recess 420 (shown at b) may have a plasma processing region; on this basis, the deposition rate of the second interlayer dielectric layer 500 in the plasma treatment region is greater than that in the lower portion of the sidewall of the recess 420 and the bottom (shown at a) of the recess 420.
With continued reference to fig. 9, in some embodiments, the semiconductor structure may further include a capping dielectric layer 700 and a conductive plug 710. Wherein the capping dielectric layer 700 is located on the upper surface of the substrate 100; conductive plugs 710 are located within the capping dielectric layer 700.
As shown in fig. 9, the first interlayer dielectric layer 300 and the conductive layer 200 are both formed on the capping dielectric layer 700, and the conductive layer 200 is in contact with the conductive plugs 710.
With continued reference to fig. 9, in some embodiments, the first interlayer dielectric layer 300 and the conductive layer 200 are both formed on the upper surface of the capping dielectric layer 700; the groove 420 penetrates through the first interlayer dielectric layer 300 in the thickness direction to expose the capping dielectric layer 700; the deposition rate of the second interlayer dielectric layer 500 on the surface of the capping dielectric layer 700 is less than the deposition rate of the first interlayer dielectric layer 300.
With continued reference to fig. 16, in some embodiments, the semiconductor structure may further include an isolation layer 800.
As shown in fig. 16, the isolation layer 800 is disposed on the upper surface of the dielectric layer 700 and the upper surface of the conductive layer 200; the first interlayer dielectric layer 300 is located on the upper surface of the isolation layer 800; the groove 420 penetrates through the first interlayer dielectric layer 300 in the thickness direction to expose the capping dielectric layer 700; the deposition rate of the second interlayer dielectric layer 500 on the surface of the capping dielectric layer 700 is less than the deposition rate of the first interlayer dielectric layer 300.
It should be noted that the semiconductor structures in the embodiments of the present application may be prepared by corresponding methods for preparing semiconductor structures, so that technical features between the method embodiments and the structural embodiments may be replaced and supplemented with each other without generating conflict, so that those skilled in the art can learn about the technical content of the present application.
The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the claims. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.

Claims (20)

1. A method of fabricating a semiconductor structure, comprising:
providing a substrate;
forming a plurality of conducting layers and first interlayer dielectric layers which are horizontally arranged at intervals on the substrate; the first interlayer dielectric layer covers the conductive layers and fills gaps between adjacent conductive layers;
forming a groove in the first interlayer dielectric layer; the grooves are positioned between adjacent conductive layers;
Forming a second interlayer dielectric layer at least in the groove; the second interlayer dielectric layer is deposited at a rate at least less in the lower region of the recess than in the upper region of the recess, and an air gap is formed in the second interlayer dielectric layer within the recess.
2. The method of claim 1, wherein the lower region of the recess comprises the recess bottom or comprises the recess bottom and the recess sidewall lower portion;
the recess upper region includes the recess sidewall upper portion.
3. The method of claim 1, wherein the depth of the recess is less than the thickness of the first interlayer dielectric layer;
Forming a groove in the first interlayer dielectric layer comprises the following steps:
forming an initial groove in the first interlayer dielectric layer; the depth of the initial groove is smaller than that of the groove;
performing plasma treatment on the side wall and the bottom of the initial groove to form a plasma treatment area on the side wall and the bottom of the initial groove;
continuing to etch the first interlayer dielectric layer based on the initial groove to form the groove; the upper part of the side wall of the groove comprises the plasma treatment area, and the deposition rate of the second interlayer dielectric layer in the plasma treatment area is higher than that in the lower part of the side wall of the groove and the bottom of the groove.
4. The method of claim 3, wherein the performing plasma treatment on the sidewall and the bottom of the initial recess comprises:
Performing plasma treatment on the side wall and the bottom of the initial groove by using argon plasma and helium plasma; the gas flow of the argon plasma is 50 sccm-150 sccm, the gas flow of the helium plasma is 200 sccm-800 sccm, and the radio frequency power in the plasma treatment process is 300W-1000W.
5. The method for manufacturing a semiconductor structure according to claim 4, further comprising, before forming a plurality of conductive layers and a first interlayer dielectric layer on the substrate, wherein the conductive layers and the first interlayer dielectric layer are horizontally arranged at intervals:
forming a covering dielectric layer on the upper surface of the substrate;
forming a plurality of conductive plugs in the covering dielectric layer; the first interlayer dielectric layer and the conductive layer are both formed on the upper surface of the covering dielectric layer; the conductive layer is in contact with the conductive plug.
6. The method for manufacturing a semiconductor structure according to claim 5, wherein forming a capping dielectric layer on the upper surface of the substrate comprises:
Taking silane and nitric oxide gas as reaction gases, and adopting a plasma enhanced chemical vapor deposition process to deposit an oxide layer on the upper surface of the substrate as the covering medium layer; the deposition rate of the covering dielectric layer is 10 nm/s-30 nm/s;
the forming a first interlayer dielectric layer on the substrate comprises the following steps:
Oxygen and tetraethoxysilane are used as reactants, and a plasma enhanced chemical vapor deposition process is adopted to deposit an oxide layer on the substrate to be used as the first interlayer dielectric layer; the deposition rate of the first interlayer dielectric layer is 1 nm/s-20 nm/s;
forming a second interlayer dielectric layer in at least the groove, including:
Ozone and tetraethoxysilane are used as reactants, and a low-pressure chemical vapor deposition process is adopted to form a deposition oxide layer in at least the groove to be used as the second interlayer dielectric layer; the deposition temperature of the second interlayer dielectric layer is 400-500 ℃; in the low-pressure chemical vapor deposition process, the molar ratio of ozone to tetraethoxysilane is 3-15.
7. The method for manufacturing a semiconductor structure according to any one of claims 1 to 6, further comprising, before forming a plurality of conductive layers and a first interlayer dielectric layer arranged horizontally at intervals on the substrate:
forming a covering dielectric layer on the upper surface of the substrate;
forming a plurality of conductive plugs in the covering dielectric layer; the first interlayer dielectric layer and the conductive layer are formed on the covering dielectric layer; the conductive layer is in contact with the conductive plug.
8. The method for manufacturing a semiconductor structure according to claim 1, wherein before forming the plurality of conductive layers and the first interlayer dielectric layers on the substrate, the method further comprises:
forming a covering dielectric layer on the upper surface of the substrate;
Forming a plurality of conductive plugs in the covering dielectric layer; the first interlayer dielectric layer and the conductive layer are formed on the covering dielectric layer; the conductive layer is in contact with the conductive plug;
Wherein, the first interlayer dielectric layer and the conductive layer are both formed on the covering dielectric layer; the groove penetrates through the first interlayer dielectric layer along the thickness direction so as to expose the covering dielectric layer; the deposition rate of the second interlayer dielectric layer on the surface of the covering dielectric layer is smaller than that of the first interlayer dielectric layer.
9. The method for manufacturing a semiconductor structure according to claim 7, wherein after the forming of the plurality of conductive layers horizontally arranged at intervals on the substrate, before the forming of the first interlayer dielectric layer, further comprises:
Forming an isolation layer on the upper surface of the covering dielectric layer and the upper surface of the conductive layer; the first interlayer dielectric layer is positioned on the upper surface of the isolation layer; the groove penetrates through the first interlayer dielectric layer along the thickness direction so as to expose the isolation layer; the deposition rate of the second interlayer dielectric layer on the surface of the isolation layer is smaller than that of the first interlayer dielectric layer.
10. The method for fabricating a semiconductor structure according to claim 8 or 9, wherein,
Forming a covering dielectric layer on the upper surface of the substrate, including:
oxygen and tetraethoxysilane are used as reactants, and a plasma enhanced chemical vapor deposition process is adopted to deposit an oxide layer on the substrate to be used as the covering medium layer; the deposition rate of the first interlayer dielectric layer is 1 nm/s-20 nm/s;
the forming a first interlayer dielectric layer on the substrate comprises the following steps:
Taking silane and nitric oxide gas as reaction gases, and adopting a plasma enhanced chemical vapor deposition process to deposit an oxide layer on the upper surface of the substrate to serve as the first interlayer dielectric layer; the deposition rate of the first interlayer dielectric layer is 10 nm/s-30 nm/s;
forming a second interlayer dielectric layer in at least the groove, including:
Ozone and tetraethoxysilane are used as reactants, and a low-pressure chemical vapor deposition process is adopted to form a deposition oxide layer in at least the groove to be used as the second interlayer dielectric layer; the deposition temperature of the second interlayer dielectric layer is 400-500 ℃, and the molar ratio of ozone to tetraethoxysilane in the low-pressure chemical vapor deposition process is 3-15.
11. The method of manufacturing a semiconductor structure according to claim 9, wherein forming an isolation layer on the upper surface of the capping dielectric layer and the upper surface of the conductive layer comprises:
forming an oxide layer on the surface of the covering dielectric layer and the upper surface of the conductive layer by adopting a thermal oxidation process to serve as the isolation layer; the temperature of the thermal oxidation process is 300-500 ℃.
12. The method of claim 1, wherein the second interlayer dielectric layer is further located on an upper surface of the first interlayer dielectric layer.
13. The method of manufacturing a semiconductor structure according to claim 12, wherein a thickness of the second interlayer dielectric layer located on the upper surface of the first interlayer dielectric layer is 30nm to 200nm.
14. A semiconductor structure, comprising:
A substrate;
A plurality of parallel conductive layers arranged at intervals and positioned on the substrate;
the first interlayer dielectric layer covers the conductive layers and fills gaps between adjacent conductive layers; the first interlayer dielectric layer is internally provided with a groove, and the groove is positioned between adjacent conductive layers;
The second interlayer dielectric layer is at least positioned in the groove, the deposition rate of the second interlayer dielectric layer in the lower area of the groove is at least smaller than that of the upper area of the groove, and an air gap is formed in the second interlayer dielectric layer in the groove.
15. The semiconductor structure of claim 14, wherein the recess lower region comprises the recess bottom or comprises the recess bottom and the recess sidewall lower portion;
the recess upper region includes the recess sidewall upper portion.
16. The semiconductor structure of claim 14, wherein a depth of the recess is less than a thickness of the first interlayer dielectric layer; the upper part of the side wall of the groove is provided with a plasma treatment area, and the deposition rate of the second interlayer dielectric layer in the plasma treatment area is larger than that of the lower part of the side wall of the groove and the bottom of the groove.
17. The semiconductor structure of any one of claims 14 to 16, further comprising:
The dielectric layer is covered and positioned on the upper surface of the substrate;
A conductive plug in the dielectric layer; the first interlayer dielectric layer and the conductive layer are formed on the covering dielectric layer; the conductive layer is in contact with the conductive plug.
18. The semiconductor structure of claim 14, further comprising:
The dielectric layer is covered and positioned on the upper surface of the substrate;
A conductive plug in the dielectric layer; the first interlayer dielectric layer and the conductive layer are formed on the covering dielectric layer; the conductive layer is in contact with the conductive plug;
The first interlayer dielectric layer and the conductive layer are formed on the upper surface of the covering dielectric layer; the groove penetrates through the first interlayer dielectric layer along the thickness direction so as to expose the covering dielectric layer; the deposition rate of the second interlayer dielectric layer on the surface of the covering dielectric layer is smaller than that of the first interlayer dielectric layer.
19. The semiconductor structure of claim 17, further comprising:
The isolation layer is positioned on the upper surface of the covering dielectric layer and the upper surface of the conductive layer;
The first interlayer dielectric layer is positioned on the upper surface of the isolation layer; the groove penetrates through the first interlayer dielectric layer along the thickness direction so as to expose the covering dielectric layer; the deposition rate of the second interlayer dielectric layer on the surface of the covering dielectric layer is smaller than that of the first interlayer dielectric layer.
20. The semiconductor structure of claim 14, wherein the second interlayer dielectric layer is further located on an upper surface of the first interlayer dielectric layer; the thickness of the second interlayer dielectric layer positioned on the upper surface of the first interlayer dielectric layer is 30 nm-200 nm.
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