CN117954320A - Manufacturing method of semiconductor chip, semiconductor chip and application thereof - Google Patents
Manufacturing method of semiconductor chip, semiconductor chip and application thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
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- 239000002184 metal Substances 0.000 claims abstract description 97
- 239000003990 capacitor Substances 0.000 claims abstract description 83
- 238000005530 etching Methods 0.000 claims abstract description 14
- 238000003475 lamination Methods 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 claims description 467
- 238000000034 method Methods 0.000 claims description 44
- 239000011241 protective layer Substances 0.000 claims description 13
- 238000004891 communication Methods 0.000 claims description 5
- 230000003071 parasitic effect Effects 0.000 abstract description 17
- 238000010030 laminating Methods 0.000 abstract 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 20
- 238000000605 extraction Methods 0.000 description 19
- 238000000151 deposition Methods 0.000 description 13
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- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 4
- 239000001257 hydrogen Substances 0.000 description 4
- 229910052739 hydrogen Inorganic materials 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 4
- 230000002633 protecting effect Effects 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
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- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
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- 238000000231 atomic layer deposition Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention discloses a manufacturing method of a semiconductor chip, which comprises the steps of sequentially forming a first dielectric layer and a second dielectric layer on an epitaxial structure formed with a source electrode and a drain electrode, etching a dielectric layer lamination layer between the source electrode and the drain electrode of a first device region to form an opening, forming a grid in the opening, forming a third dielectric layer as a grid protection layer, and laminating the second dielectric layer and the third dielectric layer on a capacitor structure region outside the first device region to form a capacitor dielectric layer; and forming a metal wire in the first device region and forming a capacitor plate on the capacitor structure region. The invention also discloses a formed semiconductor chip structure, which reduces the thickness of the gate covering dielectric layer and reduces the parasitic capacitance of the active device, thereby effectively reducing the noise coefficient of the device and improving the application performance in the radio frequency module.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a manufacturing method of a semiconductor chip, the semiconductor chip and application of the semiconductor chip.
Background
High Electron Mobility Transistors (HEMTs) and pseudomorphic high electron mobility transistors (pHEMT) have important applications in radio frequency circuits and radio frequency integrated circuits, commonly used as Power Amplifiers (PA), low noise power amplifiers (LNA), and the like. The low noise amplifier is used as the front end device of the wireless communication receiving system, and has the main function of amplifying weak signals, and the performances of noise, gain, linearity and the like of the low noise amplifier directly influence the performance of a receiver. The parasitic capacitance of HEMTs and pHEMT is an important factor affecting their noise characteristics, and the gate-related parasitic capacitance is an important component of their parasitic capacitance, the main source of which is the protective layer material that covers the gate. These protective layer materials are typically thin film materials such as silicon nitride (SiNx), silicon dioxide (SiOx), aluminum oxide (AlOx), etc., which serve to reduce the environmental factors such as moisture and oxygen from damaging HEMTs, pHEMT, and other device performance on integrated circuits. The parasitic capacitance caused by the protective layer material is related to the composition, area and thickness of its material. Therefore, how to reduce parasitic capacitance caused by the protective layer material remains an important challenge in the design and fabrication process of HEMTs and pHEMT devices.
The prior art mainly adopts a method for reducing the area of the protective layer to reduce the parasitic capacitance, and the main method is to reduce the widths of the grid electrode and the etching groove, thereby reducing the area of the protective layer covered on the grid electrode and the etching groove. These techniques have developed HEMTs and pHEMT from 0.5 μm gate technology to below 0.1 μm gate technology, effectively reducing parasitic capacitance. However, the manufacturing complexity of HEMTs and pHEMT is higher and higher due to the technology alternation, the effect of further reducing parasitic capacitance is more and more difficult to achieve, and the manufacturing cost of HEMTs and pHEMT related products is higher and higher, so that further breakthrough is difficult to achieve.
Disclosure of Invention
The invention provides a manufacturing method of a semiconductor chip, the semiconductor chip and application thereof, aiming at the defects existing in the prior art.
In order to achieve the above object, the technical scheme of the present invention is as follows:
A method for manufacturing a semiconductor chip comprises the following steps:
1) Forming a source electrode and a drain electrode on a first device region of the epitaxial structure;
2) Sequentially forming a first dielectric layer and a second dielectric layer, wherein the first dielectric layer and the second dielectric layer form a dielectric layer lamination on the surface of the epitaxial structure between the source electrode and the drain electrode;
3) Etching the dielectric laminated layer between the source electrode and the drain electrode to form a first opening;
4) Forming a gate on the epitaxial structure in the first opening;
5) Forming a third dielectric layer, wherein the third dielectric layer covers the surface of the gate as a protective layer; meanwhile, the second dielectric layer and the third dielectric layer are laminated on a capacitor structure area outside the first device area to serve as a capacitor dielectric layer;
Wherein, in the step after step 1), the method further comprises the step of forming a patterned first metal layer, wherein, in the first device region, the first metal layer is positioned on the source electrode and the drain electrode and is contacted with the source electrode and the drain electrode; and in the capacitor structure area, the first metal layer forms a capacitor plate.
In an embodiment, the first metal layer is formed between the steps of forming the first dielectric layer and the second dielectric layer in the step 2), and the first metal layer penetrates through the first dielectric layer in the first device region to contact with the source electrode and the drain electrode respectively; and in the capacitor structure area, the first metal layer forms a capacitor lower polar plate. The method also comprises the steps of:
6) Forming a patterned second metal layer, wherein the second metal layer penetrates through the second dielectric layer and the third dielectric layer respectively to be in contact with the first metal layer in the first device region and form an air bridge structure; and forming a capacitor upper polar plate on the capacitor structure area by the second metal layer.
In another embodiment, the method further comprises the steps of:
6) Forming a first metal layer, wherein the first metal layer penetrates through the first dielectric layer, the second dielectric layer and the third dielectric layer respectively and is in contact with the source electrode and the drain electrode in the first device region; forming a capacitor upper polar plate on the capacitor structure region by the first metal layer;
in the step 2), between the steps of forming the first dielectric layer and the second dielectric layer, a step of forming a capacitor bottom plate in the capacitor structure area is further included.
7) Forming a patterned second metal layer, wherein the second metal layer is respectively contacted with the first metal layer in the first device region and forms an air bridge structure; in the capacitor structure region, the second metal layer is disposed on the first metal layer and contacts the first metal layer.
Optionally, the epitaxial structure is a pHEMT epitaxial structure or a HEMT epitaxial structure, and the top layer is a cap layer; in the step 4), a groove is formed on the surface of the epitaxial structure in the first opening, the etching depth of the groove is not smaller than the thickness of the cap layer, and the width of the groove is smaller than the width of the first opening; the grid electrode is arranged in the groove.
Optionally, after the step 5), the method further includes a step of forming a top dielectric layer, where the top dielectric layer forms a protective layer stack with the third dielectric layer on the surface of the gate.
Optionally, a resistor structure is formed on the first dielectric layer outside the first device region, the resistor structure comprises a resistor layer arranged on the first dielectric layer, and the first metal layer is arranged at two ends of the resistor layer to serve as outgoing lines; the resistor layer is formed between the first dielectric layer and the second dielectric layer, and the second dielectric layer and the third dielectric layer form a laminated layer which covers the resistor layer.
A semiconductor chip comprises an epitaxial structure, wherein a source electrode, a drain electrode, a grid electrode, a first dielectric layer, a second dielectric layer, a third dielectric layer and a patterned first metal layer are arranged on the epitaxial structure; the epitaxial structure has a first device region on which a source and a drain are disposed, and a second device region on which:
The first dielectric layer and the second dielectric layer cover the source electrode and the drain electrode in sequence, a dielectric layer lamination is formed on the surface of the epitaxial structure between the source electrode and the drain electrode, the dielectric layer lamination between the source electrode and the drain electrode is provided with a first opening, the grid electrode is arranged on the epitaxial structure in the first opening, the third dielectric layer is arranged on the second dielectric layer and covers the exposed surface of the epitaxial structure and the surface of the grid electrode in the first opening, and the first metal layer is arranged on the source electrode and the drain electrode and is contacted with the source electrode and the drain electrode;
a capacitor structure is arranged on the first dielectric layer outside the first device region, and the capacitor structure region is:
The second dielectric layer and the third dielectric layer are stacked to be used as a capacitance dielectric layer, and the first metal layer is used as a capacitance polar plate.
Optionally, the semiconductor device further comprises a patterned second metal layer, wherein the second metal layer is respectively contacted with the first metal layer on the first device region and has an air bridge structure; the second metal layer is used as a capacitor plate or is in contact with the first metal layer on the capacitor structure area.
Optionally, the semiconductor device further includes a resistor structure disposed on the first dielectric layer outside the first device region, and in the resistor structure region:
the resistor comprises a resistor layer arranged on a first dielectric layer, and the first metal layer is arranged at two ends of the resistor layer to serve as outgoing lines.
Optionally, the semiconductor device further comprises a top dielectric layer, wherein the top dielectric layer and the third dielectric layer form a protective layer lamination on the surface of the grid electrode; the thickness of the top dielectric layer is 20-100 nm.
Optionally, the thickness of the first dielectric layer is 10-100 nm; the thickness of the second dielectric layer is 100-250 nm; the thickness of the third dielectric layer is 20-100 nm.
A radio frequency module comprises the semiconductor chip.
Optionally, the first device region is a HEMT device or a pHEMT device, and the HEMT device or the pHEMT device is used for a low noise amplifier in a radio frequency module.
Further, the density of the first medium layer is smaller than that of the third medium layer. The first dielectric layer is loose, so that damage to the epitaxial layer during deposition of the first dielectric layer can be reduced, and the third dielectric layer is denser, so that the influence of subsequent thermal processing on the device characteristics can be avoided.
Further, in the preparation process, the third dielectric layer adopts a deposition temperature higher than that of the first dielectric layer, and the third dielectric layer adopts a deposition temperature higher than that of the first dielectric layer, so that the deposited film layer can be ensured to be more compact and uniform, a good protection effect is achieved on the grid electrode, and the failure problem caused by the hydrogen effect can be reduced when the concentration of hydrogen in the generated film is reduced.
Further, in the preparation process, the deposition rate of the third dielectric layer is smaller than that of the first dielectric layer. The bombardment energy of the third dielectric layer to the epitaxial layer is smaller when the deposition rate of the third dielectric layer is controlled to be smaller, and the phenomenon that the device current is damaged after the bombardment of the epitaxial layer to cause the performance of the device to be reduced is avoided.
The radio frequency module is applied to a base station, a radar, communication or remote sensing.
The beneficial effects of the invention are as follows:
1) The thickness of the gate covering dielectric layer is reduced, and the parasitic capacitance of an active device is reduced, so that the noise coefficient of the device is effectively reduced;
2) Through the process step sequence of the invention, the source and the drain are covered and protected by the dielectric layer when the grid is manufactured, and various devices with different grid sizes can be integrated without affecting the performance of the devices;
3) The method can be integrated with devices such as a capacitor and a resistor to effectively improve the performance of an active device on the premise of not influencing the performance of other devices such as a capacitance value of the capacitor;
4) Is suitable for practical production and application.
Drawings
Fig. 1a to 1f are schematic structural views obtained by the steps of the method for manufacturing a semiconductor chip of embodiment 1;
fig. 2 is a schematic structural view of a first device region of the semiconductor chip of embodiment 1;
Fig. 3a to 3e are schematic structural views obtained by each step of the method for manufacturing a semiconductor chip of embodiment 2;
Fig. 4 is a schematic structural view of a first device region of the semiconductor chip of embodiment 2;
FIG. 5 is a photomicrograph of the gate electrode and the vicinity of the gate electrode of the semiconductor chip of example 2, showing the coverage of the gate electrode surface and the dielectric layer adjacent to the source and drain electrodes;
Fig. 6 is a schematic structural view of a first device region of the semiconductor chip of embodiment 3.
Detailed Description
The invention is further explained below with reference to the drawings and specific embodiments. The drawings of the present invention are merely schematic to facilitate understanding of the present invention, and specific proportions thereof may be adjusted according to design requirements. The definition of the context of the relative elements and the front/back of the figures described herein should be understood by those skilled in the art to refer to the relative positions of the elements and thus all the elements may be reversed to represent the same elements, which are all within the scope of the present disclosure.
Example 1
A method for manufacturing a semiconductor chip of embodiment 1, which integrates a pHEMT device, a capacitive device, and/or a resistive device, will be described below with reference to fig. 1a to 1f in conjunction with fig. 2. The semiconductor chip is integrated with a pHEMT device, a capacitor device, and a resistor device as follows. The semiconductor device can be applied to the field of radio frequency communication, and the semiconductor is integrated with a capacitor device, the capacitance value of the capacitor is of the pF magnitude, in the embodiment of the invention, the capacitance value range of the capacitor is 300-1000 pF, and the thickness range of a dielectric layer of the capacitor is 120-350 nm.
Referring to fig. 1a, a pHEMT epitaxial structure 1 is provided, and a conventional pHEMT epitaxial structure may be applied to the present embodiment, the materials of which include AlGaAs, inGaAs, inGaP, gaAs, gaN, alGaN and the like. For example, in connection with fig. 2, it comprises, from bottom to top, a GaAs substrate 11, a GaAs buffer layer 12, an AlGaAs spacer layer 13, an InGaAs channel layer 14, an AlGaAs spacer layer 15, an AlGaAs barrier layer 16, and an n-GaAs cap layer 17, wherein the thickness of the cap layer 17 is 40nm. The epitaxial structure may be formed by deposition processes including molecular beam epitaxy (molecular beam epitaxy; MBE), liquid phase epitaxy (liquid phase epitaxy; LPE), metal organic chemical vapor deposition (metal organic chemical vapor deposition; MOCVD), metal organic vapor phase epitaxy (metal organic vapor phase epitaxy; MOVPE), similar processes, or combinations of the foregoing. The epitaxial structure is a gallium arsenide-based pHEMT epitaxial structure and has double heterojunctions, so that the temperature stability of the threshold voltage of the device is improved, the output volt-ampere characteristic of the device is also improved, and the device has larger output resistance, higher transconductance, larger current processing capacity, higher working frequency and the like. The epitaxial structure 1 forms a first device region a through device isolation, the first device region a is an active device region, and a resistance structure region b and a capacitance structure region c are planned outside the first device region a. Source S and drain D are formed over the first device region a, and may each comprise Ti, al, W, au, pd, au, ge, ni, mo, pt, other suitable metals, alloys thereof, or combinations thereof, for example, using Au/Ge/Ni/Au metal stacks. The source electrode S and the drain electrode D form ohmic contacts with the cap layer 17, respectively.
Referring to fig. 1b, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process is used to cover the entire surface of the chip with the first dielectric layer 2 having a thickness of 10-100 nm. The first dielectric layer 2 is used as a passivation layer for protecting the source/drain electrodes, so that the source/drain electrodes are prevented from being subjected to electrochemical corrosion in the subsequent process, the ohmic contact resistance is increased, and the device characteristics are influenced, so that the thickness can be varied from 10nm to 100nm, the device performance and the cost relationship are balanced, the cost of the device is greatly increased when the thickness is greater than 100nm, and the device characteristics are possibly influenced when the thickness of the first dielectric layer 2 is less than 10nm in consideration of the capability of a machine and the process stability. The material of the first dielectric layer 2 may be silicon nitride, silicon oxide, silicon oxynitride or aluminum oxide, and in this embodiment, silicon nitride is used. In other embodiments, the first dielectric layer may also be blanket deposited by atomic layer deposition. Further, a resistive layer 3 is formed on the first dielectric layer 2 in the resistive structure region b, where the resistive layer 3 is, for example, taN, tiW, au, etc., and in this embodiment, taN materials are used to obtain a thin film resistive structure. Forming a patterned first metal layer on the first dielectric layer 2 through a metal process, wherein the first metal layer is respectively arranged on the source electrode S and the drain electrode D in the first device region a and is respectively contacted with the source electrode S and the drain electrode D through etching openings of the first dielectric layer 2 to serve as a first connecting line layer 41; in the resistor structure region b, the first metal layers are disposed at both ends of the resistor layer 3 as the first extraction layers 42; the first metal layer on the first dielectric layer 2 of the capacitive structure region c forms a capacitive lower plate 43. A metallic material of the first metallic layer such as Co, W, ru, al, mo, ti, cu, au, pt, a metallic alloy, other suitable conductive materials, or a combination thereof; in this example a Ti/Pt/Au/Ti stack is used.
Referring to fig. 1c, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process is used to deposit the second dielectric layer 5 with a thickness of 100-250 nm, and specifically, the second dielectric layer 5 may be a silicon nitride film. The second dielectric layer 5 is stacked on the first dielectric layer 2 between the source S and the drain D to form a dielectric layer stack.
Referring to fig. 1D, the dielectric stack layer between the source S and drain D is etched to form a first opening a, the bottom of which exposes the surface of the cap layer 17. The surface of the epitaxial structure 1 in the first opening A is etched to form a groove 18, the etching depth of the groove 18 is not less than the thickness of the cap layer 17, and the bottom of the groove 18 exposes the barrier layer 16. The width of the groove 18 (the span in the direction in which the source S and drain D are arranged) is smaller than the width of the first opening a. A gate G is formed in the groove 18, and the gate G may be a Y-type gate, a T-type gate, or the like, and the width of the gate root is smaller than the width of the groove 18. The gate G may be a metal layer such as Pt/Ti/Pt/Au/Ti, etc., forming a Schottky contact with the barrier layer 16.
Referring to fig. 1e, a third dielectric layer 6 is deposited by a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, the third dielectric layer 6 may be a silicon nitride film, and the third dielectric layer 6 covers the gate G and the vicinity thereof as a gate protection layer. Preferably, the thickness of the third dielectric layer 6 is 20-100 nm, so that the effect of protecting the gate and the parasitic capacitance effect can be considered, the deterioration of the noise characteristic of the device caused by the improvement of the parasitic capacitance can be avoided within the thickness range, the capability of a machine and the stability of the process can be met, and the good protecting effect is ensured. In a specific embodiment, the thickness of the third dielectric layer 6 may be 20nm, or 50nm, or 80nm, or 100nm.
Referring to fig. 1f, a patterned second metal layer is formed on the third dielectric layer 6 through a metal process, and in the first device region a, the second metal layer is respectively disposed on the first connection layer 41 and is respectively contacted with the first connection layer 41 through the etching openings of the second dielectric layer 5 and the third dielectric layer 6, so as to serve as a second connection layer 71; in the resistor structure region b, the second metal layers are respectively arranged on the first extraction layer 42 and respectively contacted with the first extraction layer 42 through etching openings of the second dielectric layer 5 and the third dielectric layer 6 to serve as a second extraction layer 72; in the capacitor structure region c, the second metal layer is located above the capacitor lower plate 43 to form the capacitor upper plate 73, and the second dielectric layer 5 and the third dielectric layer 6 stacked between the capacitor lower plate 43 and the capacitor upper plate 73 serve as capacitor dielectric layers. A metallic material of the second metallic layer such as Co, W, ru, al, mo, ti, cu, au, pt, a metallic alloy, other suitable conductive materials, or a combination thereof; in this example a Ti/Pt/Au/Ti stack is used.
The second metal layer forms an air bridge structure, the manufacturing method can adopt a photoresist as a support, a through hole area of Jin Shuyu photoresist and a part of the surface near the through hole area are deposited, and the photoresist is removed, so that the air bridge structure can be formed. The air bridge structure can reduce parasitic capacitance and improve the cut-off frequency of the device.
The resulting semiconductor chip has, as shown in fig. 1f and 2, an epitaxial structure 1 having a first device region a by device isolation, and a resistive structure region b and a capacitive structure region c located outside the first device region a, the first device region a being provided with a source S, a drain D and a gate G, and the gate G being located between the source S and the drain D. The epitaxial structure 1 is provided with a first dielectric layer 2, a second dielectric layer 5 and a third dielectric layer 6 in sequence. The first dielectric layer 2 covers the source S, drain D and epitaxial structure 1 surfaces. The source electrode S and the drain electrode D are respectively provided with a first connecting line layer 41 which penetrates through the first dielectric layer 2 and is contacted with the source electrode S and the drain electrode D; the resistor structure region b is provided with a resistor layer 4 on the first dielectric layer 2, and two ends of the resistor layer are provided with a first leading-out layer 42 contacted with the resistor layer; the capacitor structure area c is provided with a capacitor lower polar plate 43 on the first dielectric layer 2; the first wiring layer 41, the first extraction layer 42, and the capacitor lower plate 43 are arranged in the same layer by a patterned first metal layer. The second dielectric layer 5 covers the first dielectric layer 2 and the first metal layer. The first dielectric layer 2 and the second dielectric layer 5 between the source S and the drain D are stacked to have a first opening a, the surface of the epitaxial structure 1 in the first opening has a recess 18, and the gate G is provided in the recess 18. The third dielectric layer 6 covers the second dielectric layer 5 and the gate G surface and the first opening a surface. The first wiring layer 41 is provided with a second wiring layer 71 penetrating through the second dielectric layer 5 and the third dielectric layer 6 and contacting the first wiring layer 41, the first lead-out layer 42 is provided with a second lead-out layer 72 penetrating through the second dielectric layer 5 and the third dielectric layer 6 and contacting the first lead-out layer 42, the capacitor upper electrode plate 73 is arranged above the capacitor lower electrode plate 43, and the second dielectric layer 5 and the third dielectric layer 6 between the capacitor upper electrode plate 43 and the capacitor upper electrode plate 73 are laminated to be used as capacitor dielectric layers. The second wiring layer 71, the second extraction layer 72, and the capacitor upper plate 73 are arranged in the same layer by a patterned second metal layer. And the surface of the grid electrode G is only covered with the third dielectric layer 6 as a protective layer, and the first dielectric layer 2 and the second dielectric layer 5 are not covered, so that the thickness of the dielectric layer on the surface of the grid electrode G is reduced, and the parasitic capacitance of an active device is reduced.
Preferably, the density of the first dielectric layer 2 is less than the density of the third dielectric layer 6. The first dielectric layer 2, the second dielectric layer 5 and the third dielectric layer 6 are sequentially deposited on the epitaxial layer, and the porosity of each dielectric layer can be realized by adjusting the gas proportion and the flow rate during deposition and the deposition temperature. The first dielectric layer 2 is controlled to be loose, so that damage to the outer layer during deposition of the first dielectric layer 2 can be reduced; the third dielectric layer 6 is controlled to be denser, so that the influence of the subsequent thermal process on the device characteristics can be avoided, the deviation (such as Vt shift) of the device characteristics can be avoided, and the effect of protecting the grid electrode and the parasitic capacitance effect can be further considered. Preferably, the third dielectric layer 6 adopts a deposition temperature higher than that of the first dielectric layer 2, so that the deposited film layer is more compact and uniform, good protection effect is achieved on the grid electrode, and the failure problem caused by the hydrogen effect can be reduced when the concentration of hydrogen in the generated film is reduced. Preferably, the third dielectric layer 6 is deposited at a rate less than the first dielectric layer 2. In a specific implementation manner, the first dielectric layer 2, the second dielectric layer 5 and the third dielectric layer 6 may be formed by using the same material and different process conditions, and the three dielectric layers are analyzed by using a transmission electron microscope (english Transmission Electron Microscope, abbreviated as TEM), and the contrast of the third dielectric layer 6 is higher than that of the first dielectric layer 2 and the second dielectric layer 5 from the perspective of a bright field TEM photograph.
The deposition rate of the third dielectric layer 6 is smaller than that of the first dielectric layer 2, the deposition temperature of the third dielectric layer 6 is larger than that of the first dielectric layer 2, and the quality and uniformity of a dielectric film of the third dielectric layer 6 are higher, so that the formed third dielectric layer 6 is higher in density, device performance drift (starting voltage and source leakage current) is avoided, the bombardment energy of the epitaxial layer caused by the smaller deposition rate of the third dielectric layer 6 is controlled to be smaller, and the device performance is prevented from being reduced due to current damage caused by the bombardment of the epitaxial layer;
The obtained semiconductor chip can be used in a radio frequency module, wherein the pHEMT device is applied to a Low Noise Amplifier (LNA) in the radio frequency module, and parasitic capacitance of an active device is reduced through controlling the thickness of a silicon nitride film on the surface of a grid electrode of the pHEMT device in an integrated circuit process, so that noise coefficient of the amplifier is effectively reduced, and better performance is obtained. The radio frequency module is applied to the fields of base stations, radars, communication or remote sensing and the like.
Example 2
A method for manufacturing a semiconductor chip of embodiment 2, which integrates a pHEMT device, a capacitive device, and/or a resistive device, is described below with reference to fig. 3a to 3e and fig. 4. The following semiconductor chip is exemplified by a pHEMT device, a capacitive device, and a resistive device integrated therein.
PHEMT epitaxial structure 1 is provided. The epitaxial structure 1 forms a first device region a through device isolation, and a resistance structure region b and a capacitance structure region c are planned outside the first device region a. Source S and drain D are formed on the first device region a, with particular reference to fig. 1a and the associated discussion of fig. 1a for embodiment 1.
Referring to fig. 3a, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process is used to cover the entire surface of the chip with the first dielectric layer 2 having a thickness of 10-100 nm. A resistive layer 4 is formed on the first dielectric layer 2 in the resistive structure region b. The capacitor bottom plate 81 is formed on the first dielectric layer 2 in the capacitor structure region b, and the lead-out connection layers 82 are formed synchronously with the two ends of the resistor layer 3, the materials of the capacitor bottom plate 81 and the connection layers 82 are multi-layer metal lamination, such as Ti/Pt/Au/Ti, the second dielectric layer 5 is deposited entirely by adopting a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, and the thickness is 100-250 nm, so that the second dielectric layer 5 is overlapped on the first dielectric layer 2 between the source electrode S and the drain electrode D to form a dielectric layer lamination.
Referring to fig. 3b, the dielectric stack between the source S and drain D is etched to form a first opening a, the bottom of which exposes the surface of the cap layer 17. The surface of the epitaxial structure 1 within the first opening a is etched to form a recess 18. A gate G is formed in the recess 18.
Referring to fig. 3c, a third dielectric layer 6 is deposited using a Plasma Enhanced Chemical Vapor Deposition (PECVD) process over the entire surface, the third dielectric layer 6 covering the gate G and the vicinity thereof as a gate protection layer.
Referring to fig. 3D, a patterned first metal layer is formed through a metal process, and in the first device region a, the first metal layer is respectively disposed on the source S and the drain D and is respectively contacted with the source S and the drain D through the etched openings of the first dielectric layer 2, the second dielectric layer 5 and the third dielectric layer 6, so as to serve as a first connection layer 41; in the resistor structure region b, a first metal layer is arranged on the extraction connection layer 82, and penetrates through the first dielectric layer 2, the second dielectric layer 5 and the third dielectric layer 6 to be in contact with the extraction connection layer 82 so as to serve as a first extraction layer 42; in the capacitor structure region c, the first metal layer forms the capacitor top plate 44. The second dielectric layer 5 and the third dielectric layer 6 between the capacitor lower plate 81 and the capacitor upper plate 43 are stacked as capacitor dielectric layers.
Referring to fig. 3e, a patterned second metal layer is formed through a metal process, and in the first device region a, the second metal layer is respectively disposed on the first connection layer 41 as the second connection layer 71; in the resistive structure region b, the second metal layers are respectively disposed on the first extraction layers 42 as the second extraction layers 72; in the capacitor structure region c, a second metal layer is disposed on the capacitor top plate 44 as the capacitor connection layer 74. Also, the second metal layer forms an air bridge structure. Similar processes and structures are described with reference to embodiment 1, and are not repeated.
The resulting semiconductor chip has, as shown in fig. 3e and 4, an epitaxial structure 1 having a first device region a by device isolation, and a resistive structure region b and a capacitive structure region c located outside the first device region a, the first device region a being provided with a source S, a drain D and a gate G, and the gate G being located between the source S and the drain D. The epitaxial structure 1 is provided with a first dielectric layer 2, a second dielectric layer 5 and a third dielectric layer 6 in sequence. The first dielectric layer 2 covers the source S, drain D and epitaxial structure 1 surfaces. The resistor structure region b is provided with a resistor layer 4 on the first dielectric layer 2, and lead-out connection layers 82 located at both ends of the resistor layer 4. The capacitor structure area c is provided with a capacitor bottom plate 81 on the first dielectric layer 2. The second dielectric layer 5 covers the first dielectric layer 2, the resistive layer 4, the capacitor lower plate 81 and the extraction connection layer 82. The first dielectric layer 2 and the second dielectric layer 5 between the source S and the drain D are stacked to have a first opening a, the surface of the epitaxial structure 1 in the first opening has a recess 18, and the gate G is provided in the recess 18. The third dielectric layer 6 covers the second dielectric layer 5 and the gate G surface and the first opening a surface. The source electrode S and the drain electrode D are respectively provided with a first connecting line layer 41 which penetrates through the first dielectric layer 2, the second dielectric layer 5 and the third dielectric layer 6 and is contacted with the source electrode S and the drain electrode D; the first extraction layer 42 penetrating through the second dielectric layer 5 and the third dielectric layer 6 and contacting the extraction connection layer 82 is respectively arranged on the extraction connection layer 82; a capacitor upper polar plate 44 is arranged above the capacitor lower polar plate 81, and a second dielectric layer 5 and a third dielectric layer 6 between the capacitor lower polar plate 81 and the capacitor upper polar plate 44 are laminated to be used as a capacitor dielectric layer. The first wiring layer 41, the first extraction layer 42, and the capacitor upper plate 44 are arranged in the same layer by a patterned first metal layer. The first wiring layer 41 is provided with a second wiring layer 71, the first extraction layer 42 is provided with a second extraction layer 72, and the capacitor upper electrode plate 44 is provided with a capacitor wiring layer 74. The second wiring layer 71, the second extraction layer 72, and the capacitor wiring layer 74 are provided by patterning the second metal layer in the same layer. Referring to the photograph of fig. 5, the surface of the gate electrode G is covered with only the third dielectric layer 6 as a protective layer, which does not cover the first and second dielectric layers 2 and 5 with respect to the adjacent source and drain electrodes, reducing the dielectric layer thickness of the surface of the gate electrode G and also reducing the parasitic capacitance of the active device.
Example 3
The semiconductor chip of embodiment 3 may include only the pHEMT device, or the pHEMT device may be integrated with other components, such as a BiHEMT device, and the other components are not limited.
Referring to fig. 6, the semiconductor chip of embodiment 3 includes a source electrode S, a drain electrode D, and a gate electrode G on the epitaxial structure 1 thereof, and the gate electrode G is located between the source electrode S and the drain electrode D. The epitaxial structure 1 is provided with a first dielectric layer 2, a second dielectric layer 5, a third dielectric layer 6 and a top dielectric layer 9 in sequence. The first dielectric layer 2 covers the source S, drain D and epitaxial structure 1 surfaces. The source electrode S and the drain electrode D are respectively provided with a first connecting layer 4 which penetrates through the first dielectric layer 2 and is contacted with the source electrode S and the drain electrode D. The second dielectric layer 5 covers the first dielectric layer 2 and the first wiring layer 4. The first dielectric layer 2 and the second dielectric layer 5 between the source S and the drain D are stacked to have a first opening a, the surface of the epitaxial structure 1 in the first opening has a recess 18, and the gate G is provided in the recess 18. The third dielectric layer 6 covers the second dielectric layer 5 and the gate G surface and the first opening a surface. The top dielectric layer 9 covers the third dielectric layer 6. The top dielectric layer 9 may be silicon nitride, silicon oxide, silicon oxynitride or aluminum oxide, and has a thickness of 20-100 nm, and in this embodiment, silicon nitride is used, and has a thickness of 50nm. Therefore, the surface of the gate G is covered with the third dielectric layer 6 and the top dielectric layer 9, so that more flexible application is realized, and more requirements are met.
The method for manufacturing the semiconductor chip may refer to embodiment 1, and specifically includes:
forming a source electrode S and a drain electrode D on the pHEMT epitaxial structure 1;
the first dielectric layer 2 is covered on the whole surface of the chip by adopting a Plasma Enhanced Chemical Vapor Deposition (PECVD) process;
Forming a first metal layer on the first dielectric layer 2 through a metal process, wherein the first metal layer is respectively arranged on the source electrode S and the drain electrode D and is respectively contacted with the source electrode S and the drain electrode D through etching openings of the first dielectric layer 2 to serve as a first connecting layer;
Depositing a second dielectric layer 5 in an overall manner by adopting a Plasma Enhanced Chemical Vapor Deposition (PECVD) process;
Etching the dielectric laminated layer between the source electrode S and the drain electrode D to form a first opening A, etching the surface of the epitaxial structure 1 in the first opening A to form a groove 18, and forming a grid electrode G in the groove 18;
A third dielectric layer 6 is deposited in an integral mode by adopting a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, and the third dielectric layer 6 covers the grid G and the nearby area to serve as a grid protection layer;
The top dielectric layer 9 is deposited blanket by a Plasma Enhanced Chemical Vapor Deposition (PECVD) process.
In addition, in other embodiments, a top dielectric layer may be deposited on the surface of the structure formed in embodiments 1 and 2, so that the top dielectric layer covers the air bridge structure and the gate surface as a protection layer, where the gate portion and the surrounding dielectric layer cover the case referring to fig. 6.
Furthermore, in other embodiments, a plurality of first device regions may be provided on the semiconductor chip, each of the first device regions forming a gate of different width to form devices of different sizes, e.g., depletion/enhancement HEMT devices of 0.15 μm, 0.25 μm, 0.5 μm. Because the source and drain metal is protected by the dielectric layer during the gate fabrication, various devices can be integrated without affecting the device characteristics.
The above embodiments are only used to further illustrate a method for manufacturing a semiconductor chip, a semiconductor chip and applications thereof, but the invention is not limited to the embodiments, and any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the invention falls within the scope of the technical solution of the invention.
Claims (16)
1. A method of fabricating a semiconductor chip, comprising the steps of:
1) Forming a source electrode and a drain electrode on a first device region of the epitaxial structure;
2) Sequentially forming a first dielectric layer and a second dielectric layer, wherein the first dielectric layer and the second dielectric layer form a dielectric layer lamination on the surface of the epitaxial structure between the source electrode and the drain electrode;
3) Etching the dielectric laminated layer between the source electrode and the drain electrode to form a first opening;
4) Forming a gate on the epitaxial structure in the first opening;
5) Forming a third dielectric layer, wherein the third dielectric layer covers the surface of the gate as a protective layer; meanwhile, the second dielectric layer and the third dielectric layer are laminated on a capacitor structure area outside the first device area to serve as a capacitor dielectric layer;
Wherein, in the step after step 1), the method further comprises the step of forming a patterned first metal layer, wherein, in the first device region, the first metal layer is positioned on the source electrode and the drain electrode and is contacted with the source electrode and the drain electrode; and in the capacitor structure area, the first metal layer forms a capacitor plate.
2. The method of manufacturing a semiconductor chip according to claim 1, wherein: the first metal layer is formed between the steps of forming the first dielectric layer and the second dielectric layer in the step 2), and the first metal layer penetrates through the first dielectric layer in the first device region to be in contact with the source electrode and the drain electrode respectively; and in the capacitor structure area, the first metal layer forms a capacitor lower polar plate.
3. The method for manufacturing a semiconductor chip according to claim 2, further comprising:
6) Forming a patterned second metal layer, wherein the second metal layer penetrates through the second dielectric layer and the third dielectric layer respectively to be in contact with the first metal layer in the first device region and form an air bridge structure; and forming a capacitor upper polar plate on the capacitor structure area by the second metal layer.
4. The method for manufacturing a semiconductor chip according to claim 1, further comprising:
6) Forming a first metal layer, wherein the first metal layer penetrates through the first dielectric layer, the second dielectric layer and the third dielectric layer respectively and is in contact with the source electrode and the drain electrode in the first device region; forming a capacitor upper polar plate on the capacitor structure region by the first metal layer;
in the step 2), between the steps of forming the first dielectric layer and the second dielectric layer, a step of forming a capacitor bottom plate in the capacitor structure area is further included.
5. The method of manufacturing a semiconductor chip according to claim 4, further comprising:
7) Forming a patterned second metal layer, wherein the second metal layer is respectively contacted with the first metal layer in the first device region and forms an air bridge structure; in the capacitor structure region, the second metal layer is disposed on the first metal layer and contacts the first metal layer.
6. The method of manufacturing a semiconductor chip according to claim 1, wherein: the epitaxial structure is a pHEMT epitaxial structure or a HEMT epitaxial structure, and the top layer is a cap layer; in the step 4), a groove is formed on the surface of the epitaxial structure in the first opening, the etching depth of the groove is not smaller than the thickness of the cap layer, and the width of the groove is smaller than the width of the first opening; the grid electrode is arranged in the groove.
7. The method of manufacturing a semiconductor chip according to claim 1, wherein: after the step 5), the method further comprises a step of forming a top dielectric layer, wherein the top dielectric layer and the third dielectric layer form a protective layer lamination on the surface of the grid electrode.
8. The method of manufacturing a semiconductor chip according to claim 1, wherein: forming a resistor structure on a first dielectric layer outside the first device region, wherein the resistor structure comprises a resistor layer arranged on the first dielectric layer, and the first metal layer is arranged at two ends of the resistor layer to serve as outgoing lines; the resistor layer is formed between the first dielectric layer and the second dielectric layer, and the second dielectric layer and the third dielectric layer form a laminated layer which covers the resistor layer.
9. A semiconductor chip, characterized in that: the semiconductor device comprises an epitaxial structure, wherein the epitaxial structure is provided with a source electrode, a drain electrode, a grid electrode, a first dielectric layer, a second dielectric layer, a third dielectric layer and a patterned first metal layer; the epitaxial structure has a first device region on which a source and a drain are disposed, and a second device region on which:
The first dielectric layer and the second dielectric layer cover the source electrode and the drain electrode in sequence, a dielectric layer lamination is formed on the surface of the epitaxial structure between the source electrode and the drain electrode, the dielectric layer lamination between the source electrode and the drain electrode is provided with a first opening, the grid electrode is arranged on the epitaxial structure in the first opening, the third dielectric layer is arranged on the second dielectric layer and covers the exposed surface of the epitaxial structure and the surface of the grid electrode in the first opening, and the first metal layer is arranged on the source electrode and the drain electrode and is contacted with the source electrode and the drain electrode;
a capacitor structure is arranged on the first dielectric layer outside the first device region, and the capacitor structure region is:
The second dielectric layer and the third dielectric layer are stacked to be used as a capacitance dielectric layer, and the first metal layer is used as a capacitance polar plate.
10. The semiconductor chip of claim 9, wherein: the second metal layer is in contact with the first metal layer respectively and has an air bridge structure; the second metal layer is used as a capacitor plate or is in contact with the first metal layer on the capacitor structure area.
11. The semiconductor chip of claim 9, wherein: the resistor structure is arranged on the first dielectric layer outside the first device region, and the resistor structure is arranged in the resistor structure region:
the resistor comprises a resistor layer arranged on a first dielectric layer, and the first metal layer is arranged at two ends of the resistor layer to serve as outgoing lines.
12. The semiconductor chip according to claims 9 to 11, characterized in that: the gate electrode comprises a gate electrode, a third dielectric layer and a top dielectric layer, wherein the gate electrode is arranged on the surface of the gate electrode; the thickness of the top dielectric layer is 20-100 nm.
13. The semiconductor chip of claim 9, wherein: the thickness of the first dielectric layer is 10-100 nm; the thickness of the second dielectric layer is 100-250 nm; the thickness of the third dielectric layer is 20-100 nm.
14. A radio frequency module, characterized in that: a semiconductor chip comprising the semiconductor chip of any one of claims 10 to 13.
15. The radio frequency module of claim 14, wherein: the first device region is a HEMT device or a pHEMT device, and the HEMT device or the pHEMT device is used for a low noise amplifier in a radio frequency module.
16. The radio frequency module of claim 15 applied to a base station, radar, communication or remote sensing.
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