CN117953950A

CN117953950A - Method for simulating and testing performance of sense amplifier and electronic equipment

Info

Publication number: CN117953950A
Application number: CN202211282029.4A
Authority: CN
Inventors: 韩香云; 王元龙
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-10-19
Filing date: 2022-10-19
Publication date: 2024-04-30

Abstract

The disclosure provides a performance simulation test method of an induction amplifier and electronic equipment, wherein the simulation method comprises the following steps: determining at least one target memory cell to which a target bit line is connected and a first number of environmental memory cells adjacent to the at least one target memory cell; assigning values to the target storage unit and the environment storage unit according to at least one data map in a plurality of data maps; setting threshold voltages of transistors in a target sense amplifier connected to the target bit line according to a target threshold voltage parameter set, wherein the target threshold voltage parameter set is one of a plurality of threshold voltage parameter sets; and reading the target storage unit, and recording the current corresponding data map and the target threshold voltage parameter set of the target storage unit when the data is read out in error. The embodiment of the disclosure can measure the design parameters of the sense amplifier which optimize the read-write success rate of the memory.

Description

Method for simulating and testing performance of sense amplifier and electronic equipment

Technical Field

The disclosure relates to the technical field of integrated circuit testing, in particular to a performance simulation testing method of an induction amplifier and electronic equipment.

Background

The sense amplifier (SENSE AMPLIFIER, SA) is an important module in the memory to amplify the small voltage difference on the bit line to enable writing and reading of the memory cell. The minimum voltage difference that can be detected by the sense amplifier is called a sense margin (SENSE MARGIN, SM) of the sense amplifier, and the higher the read-write success rate of the sense amplifier with a larger sense margin.

In the manufacturing process of the memory, the manufacturing process can cause the sensing boundaries of different sensing amplifiers to float up and down based on the design value, and meanwhile, the fluctuation of voltages (such as power supply voltage, ground voltage and balanced voltage) in the circuit and the manufacturing process of the transistor (such as the threshold voltage of the transistor) can influence the sensing boundaries of different sensing amplifiers. In the related art, the same electrical parameters are generally set for the sense amplifiers of the same memory, which results in that the different sense amplifiers are not used, and in severe cases, partial memory cells may fail to read or write.

It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The disclosure aims to provide a performance simulation test method for a sense amplifier and electronic equipment, which are used for measuring optimal configuration parameters of different sense amplifiers so as to optimize the sense boundaries of the different sense amplifiers.

According to a first aspect of the present disclosure, there is provided a performance simulation test method of a sense amplifier, including: determining at least one target memory cell to which a target bit line is connected and a first number of environmental memory cells adjacent to the at least one target memory cell; assigning values to the target storage unit and the environment storage unit according to at least one data map in a plurality of data maps; setting threshold voltages of transistors in a target sense amplifier connected to the target bit line according to a target threshold voltage parameter set, wherein the target threshold voltage parameter set is one of a plurality of threshold voltage parameter sets; and reading the target storage unit, and recording the current corresponding data map and the target threshold voltage parameter set of the target storage unit when the data is read out in error.

In one exemplary embodiment of the present disclosure, the number of the target memory cells is a plurality, and the first number of the environmental memory cells includes memory cells connected to a preset value bit line closest to the target bit line.

In an exemplary embodiment of the present disclosure, the number of the target memory cells is one, and the first number of the environmental memory cells includes the memory cells of the target word line connection corresponding to the target memory cells.

In an exemplary embodiment of the disclosure, assigning the target storage unit and the environment storage unit according to one of a plurality of data maps includes: and writing a first value into the target storage unit and writing a second value into the environment storage unit.

In an exemplary embodiment of the disclosure, assigning the target storage unit and the environment storage unit according to one of a plurality of data maps includes: determining a target word line to which the target memory cell is connected; and writing a first value and a second value into the target memory cell and the environment memory cell which are connected with the same target word line at intervals according to the word line connection sequence.

In an exemplary embodiment of the present disclosure, the writing the first value and the second value at intervals in the word line connection order includes: and writing the first value and the second value into a plurality of groups of adjacent memory cells at intervals according to a word line connection sequence, wherein the plurality of groups of adjacent memory cells are arranged according to the word line connection sequence, and each group of adjacent memory cells comprises a second number of adjacent memory cells.

In one exemplary embodiment of the present disclosure, one threshold voltage parameter set includes: setting a threshold voltage of a first P-type transistor of the target sense amplifier to a first value; setting a threshold voltage of a second P-type transistor of the target sense amplifier to a second value; setting a threshold voltage of a first N-type transistor of the target sense amplifier to a third value; the threshold voltage of the second N-type transistor of the target sense amplifier is set to a fourth value.

In one exemplary embodiment of the present disclosure, the plurality of threshold voltage parameter sets includes at least the following threshold voltage parameter sets: a first set of threshold voltage parameters, the first value being greater than a first preset value, the second value being less than the first preset value, the third value being greater than a second preset value, the fourth value being less than the second preset value; a second set of threshold voltage parameters, the first value being greater than a first preset value, the second value being greater than the first preset value, the third value being less than a second preset value, the fourth value being less than the second preset value; a third set of threshold voltage parameters, the first value being less than a first preset value, the second value being greater than the first preset value, the third value being less than a second preset value, the fourth value being greater than the second preset value; a fourth set of threshold voltage parameters, the first value being less than a first preset value, the second value being less than the first preset value, the third value being greater than a second preset value, the fourth value being greater than the second preset value; a fifth set of threshold voltage parameters, the first value being greater than a first preset value, the second value being less than the first preset value, the third value being less than a second preset value, the fourth value being greater than the second preset value; a sixth set of threshold voltage parameters, the first value being less than a first preset value, the second value being greater than the first preset value, the third value being greater than a second preset value, and the fourth value being less than the second preset value.

In one exemplary embodiment of the present disclosure, the first value is equal to a first target value when the first value is greater than the first preset value, and the second value is equal to the first target value when the second value is greater than the first preset value; when the first value is smaller than the first preset value, the first value is equal to a second target value, and when the second value is smaller than the first preset value, the second value is equal to the second target value; when the third value is greater than the second preset value, the third value is equal to a third target value, and when the fourth value is greater than the second preset value, the fourth value is equal to the third target value; when the third value is smaller than the second preset value, the third value is equal to a fourth target value, and when the fourth value is smaller than the second preset value, the fourth value is equal to the fourth target value.

In one exemplary embodiment of the present disclosure, the setting the threshold voltage of each transistor in the target bit line connected target sense amplifier according to the target threshold voltage parameter set includes: and setting the threshold voltage of each transistor in the target sense amplifier to be the threshold voltage corresponding to the transistor in the target threshold voltage parameter set by setting the transistor parameters of each transistor in the target sense amplifier.

In one exemplary embodiment of the present disclosure, the transistor parameters include a channel length and a channel width.

In an exemplary embodiment of the present disclosure, further comprising: determining a reading result when the target sensing amplifier corresponds to each threshold voltage parameter set when the target storage unit and the environment storage unit correspond to one data map; determining a reading result when the target storage unit and the environment storage unit correspond to each data map and the target sensing amplifier corresponds to each threshold voltage parameter set; and determining target storage units and environment storage units corresponding to a plurality of target bit lines, wherein each target sense amplifier corresponds to a read result of each threshold voltage parameter set when corresponding to each data map.

According to a second aspect of the present disclosure, there is provided an electronic device comprising: a memory for storing codes; a processor for executing the code stored by the memory to implement the sense amplifier performance simulation test method as described in any one of the above.

According to the embodiment of the disclosure, the read-write performance of the target sense amplifier under different transistor threshold voltage setting schemes is tested under different storage data environments, so that an optimal transistor threshold voltage setting scheme for enabling the target sense amplifier to read successfully under different storage data environments can be obtained, manufacturing parameters of the sense amplifier are generated according to the optimal transistor threshold voltage setting scheme, and the performance of the sense amplifier is optimized.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort.

FIG. 1 is a flow chart of a method of simulating testing the performance of a sense amplifier in an exemplary embodiment of the disclosure.

Fig. 2 is a schematic circuit configuration diagram of a sense amplifier in an embodiment of the present disclosure.

Fig. 3A and 3B are schematic diagrams of target memory cells in an embodiment of the disclosure.

Fig. 4A to 4E are schematic diagrams of data maps in the embodiment of the present disclosure.

Fig. 5A to 5D are schematic diagrams of a threshold voltage setting scheme in an embodiment of the present disclosure.

Fig. 6A and 6B are the effects of different threshold voltage setting schemes under different test conditions, respectively.

Fig. 7 is a flow chart of a test method in another embodiment of the present disclosure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the present disclosure. One skilled in the relevant art will recognize, however, that the aspects of the disclosure may be practiced without one or more of the specific details, or with other methods, components, devices, steps, etc. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.

Furthermore, the drawings are only schematic illustrations of the present disclosure, in which the same reference numerals denote the same or similar parts, and thus a repetitive description thereof will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software or in one or more hardware modules or integrated circuits or in different networks and/or processor devices and/or microcontroller devices.

The following describes example embodiments of the present disclosure in detail with reference to the accompanying drawings.

Referring to fig. 1, a sense amplifier performance simulation test method 100 may include:

Step S1, determining at least one target storage unit connected with a target bit line and a first number of environment storage units adjacent to the at least one target storage unit;

Step S2, assigning values to the target storage unit and the environment storage unit according to at least one data map in a plurality of data maps;

Step S3, setting the threshold voltage of each transistor in a target sense amplifier connected with the target bit line according to a target threshold voltage parameter set, wherein the target threshold voltage parameter set is one threshold voltage parameter set in a plurality of threshold voltage parameter sets;

and S4, reading the target storage unit, and recording a data map and a target threshold voltage parameter set which are currently corresponding to the target storage unit when the data is read out in error.

In the embodiment shown in fig. 1, the target bit line refers to the currently detected bit line, the target memory cell refers to the memory cell to which the target bit line is connected, and the target sense amplifier refers to the sense amplifier to which the target bit line is connected, each sense amplifier includes four sense transistors including two P-type transistors and two N-type transistors, and the target threshold voltage parameter set includes the preset threshold voltages of the four sense transistors.

The purpose of the embodiments of the present disclosure is to obtain design parameters (channel length and channel width of each transistor in the sense amplifier) that optimize the performance of the sense amplifier, so each test of the embodiments of the present disclosure may test the sense amplifier design model by design software, and each operation shown in fig. 1 may be completed by the design software. In some embodiments, the design software may be configured to automatically complete testing of the target sense amplifier according to the flow shown in FIG. 1, and to automatically complete testing of all sense amplifiers in the memory.

Referring to fig. 2, a bit line BL connects a memory cell 21, a column selecting unit 22, an equalizing unit 23, and a sense amplifier 24.

The memory cell 21 includes a first transistor M1 and a storage capacitor C, where the first transistor M1 may be, for example, an N-type transistor, and the source of the first transistor M1 is connected to the storage capacitor C, the drain is connected to the bit line BL, and the gate is connected to the word line WL. A column selection unit 22, an equalization unit 23, and a sense amplifier 24 are sequentially provided on the bit line BL.

The column selecting unit 22 includes a second transistor M2, the second transistor M2 being an N-type transistor, a source connected to a Local Input/Output signal line LIO (Local Input/Output), a drain connected to a bit line BL, and a gate connected to a column selecting signal line YS (Y Select), or called a column selecting signal line CSL (Column Select). The column selection signal line YS is used for controlling data on the bit line BL to be transferred to the local input/output signal line LIO to complete data reading or data on the local input/output signal line LIO to be transferred to the bit line BL to complete data writing.

The equalizing unit 23 includes a third transistor M3, a fourth transistor M2, and a fifth transistor M5, where the third transistor M3, the fourth transistor M2, and the fifth transistor M5 are all N-type transistors, and gates of the third transistor M3, the fourth transistor M2, and the fifth transistor M5 are all connected to the bit line equalizing signal VEQ (Voltage of Equalizer). The source of the third transistor M3 and the drain of the fourth transistor M2 are both connected to the Bit line precharge Voltage VBLP (Voltage of Bit LINE PRECHARGE), the drain of the third transistor M3 is connected to the Bit line BL, and the source of the fourth transistor M2 is connected to the complementary Bit line/BL.

The sense amplifier 24 is a differential amplifier having two input terminals connected to the bit line BL and the complementary bit line/BL, respectively, for amplifying a voltage difference between the bit line BL and the complementary bit line/BL. The sense amplifier 24 includes a first N-type transistor MN1, a second N-type transistor MN2, a first P-type transistor MP1, and a second P-type transistor MP2 (the target threshold voltage parameter set includes the threshold voltages of these four transistors). The first N-type transistor MN1 and the second N-type transistor MN2 are both N-type transistors, and the first P-type transistor MP1 and the second P-type transistor MP2 are both P-type transistors. One end of the first N-type transistor MN1 is connected with the bit line BL through the first node N1, the other end of the first N-type transistor MN1 is connected with the low-potential node NCS, the low-potential node NCS is connected with the second voltage Vss, and the control end of the first N-type transistor MN1 is connected with the complementary bit line/BL. One end of the second N-type transistor MN2 is connected with the complementary bit line/BL through a second node N2, the other end of the second N-type transistor MN2 is connected with the low potential node NCS, and the control end of the second N-type transistor MN2 is connected with the bit line BL. One end of the first P-type transistor MP1 is connected with the bit line BL through the first node N1, the other end of the first P-type transistor MP1 is connected with the high-potential node PCS, the high-potential node PCS is connected with the second voltage Vary, and the control end of the first P-type transistor MP1 is connected with the complementary bit line/BL. One end of the second P-type transistor MP2 is connected with the complementary bit line/BL through a second node N2, the other end of the second P-type transistor MP2 is connected with the high-potential node PCS, and the control end of the second P-type transistor MP2 is connected with the bit line BL.

The embodiments of the present disclosure may be applied to testing various types of sense amplifiers, including but not limited to the sense amplifier shown in fig. 2 including only four sense transistors, NCSA (Noise CANCEL SENSE AMPLIFIER) including four sense transistors and NC (Noise Cancel) transistors, or sense amplifiers including other transistors as well.

The steps shown in method 100 are described in detail below.

Step S1, at least one target storage unit connected with a target bit line and a first number of environment storage units adjacent to the at least one target storage unit are determined.

In fig. 3A and 3B, the memory array includes a plurality of bit lines BL0 to BL7 arranged in parallel in a first direction, and a plurality of word lines WL0 to WL3 arranged in parallel in a second direction, the first direction being perpendicular to the second direction. The memory array further includes a plurality of memory cells 300, each memory cell 300 being connected to a word line and a bit line, respectively, the word lines and bit lines to which different memory cells 300 are connected not being identical. Let the target bit line of the current operation be BL4.

Referring to fig. 3A, in one embodiment of the present disclosure, the number of target memory cells 31 is plural, and the first number of environmental memory cells 32 includes memory cells connected to a predetermined value bit line closest to the target bit line BL 4. In the embodiment shown in FIG. 3A, the preset value is, for example, 6, i.e., three bit lines BL 0-BL 3 to the left of the target bit line BL4, and three bit lines BL 5-BL 7 to the right of the target bit line BL 4.

In practical applications, the preset value may be determined according to the specific number and arrangement of the bit lines, for example, the preset value is set to 72, that is, the memory cells connected to 72 bit lines (36 bit lines on the left and right of the target bit line) closest to the target bit line are set as the environmental memory cells.

The number and the position of the environmental memory cells on each bit line may correspond to the number and the position of the target memory cells on the target bit line. For example, if three memory cells connected to three word lines WL1, WL2, and WL3 are provided as target memory cells on the target bit line, 3×6=18 memory cells connected to three word lines WL1, WL2, and WL3 on each of the three bit lines (6 bit lines in total) on the left and right of the target bit line may be provided as environmental memory cells. If all the memory cells connected to the target bit line are set as target memory cells, all the memory cells connected to the left and right bit lines of the target bit line may be set as ambient memory cells.

The environmental memory cells determined in the embodiment shown in fig. 3A may be used to set the voltage-affected environment of each target memory cell by other adjacent memory cells connected to the same word line.

Referring to fig. 3B, in another embodiment, the number of target memory cells 31 is one, and the first number of ambient memory cells 32 includes memory cells connected by the target word line WL3 corresponding to the target memory cells 31.

The embodiment shown in fig. 3B can test the sensing performance of the target sense amplifier connected to the target bit line BL4 under the condition that the target memory cell 31 is affected by the voltage variation of the target word line WL3, and so on under the condition that the target sense amplifier is affected by the voltage variation of each word line.

And S2, assigning values to the target storage unit and the environment storage unit according to at least one data map in the plurality of data maps.

The data pattern (topo) refers to writing a plurality of memory cells according to preset memory data, so that the memory cells storing the same data in the memory array form a preset pattern, such as a stripe pattern (the memory cells with the same value in the memory array are arranged in stripes), a checkerboard pattern (the memory cells with the same value in the memory array are arranged in checkerboard), a dot pattern, and the like. The data map may be used to set the storage states of one or more target memory cells and the storage states of adjacent ambient memory cells, thereby constructing different ambient voltage environments for the target memory cells.

In the embodiment of the disclosure, when selecting the data map, it is first required to determine a target storage state of a target storage unit, that is, a currently tested sense amplifying state of a target sense amplifier corresponding to a target bit line connected to the target storage unit. Each target sense amplifier corresponds to two sense amplifying states, namely sense amplifying 1 and sense amplifying 0, and the test of one target sense amplifier at least comprises the test of sense amplifying 1 and the test of sense amplifying 0.

And if the current tested sense amplification state is the sense amplification 1, the target storage state of the target storage unit is the storage data 1, and the data map of the corresponding storage data 1 of the target storage unit is selected from the data maps. If the current tested sense amplification state is sense amplification 0, the target storage state of the target storage unit is stored data 0, and a data map of the target storage unit corresponding to the stored data 0 is selected from the data maps.

The values stored in the target memory cells are the same, e.g., 1 or 0, regardless of whether the target memory cells are one or more, because the target memory cells are each connected to a target bit line and a target sense amplifier, one sense amplified state for each test of the target sense amplifier.

Referring to fig. 4A, in order to form different voltage-influencing environments for the target bit line, in one embodiment of the present disclosure, step S2 may include writing a first value a to the target memory cell and writing a second value B to the surrounding memory cell. Wherein the first value a may be 1 and the second value B may be 0; or the first value a may be 0 and the second value B may be 1. By writing different values into the target memory cell and the environment memory cell, a test environment with different voltages between the target bit line and the adjacent bit line with preset values can be formed, namely, a test environment with different sensing states between the target sense amplifier and the sense amplifier corresponding to the adjacent bit line with preset values is formed.

The target storage state of the corresponding target storage unit above fig. 4A is to store the first value a, and the target storage state of the corresponding target storage unit below fig. 4A is to store the second value B.

In another embodiment, step S2 may further determine the target word line connected to the target memory cell first, and then write the first value a and the second value B to the target memory cell and the environmental memory cell connected to the same target word line at intervals according to the word line connection sequence. Wherein the first value a may be 1 and the second value B may be 0; or the first value a may be 0 and the second value B may be 1.

Referring to fig. 4B, when the first value 1 and the second value 0 are written to the target memory cell 41 and the environmental memory cell 42 connected to the same target word line WLT at intervals in the word line connection order, the write operation may be performed to the target memory cell 41 and the environmental memory cell 42 at one-to-one intervals.

The target storage state of the corresponding target storage unit above fig. 4B is to store the first value a, and the target storage state of the corresponding target storage unit below fig. 4B is to store the second value B.

Referring to fig. 4C, in the target memory cell 41 and the environmental memory cell 42 connected to the same target word line WLT, the first value 1 and the second value 0 may be written at intervals in the word line connection order, and the first value and the second value may be written at intervals to a plurality of sets of adjacent memory cells arranged in the word line connection order, each set of adjacent memory cells including a second number of adjacent memory cells. In the embodiment shown in fig. 4C, the second number is equal to 3.

The target storage state of the corresponding target storage unit above fig. 4C is to store the first value a, and the target storage state of the corresponding target storage unit below fig. 4C is to store the second value B.

Fig. 4A, 4B, and 4C show only one data pattern corresponding to one target storage unit, and when there are a plurality of target storage units, each target storage unit may correspond to one data pattern. The data patterns corresponding to different target storage units can be the same or different, and the data patterns commonly corresponding to a plurality of target storage units are two-dimensional data patterns comprising a first direction pattern and a second direction pattern.

Referring to fig. 4D and 4E, when there are a plurality of target memory cells, the plurality of target memory cells correspond to the same data map, and actually constitute a two-dimensional data map.

The data patterns corresponding to fig. 4A to 4E are only examples, and a person skilled in the art can adjust the data patterns according to the arrangement density of the memory cells, the power supply voltage, and other factors.

The assignment of memory cells may be performed using conventional recursive writing methods, such as writing to memory cells on one bit line at a time. Since writing to memory cells to assign values to each memory cell belongs to a conventional operation, the description thereof will not be repeated.

And S3, setting the threshold voltage of each transistor in the target sense amplifier connected with the target bit line according to a target threshold voltage parameter set, wherein the target threshold voltage parameter set is one threshold voltage parameter set in a plurality of threshold voltage parameter sets.

After the assignment of the value to each memory cell is completed, the memory data of the target memory cell and the memory state of the environmental memory cell are set, the voltage influence environment of each bit line and each memory cell on the target bit line is formed, and the sense amplifying state of the target sense amplifier connected with the target bit line is determined. At this time, the performance test of the target sense amplifier may be performed under the determined sense amplification state and voltage influence environment.

As can be seen from fig. 2, the target sense amplifier mainly includes four sense transistors, namely, a first P-type transistor MP1, a second P-type transistor MP2, a first N-type transistor MN1, and a second N-type transistor MN2. Next, the threshold voltages of the four sense transistors may be set in accordance with the set of target threshold voltage parameters.

Since the embodiments of the present disclosure aim to obtain design parameters that optimize the performance of the sense amplifier, various tests of the embodiments of the present disclosure can test the sense amplifier design model through design software. At this time, in one embodiment of the present disclosure, the threshold voltage of each transistor may be set to the threshold voltage corresponding to the transistor in the target threshold voltage parameter set by setting the transistor parameters of the transistors in the target sense amplifier. The transistor parameters include, for example, a channel length L and a channel width W.

By adjusting the channel length L and channel width W of each sense transistor in the design software, the threshold voltage of each transistor of the sense amplifier can be set to a value in the set of target threshold voltage parameters.

For a set of sense amplifying states and voltage influencing environments, multiple tests can be performed on the target sense amplifier, each test corresponds to a set of threshold voltage parameter sets, and the threshold voltage parameter set corresponding to the current test is called a target threshold voltage parameter set.

In one exemplary embodiment of the present disclosure, each set of threshold voltage parameters includes four values. One set of threshold voltage parameters may include: the threshold voltage of the first P-type transistor MP1 of the target sense amplifier is a first value (e.g., recorded as VthMP 1=a1); the threshold voltage of the second P-type transistor MP2 of the target sense amplifier is a second value (e.g., noted VthMP 2=a2); the threshold voltage of the first N-type transistor MN1 of the target sense amplifier is a third value (e.g., noted VthMN 1=a3); the threshold voltage of the second N-type transistor MN2 of the target sense amplifier is a fourth value (e.g., noted VthMN 2=a4).

In the different threshold voltage parameter sets, the first values are not necessarily the same, the second values are not necessarily the same, the third values are not necessarily the same, and the fourth values are not necessarily the same. Furthermore, the four values in the different sets of threshold voltage parameters are not exactly the same.

In order to accurately test the threshold voltage setting scheme with the optimal reading effect, and further obtain the design value of the process parameter of each transistor, in the embodiment of the disclosure, a plurality of selectable threshold voltage values may be calculated in advance, and a plurality of threshold voltage parameter sets may be formed based on the threshold voltage values, so that the test is performed according to the plurality of threshold voltage parameter sets, and the threshold voltage parameter sets capable of enabling the sense amplifier to successfully read data in a plurality of test environments are measured.

In one exemplary embodiment of the present disclosure, the plurality of threshold voltage parameter sets includes at least the following threshold voltage parameter sets:

The first threshold voltage parameter set has a first value greater than a first preset value Vth1, a second value less than the first preset value Vth1, a third value greater than a second preset value Vth2, and a fourth value less than the second preset value Vth2;

the second threshold voltage parameter set, the first value is greater than the first preset value Vth1, the second value is greater than the first preset value Vth1, the third value is less than the second preset value Vth2, and the fourth value is less than the second preset value Vth2;

the third threshold voltage parameter set, the first value is smaller than the first preset value Vth1, the second value is larger than the first preset value Vth1, the third value is smaller than the second preset value Vth2, and the fourth value is larger than the second preset value Vth2;

a fourth set of threshold voltage parameters, the first value being less than a first preset value Vth1, the second value being less than the first preset value Vth1, the third value being greater than a second preset value Vth2, the fourth value being greater than the second preset value Vth2;

A fifth set of threshold voltage parameters, the first value being greater than a first preset value Vth1, the second value being less than the first preset value Vth1, the third value being less than a second preset value Vth2, the fourth value being greater than the second preset value Vth2;

The sixth threshold voltage parameter set has a first value less than a first preset value Vth1, a second value greater than the first preset value Vth1, a third value greater than a second preset value Vth2, and a fourth value less than the second preset value Vth2.

The first preset value Vth1 corresponds to the threshold voltage of the P-type transistor, and the second preset value Vth2 corresponds to the threshold voltage of the N-type transistor, and is used for measuring the threshold voltage.

For example, in the setting corresponding to the first threshold voltage parameter set, the threshold voltage of the first P-type transistor MP1 is higher, the threshold voltage of the second P-type transistor MP1 is lower, the threshold voltage of the first N-type transistor MN1 is higher, and the threshold voltage of the second N-type transistor MN2 is lower. Other threshold voltage parameter sets are the same.

In the different threshold voltage parameter sets, even if the same threshold voltage is higher (for example, the first values are all greater than the first preset value Vth 1), the corresponding threshold voltage values may still be different. In order to improve the test efficiency, two sets of data including a plurality of different values may be preset, the first set of data including one or more values greater than the first preset value Vth1 and one or more values less than the first preset value Vth1, and the second set of data including one or more values greater than the second preset value Vth2 and one or more values less than the second preset value Vth 2.

And then respectively selecting two values from the first group of data and the second group of data, and generating six threshold voltage parameter sets according to the value-taking logic of the first threshold voltage parameter set to the sixth threshold voltage parameter set until the permutation and combination of the values are exhausted.

It is assumed that the first set of data may comprise only two values: the first target value VthPH that is greater than the first preset value Vth1 and the second target value VthPL that is less than the first preset value Vth1, the second set of data may include only two values: a third target value VthNH that is greater than the second preset value Vth2 and VthNL that is less than the second preset value Vth 2.

In forming the threshold voltage parameter sets, for example, the first to sixth threshold voltage parameter sets, the first and second values larger than the first preset value Vth1 may be set to the first target value VthPH, the first and second values smaller than the first preset value Vth1 may be set to the second target value VthPL, the third and fourth values larger than the second preset value Vth2 may be set to the third target value VthNH, and the third and fourth values smaller than the second preset value Vth2 may be set to the fourth target value VthNL.

That is, when the first value is greater than the first preset value Vth1, the first value is equal to the first target value VthPH, and when the second value is greater than the first preset value Vth1, the second value is equal to the first target value VthPH; when the first value is less than the first preset value Vth1, the first value is equal to the second target value VthPL, and when the second value is less than the first preset value Vth1, the second value is equal to the second target value VthPL; when the third value is greater than the second preset value Vth2, the third value is equal to the third target value VthNH, and when the fourth value is greater than the second preset value Vth2, the fourth value is equal to the third target value VthNH; when the third value is less than the second preset value Vth2, the third value is equal to the fourth target value VthNL, and when the fourth value is less than the second preset value Vth2, the fourth value is equal to the fourth target value VthNL.

Since each sense transistor corresponds to two voltage states (greater than or less than the threshold voltage), a total of four sense transistors, the present embodiment can generate 2 ⁴ =16 threshold voltage setting schemes.

In actual testing, however, both the first set of data and the second set of data need to include multiple values for testing, since the optimal threshold voltage setting scheme is not known. According to the above embodiment, if the first set of data includes x data and the second set of data includes y data, x×y sets of data may be formed, each set of data may form 16 threshold voltage setting schemes, and x×y×16 threshold voltage setting combinations may be formed in total, where x and y are both natural numbers.

The principle will be described below with reference to the case where the first set of data and the second set of data each comprise one data. Other threshold voltage setting schemes can be deduced according to the following principles, and will not be described in detail in this disclosure.

Referring to fig. 5A, when the third value is equal to VthNH and the fourth value is equal to VthNL, four threshold voltage setting schemes may be generated, the first and second values being (vtthpl, vtthph), (vtthph, vtthpl), (vtthph ), (vtthpl, vtthpl), respectively.

Referring to fig. 5B, also, when the third value is equal to VthNH and the fourth value is equal to VthNH, four threshold voltage setting schemes may be generated, the first and second values being (vtthpl, vtthph), (vtthph, vtthpl), (vtthph ), (vtthpl, vtthpl), respectively.

Referring to fig. 5C, also, when the third value is equal to VthNL and the fourth value is equal to VthNH, four threshold voltage setting schemes may be generated, the first and second values being (vtthpl, vtthph), (vtthph, vtthpl), (vtthph ), (vtthpl, vtthpl), respectively.

Referring to fig. 5D, also, when the third value is equal to VthNL and the fourth value is equal to VthNL, four threshold voltage setting schemes may be generated, the first and second values being (vtthpl, vtthph), (vtthph, vtthpl), (vtthph ), (vtthpl, vtthpl), respectively.

The 16 threshold voltage setting schemes of fig. 5A to 5D are obtained assuming that the above-described first and second sets of data each include only two values, and if more than two values are set in each of the first and second sets of data, more sets of threshold voltage setting schemes may be generated.

Different threshold voltage setting schemes may correspond to different test conditions (a set of sense amp states and voltage influencing environments).

Referring to fig. 6A, the target memory cell is written with 0.

The ability to sense 0 is worst (Sense Worst) when the first, second, third, and fourth values of the target sense amplifier are (VthPL, vthPH, vthNH, vthNL) respectively, i.e., correspond to the sixth set of threshold voltage setting schemes.

The ability to Sense 0 is optimal (Sense Best) when the first, second, third, and fourth values of the target Sense amplifier are (VthPH, vthPL, vthNL, vthNH) respectively, i.e., correspond to the fifth set of threshold voltage setting schemes.

The offset cancellation capability of the sense amplifier is worst (Offset Cancel Worst) when the first, second, third, and fourth values of the target sense amplifier are (VthPH, vthPH, vthNL, vthNL) respectively, i.e., correspond to the second set of threshold voltage setting schemes.

The offset cancellation capability of the sense amplifier is optimized (Offset Cancel Best) when the first, second, third, and fourth values of the target sense amplifier are (VthPL, vthPL, vthNH, vthNH) respectively, i.e., correspond to the fourth set of threshold voltage setting schemes.

When the first value, the second value, the third value, and the fourth value of the target sense amplifier are (VthPH, vthPL, vthNH, vthNL) respectively, that is, correspond to the first set of threshold voltage setting schemes, the ability of the N-type transistor in the sense amplifier to sense 0 is the worst, and the ability of the P-type transistor to sense 0 is the best, such a setting scheme may be referred to as a mixed environment (Sense Worst Mix) that is unfavorable to sense 0.

When the first value, the second value, the third value, and the fourth value of the target Sense amplifier are (VthPL, vthPH, vthNL, vthNH) respectively, that is, correspond to the third set of threshold voltage setting schemes, the N-type transistor of the Sense amplifier has the Best ability to Sense 0, and the P-type transistor has the worst ability to Sense 0, and such setting scheme may be referred to as a mixed environment (Sense Best Mix) that is advantageous to Sense 0.

Referring to fig. 6B, the target memory cell is written to 1.

The ability to sense 1 is worst (Sense Worst) when the first, second, third, and fourth values of the target sense amplifier are (VthPH, vthPL, vthNL, vthNH) respectively, i.e., correspond to the fifth set of threshold voltage setting schemes.

The ability to Sense 1 is optimal (Sense Best) when the first, second, third, and fourth values of the target Sense amplifier are (VthPL, vthPH, vthNH, vthNL) respectively, i.e., correspond to the sixth set of threshold voltage setting schemes.

The offset cancellation capability of the sense amplifier is worst (Offset Cancel Worst) when the first, second, third, and fourth values of the target sense amplifier are (VthPL, vthPL, vthNH, vthNH) respectively, i.e., correspond to the fourth set of threshold voltage setting schemes.

The offset cancellation capability of the sense amplifier is optimized (Offset Cancel Best) when the first, second, third, and fourth values of the target sense amplifier are (VthPH, vthPH, vthNL, vthNL) respectively, i.e., correspond to the second set of threshold voltage setting schemes.

When the first value, the second value, the third value, and the fourth value of the target sense amplifier are (VthPL, vthPH, vthNL, vthNH) respectively, that is, correspond to the third set of threshold voltage setting schemes, the ability of the N-type transistor in the sense amplifier to sense 1 is the worst, and the ability of the P-type transistor to sense 0 is the best, such a setting scheme may be referred to as a mixed environment (Sense Worst Mix) that is unfavorable to sense 1.

When the first value, the second value, the third value, and the fourth value of the target Sense amplifier are (VthPH, vthPL, vthNH, vthNL) respectively, that is, correspond to the first set of threshold voltage setting schemes, the ability of the N-type transistor of the Sense amplifier to Sense 1 is optimal, the ability of the P-type transistor to Sense 1 is worst, and such setting schemes may be referred to as a Sense Best Mix (Sense Best Mix) that is advantageous for Sense 1.

Therefore, for a set of test conditions (a set of sense amplifying states and voltage influencing environments) of the target sense amplifier, several threshold voltage setting schemes may be selected for testing respectively, and if necessary, all threshold voltage setting schemes may be selected for testing respectively.

After the threshold voltages of the transistors of the target sense amplifier are set according to the target threshold voltage setting scheme, a read test can be performed.

And S4, reading the target storage unit, and recording the current corresponding data map and the target threshold voltage parameter set of the target storage unit when the data is read out in error.

Under a set of sensing amplification state, voltage influence environment and target threshold voltage setting scheme, if the sensing capability of the target sensing amplifier is poor at the moment, the sensing amplification state, the voltage influence environment (corresponding to a test map) and the target threshold voltage parameter set can be recorded, so that whether the target sensing amplifier is rejected or not can be determined later when the optimal threshold voltage setting scheme is selected.

Referring to fig. 7, in an exemplary embodiment of the present disclosure, the test method 100 further includes:

Step S71, when a data map corresponding to the target storage unit and the environment storage unit is determined, a reading result corresponding to each threshold voltage parameter set by the target sense amplifier is determined;

step S72, when the target storage unit and the environment storage unit correspond to each data map, a reading result when the target sense amplifier corresponds to each threshold voltage parameter group is determined;

In step S73, the target memory cells and the environment memory cells corresponding to the plurality of target bit lines are determined, and when each data map is corresponding to each data map, each target sense amplifier corresponds to the read result of each threshold voltage parameter set.

After the target memory cell is read and tested for the selected multiple threshold voltage setting schemes under the sense amplifying state and voltage influencing environment (step S71), the sense amplifying state and the voltage influencing environment (data pattern) may be replaced, and the read and test for the selected multiple threshold voltage setting schemes may be continued until all the tests for the selected data pattern are completed (step S72). Next, the target bit line is replaced, and the test as in step S71 and step S72 is performed for each bit line (step S73), so that the test of the memory array to be tested is completed.

And finally, selecting the optimal threshold voltage parameter set for all the sense amplifiers in the memory array to be tested according to a plurality of read results corresponding to each threshold voltage parameter set, namely the number of times of data reading errors.

In some embodiments, the set of threshold voltage parameters that minimizes the number of read errors may be selected to be the optimal set of threshold voltage parameters; in other embodiments, the set of threshold voltage parameters with the least number of read errors corresponding to the data patterns with high occurrence frequency may be set as the optimal set of threshold voltage parameters according to the possible occurrence frequency of the different data patterns.

The optimal set of threshold voltage parameters and their corresponding transistor parameters (channel width W, channel length L) may be provided to the process sector as design parameters in the fabrication of the sense amplifier.

According to a second aspect of the present disclosure, there is provided an electronic device comprising: a memory for storing codes; and a processor for executing the codes stored in the memory to implement the sense amplifier performance simulation test method according to any of the above embodiments.

In summary, according to the embodiment of the disclosure, the plurality of sense amplifiers are tested under the plurality of data patterns and the plurality of threshold voltage parameter sets, so that the threshold voltage parameter set with the optimal sense amplifying capability can be obtained, and the manufactured sense amplifier has the optimal sense amplifying performance.

It should be noted that although in the above detailed description several modules or units of a device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit in accordance with embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into a plurality of modules or units to be embodied.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A method for simulating performance of an induction amplifier, comprising:

Determining at least one target memory cell to which a target bit line is connected and a first number of environmental memory cells adjacent to the at least one target memory cell;

assigning values to the target storage unit and the environment storage unit according to at least one data map in a plurality of data maps;

setting threshold voltages of transistors in a target sense amplifier connected to the target bit line according to a target threshold voltage parameter set, wherein the target threshold voltage parameter set is one of a plurality of threshold voltage parameter sets;

And reading the target storage unit, and recording the current corresponding data map and the target threshold voltage parameter set of the target storage unit when the data is read out in error.

2. The method of testing of claim 1, wherein the number of target memory cells is a plurality, and the first number of environmental memory cells includes memory cells connected to a bit line of a predetermined value that is closest to the target bit line.

3. The test method of claim 1, wherein the number of target memory cells is one, and the first number of environmental memory cells includes the memory cell to which the target word line corresponding to the target memory cell is connected.

4. The method of testing of claim 1, wherein assigning the target storage unit and the environmental storage unit according to one of a plurality of data patterns comprises:

And writing a first value into the target storage unit and writing a second value into the environment storage unit.

5. The method of testing of claim 1, wherein assigning the target storage unit and the environmental storage unit according to one of a plurality of data patterns comprises:

Determining a target word line to which the target memory cell is connected;

And writing a first value and a second value into the target memory cell and the environment memory cell which are connected with the same target word line at intervals according to the word line connection sequence.

6. The method of testing of claim 5, wherein the writing the first value and the second value at intervals in the word line connection order comprises:

and writing the first value and the second value into a plurality of groups of adjacent memory cells at intervals according to a word line connection sequence, wherein the plurality of groups of adjacent memory cells are arranged according to the word line connection sequence, and each group of adjacent memory cells comprises a second number of adjacent memory cells.

7. The test method of claim 1, wherein a set of threshold voltage parameters comprises:

setting a threshold voltage of a first P-type transistor of the target sense amplifier to a first value;

setting a threshold voltage of a second P-type transistor of the target sense amplifier to a second value;

Setting a threshold voltage of a first N-type transistor of the target sense amplifier to a third value;

The threshold voltage of the second N-type transistor of the target sense amplifier is set to a fourth value.

8. The test method of claim 7, wherein the plurality of sets of threshold voltage parameters includes at least the following sets of threshold voltage parameters:

a first set of threshold voltage parameters, the first value being greater than a first preset value, the second value being less than the first preset value, the third value being greater than a second preset value, the fourth value being less than the second preset value;

A second set of threshold voltage parameters, the first value being greater than a first preset value, the second value being greater than the first preset value, the third value being less than a second preset value, the fourth value being less than the second preset value;

A third set of threshold voltage parameters, the first value being less than a first preset value, the second value being greater than the first preset value, the third value being less than a second preset value, the fourth value being greater than the second preset value;

a fourth set of threshold voltage parameters, the first value being less than a first preset value, the second value being less than the first preset value, the third value being greater than a second preset value, the fourth value being greater than the second preset value;

a fifth set of threshold voltage parameters, the first value being greater than a first preset value, the second value being less than the first preset value, the third value being less than a second preset value, the fourth value being greater than the second preset value;

a sixth set of threshold voltage parameters, the first value being less than a first preset value, the second value being greater than the first preset value, the third value being greater than a second preset value, and the fourth value being less than the second preset value.

9. The test method of claim 8, wherein the first value is equal to a first target value when the first value is greater than the first preset value, and wherein the second value is equal to the first target value when the second value is greater than the first preset value; when the first value is smaller than the first preset value, the first value is equal to a second target value, and when the second value is smaller than the first preset value, the second value is equal to the second target value; when the third value is greater than the second preset value, the third value is equal to a third target value, and when the fourth value is greater than the second preset value, the fourth value is equal to the third target value; when the third value is smaller than the second preset value, the third value is equal to a fourth target value, and when the fourth value is smaller than the second preset value, the fourth value is equal to the fourth target value.

10. The test method of any one of claims 1, 7, 8, 9, wherein setting the threshold voltage of each transistor in the target bit line connected target sense amplifier according to a target threshold voltage parameter set comprises:

And setting the threshold voltage of each transistor in the target sense amplifier to be the threshold voltage corresponding to the transistor in the target threshold voltage parameter set by setting the transistor parameters of each transistor in the target sense amplifier.

11. The test method of claim 10, wherein the transistor parameters include a channel length and a channel width.

12. The test method of claim 1, further comprising:

Determining a reading result when the target sensing amplifier corresponds to each threshold voltage parameter set when the target storage unit and the environment storage unit correspond to one data map;

Determining a reading result when the target storage unit and the environment storage unit correspond to each data map and the target sensing amplifier corresponds to each threshold voltage parameter set;

and determining target storage units and environment storage units corresponding to a plurality of target bit lines, wherein each target sense amplifier corresponds to a read result of each threshold voltage parameter set when corresponding to each data map.

13. An electronic device, comprising:

A memory for storing codes;

a processor for executing the code stored by the memory to implement the sense amplifier performance simulation test method of any one of claims 1-12.