CN117951065A - Communication protocol for multi-chip cascading - Google Patents

Abstract

The invention belongs to the technical field of communication protocols, and particularly relates to a communication protocol for multi-chip cascading. The communication protocol implementation method provided by the invention is as follows: setting each chip to sample the data input by the chip data input end when the chip clock input end is the rising edge; the set data format is composed of a start byte, a data byte and an end byte, after the controller sends the transmission data to the first chip under the control of the clock signal, the first chip sends the transmission data to the next chip, and the like, the transmission data is transferred in the whole multi-chip cascade structure, so that each chip receives the same data. The invention can realize reliable control of a large number of chips, has small on-line load and can realize high-speed data transmission; meanwhile, the system chip and the controller based on the communication protocol have simple chip-to-chip connection and are particularly easy to wire on board.

Description

Communication protocol for multi-chip cascading

Technical Field

The invention belongs to the technical field of communication protocols, and particularly relates to a communication protocol for multi-chip cascading.

Background

The communication interface is widely applied to the semiconductor chip and is used for realizing the communication between the controller and the chip. The most common universal interfaces include an I2C interface, an SPI interface and a UART interface. The I2C interface consists of two lines, SDA and SCL, and has the advantage of simple circuitry, one controller can connect multiple devices, and has the disadvantage of slow speed, while one controller can connect up to 127 devices. The SPI interface consists of 4 lines: CLK, CS, DIN, DOUT. The SPI interface has the advantages that the speed is high, but the controller needs more lines and is not suitable for the scene of a plurality of chips, the clock is in a bus form in the application of the SPI interface, the clock lines of the SPI interface need to drive all control chips, the load seen on the clock is particularly large if the number of the control chips is large, and the transmission rate is reduced. The UART interface can be composed of two wires of TX and RX, and can realize duplex communication of 1 to 1. The other type is a single-wire interface protocol, a single-input single-output type is adopted, the interface is generally encoded by adopting a return-to-0 code or a non-return-to-0 code, and a high-speed clock is used for sampling and decoding values on a transmission line in a chip; the realization of the interface is more negative and the requirements on the frequency and the precision of an internal clock are higher, and because of the oversampling precision requirement, the common transmission rate of the interface is hundreds of KHz, and the immediate transmission of a large data volume of multiple chips cannot be satisfied.

With the development of technology, in some systems, there may be hundreds or thousands of chips of the same type, and how to implement high-speed communication by using a suitable communication protocol is a big difficulty, and meanwhile, because of the large number of chips, how to make the wiring of PCBs easier, reducing the jumper wires of PCBs or reducing the number of PCB layers required by the system is a big challenge.

Disclosure of Invention

In view of the above problems, the present invention proposes a communication protocol for multi-chip cascade, through which a controller can conveniently and independently control any selected chip or chips in a cascade structure, and has a positive effect on the field of multi-chip control.

The technical scheme of the invention is as follows:

The utility model provides a communication protocol for multi-chip cascade, a serial communication port, adopt 1 controller and through the clock output of controller and the data output of controller with the multi-chip connection, wherein the controller is connected with the clock input of first chip and the data input of first chip, the clock output of first chip is connected with the clock input of second chip, the data output of first chip is connected with the data input of second chip, and so on, the clock input of nth chip termination N-1 clock output, the data input of nth chip termination N-1 chip data output, thereby constitute multi-chip cascade structure, multi-chip cascade structure's communication mode is:

setting each chip to sample the data input by the chip data input end when the chip clock input end is the rising edge;

The set data format is composed of a start byte, a data byte and an end byte, after the controller sends the transmission data to the first chip under the control of the clock signal, the first chip sends the transmission data to the next chip, and the like, the transmission data is transferred in the whole multi-chip cascade structure, so that each chip receives the same data.

Further, the data bytes include command characters and data characters, wherein the command characters are used for defining the operation mode of the data, and the data characters are 1 or more data bytes.

Further, when the multi-chip cascade structure is initialized, the controller numbers all chips through the set command characters, each chip stores own ID, and then controls the designated single chip or a plurality of chips through the set command characters.

Further, all data bytes are 16 bits wide or an integer multiple of 16 bits wide.

Further, the start byte, the data byte, and the end byte are distinguished by setting the most significant bit of the start byte and the end byte to 1 and the most significant bit of the data byte to 0.

The beneficial effects of the invention are as follows: the invention can realize reliable control of a large number of chips, has small on-line load and can realize high-speed data transmission; meanwhile, the system chip and the controller based on the communication protocol have simple chip-to-chip connection and are particularly easy to wire on board.

Drawings

FIG. 1 is a system based on a two-wire protocol;

FIG. 2 is a two-wire signal line timing;

FIG. 3 is a two-wire communication data structure;

FIG. 4 is a command timing for setting a chip ID;

FIG. 5 is a timing diagram of a broadcast configuration command for all chips;

FIG. 6 is a command timing sequence for a selected chip configuration;

fig. 7 is a command form for a multi-chip operation.

Detailed Description

The technical scheme of the invention is described in detail below with reference to the accompanying drawings.

As shown in fig. 1, the communication protocol proposed by the present invention is two-wire, and the master controller can control hundreds of thousands of chips by only requiring 2-wire CLK (clock wire)/DATA (DATA wire) outputs. There are 4 PINs per controlled chip: CLKI/DATAI/CLKO/DATAO. For the first chip, its CLKI/DATAI is connected to the CLK and DATA outputs of the controller, respectively, while the input CLKI and DATAI are redriven through circuitry internal to the chip, outputting as CLKI and DATAO. For the chips cascaded after the first chip, its CLKI/DATAI is connected to CLKO and DATAO outputs of the preceding chip, respectively. Through the cascade structure, the CLKI/DATAI of the controller and the CLKI/DATAO of the output of the chip only need to drive one chip, the load on the line is small, and high-speed data transmission can be realized; at the same time, systems based on such interfaces are also particularly easy to board-level wiring; in the initialization stage, the controller sends a chip ID setting command to all chips in the series for numbering, and after numbering, a certain chip or a plurality of chips can be selected through a selected ID byte in the protocol for controlling together, so that high-speed and convenient control is realized.

In fig. 1, each controlled chip has a clock output pin and a data pin, the clock and data outputs of the chip directly drive the next chip, and the number of chips driven by each chip is only 1, so that parasitic load seen by each control line is small, and the signal line can realize higher transmission rate.

As shown in fig. 2, the interface signal line consists of CLKI/DATAI, and the value on the data line DATAI is de-sampled at the rising edge of the clock line CLKI, ensuring adequate signal setup and hold time.

The specific command structure diagram of an interface employing the invention is shown in fig. 3, the protocol consists of the following data structure (the upper diagram takes 16 bits as the minimum data set as an example): START (START byte), DATA (DATA byte), END (END byte). Each word is 16 bits wide or an integer multiple of 16 bits wide. Wherein the DATA portion can be divided into head_byte and data_byte. Different command types can be defined by the head_byte, different command types, and the number of data_bytes to be transmitted later can be different, as shown in table 1:

TABLE 1 Command Structure for communication

Command type	START	head_byte	data_byte0	DATA/END	END
						Setting chip ID	FFFF	HB0	0001	FFFF
Configuring all chips (broadcast command)	FFFF	HB1	DATA	FFFF
						Configuring a single selected chip	FFFF	HB2	ID	Register	FFFF
Configuring multiple successive ID chips	FFFF	HB3	ID	Register	FFFF

Taking the 16-bit width protocol as an example, START and END are at 16-bit high level, namely 0xFFFF; the data bytes are also 16 bits wide, each 16 bits consisting of 15 bits of valid data and the most significant 1 bit of 0. This highest bit 0 is used to distinguish the DATA byte DATA from the START byte START/END byte END. By adopting the method for processing the data and the highest bit of the START/END byte, the variable length of the command can be conveniently realized.

Taking N sub-chips in the system of fig. 1 as an example, each chip will forward the value on the CLKI/DATAI line to the next chip through CLKO/DATAO after receiving the data, so that each chip can see the same data.

Taking the set chip ID command as an example, as shown in FIG. 4, taking HB0 as the Head_byte for the set chip ID, the first chip, upon receiving HB0, can know that this chip is the set chip ID, which receives 0001 following HB0 as its own number. Upon receiving 0001, it will send the value of 0001+1, 0002, to the subsequent stage. The corresponding process is repeated at the later stage, so that all chips can obtain an ID of the own chip after receiving the command.

The broadcast command may configure all chips, the command timing of which is shown in fig. 5. HB1 is defined as the command header of the broadcast command. All chips receive the following DATA to the corresponding memory address of the chip after HB1 is received.

After the chip ID is set, we can select a different chip to operate independently, as shown in FIG. 6, and define HB2 as the command Head_byte for the selected chip operation. The selected chip ID receives the DATA DATA0 and the following DATA in the command into the corresponding memory space of the chip, and the command is ended after the END is received.

Multi-chip operation command: the command head_byte defining HB2 as a multi-chip continuous operation command is shown in fig. 7, in which ID indicates the first chip selected by the command and DATA _ID indicates that this DATA is DATA allocated to the ID-th chip. DATA _ID+1 indicates that this DATA is DATA sent to the id+1th chip, and DATA _ID+2 indicates that this DATA is DATA sent to the id+2th chip. An indication register of the selected chip is built in the chip, after receiving HB2 and ID after the first chip, the indication register is set to the value of ID, then after receiving DATA _ID, after storing the DATA, the indication register is correspondingly +1, indicating the corresponding chip ID number to which the next DATA is assigned. Each chip receives only the corresponding data indicating that the register is identical to the own number ID. The command is ended after the END is received.

Through the above protocol, the external controller can conveniently operate independently for application of one chip or select a plurality of chips to operate together.

Claims (5)

1. The utility model provides a communication protocol for multi-chip cascade, a serial communication port, adopt 1 controller and through the clock output of controller and the data output of controller with the multi-chip connection, wherein the controller is connected with the clock input of first chip and the data input of first chip, the clock output of first chip is connected with the clock input of second chip, the data output of first chip is connected with the data input of second chip, and so on, the clock input of nth chip termination N-1 clock output, the data input of nth chip termination N-1 chip data output, thereby constitute multi-chip cascade structure, multi-chip cascade structure's communication mode is:

setting each chip to sample the data input by the chip data input end when the chip clock input end is the rising edge;

The set data format is composed of a start byte, a data byte and an end byte, after the controller sends the transmission data to the first chip under the control of the clock signal, the first chip sends the transmission data to the next chip, and the like, the transmission data is transferred in the whole multi-chip cascade structure, so that each chip receives the same data.

2. A communication protocol for a multi-chip cascade according to claim 1 wherein the data bytes comprise command characters and data characters, wherein the command characters are used to define the manner in which the data operates, the data characters being 1 or more data bytes.

3. A communication protocol for multi-chip cascading according to claim 2, wherein the controller, upon initialization of the multi-chip cascading structure, numbers all chips by means of set command characters, each chip stores its own ID, and then controls the designated single chip or multiple chips by means of the set command characters.

4. A communication protocol for a multi-chip cascade according to claim 2 wherein all data bytes are 16 bits wide or an integer multiple of 16 bits wide.

5. A communication protocol for a multi-chip cascade according to claim 1 wherein the start byte, the data byte and the end byte differ in that the most significant bit of the start byte and the end byte is set to 1 and the most significant bit of the data byte is set to 0.