CN117951055A - Simple bus system of RISC-V architecture - Google Patents
Simple bus system of RISC-V architecture Download PDFInfo
- Publication number
- CN117951055A CN117951055A CN202410077431.1A CN202410077431A CN117951055A CN 117951055 A CN117951055 A CN 117951055A CN 202410077431 A CN202410077431 A CN 202410077431A CN 117951055 A CN117951055 A CN 117951055A
- Authority
- CN
- China
- Prior art keywords
- slave
- master
- slave device
- bus
- arbitration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000013461 design Methods 0.000 abstract description 6
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 230000005540 biological transmission Effects 0.000 abstract description 2
- 230000002093 peripheral effect Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 4
- LHMQDVIHBXWNII-UHFFFAOYSA-N 3-amino-4-methoxy-n-phenylbenzamide Chemical compound C1=C(N)C(OC)=CC=C1C(=O)NC1=CC=CC=C1 LHMQDVIHBXWNII-UHFFFAOYSA-N 0.000 description 3
- 230000000630 rising effect Effects 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Landscapes
- Bus Control (AREA)
Abstract
The invention relates to the technical field of chip design, in particular to a simple bus system of RISC-V architecture, which consists of a master device module, a slave device module and a logic arbitration module; the master device module comprises a master device 1, a master device 2 and a master device 3; the slave device module comprises a slave device 1, a slave device 2 and a slave device 3; the logic arbitration module mainly comprises a host arbitration and a slave arbitration; the beneficial effects are as follows: the simple bus system of RISC-V architecture can complete one bus access by 2 clock cycles, can complete the switching of different master devices by one clock cycle, and also supports the connection of multiple master devices and multiple slave devices. The bus interface is simple, the code quantity is less, the transplanting is convenient, the basic requirement of bus transmission can be met, the application scene is wider, and the requirements of different clients can be met.
Description
Technical Field
The invention relates to the technical field of chip design, in particular to a simple bus system of RISC-V architecture.
Background
The integrated circuit special for ASIC has the advantages of high density, high speed and low cost. RISC is a reduced instruction set architecture featuring an open source instruction set, while ARM is non-open source.
In the prior art, before a bus exists, a plurality of address lines and data lines are needed for communication between a processor core and a peripheral device, and redundancy is quite high. After the bus is provided, the processor core only needs one address bus and one data bus, so that the connection between the processor core and the peripheral is greatly simplified. Currently, there are many mature and standard buses, such as AMBA, wishbone, AXI, AHB buses, and most of the existing standard buses are complex in design and expensive in purchasing IP cores.
Disclosure of Invention
The present invention is directed to a simple bus system with RISC-V architecture to solve the above-mentioned problems.
In order to achieve the above purpose, the present invention provides the following technical solutions: a simple bus system of RISC-V architecture, the said system is made up of master device module, slave device module and logic arbitration module;
the master device module comprises a master device 1, a master device 2 and a master device 3;
The slave device module comprises a slave device 1, a slave device 2 and a slave device 3;
the logic arbitration module mainly comprises a host arbitration and a slave arbitration.
Preferably, the interface input signal of the master device 1 includes a read-write address of the master device 1, write data of the master device 1, an access request mark of the master device 1, and a write mark of the master device 1, and the interface output signal of the master device 1 is data read by the master device 1;
The interface input signals of the main device 2 comprise a read-write address of the main device 2, data written by the main device 2, a request mark accessed by the main device 2 and a write mark written by the main device 2, and the interface output signals of the main device 2 are data read by the main device 2;
the interface input signals of the master device 3 include a read-write address of the master device 3, data written by the master device 3, an access request flag of the master device 3, and a write flag of the master device 3, and the interface output signals of the master device 3 are data read by the master device 3.
Preferably, the interface output signal of the slave device 1 includes a read-write address of the slave device 1, write data of the slave device 1, and write a flag of the slave device 1, and the interface input signal of the slave device 1 is data read from the slave device 1;
the interface output signal of the slave device 2 comprises a read-write address of the slave device 2, data written by the slave device 2 and a write mark of the slave device 2, and the interface input signal of the slave device 2 is the data read by the slave device 2;
The interface output signal of the slave device 3 includes the read-write address of the slave device 3, the write data of the slave device 3, and the write flag of the slave device 3, and the interface input signal of the slave device 3 is the data read from the slave device 3.
Preferably, the host arbitration adopts a fixed priority arbitration mechanism, and sets priority master 1> device 2> device 3, namely when master 1, master 2 and master 3 initiate bus access requests at the same time, master 1 has high priority and can occupy buses preferentially; when the master device 2 and the master device 3 initiate a bus access request at the same time, the master device 2 has high priority and can occupy the bus preferentially; the slave arbitration selects the corresponding slave devices according to the upper four-bit numerical value of the address bus, and supports 16 slave devices at maximum.
Compared with the prior art, the invention has the beneficial effects that:
The simple bus system of RISC-V architecture can complete one bus access by 2 clock cycles, can complete the switching of different master devices by one clock cycle, and also supports the connection of multiple master devices and multiple slave devices. The bus interface is simple, the code quantity is less, the transplanting is convenient, the basic requirement of bus transmission can be met, the application scene is wider, and the requirements of different clients can be met.
Drawings
FIG. 1 is a block diagram of the connection of a core and a peripheral in the RISC-V architecture of the present invention;
FIG. 2 is a block diagram of a simplified bus architecture of the present invention;
FIG. 3 is a timing diagram of a simplified bus of the present invention.
Detailed Description
In order to make the objects, technical solutions, and advantages of the present invention more apparent, the embodiments of the present invention will be further described in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are some, but not all, embodiments of the present invention, are intended to be illustrative only and not limiting of the embodiments of the present invention, and that all other embodiments obtained by persons of ordinary skill in the art without making any inventive effort are within the scope of the present invention.
Example 1
Referring to fig. 1, the present invention provides a technical solution: a simple bus system of RISC-V architecture, the said system is made up of master device module, slave device module and logic arbitration module;
The hierarchical control relationships of the various modules are shown in fig. 1. The processor core in the figure interacts directly with each peripheral. Assuming one peripheral device has an address bus and a data bus, and a total of N peripheral devices, the processor core has N address buses and N data buses, and the code of the core is modified every time one peripheral device is added. After the bus is provided, the processor core only needs one address bus and one data bus, so that the connection between the processor core and the peripheral is greatly simplified. There are now well established, standard buses such as AMBA, wishbone, AXI, AHB buses and the like. When designing the CPU, one of them can be directly used, so as to save development time. However, AMBA, wishbone, AXI, AHB buses and other interfaces are complex, and in order to simplify the design, the invention designs a simple bus. The bus supports multi-master multi-slave connections, but only one master-slave communication at a time. A fixed priority arbitration mechanism is employed between the various masters on the bus.
The master module includes a plurality of masters, including a master 1, a master 2, and a master 3, as shown in fig. 2. The interface input signals of the master device 1 include a read-write address of the master device 1, data written by the master device 1, an access request flag of the master device 1, and a write flag of the master device 1, and the interface output signals of the master device 1 are data read by the master device 1. The interface input signals of the master device 2 include a read-write address of the master device 2, data written by the master device 2, an access request flag of the master device 2, and a write flag of the master device 2, and the interface output signals of the master device 2 are data read by the master device 2. The interface input signals of the master device 3 include a read-write address of the master device 3, data written by the master device 3, an access request flag of the master device 3, and a write flag of the master device 3, and the interface output signals of the master device 3 are data read by the master device 3. When multiple masters initiate requests to access the bus, the multiple access request signals are sent to the host arbitration, which uses a fixed priority arbitration mechanism, where priority master 1> device 2> device 3 is set.
The slave device module includes a plurality of slave devices, including a slave device 1, a slave device 2, and a slave device 3, as shown in fig. 2. The interface output signal of the slave device 1 includes the read-write address of the slave device 1, the write data of the slave device 1, and the write flag of the slave device 1, and the interface input signal of the slave device 1 is the data read from the slave device 1. The interface output signal of the slave device 2 includes the read-write address of the slave device 2, the write data of the slave device 2, and the write flag of the slave device 2, and the interface input signal of the slave device 2 is the read data of the slave device 2. The interface output signal of the slave device 3 includes the read-write address of the slave device 3, the write data of the slave device 3, and the write flag of the slave device 3, and the interface input signal of the slave device 3 is the data read from the slave device 3. The host arbitration adopts a fixed priority arbitration mechanism to determine that a certain master device accesses a bus, and the bus acquires input address signals addr [31:0] of the certain bus. The upper four bits of the address signal, addr [31:28], are sent to the slave arbitration to perform slave arbitration selection, and a maximum of 16 slave devices can be supported. After the slave arbitration, the bus selects the corresponding slave device and writes the 28-bit address signals addr [27:0] into the corresponding slave address interface.
The logic arbitration module mainly comprises a host arbitration and a slave arbitration. The host arbitration employs a fixed priority arbitration mechanism, where priority master 1> device 2> device 3 is set. That is, when the master 1, the master 2, and the master 3 simultaneously initiate the access bus request, the master 1 has a high priority and can occupy the bus preferentially. When the master device 2 and the master device 3 simultaneously initiate the access bus request, the master device 2 has high priority and can occupy the bus preferentially. The slave arbitration selects the corresponding slave devices according to the upper four-bit numerical value of the address bus, and supports 16 slave devices at maximum.
Example two
Based on the first embodiment, the relationship between the modules in the design method of the RISC-V architecture simple bus is shown in fig. 2, mux1-4 is 4 multiplexers, master Arbiter is host arbitration, slave Arbiter is slave arbitration, master1-3 is host device, slave1-3 is slave device. A certain master device initiates a request for accessing the bus, the host arbitrates to judge the priority, the output of mux1 is controlled, and the master device with high priority occupies the bus. The upper four bits of the output address of the master device are sent to the slave arbitration, and the slave arbitration controls the output of mux2 to select the corresponding slave device. The data output by the host is also sent to the corresponding slave device through mux1 and mux2 multiplexers. In addition, the master arbitrates the output of control mux4, and the slave arbitrates the output of control mux 3. The data output from the slave is also sent to the corresponding host device through mux3 and mux4 selectors.
A timing diagram of the simple bus is shown in fig. 3. Accessing the bus once requires 2 clock cycles. The first clock rising edge, the host sends the access request, after host arbitration and slave arbitration, the second clock rising edge, the slave obtains the address and the written data, the host obtains the data read by the slave; and the third clock rising edge, the access request is set low, and the BUSY is set high at the same time, so as to release the bus.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (4)
1. A simple bus system of RISC-V architecture, characterized by: the system consists of a master device module, a slave device module and a logic arbitration module;
the master device module comprises a master device 1, a master device 2 and a master device 3;
The slave device module comprises a slave device 1, a slave device 2 and a slave device 3;
the logic arbitration module mainly comprises a host arbitration and a slave arbitration.
2. A reduced complexity bus system of RISC-V architecture as claimed in claim 1, wherein: the interface input signals of the main device 1 comprise a read-write address of the main device 1, data written by the main device 1, an access request mark of the main device 1 and a write mark of the main device 1, and the interface output signals of the main device 1 are data read by the main device 1;
The interface input signals of the main device 2 comprise a read-write address of the main device 2, data written by the main device 2, a request mark accessed by the main device 2 and a write mark written by the main device 2, and the interface output signals of the main device 2 are data read by the main device 2;
the interface input signals of the master device 3 include a read-write address of the master device 3, data written by the master device 3, an access request flag of the master device 3, and a write flag of the master device 3, and the interface output signals of the master device 3 are data read by the master device 3.
3. A reduced complexity bus system of RISC-V architecture as claimed in claim 1, wherein: the interface output signal of the slave device 1 comprises a read-write address of the slave device 1, data written by the slave device 1 and a write mark of the slave device 1, and the interface input signal of the slave device 1 is the data read by the slave device 1;
the interface output signal of the slave device 2 comprises a read-write address of the slave device 2, data written by the slave device 2 and a write mark of the slave device 2, and the interface input signal of the slave device 2 is the data read by the slave device 2;
The interface output signal of the slave device 3 includes the read-write address of the slave device 3, the write data of the slave device 3, and the write flag of the slave device 3, and the interface input signal of the slave device 3 is the data read from the slave device 3.
4. A reduced complexity bus system of RISC-V architecture as claimed in claim 1, wherein: the host arbitration adopts a fixed priority arbitration mechanism, and sets priority master 1> device 2> device 3, namely when master 1, master 2 and master 3 initiate bus access requests at the same time, master 1 has high priority and can occupy buses preferentially; when the master device 2 and the master device 3 initiate a bus access request at the same time, the master device 2 has high priority and can occupy the bus preferentially; the slave arbitration selects the corresponding slave devices according to the upper four-bit numerical value of the address bus, and supports 16 slave devices at maximum.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410077431.1A CN117951055A (en) | 2024-01-19 | 2024-01-19 | Simple bus system of RISC-V architecture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410077431.1A CN117951055A (en) | 2024-01-19 | 2024-01-19 | Simple bus system of RISC-V architecture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117951055A true CN117951055A (en) | 2024-04-30 |
Family
ID=90804339
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410077431.1A Pending CN117951055A (en) | 2024-01-19 | 2024-01-19 | Simple bus system of RISC-V architecture |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117951055A (en) |
-
2024
- 2024-01-19 CN CN202410077431.1A patent/CN117951055A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6601126B1 (en) | Chip-core framework for systems-on-a-chip | |
| US5819096A (en) | PCI to ISA interrupt protocol converter and selection mechanism | |
| CN110109847B (en) | Arbitration method, system and storage medium for multiple master devices of APB bus | |
| US8041867B2 (en) | Method and apparatus for enhancing data rate of advanced micro-controller bus architecture | |
| US11768607B1 (en) | Flash controller for ASIC and control method therefor | |
| US8339869B2 (en) | Semiconductor device and data processor | |
| CN104298628A (en) | Data storage device arbitration circuit and method for concurrent access | |
| CN112965924A (en) | AHB-to-AXI bridge and aggressive processing method | |
| CN112988647B (en) | TileLink bus-to-AXI 4 bus conversion system and method | |
| KR100633773B1 (en) | Bus system and method of bus arbitration | |
| EP1222551B1 (en) | Asynchronous centralized multi-channel dma controller | |
| CN116028413A (en) | Bus arbiter, bus arbitration method, device and medium | |
| CN112256615B (en) | USB conversion interface device | |
| US6954869B2 (en) | Methods and apparatus for clock domain conversion in digital processing systems | |
| US20150177816A1 (en) | Semiconductor integrated circuit apparatus | |
| CN102591817B (en) | Multi-bus bridge controller and implementing method thereof | |
| CN117951055A (en) | Simple bus system of RISC-V architecture | |
| CN106326172B (en) | A kind of APB bus slave Interface Expanding circuit and its application method | |
| US8799699B2 (en) | Data processing system | |
| JP2002149591A (en) | Method and device for optimizing bus in processor local bus system | |
| CN112100098B (en) | DDR control system and DDR memory system | |
| CN117312210B (en) | Method for expanding performance of RISC-V processor | |
| Zhao et al. | A Novel Design of High-speed Multi-port Memory Interface for Digital Signal Processor | |
| CN113868179B (en) | Communication device of LPC-DPRam and data conversion method | |
| US20040064662A1 (en) | Methods and apparatus for bus control in digital signal processors |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination |