CN117950827A

CN117950827A - Computing device, computing task processing method and electronic device

Info

Publication number: CN117950827A
Application number: CN202311817537.2A
Authority: CN
Inventors: 蒋常龙; 刘晨; 冷祥纶; 周琳; 刘文龙; 李南
Original assignee: Shanghai Power Tensors Intelligent Technology Co Ltd
Current assignee: Shanghai Power Tensors Intelligent Technology Co Ltd
Priority date: 2023-12-26
Filing date: 2023-12-26
Publication date: 2024-04-30

Abstract

The application discloses a computing device which is connected with a main control device, wherein the main control device is provided with a first dispatcher; the computing device is used for processing computing tasks, and the computing tasks are divided into at least two tasks; the computing device comprises a synchronous interrupt controller and a second scheduler connected with the synchronous interrupt controller, wherein the synchronous interrupt controller generates an interrupt corresponding to the identification information in response to the identification information being synchronized to the synchronous interrupt controller through the first scheduler, and the synchronous interrupt controller sends the interrupt to the second scheduler in response to the synchronous interrupt controller indicating a pull-down enabling state; the second scheduler receives the interrupt and acquires a task entry from the master control device during the interrupt, thereby pulling down the task corresponding to the task entry from the master control device. The application also discloses a computing task processing method and electronic equipment. The application realizes the completion of task pull-down based on soft and hard combination, reduces the synchronization times between the main control end and the computing end, and increases the robustness of the computing system.

Description

Computing device, computing task processing method and electronic device

Technical Field

The application relates to the technical field of artificial intelligent chips, in particular to a computing device, a computing task processing method and electronic equipment.

Background

With the development of information technology, heterogeneous computing is adopted in high-performance computing systems or data centers to meet the increasing demands. In a computing system, there are typically multiple or multiple sets of chips of different configurations that make up a complete complex computing system, such as CPU, GPU, FPGA, ASIC in a computing system. The CPU mainly plays a role of control in the whole system, other chips finish specific calculation tasks according to different scenes or requirements, the CPU can be regarded as a control center of the system, and other chips are calculation centers.

In such heterogeneous computing systems, the computing scenario is more complex, multiple computing chips are required to complete the computing scenario together, or a complete computing Task is required to be split into multiple small tasks (tasks), the specific computing Task is required to be managed by a CPU, and is required to be issued to computing hardware (device) for computing, that is, task information is synchronized to a specific position of the device, the device adopts a polling mode to check whether a Task needs to be pulled down, but the method is not efficient enough, for example, when no Task needs to be pulled down, the device still needs to continuously perform polling check, and therefore cannot sleep, so that the power consumption is higher.

Disclosure of Invention

The application provides a computing device, a computing task processing method and an electronic device.

The first aspect of the application provides a computing device connected with a main control device, wherein the main control device is provided with a first dispatcher; the computing device is used for processing a computing task, and the computing task is divided into at least two tasks; the computing device includes a synchronous interrupt controller and a second scheduler coupled to the synchronous interrupt controller, wherein: the method comprises the steps that at least two task identification information are synchronized to the synchronous interrupt controller through the first scheduler, the synchronous interrupt controller generates an interrupt corresponding to the identification information, and the synchronous interrupt controller sends the interrupt to the second scheduler in response to the synchronous interrupt controller indicating a pull-down enabling state; ; the identification information is used for representing a task item of one task of the at least two tasks; the second scheduler receives the interrupt and acquires the task item from the main control equipment during the interrupt, so that the task corresponding to the task item is pulled down from the main control equipment.

In some embodiments, the synchronization interrupt controller is further to indicate the interrupt in response to the identification information being synchronized to the synchronization interrupt controller by the first scheduler.

In some embodiments, the synchronous interrupt controller does not send the interrupt to the second scheduler and records the interrupt in response to the synchronous interrupt controller indicating a pull-down disabled state.

In some embodiments, the synchronous interrupt controller indicates a pull-down disabled state in response to the second scheduler receiving the interrupt.

In some embodiments, the synchronous interrupt controller includes a set of pull-down interrupt registers for indicating or recording the interrupt and indicating the pull-down enable state or the pull-down disable state.

In some embodiments, the set of pull-down interrupt registers includes a pull-down interrupt status register for indicating or recording the interrupt and a pull-down interrupt mask register for indicating the pull-down enable state or the pull-down disable state.

In some embodiments, in response to the identification information being synchronized by the first scheduler to the synchronous interrupt controller, the synchronous interrupt controller sets the pull-down interrupt status register to indicate the interrupt.

In some embodiments, in response to the second scheduler receiving the interrupt, the synchronous interrupt controller sets the pull-down interrupt mask register to indicate the pull-down disabled state.

In some embodiments, in response to the second scheduler receiving the interrupt, the synchronous interrupt controller further clears the pull-down interrupt status register.

In some embodiments, the synchronous interrupt controller includes a pull-down interrupt trigger register; the identification information is written to the pull-down interrupt trigger register by the first scheduler such that a value of the pull-down interrupt trigger register is changed such that the identification information is synchronized to the synchronous interrupt controller by the first scheduler.

In some embodiments, the synchronous interrupt controller is initialized by the master device such that the synchronous interrupt controller indicates an interrupt enable state; in response to the synchronous interrupt controller indicating the interrupt enable state and the task being a first task of the at least two tasks, the synchronous interrupt controller sends the interrupt to the second scheduler.

In some embodiments, the synchronous interrupt controller includes an interrupt enable register for initialization by the master device to indicate the interrupt enable state.

In some embodiments, in response to the second scheduler completing the task in a pull-down manner, the second scheduler synchronizes the identification information corresponding to the task to the synchronous interrupt controller; and responding to the second scheduler to synchronize the identification information corresponding to the task to the synchronous interrupt controller, and setting the synchronous interrupt controller by the second scheduler to indicate whether to send the interrupt to the first scheduler.

In some embodiments, in response to the second scheduler synchronizing the identification information corresponding to the task to the synchronous interrupt controller, the second scheduler further sets the synchronous interrupt controller to indicate the pull-down enabled state.

In some embodiments, the synchronous interrupt controller includes a completion interrupt register set for indicating that the task is completed in a pull-down manner, to indicate that the interrupt is completed, and to indicate whether to send the interrupt to the first scheduler.

In some embodiments, the completion interrupt register set includes a completion interrupt status register for indicating that the task is completed by pulling down and a completion interrupt mask register for indicating whether to send the interrupt to the first scheduler.

In some embodiments, in response to the second scheduler synchronizing the identification information corresponding to the task to the synchronous interrupt controller, the synchronous interrupt controller sets the completion interrupt status register to indicate that the interrupt is complete.

In some embodiments, the completion interrupt mask register indicates that the interrupt is to be sent to the first scheduler in response to the second scheduler synchronizing the identification information corresponding to the task to the synchronized interrupt controller.

In some embodiments, in response to the second scheduler synchronizing the identification information corresponding to the task to the synchronous interrupt controller, the synchronous interrupt controller sets the completion interrupt mask register to indicate that the interrupt is disabled to be sent to the first scheduler.

In some embodiments, the synchronous interrupt controller includes a completion interrupt trigger register; the second scheduler writes the identification information corresponding to the task into the completion interrupt trigger register so as to change the value of the completion interrupt trigger register, and therefore the second scheduler synchronizes the identification information corresponding to the task to the synchronous interrupt controller.

A second aspect of the present application provides a computing task processing method applied to a second device, where the second device is a computing device as described in the first aspect, and is connected to a first device, and the first device is installed with a first scheduler, and the computing task is divided into at least two tasks; the method comprises the following steps: the method comprises the steps that at least two task identification information are synchronized to the synchronous interrupt controller through the first scheduler, the synchronous interrupt controller generates an interrupt corresponding to the identification information, and the synchronous interrupt controller sends the interrupt to the second scheduler in response to the synchronous interrupt controller indicating a pull-down enabling state; the identification information is used for representing a task item of one task of the at least two tasks; the second scheduler receives the interrupt and acquires the task item from the first device during the interrupt, so that the task corresponding to the task item is pulled down from the first device.

The third aspect of the present application provides a computing task processing method, applied to a first device, where the first device is connected to a second device, the first device is provided with a first scheduler, the second device includes a synchronous interrupt controller and a second scheduler, and the computing task is divided into at least two tasks; the method comprises the following steps: acquiring a task from the at least two tasks, and representing the task as a task item; and acquiring the identification information of the task item through the first scheduler, and synchronizing the identification information of the task item to the synchronous interrupt controller, so that the synchronous interrupt controller responds to the identification information to generate an interrupt corresponding to the identification information, and responds to the synchronous interrupt controller to indicate a pull-down enabling state, the interrupt is sent to the second scheduler, and the second scheduler receives the interrupt and acquires the task item from the first device during the interrupt, thereby pulling down the task corresponding to the task item from the first device.

In some embodiments, the identification information of the task item includes address information or index information of the task item.

In some embodiments, the method further comprises: and initializing the synchronous interrupt controller before acquiring the task in response to the task being the first task of the at least two tasks, so that the synchronous interrupt controller indicates an interrupt enable state.

In some embodiments, the method further comprises: transmitting the interrupt to the first scheduler in response to the synchronous interrupt controller indication, receiving the interrupt by the first scheduler; in response to receiving the interrupt through the first scheduler, viewing the identification information corresponding to the interrupt from the synchronous interrupt controller, and updating the task entry according to the identification information.

A fourth aspect of the present application provides an electronic device, including a memory and a processor coupled to each other, the processor configured to execute program instructions stored in the memory, to implement the training method for computing task processing in the third aspect.

A fifth aspect of the present application provides an electronic device comprising a processor, and a memory and a computing device coupled to the processor, the computing device being as described in the first aspect, the processor being configured to execute program instructions stored in the memory to implement the computing task processing method of the third aspect.

According to the scheme, the computing device is connected with the main control device, the first scheduler is installed on the main control device, the computing device comprises the synchronous interrupt controller and the second scheduler connected with the synchronous interrupt controller, the synchronous interrupt controller generates an interrupt corresponding to the identification information by responding to the identification information of the task item for representing one task of at least two tasks and is synchronized to the synchronous interrupt controller through the first scheduler, the interrupt is sent to the second scheduler by responding to the pull-down enabling state indicated by the synchronous interrupt controller, further, the second scheduler receives the interrupt and acquires the task item from the main control device during the interrupt, so that the task corresponding to the task item is pulled down from the main control device, that is, the number of times of synchronization between a main control end and the computing end is reduced based on soft-hard combination completion of task pull-down, and the robustness of the computing system is improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.

FIG. 1 is a schematic diagram of a framework of one embodiment of a computing device of the present application;

FIG. 2 is a schematic diagram of a framework of yet another embodiment of a computing device of the present application;

FIG. 3 is a schematic diagram of an electronic device according to an embodiment of the present application

FIG. 4 is a flow chart of an embodiment of a computing task processing method according to the present application;

FIG. 5 is a flow chart of a computing task processing method according to another embodiment of the present application;

FIG. 6 is a flow chart of one embodiment of the task processing of the present application;

FIG. 7 is a flow chart of one embodiment of the task processing of the present application;

FIG. 8 is a schematic diagram of a frame of yet another embodiment of an electronic device of the present application;

Fig. 9 is a schematic frame diagram of another embodiment of the electronic device of the present application.

Detailed Description

The following describes embodiments of the present application in detail with reference to the drawings.

In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, interfaces, techniques, etc., in order to provide a thorough understanding of the present application.

The term "and/or" is herein merely an association relationship describing an associated object, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship. Further, "a plurality" herein means two or more than two. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of A, B, C, may mean including any one or more elements selected from the group consisting of A, B and C.

Referring to fig. 1, fig. 1 is a schematic diagram of a frame of an electronic device according to an embodiment of the application, wherein an electronic device a includes a computing device 100 and a master device 200, and the computing device 100 is connected to the master device 200.

The computing Device 100 may be a Device, where the Device may be general-purpose parallel computing hardware similar to a GPU (graphics processing unit, a graphics processing unit), may be a DPU (Data Processing Unit, a data processor)), may be an ASIC (Application SPECIFIC INTEGRATED Circuit) hardware unit similar to a DSA, and the computing Device 100 is configured to process a computing Task, where the computing Task is divided into at least two tasks, for example, the computing Task is divided into a plurality of tasks, for example, task 1, task 2 … … Task N, where the plurality of tasks may be continuous or discontinuous in physical address. The master device 200 is installed with a first scheduler 210, and the master device 200 may be a Host CPU for performing management and control in a computing system, and the first scheduler 210 is used for issuing tasks and recording task information acquired from the computing device 100. The connection between the computing Device 100 and the master Device 200 may be performed by using a board-level interconnection bus, for example, PCIE, ILKN, or the like, or the Host CPU and the Device may be packaged in the same packet (packet), and the two may be connected by using a chip-to-chip (Die) specific bus.

Specifically, the computing device 100 includes a synchronous interrupt controller 110 and a second scheduler 120 connected to the synchronous interrupt controller 110, wherein, in response to identification information for representing a task entry of one of at least two tasks being synchronized to the synchronous interrupt controller 110 by the first scheduler 210, the synchronous interrupt controller 110 generates an interrupt corresponding to the identification information, and in response to the synchronous interrupt controller 110 indicating a pull-down enable state, the synchronous interrupt controller 110 transmits the interrupt to the second scheduler 120.

The identification information of the Task Entry may be Task Entry address information or Task Entry index information, and the software (the master control device 200) identifies a specific Task by using a Task Entry (Entry), for example, task 1 corresponds to Entry1, task 2 corresponds to Entry2, … … Task N corresponds to Entry N, and the like, so that after the computing device 100 obtains the address of the first Task Entry, the subsequent Task Entry address may be obtained according to a certain rule.

In response to the identification information for the task entry representing one of the at least two tasks being synchronized to the synchronous interrupt controller 110 by the first scheduler 210, i.e., the identification information of the task entry of the related task is written to the synchronous interrupt controller 110 by the first scheduler 210, the one of the at least two tasks may be a task to be issued in the master device 200. After the synchronous interrupt controller 110 synchronizes to the identification information of the task entry of a task, an interrupt corresponding to the identification information is generated, the identification information is the identification information of the task entry of one task of at least two tasks, the interrupt corresponding to the identification information indicates that the task corresponding to the identification information needs to be pulled down, and if the synchronous interrupt controller 110 indicates a pull-down enabling state, that is, the pull-down enabling state indicates that the synchronous interrupt controller 110 can send the interrupt to the second scheduler 120, the synchronous interrupt controller 110 sends the interrupt corresponding to the identification information to the second scheduler 120 according to the pull-down enabling state.

Further, the second scheduler 120 receives the interrupt and acquires the task entry from the main control device 200 during the interrupt, thereby pulling down the task corresponding to the task entry from the main control device 200.

The second scheduler 120 receives the interrupt corresponding to the identification information of the task entry, and acquires the task entry from the master control device 200 during the interrupt, i.e., parses the identification information of the task entry to acquire the task entry, thereby implementing the pull-down of the task corresponding to the task entry from the master control device 200.

In this embodiment, a computing device is connected to a master device, where the master device is provided with a first scheduler, and the computing device includes a synchronous interrupt controller and a second scheduler connected to the synchronous interrupt controller, and by synchronizing identification information of a task entry for representing one of a plurality of tasks to the synchronous interrupt controller through the first scheduler in response to the identification information, the synchronous interrupt controller generates an interrupt corresponding to the identification information, and instructs a pull-down enable state in response to the synchronous interrupt controller to send the interrupt to the second scheduler, further, the second scheduler receives the interrupt, and acquires the task entry from the master device during the interrupt, thereby implementing a pull-down of the task corresponding to the task entry from the master device, that is, completing the task pull-down based on soft-hard combination, reducing a number of times of synchronization between a master terminal and a computing terminal, and increasing robustness of the computing system.

In some embodiments, in response to the identification information being synchronized to the synchronous interrupt controller 110 by the first scheduler 210, the synchronous interrupt controller 110 also indicates the interrupt.

In response to the identification information being synchronized to the synchronous interrupt controller 110 by the first scheduler 210, i.e. the identification information of the task entry of the relevant task is written to the synchronous interrupt controller 110 by the first scheduler 210, for example, the identification information may be address information or index information of the task entry of the task to be issued in the master device 200, the synchronous interrupt controller 110 further indicates the interrupt, i.e. performs a set operation, recording the interrupt information.

In this embodiment, in response to the identification information being synchronized to the synchronous interrupt controller through the first scheduler, the synchronous interrupt controller further indicates the interrupt, so that task pull-down based on soft and hard combination is achieved, synchronization times between the main control end and the computing end are reduced, and robustness of the computing system is increased.

In some embodiments, in response to the synchronous interrupt controller 110 not sending the interrupt to the second scheduler 120 and indicating a pull-down disabled state, the synchronous interrupt controller 110 records the interrupt.

If the synchronous interrupt controller 110 indicates a pull-down disabled state, that is, the pull-down disabled state indicates that the synchronous interrupt controller 110 is disabled from sending the interrupt to the second scheduler 120, at this time, the synchronous interrupt controller 110 records the interrupt, that is, records the interrupt corresponding to the identification information, and is not sent to the second scheduler 120.

In this embodiment, in response to the synchronous interrupt controller indicating the pull-down disabled state, the synchronous interrupt controller records the interrupt, so that the task pull-down based on soft-hard combination is completed, the synchronization times between the main control end and the computing end are reduced, and the robustness of the computing system is increased.

In some embodiments, in response to the second scheduler 120 receiving the interrupt, the synchronous interrupt controller 110 indicates a pull-down disabled state.

The synchronous interrupt controller 110 generates an interrupt corresponding to the identification information, and in response to the synchronous interrupt controller 110 indicating a pull-down enabling state, the synchronous interrupt controller 110 sends the interrupt to the second scheduler 120, and in response to the second scheduler 120 receiving the interrupt, the synchronous interrupt controller 110 indicates a pull-down disabling state, i.e., the synchronous interrupt controller 110 prohibits sending the interrupt to the second scheduler 120, i.e., after the second scheduler 120 receives the interrupt, the synchronous interrupt controller 110 indicates a pull-down disabling state, i.e., records a newly added interrupt, but does not send the interrupt to the second scheduler 120.

In this embodiment, in response to the second scheduler receiving the interrupt, the synchronous interrupt controller indicates the pull-down disabled state, so that the task pull-down based on soft-hard combination is achieved, the synchronization times between the main control end and the computing end are reduced, and the robustness of the computing system is increased.

In some embodiments, as shown in fig. 2, fig. 2 is a schematic diagram of a framework of another embodiment of the computing device of the present application, where the synchronous interrupt controller 110 includes a set of pull-down interrupt registers 1101, where the set of pull-down interrupt registers 1101 is used to indicate or record the interrupt and indicate a pull-down enable state or a pull-down disable state.

The pull-down interrupt register set 1101 is used for indicating or recording the interrupt, that is, recording interrupt information corresponding to the identification information in the pull-down interrupt register set 1101, and performing a set operation. The pull-down interrupt register set 1101 is configured to indicate a pull-down enabled state or a pull-down disabled state, where the pull-down enabled state indicates that the synchronous interrupt controller 110 may send an interrupt to the second scheduler 120, and the pull-down disabled state indicates that the synchronous interrupt controller 110 is disabled from sending an interrupt to the second scheduler 120.

In this embodiment, the synchronous interrupt controller includes a pull-down interrupt register set, where the pull-down interrupt register set is used to indicate or record the interrupt and indicate a pull-down enabled state or a pull-down disabled state, so that task pull-down based on soft-hard combination is achieved, synchronization times between the main control end and the computing end are reduced, and robustness of the computing system is increased.

In some embodiments, as shown in fig. 2, the set of pull-down interrupt registers 1101 includes a pull-down interrupt status register 11011 and a pull-down interrupt mask register 11012, wherein the pull-down interrupt status register 11011 is used to indicate or record the interrupt, and the pull-down interrupt mask register 11012 is used to indicate a pull-down enable state or a pull-down disable state.

The pull-down interrupt status register 11011 is used for indicating or recording the interrupt, that is, interrupt information corresponding to the identification information is recorded in the pull-down interrupt status register 11011, and a set operation is performed. The pull-down interrupt mask register 11012 is configured to indicate a pull-down enabled state or a pull-down disabled state, i.e., determine whether to send an interrupt to the second scheduler 120 according to a mask condition of the interrupt, i.e., the pull-down interrupt mask register 11012 indicates the pull-down enabled state or the pull-down disabled state, wherein the pull-down enabled state indicates that the synchronous interrupt controller 110 may send the interrupt to the second scheduler 120, and the pull-down disabled state indicates that the synchronous interrupt controller 110 is prohibited from sending the interrupt to the second scheduler 120.

In this embodiment, the pull-down interrupt register set includes a pull-down interrupt status register and a pull-down interrupt mask register, where the pull-down interrupt status register is used to indicate or record the interrupt, and the pull-down interrupt mask register is used to indicate a pull-down enable status or a pull-down disable status, so that task pull-down based on soft and hard combination is achieved, synchronization times between the main control end and the computing end are reduced, and robustness of the computing system is increased.

Specifically, in some embodiments, in response to the identification information being synchronized to the synchronous interrupt controller 110 by the first scheduler 210, the synchronous interrupt controller 110 sets the pull-down interrupt status register 11011 to indicate the interrupt.

The identification information of the task entry of one of the plurality of tasks is synchronized to the synchronous interrupt controller 110 by the first scheduler 210, and the synchronous interrupt controller 110 sets the pull-down interrupt status register 11011 to indicate an interrupt corresponding to the identification information, that is, records the interrupt in the pull-down interrupt status register 11011.

In this embodiment, in response to the identification information being synchronized to the synchronous interrupt controller through the first scheduler, the synchronous interrupt controller sets the pull-down interrupt status register to indicate the interrupt, so that the task pull-down based on soft-hard combination is achieved, the synchronization times between the master control end and the computing end are reduced, and the robustness of the computing system is increased.

In some embodiments, in response to the second scheduler 120 receiving the interrupt, the synchronous interrupt controller 110 sets the pull-down interrupt mask register 11012 to indicate a pull-down disabled state.

The synchronous interrupt controller 110 transmits an interrupt corresponding to the identification information to the second scheduler 120 according to the pull-down enable state, and the second scheduler 120 receives the interrupt, and at the same time, the synchronous interrupt controller 110 sets the pull-down interrupt mask register 11012 to indicate the pull-down disable state, that is, sets the mask of the pull-down interrupt, and disables the pull-down interrupt.

In this embodiment, in response to the second scheduler receiving the interrupt, the synchronous interrupt controller sets the pull-down interrupt mask register to indicate the pull-down disabled state, so that the task pull-down based on soft and hard combination is achieved, the synchronization times between the main control end and the computing end are reduced, and the robustness of the computing system is increased.

Further, in some embodiments, in response to the second scheduler 120 receiving the interrupt, the synchronous interrupt controller 110 also clears the pull-down interrupt status register 11011.

The synchronous interrupt controller 110 sends the interrupt corresponding to the identification information to the second scheduler 120 according to the pull-down enabling state, the second scheduler 120 receives the interrupt, and meanwhile, the synchronous interrupt controller 110 also clears the pull-down interrupt state register 11011, sets a mask of the pull-down interrupt, and disables the pull-down interrupt.

In this embodiment, in response to the second scheduler receiving the interrupt, the synchronous interrupt controller further clears the pull-down interrupt status register, that is, the main control device may modify the entry representing information to generate the interrupt as required, the generated interrupt may be recorded in the status register, and since the interrupt direction mask is set, the interrupt may not be sent to the second scheduler, the ongoing pull-down action of the computing device may not be broken, so that the task pull-down based on soft-hard combination is achieved, the number of times of synchronization between the main control terminal and the computing terminal is reduced, and the robustness of the computing system is increased.

In some embodiments, as shown in FIG. 2, the synchronous interrupt controller 110 includes a pull-down interrupt trigger register 1102.

Further, identification information is written to the pull-down interrupt trigger register 1102 through the first scheduler 210 such that the value of the pull-down interrupt trigger register 1102 is changed, whereby the identification information is synchronized to the synchronous interrupt controller 110 through the first scheduler 210.

The identification information of the task entry representing one of the plurality of tasks, which may be, for example, index information of the task entry, is written to the pull-down interrupt trigger register 1102 through the first scheduler 210 such that the value of the pull-down interrupt trigger register 1102 is changed so that the identification information is synchronized to the synchronous interrupt controller 110 to generate an interrupt corresponding to the identification information.

In this embodiment, the identification information is written into the pull-down interrupt trigger register through the first scheduler, so that the value of the pull-down interrupt trigger register changes, and thus the identification information is synchronized to the synchronous interrupt controller through the first scheduler, so that task pull-down based on soft-hard combination is achieved, the synchronization times between the main control end and the computing end are reduced, and the robustness of the computing system is increased.

In some embodiments, the synchronous interrupt controller 110 is initialized by the master device 200 such that the synchronous interrupt controller 110 indicates an interrupt enable state; in response to the synchronous interrupt controller 110 indicating the interrupt enable state, and the task being the first of the at least two tasks, the synchronous interrupt controller 110 sends the interrupt to the second scheduler 120.

The synchronous interrupt controller 110 is initialized by the master device 200 such that the synchronous interrupt controller 110 indicates an interrupt enable state. Further, in response to the synchronous interrupt controller 110 indicating an interrupt enable state and the task being the first of at least two, the synchronous interrupt controller 110 sends the interrupt to the second scheduler 120, it is understood that the synchronous interrupt controller 110 decides whether to send the interrupt to the second scheduler 120 according to the indication of the pull-down interrupt mask register 11012, wherein upon first receiving the task, for example, identification information corresponding to the first of the plurality of tasks is written to the pull-down interrupt trigger register 1102 by the first scheduler 210, such that the value of the pull-down interrupt trigger register 1102 changes, generating an interrupt corresponding to the identification information, which is enabled in the initialization phase, i.e., the interrupt is sent to the second scheduler 120.

In this embodiment, the synchronous interrupt controller is initialized by the master control device, so that the synchronous interrupt controller indicates an interrupt enable state; and responding to the interrupt enabling state indicated by the synchronous interrupt controller, wherein the task is the first task of at least two tasks, and the synchronous interrupt controller sends the interrupt to the second scheduler, so that the task pull-down based on soft and hard combination is realized, the synchronization times between the main control end and the computing end are reduced, and the robustness of the computing system is improved.

In some embodiments, as shown in fig. 2, the synchronous interrupt controller 110 includes an interrupt enable register 1103, the interrupt enable register 1103 being for initialization by the master device 200 to indicate an interrupt enable state.

The interrupt enable register 1103 is used for being initialized by the master device 200 to indicate an interrupt enable state, for example, identification information corresponding to a first task of the plurality of tasks is written into the pull-down interrupt trigger register 1102 through the first scheduler 210, such that the value of the pull-down interrupt trigger register 1102 is changed, and the interrupt enable register 1103 is used for being initialized by the master device 200 to indicate an interrupt enable state, and an interrupt corresponding to the identification information is generated, that is, the interrupt is enabled in the initialization phase, that is, the interrupt is sent into the second scheduler 120.

In this embodiment, the synchronous interrupt controller includes an interrupt enable register, where the interrupt enable register is used for being initialized by the main control device to indicate an interrupt enable state, so that task pull-down based on soft and hard combination is achieved, synchronization times between the main control terminal and the computing terminal are reduced, and robustness of the computing system is increased.

In some embodiments, in response to the second scheduler 120 pulling down to complete the task, the second scheduler 120 synchronizes identification information corresponding to the task to the synchronous interrupt controller 110; in response to the second scheduler 120 synchronizing the identification information corresponding to the task to the synchronous interrupt controller 110, the second scheduler 120 sets the synchronous interrupt controller 110 to indicate whether to send the interrupt to the first scheduler 210.

The second scheduler 120 pulls down to complete the task, that is, the second scheduler 120 receives an interrupt corresponding to the identification information of the task entry, and obtains the task entry information from the master device 200 during the interrupt, and obtains the task information based on the task entry information, where the task information includes a position in the master device, a data size, a position that needs to be stored in a queue of the computing device, and the like, and further, the second scheduler 120 pulls down the corresponding task from the master device 200 to the corresponding queue in the computing device 100, where the corresponding task may be one task or multiple tasks, and is determined according to a scheduler policy and the number of tasks that need to be pulled down.

After the second scheduler 120 pulls down to complete the task, the second scheduler 120 synchronizes the identification information corresponding to the task to the synchronous interrupt controller 110, the second scheduler 120 sets the synchronous interrupt controller 110 to indicate whether to send the interrupt to the first scheduler 210, for example, after the task N is completed by the second scheduler 120, the second scheduler 120 synchronizes the identification information corresponding to the task N to the synchronous interrupt controller 110, and the second scheduler 120 sets the synchronous interrupt controller 110 to indicate whether to send the interrupt to the first scheduler 210, which is generated after the identification information of the task entry corresponding to the completed pull-down task is written to the synchronous interrupt controller 110.

In this embodiment, in response to the second scheduler completing the task by pulling down, the second scheduler synchronizes the identification information corresponding to the task to the synchronous interrupt controller; in response to the second scheduler synchronizing the identification information corresponding to the task to the synchronous interrupt controller, the second scheduler 120 sets the synchronous interrupt controller to indicate whether to send the interrupt to the first scheduler, so that the task pull-down based on soft-hard combination is achieved, the synchronization times between the main control end and the computing end are reduced, and the robustness of the computing system is improved.

In some embodiments, in response to the second scheduler 120 synchronizing the identification information corresponding to the task to the synchronous interrupt controller 110, the second scheduler 120 also sets the synchronous interrupt controller 110 to indicate a pull-down enabled state.

In response to the second scheduler 120 synchronizing the identification information corresponding to the task to the synchronous interrupt controller 110, the second scheduler 120 further sets the synchronous interrupt controller 110 to indicate a pull-down enabled state, where the pull-down enabled state indicates that the synchronous interrupt controller 110 can send an interrupt to the second scheduler 120, and the synchronous interrupt controller 110 continues to send the interrupt corresponding to the identification information to the second scheduler 120 according to the pull-down enabled state.

In this embodiment, in response to the second scheduler synchronizing the identification information corresponding to the task to the synchronous interrupt controller, the second scheduler further sets the synchronous interrupt controller to indicate a pull-down enabling state, so that the task pull-down is completed based on soft-hard combination, the synchronization times between the main control end and the computing end are reduced, and the robustness of the computing system is increased.

In some embodiments, as shown in FIG. 2, the synchronous interrupt controller 110 includes a completion interrupt register set 1104, the completion interrupt register set 1104 being used to indicate that the task is completed in a pull down manner, to indicate that the interrupt is complete, and to indicate whether the interrupt is to be sent to the first scheduler 210.

After the second scheduler 120 pulls down to complete the task, the second scheduler 120 synchronizes the identification information corresponding to the task into the synchronous interrupt controller 110, and the completion interrupt register set 1104 indicates that the task is completed in a pull-down manner, so as to indicate that the interrupt corresponding to the identification information corresponding to the task is completed, and indicates whether to send the interrupt to the first scheduler 210, so that the master control device 200 updates the task entry information.

In this embodiment, the synchronous interrupt controller 110 includes a completion interrupt register set, where the completion interrupt register set is used to indicate that the task is pulled down to complete, to indicate whether the interrupt is sent to the first scheduler, so as to achieve that the task is pulled down based on soft-hard combination, reduce the synchronization times between the main control end and the computing end, and increase the robustness of the computing system.

In some embodiments, as shown in FIG. 2, completion interrupt register set 1104 includes completion interrupt status register 11041 and completion interrupt mask register 11042.

Wherein the completion interrupt status register 11041 is used to indicate that the task is completed by pulling down to indicate that the interrupt is completed, and the completion interrupt mask register 11042 is used to indicate whether the interrupt is sent to the first scheduler 210.

The completion interrupt status register 11041 is used for indicating that the task is completed by pulling down, that is, the second scheduler 120 completes the task by pulling down, and synchronizes the identification information corresponding to the task to the synchronous interrupt controller 110. The completion interrupt mask register 11042 is used to indicate whether to send the interrupt to the first scheduler 210, that is, the synchronous interrupt controller 110 in the computing device 100 determines whether to send the corresponding interrupt to the master device 200 according to the corresponding completed interrupt mask condition, and if the completion interrupt is indicated to be enabled, the master device 200 will receive the corresponding interrupt information.

In this embodiment, the completion interrupt status register is used to indicate that the task is pulled down to complete the interrupt, and the completion interrupt mask register is used to indicate whether to send the interrupt to the first scheduler, so that the task is pulled down based on soft-hard combination, the synchronization times between the main control end and the computing end are reduced, and the robustness of the computing system is increased.

In some embodiments, in response to the second scheduler 120 synchronizing the identification information corresponding to the task to the synchronous interrupt controller 110, the synchronous interrupt controller 110 sets the completion interrupt status register 11041 to indicate that the interrupt is complete.

The second scheduler 120 synchronizes the identification information corresponding to the task that has completed the pull-down to the synchronous interrupt controller 110, and the synchronous interrupt controller 110 sets the completion interrupt status register 11041 to indicate that the interrupt corresponding to the task that has completed the pull-down is completed, i.e., records the interrupt in the interrupt status register 11041.

In this embodiment, in response to the second scheduler synchronizing the identification information corresponding to the task to the synchronous interrupt controller, the synchronous interrupt controller sets the interrupt completion status register to indicate that the interrupt is completed, so that the task is completed based on soft and hard combination and is pulled down, the synchronization times between the main control end and the computing end are reduced, and the robustness of the computing system is increased.

In some embodiments, completion interrupt mask register 11042 indicates that the interrupt is to be sent to first scheduler 210 in response to second scheduler 120 synchronizing the identification information corresponding to the task to synchronous interrupt controller 110.

The second scheduler 120 synchronizes the identification information corresponding to the task that has completed the pull-down to the synchronous interrupt controller 110, and the completion interrupt mask register 11042 indicates that the interrupt corresponding to the identification information is transmitted to the first scheduler 210, i.e., the completion interrupt mask register 11042 indicates that the interrupt corresponding to the task that has completed the pull-down can be transmitted to the first scheduler 210.

In this embodiment, in response to the second scheduler synchronizing the identification information corresponding to the task to the synchronous interrupt controller, the completion interrupt mask register indicates to send the interrupt to the first scheduler, so that the task pull-down is completed based on soft-hard combination, the synchronization times between the main control end and the computing end are reduced, and the robustness of the computing system is increased.

Further, in some embodiments, in response to the second scheduler 120 synchronizing the identification information corresponding to the task to the synchronous interrupt controller 110, the synchronous interrupt controller 110 sets the completion interrupt mask register 11042 to indicate that the interrupt disable is sent to the first scheduler 210.

The second scheduler 120 synchronizes the identification information corresponding to the completed task to the synchronous interrupt controller 110, and the synchronous interrupt controller 110 sets the completion interrupt mask register 11042 to indicate that the interrupt is disabled to be sent to the first scheduler 210, i.e., the completion interrupt mask register 11042 indicates that the interrupt corresponding to the completed task is disabled to be sent to the first scheduler 210.

In this embodiment, in response to the second scheduler synchronizing the identification information corresponding to the task to the synchronous interrupt controller, the synchronous interrupt controller sets the interrupt mask completion register to indicate that the interrupt is disabled and sent to the first scheduler, so that the task pull-down is completed based on soft-hard combination, the synchronization times between the main control end and the computing end are reduced, and the robustness of the computing system is increased.

In some embodiments, the synchronous interrupt controller 110 includes a completion interrupt trigger register 1105.

The second scheduler 120 writes the identification information corresponding to the task into the completion interrupt trigger register 1105 such that the value of the completion interrupt trigger register 1105 changes, so that the second scheduler 120 synchronizes the identification information corresponding to the task to the synchronous interrupt controller 110.

The second scheduler 120 synchronizes the identification information corresponding to the task that has completed the pull-down to the synchronous interrupt controller 110, wherein the second scheduler 120 writes the identification information corresponding to the task to the completion interrupt trigger register 1105 such that the value of the completion interrupt trigger register 1105 changes, and further, the completion interrupt mask register 11042 indicates that the interrupt corresponding to the identification information is transmitted to the first scheduler 210, i.e., the completion interrupt mask register 11042 indicates that the interrupt corresponding to the task that has completed the pull-down can be transmitted to the first scheduler 210, so that the second scheduler 120 synchronizes the identification information corresponding to the task to the synchronous interrupt controller 110.

In this embodiment, the second scheduler writes the identification information corresponding to the task into the completion interrupt trigger register, so that the value of the completion interrupt trigger register changes, so that the second scheduler synchronizes the identification information corresponding to the task to the synchronous interrupt controller, thereby realizing the completion of the task pull-down based on soft and hard combination, reducing the synchronization times between the main control end and the computing end, and increasing the robustness of the computing system.

Referring to fig. 3, fig. 3 is a schematic diagram illustrating an embodiment of an electronic device, and an electronic device 300 may include a first device 310 and a second device 320, where the first device 310 is connected to the second device 320.

Wherein the first device 310 may be the master device 200 in the above embodiment, and is provided with a first scheduler 210, such as a Host CPU, for assuming management and control in a computing system; the second Device 320 is the computing Device 100 in the above embodiment, including the synchronous interrupt controller 110 and the second scheduler 120, for example, the second Device 320 may be a Device, where the Device may be general parallel computing hardware similar to a GPU (graphics processing unit, a graphics processing unit), may also be a DPU (Data Processing Unit, a data processor)), may also be an ASIC (Application SPECIFIC INTEGRATED Circuit) hardware unit similar to a DSA, and the computing Device 100 is used to process a computing Task, where the computing Task is divided into at least two tasks, for example Task 1, task 2 … … Task N.

Referring to fig. 4, fig. 4 is a flowchart illustrating an embodiment of a computing task processing method according to the present application. The subject of execution of the method is the second device 320. In some possible implementations, the computing task processing method may be implemented by way of a processor invoking computer readable instructions stored in a memory. Specifically, the method may include the steps of:

Step S41: in response to the identification information being synchronized by the first scheduler to the synchronous interrupt controller, the synchronous interrupt controller generates an interrupt corresponding to the identification information and in response to the synchronous interrupt controller indicating a pull-down enabled state, the synchronous interrupt controller sends the interrupt to the second scheduler, wherein the identification information is used to represent a task entry of one of the at least two tasks.

In response to the identification information for the task entry representing one of the plurality of tasks being synchronized to the synchronous interrupt controller 110 by the first scheduler 210, i.e., the identification information of the task entry of the related task is written to the synchronous interrupt controller 110 by the first scheduler 210, the one of the plurality of tasks may be a task to be issued in the master device 200. After the synchronous interrupt controller 110 synchronizes to the identification information of the task entry of a task, an interrupt corresponding to the identification information is generated, the identification information is the identification information of the task entry of one task of the plurality of tasks, the interrupt corresponding to the identification information indicates that the task corresponding to the identification information needs to be pulled down, and if the synchronous interrupt controller 110 indicates a pull-down enabling state, that is, the pull-down enabling state indicates that the synchronous interrupt controller 110 can send the interrupt to the second scheduler 120, the synchronous interrupt controller 110 sends the interrupt corresponding to the identification information to the second scheduler 120 according to the pull-down enabling state.

Step S42: the second scheduler receives the interrupt and acquires the task entry from the first device during the interrupt, thereby pulling down the task corresponding to the task entry from the first device.

In this embodiment, in response to identification information for representing a task entry of one task of the plurality of tasks being synchronized to the synchronous interrupt controller by the first scheduler, the synchronous interrupt controller generates an interrupt corresponding to the identification information, and in response to the synchronous interrupt controller indicating a pull-down enable state, the synchronous interrupt controller sends the interrupt to the second scheduler, the second scheduler receives the interrupt, and acquires the task entry from the master control device during the interrupt, so that the task corresponding to the task entry is pulled down from the master control device, that is, the task pull-down is completed based on soft-hard combination, the number of times of synchronization between the master control terminal and the computing terminal is reduced, and robustness of the computing system is increased.

Referring to fig. 5, fig. 5 is a flowchart of a computing task processing method according to another embodiment of the application. The subject of execution of the method is the first device 310, and in some possible implementations, the computing task processing method may be implemented by way of a processor invoking computer readable instructions stored in a memory. Specifically, the method may include the steps of:

Step S51: one task is obtained from at least two tasks and is represented as a task entry.

A Task is obtained from a plurality of tasks, and the Task is represented as a Task Entry, that is, a specific Task is identified by using a Task Entry (Entry), for example, task 1 corresponds to Entry1, task 2 corresponds to Entry2, and … … Task N corresponds to Entry N, so that after the address of the first Task Entry is obtained, the subsequent Task Entry address can be obtained according to a certain rule.

Step S52: the method comprises the steps of acquiring identification information of a task item through a first scheduler, synchronizing the identification information of the task item to a synchronous interrupt controller, enabling the synchronous interrupt controller to respond to the identification information to be synchronized, generating an interrupt corresponding to the identification information, responding to the synchronous interrupt controller to indicate a pull-down enabling state, sending the interrupt to a second scheduler, receiving the interrupt by the second scheduler, acquiring the task item from a first device during the interrupt, and accordingly pulling down the task corresponding to the task item from the first device.

The identification information of the task item, that is, the identification information of the task item representing one of the plurality of tasks is acquired through the first scheduler 210. And synchronizes the identification information of the task item to the synchronous interrupt controller 110 so that the synchronous interrupt controller 110 generates an interrupt corresponding to the identification information in response to the identification information being synchronized, the interrupt corresponding to the identification information indicating that the task corresponding to the identification information needs to be pulled down. And in response to the synchronous interrupt controller 110 indicating a pull-down enabled state, that is, the pull-down enabled state indicates that the synchronous interrupt controller 110 can send an interrupt to the second scheduler 120, and then send the interrupt to the second scheduler 120, the second scheduler 120 receives the interrupt and obtains the task entry during the interrupt, that is, parses the identification information of the task entry to obtain the task entry, thereby realizing the pull-down of the task corresponding to the task entry.

In this embodiment, the first scheduler acquires the identification information of the task entry, and synchronizes the identification information of the task entry to the synchronous interrupt controller, so that the synchronous interrupt controller generates an interrupt corresponding to the identification information in response to the identification information being synchronized, and sends the interrupt to the second scheduler in response to the synchronous interrupt controller indicating a pull-down enabling state, the second scheduler receives the interrupt, and acquires the task entry from the first device during the interrupt, thereby pulling down the task corresponding to the task entry from the first device, that is, completing the task pull-down based on soft-hard combination, reducing the number of times of synchronization between the master control end and the computing end, and increasing the robustness of the computing system.

In some embodiments, the identification information of the task entry includes address information or index information of the task entry.

The main control device 200 associates the organized task with a specific entry, specifically, the identification information of the task entry includes address information or index information of the task entry, for example, an address or index information of the current entry.

Further, in some embodiments, in response to a task being a first task of the at least two tasks, the synchronous interrupt controller is initialized prior to acquiring the task such that the synchronous interrupt controller indicates an interrupt enable state.

If the task is the first task of the at least two tasks, before the task is acquired, the master device 200 initializes the synchronous interrupt controller 110 such that the synchronous interrupt controller 110 indicates an interrupt enable state, specifically, in response to the synchronous interrupt controller 110 indicating an interrupt enable state and the task is the first task of the plurality of tasks, the synchronous interrupt controller 110 sends the interrupt to the second scheduler 120, that is, when the computing device 100 receives the task for the first time, for example, identification information corresponding to the first task of the plurality of tasks is written into the pull-down interrupt trigger register 1102 through the first scheduler 210, so that a value of the pull-down interrupt trigger register 1102 is changed, and an interrupt corresponding to the identification information is generated, and the interrupt is enabled in the initialization stage, that is, the interrupt is sent into the second scheduler 120.

Further, in some embodiments, the interrupt is received by the first scheduler in response to the synchronous interrupt controller indicating to send the interrupt to the first scheduler; in response to receiving the interrupt through the first scheduler, viewing identification information corresponding to the interrupt from the synchronous interrupt controller and updating the task entry according to the identification information.

The synchronous interrupt controller 110 instructs to send an interrupt of the identification information corresponding to the completed pull-down task to the first scheduler 210, receives the interrupt through the first scheduler 210, checks the identification information corresponding to the interrupt from the synchronous interrupt controller 110, and updates the task entry according to the identification information, i.e. the master device 200 receives the interrupt information, can check the identification information corresponding to the interrupt from the synchronous interrupt controller 110, and then updates the related information of the task entry in the master device 200 according to the specific information thereof.

For ease of understanding, the process flow of the first Task of the plurality of tasks is illustrated in fig. 6, where fig. 6 is a schematic flow chart of an embodiment of Task processing according to the present application, and software organizes tasks to be calculated into tasks in a plurality of columns, such as Task 1 … … Task n+1, where physical addresses between the plurality of tasks may be continuous or discontinuous.

Step 61: the first scheduler 210 acquires a first Task, i.e., task 1, from among the plurality of tasks, and represents the Task as a Task Entry, i.e., entry 1 corresponding to Task 1.

Step 62: the identification information of the task Entry (i.e., entry 1) is written to the pull-down interrupt trigger register 1102 by the first scheduler 210, at which point the value of the pull-down interrupt trigger register 1102 changes, thereby triggering an interrupt.

Step 63: the interrupt enable register 1103 indicates an interrupt enable status.

Step 64: because the interrupt enable register 1103 indicates the interrupt enable status, the interrupt (i.e., the interrupt corresponding to Task 1 or Entry 1) is sent to the second scheduler 120.

Step 65: the pull-down interrupt status register 11011 is set to indicate the interrupt, and at the same time, after the interrupt (i.e., the interrupt corresponding to Task 1 or Entry 1) is sent to the second scheduler, the pull-down interrupt mask register 11012 is set to indicate the pull-down disabled state.

Step 66: the second scheduler 120 parses the identification information of the task Entry, and further obtains the corresponding task Entry, i.e., entry 1, from the master device 200, and parses the task Entry.

Step 67: the second scheduler 120 obtains the corresponding Task information and pulls down the corresponding Task (i.e., task 1) from the master device to the local, e.g., to the local corresponding Task queue.

Step 68: after the second scheduler 120 completes the pull-down action of the Task (i.e., task 1), the identification information of the Task entry of the Task (i.e., task 1) is written into the completion interrupt trigger register 1105, at which time the value of the completion interrupt trigger register 1105 changes, and at the same time, the pull-down interrupt mask register 11012 is operated so as to indicate from the pull-down disabled state to the pull-down enabled state, so that the subsequent interrupt is sent to the second scheduler 120.

Step 69: after the value of the completion interrupt trigger register 1105 changes, the completion interrupt status register 11041 is set.

Step 610: the completion interrupt mask register 11042 indicates enable, and the synchronous interrupt controller 110 sends the interrupt to the master device 200, at which point the master device 200 will receive the interrupt.

Step 611: the master device 200 sets the completion interrupt mask register 11042 to indicate disable, and the synchronous interrupt controller 110 does not send the interrupt to the master device 200, at which point the master device 200 may look at the completion interrupt status register 11041 in a polling manner to obtain that the computing device 100 has completed a task pull down.

For easy understanding, the process flow of the non-first Task of the tasks is illustrated in fig. 7, fig. 7 is a schematic flow diagram of a Task processing another embodiment of the present application, where the software organizes the tasks to be calculated into tasks in some columns, such as Task 1 … … Task n+1, where physical addresses between the tasks may be continuous or discontinuous.

Step 71: the first scheduler 210 acquires a Task, i.e., task N, from among a plurality of tasks, and represents the Task as a Task Entry, i.e., entry N corresponding to the Task N.

Step 72: the identification information of the task Entry (i.e., entry N) is written to the pull-down interrupt trigger register 1102 by the first scheduler 210, at which point the value of the pull-down interrupt trigger register 1102 changes, thereby triggering an interrupt.

Step 73: the pull-down interrupt status register 11011 is set to indicate the interrupt, and at the same time, after the interrupt (i.e., the interrupt corresponding to Task 1 or Entry 1) is sent to the second scheduler, the pull-down interrupt mask register 11012 is set to indicate the pull-down disabled state.

Step 74: the drop down interrupt mask register 11012 indicates a drop down enable state and the interrupt (i.e., the interrupt corresponding to Task N or Entry N) is sent to the second scheduler 120.

Step 75: the second scheduler 120 parses the identification information of the task Entry, and further obtains the corresponding task Entry, i.e., for example, entry N, from the master device 200, and parses the task Entry.

Step 76: the second scheduler 120 obtains the corresponding Task information and pulls down the corresponding Task (i.e., task 1) from the master device to the local, e.g., to the local corresponding Task queue.

Step 77: after the second scheduler 120 completes the pull-down action for the Task (i.e., task N), the identification information of the Task entry for the Task (i.e., task 1) is written to the completion interrupt trigger register 1105, at which point the value of the completion interrupt trigger register 1105 changes, and at the same time, the pull-down interrupt mask register 11012 is operated so as to indicate from the pull-down disabled state to the pull-down enabled state, so that the subsequent interrupt is sent to the second scheduler 120.

Step 78: after the value of the completion interrupt trigger register 1105 changes, the completion interrupt status register 11041 is set.

Step 79: the completion interrupt mask register 11042 indicates enable, and the synchronous interrupt controller 110 sends the interrupt to the master device 200, at which point the master device 200 will receive the interrupt.

Step 710: the master device 200 sets the completion interrupt mask register 11042 to indicate disable, and the synchronous interrupt controller 110 does not send the interrupt to the master device 200, at which point the master device 200 may look at the completion interrupt status register 11041 in a polling manner to obtain that the computing device 100 has completed a task pull down.

It will be appreciated by those skilled in the art that in the above-described method of the specific embodiments, the written order of steps is not meant to imply a strict order of execution but rather should be construed according to the function and possibly inherent logic of the steps.

Referring to fig. 8, fig. 8 is a schematic frame diagram of an electronic device according to another embodiment of the application. The electronic device 800 comprises a memory 810 and a processor 820 coupled to each other, the processor 820 being adapted to execute program instructions stored in the memory 810 for implementing the steps of the above-described embodiments of the computing task processing method.

Referring to fig. 9, fig. 9 is a schematic frame diagram of another embodiment of the electronic device according to the present application. The electronic device 900 comprises a processor 910, and a memory 920 and a computing device 930 coupled to the processor 910, where the processor 910 is configured to execute program instructions stored in the memory 910 to implement the above-mentioned computing task processing method, and the computing device 930 is configured to implement, in operation, the above-mentioned computing task processing method. In one particular implementation scenario, electronic device 900 may include, but is not limited to: the microcomputer and the server, and the electronic device 900 may also include mobile devices such as a notebook computer and a tablet computer, which are not limited herein.

In some embodiments, functions or modules included in an apparatus provided by the embodiments of the present disclosure may be used to perform a method described in the foregoing method embodiments, and specific implementations thereof may refer to descriptions of the foregoing method embodiments, which are not repeated herein for brevity.

The foregoing description of various embodiments is intended to highlight differences between the various embodiments, which may be the same or similar to each other by reference, and is not repeated herein for the sake of brevity.

In the several embodiments provided in the present application, it should be understood that the disclosed method and apparatus may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of modules or units is merely a logical functional division, and there may be additional divisions of actual implementation, e.g., units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical, or other forms.

In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to execute all or part of the steps of the methods of the embodiments of the present application. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

Claims

1. A computing device, wherein the computing device is connected to a master device, the master device having a first scheduler installed therein; the computing device is used for processing a computing task, and the computing task is divided into at least two tasks;

the computing device includes a synchronous interrupt controller and a second scheduler coupled to the synchronous interrupt controller, wherein:

The synchronous interrupt controller generates an interrupt corresponding to the identification information in response to the identification information being synchronized to the synchronous interrupt controller by the first scheduler, and transmits the interrupt to the second scheduler in response to the synchronous interrupt controller indicating a pull-down enabling state; the identification information is used for representing a task item of one task of the at least two tasks;

The second scheduler receives the interrupt and acquires the task item from the main control equipment during the interrupt, so that the task corresponding to the task item is pulled down from the main control equipment.

2. The computing device of claim 1, wherein the synchronous interrupt controller is further to indicate the interrupt in response to the identification information being synchronized to the synchronous interrupt controller by the first scheduler.

3. The computing device of claim 1, wherein the synchronous interrupt controller records the interrupt in response to the synchronous interrupt controller not sending the interrupt to the second scheduler and indicating a pull-down disabled state.

4. The computing device of claim 1, wherein the synchronous interrupt controller indicates a pull-down disabled state in response to the second scheduler receiving the interrupt.

5. The computing device of any of claims 1-4, wherein the synchronous interrupt controller comprises a set of pull-down interrupt registers to indicate or record the interrupt and to indicate the pull-down enabled state or the pull-down disabled state.

6. The computing device of claim 5, wherein the set of pull-down interrupt registers includes a pull-down interrupt status register to indicate or record the interrupt and a pull-down interrupt mask register to indicate the pull-down enable state or the pull-down disable state.

7. The computing device of claim 6, wherein the synchronous interrupt controller sets the pull-down interrupt status register to indicate the interrupt in response to the identification information being synchronized to the synchronous interrupt controller by the first scheduler.

8. The computing device of claim 6, wherein the synchronous interrupt controller is to set the pull-down interrupt mask register to indicate the pull-down disabled state in response to the second scheduler receiving the interrupt.

9. The computing device of claim 8, wherein the synchronous interrupt controller is further to clear the pull-down interrupt status register in response to the second scheduler receiving the interrupt.

10. The computing device of any of claims 1-4, wherein the synchronous interrupt controller comprises a pull-down interrupt trigger register;

The identification information is written to the pull-down interrupt trigger register by the first scheduler such that a value of the pull-down interrupt trigger register is changed such that the identification information is synchronized to the synchronous interrupt controller by the first scheduler.

11. The computing device of any of claims 1-4, wherein the synchronous interrupt controller is initialized by the master device such that the synchronous interrupt controller indicates an interrupt enable state;

In response to the synchronous interrupt controller indicating the interrupt enable state and the task being a first task of the at least two tasks, the synchronous interrupt controller sends the interrupt to the second scheduler.

12. The computing device of claim 11, wherein the synchronous interrupt controller comprises an interrupt enable register to be initialized by the master device to indicate the interrupt enable state.

13. The computing device of any of claims 1-4, wherein in response to the second scheduler pulling down to complete the task, the second scheduler synchronizes the identification information corresponding to the task to the synchronized interrupt controller;

And responding to the second scheduler to synchronize the identification information corresponding to the task to the synchronous interrupt controller, and setting the synchronous interrupt controller by the second scheduler to indicate whether to send the interrupt to the first scheduler.

14. The computing device of claim 13, wherein in response to the second scheduler synchronizing the identification information corresponding to the task to the synchronous interrupt controller, the second scheduler further sets the synchronous interrupt controller to indicate the pull-down enabled state.

15. The computing device of claim 13, wherein the synchronous interrupt controller comprises a completion interrupt register set to indicate that the task is completed by pulling down to indicate that the interrupt is complete and to indicate whether to send the interrupt to the first scheduler.

16. The computing device of claim 15, wherein the set of completion interrupt registers includes a completion interrupt status register to indicate that the task is completed by pulling down and a completion interrupt mask register to indicate whether to send the interrupt to the first scheduler.

17. The computing device of claim 16, wherein in response to the second scheduler synchronizing the identification information corresponding to the task to the synchronous interrupt controller, the synchronous interrupt controller sets the completion interrupt status register to indicate that the interrupt is complete.

18. The computing device of claim 16, wherein the completion interrupt mask register indicates that the interrupt is to be sent to the first scheduler in response to the second scheduler synchronizing the identification information corresponding to the task to the synchronized interrupt controller.

19. The computing device of claim 18, wherein in response to the second scheduler synchronizing the identification information corresponding to the task to the synchronous interrupt controller, the synchronous interrupt controller sets the completion interrupt mask register to indicate that interrupt disabling is sent to the first scheduler.

20. The computing device of claim 13, wherein the synchronous interrupt controller comprises a completion interrupt trigger register;

The second scheduler writes the identification information corresponding to the task into the completion interrupt trigger register so as to change the value of the completion interrupt trigger register, and therefore the second scheduler synchronizes the identification information corresponding to the task to the synchronous interrupt controller.

21. A computing task processing method, characterized in that it is applied to a second device, said second device being a computing device according to any one of claims 1-20, connected to a first device, said first device being installed with a first scheduler, said computing task being divided into at least two tasks; the method comprises the following steps:

The synchronous interrupt controller generates an interrupt corresponding to the identification information in response to the identification information being synchronized to the synchronous interrupt controller through the first scheduler, and transmits the interrupt to the second scheduler in response to the synchronous interrupt controller indicating a pull-down enabling state, wherein the identification information is used for indicating a task entry of one task of the at least two tasks;

The second scheduler receives the interrupt and acquires the task item from the first device during the interrupt, so that the task corresponding to the task item is pulled down from the first device.

22. A computing task processing method, characterized in that the computing task processing method is applied to a first device, the first device is connected with a second device, the first device is provided with a first scheduler, the second device comprises a synchronous interrupt controller and a second scheduler, and the computing task is divided into at least two tasks; the method comprises the following steps:

acquiring a task from the at least two tasks, and representing the task as a task item;

And acquiring the identification information of the task item through the first scheduler, and synchronizing the identification information of the task item to the synchronous interrupt controller, so that the synchronous interrupt controller responds to the identification information to generate an interrupt corresponding to the identification information, and responds to the synchronous interrupt controller to indicate a pull-down enabling state, the interrupt is sent to the second scheduler, and the second scheduler receives the interrupt and acquires the task item from the first device during the interrupt, thereby pulling down the task corresponding to the task item from the first device.

23. The method of claim 22, wherein the identification information of the task item includes address information or index information of the task item.

24. The method of claim 23, wherein the method further comprises:

and initializing the synchronous interrupt controller before acquiring the task in response to the task being the first task of the at least two tasks, so that the synchronous interrupt controller indicates an interrupt enable state.

25. The method according to claim 22, wherein the method further comprises:

Transmitting the interrupt to the first scheduler in response to the synchronous interrupt controller indication, receiving the interrupt by the first scheduler;

In response to receiving the interrupt through the first scheduler, viewing the identification information corresponding to the interrupt from the synchronous interrupt controller, and updating the task entry according to the identification information.

26. An electronic device comprising a memory and a processor coupled to each other, the processor configured to execute program instructions stored in the memory to implement the computing task processing method of any of claims 22 to 25.

27. An electronic device comprising a processor, and a memory and a computing device coupled to the processor, the computing device being the computing device of any one of claims 1 to 20, the processor to execute program instructions stored in the memory to implement the computing task processing method of any one of claims 22 to 25.