CN117950476A - Reliable power-down data retention and recovery method based on FPGA - Google Patents
Reliable power-down data retention and recovery method based on FPGA Download PDFInfo
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Abstract
The invention provides a reliable power-down data retention and recovery method based on an FPGA. The design key points are signal filtering, FPGA fitting matching, power supply switching, embedded interrupt protection, read-write MRAM, and the core part is the identification of different power failure modes and the reliable recovery of data. Compared with the traditional scheme in the market, the method has the characteristics of high reliability, stable and nonvolatile data retention, low cost, sensitive response and strong adaptability.
Description
Technical Field
The invention belongs to the field of computer storage, and particularly relates to a reliable power-down data maintaining and recovering method based on an FPGA.
Background
In the control system of the gas turbine, the user configuration engineering and the core control parameters in the engineering such as PID parameters, brake-opening rotation speed, throttle position and the like are important, and the parameters not only record the current running state of the controlled object, but also represent the core performance and the special vector of the control system. Therefore, in the gas engine controller, the preservation of key core data and the recovery of core data after failure are of great importance.
At present, two types of key core data storage schemes exist in the industry, one type is to adopt data guiding, namely, a user stores user engineering after downloading the user engineering, and key core data is directly stored according to user selection and setting when the key core data is encountered. If the user performs the project downloading for the second time, the controller compares the project in the current Flash with the project which needs to be downloaded at the time, and adopts deflection transmission, and particularly, see fig. 1. The other scheme is that two storage devices, one NAND FLASH and one SRAM are directly adopted, user engineering is stored in NAND FLASH, programs are run in the SRAM, when the controller fails, the controller stops running, other peripheral devices of the controller gradually lose power at the moment, and the SRAM is switched to a standby battery to supply power, specifically, the scheme II is seen.
The scheme one is clear, the time of each writing can be saved in theory by adopting the displacement transmission, but the development difficulty requirement on an operating system is extremely high, before each writing, the embedded code needs to know that the data areas are changed firstly, and meanwhile, when the data are actually written, the current data are read from NAND FLASH firstly, because NAND FLASH is a paging operation; and another problem with this scheme is that it has a large vulnerability to the protection of node information. If the controller is powered down at this time while data is being written, node information will be lost or corrupted, which is fatal to data recovery.
The second main technical difficulty of the scheme is the cruising ability and anti-interference performance of the battery. The influence of power-down factors and the problem of power-down data writing do not need to be considered too much in the hardware design process. However, a fatal problem is that when the module is powered down for a long time, the backup battery may lose power, and after the power is lost, the data stored in the SRAM will be completely lost. This is also fatal to the data recovery. Another fatal effect is that the output signal is easily affected by external interference due to the low output voltage of the battery during the operation, and if the voltage drops or overvoltage occurs during the affected operation, the data in the SRAM is lost.
Disclosure of Invention
The invention aims to solve the difficult problem that core data of a core controller are difficult to maintain and recover when a power failure occurs to a gas turbine, and provides a reliable power-down data maintaining and recovering method based on an FPGA.
A reliable power-down data maintaining and recovering method based on FPGA includes the following steps:
S1: the power failure detection part circuit is designed by utilizing hardware, and when an input power supply falls and falls, a subsequent system is rapidly identified and informed;
s2: filtering the signals in real time through an FPGA to filter out high-frequency components in the signals;
s3: fitting and matching the filtered signals through an FPGA, recording and searching a self-recorded curve library in real time by the FPGA, and accurately identifying whether the current fault is voltage drop or short-time interruption through matching;
S4: judging whether to switch the standby power supply or not through hardware, if the fault occurs, directly switching the hardware to the standby power supply, ensuring that the interrupt processing function reliably runs completely and recording correct node information;
S5: the system stops the execution of all auxiliary functions once the interrupt service routine is entered by the interrupt processing function to quickly respond to external signals, directly records the key data set by a user and backups, records the fault reason, and facilitates the fault analysis;
S6: through a flexible MRAM data protection mechanism, the user key data can be recorded accurately and reliably, and even if abnormal writing occurs, the backup data can be ensured to be accurate.
Further, in the step S1, the system is divided into 3 power domains in hardware, wherein the 24V input part of the system is a first power domain, the FPGA part is a second power domain, and the main CPU part is a third power domain.
Further, in the step S3, the FPGA is used for carrying out fitting matching on the filtered signals, the FPGA is used for recording the signals in real time, a trusted reset signal module is built in the FPGA, the signals are collected by a high-speed ADC real-time sampling module in the early stage of judgment and recorded by the signal characteristics, the recorded signal characteristics are directly placed in the NOR Flash through a bin file, and the signals are matched through table lookup in actual use.
Further, the MRAM data protection mechanism in S6 introduces the current read address, the current write address, the last write OK flag, and divides the MRAM into 4 slices, and introduces a hardware flag signal, and cuts off the write operation of the MRAM when the signal fails, so as to ensure the correctness of the written information.
The invention has the beneficial effects that: the invention has the advantages of extremely low cost, no need of high-cost devices, simple design and strong adaptability, and can greatly exert advantages in the opposite direction to the specific interference under the specific environment.
Drawings
FIG. 1 is a block diagram of a conventional scheme;
FIG. 2 is a block diagram of a conventional scheme II;
FIG. 3 is a block diagram of the design of the present invention;
FIG. 4 is a general design of the present invention;
FIG. 5 is a method of designing a sliding filter window of an FPGA;
FIG. 6 is a FPGA fitting state machine;
FIG. 7 is a schematic diagram of an MRAM operating state machine;
Fig. 8 is a signal_filter filter block.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
The invention provides a brand-new reliable power-down data maintaining and recovering method based on an FPGA. The design core of the invention is based on the data type, the user engineering belongs to write-once data, the user engineering is directly written into NAND FLASH in the design, the starting data of the controller is directly stored in Nor Flash, the key data of the user is backed up to the MRAM every cycle, and the MRAM data is powered down to the nonvolatile memory, so that the write-many times can be carried out. The design core of the invention is the read-write mechanism of the MRAM and the recognition and recording of the power failure event and the recovery mechanism of the data in failure.
As shown in fig. 4, a reliable power-down data retention and recovery method based on FPGA includes the following steps:
S1: the power failure detection part circuit is designed by utilizing hardware, and when an input power supply falls and falls, a subsequent system is rapidly identified and informed;
The system is divided into 3 power domains in hardware, wherein a 24V input part of the system is a first power domain, an FPGA part is a second power domain, and a main CPU part is a third power domain. In the design, the second power domain adopts a rechargeable battery to supply power, so that the FPGA can still monitor the system in real time after the system is powered down. And the third power domain adopts 24V input power supply when the system power supply is normal, and after the system abnormality is detected, the subsequent backup power supply is directly completed by matching the Faraday capacitor with a Boost circuit, so that the power supply does not need a long time, and only the correct writing of data by the MRAM is ensured to be completed.
The core invention point of the scheme is that the traditional Farad capacitor or 18650 battery is not adopted in the power supply switching circuit part, but a plate and a capacitor are matched with the Farad capacitor and a Boost circuit to jointly complete the split power supply. The advantage of using this scheme is that a dip in the input voltage instant due to the response time of the integrated IC itself at the power supply switching instant can be avoided. Such a drop will directly cause a subsequent stage system reset. The design adopts the hardware capacitor to realize the 5V fault of the 24V fault alarm system to keep for 30ms, the establishment of the Farad capacitor and the output signal of the Boost circuit is completed in the time, and the 30ms can be adjusted according to the response time of the Boost circuit which is actually selected.
S2: filtering the signals in real time through an FPGA to filter out high-frequency components in the signals;
The FPGA sliding filter window part is realized by adopting a RAM, and a filtering algorithm block which can be configured according to the threshold value of an input signal is completed in the design, wherein a specific logic block diagram is shown in a part of fig. 5, and the filtering algorithm block is shown in a part of fig. 8. The module has the main function of performing burr filtering on the on-site primary signal. Since the field module is in the interference environment, one signal level may be negative with a plurality of burrs from high to low, and jitter of several microseconds or even several nanoseconds may occur at the high level or the low level of the field due to the interference signal. For the interference signal, the module adopts the RAM block to identify and record the number of signals 1 and the number of signals 0 in the RAM block, and confirms whether the output signal is in a high level or a low level through a high level and a low level threshold range input by a user. The minimum writing period and the RAM depth of the signals when the signals are written into the RAM block directly influence the filtering effect of the actual signals, the field actual signals are input into a module aiming at the filtering depth and the filtering interval in the design, and the minimum acquisition period of the filtering block is adjusted and recorded. After the minimum acquisition period is recorded, the module optimizes parameters and outputs all waveforms meeting the conditions according to the set value of the client in the FPGA, and the client confirms the actually needed output waveforms. The method provides a basis for strictly quantifying on-site signals into subsequent signal fitting through four steps of signal acquisition design, minimum acquisition interval determination, FPGA optimization parameters and FPGA signal output confirmation.
The core invention point of the scheme is to adopt RAM and FPGA parameter optimization to realize the removal of high-frequency interference signals.
S3: fitting and matching the filtered signals through an FPGA, recording and searching a self-recorded curve library in real time by the FPGA, and accurately identifying whether the current fault is voltage drop or short-time interruption through matching;
Wherein, the design state machine of the FPGA fitting part is shown in the part of figure 6; the part mainly completes the action waveform data recording and the actual action instruction sending. In the design, at the initial stage of power-on of the re-module, signal modeling is required to be carried out according to a trusted action signal input on site, the signal modeling is carried out by adopting an FPGA (field programmable gate array) to record signals in real time, a trusted reset signal module is built in the FPGA, the module is built by adopting actual waveform recording instead of traditional multiple data fitting, and the traditional fitting is used for inserting unknown information at an un-sampled point, wherein the unknown information is not really unknown but is useful signal loss caused by signal sampling. The design fully utilizes the high-speed response of the FPGA and the ultra-high-speed sampling of the high-speed ADC, and directly digitizes signals and records the signals in the RAM. After the field waveform is input, the field waveform is directly searched from the returned trusted table through a table lookup matching scheme, if the signals are consistent, an action signal is output, and if the signals are inconsistent, the response is ignored.
The key invention point of the scheme is that a high-speed ADC real-time sampling module is adopted to collect signals and record the signal characteristics in the early stage of judgment, the recorded signal characteristics are directly placed in NOR Flash through bin files, and the recorded signal characteristics are matched through table lookup in actual use.
S4: judging whether to switch the standby power supply or not through hardware, if the fault occurs, directly switching the hardware to the standby power supply, ensuring that the interrupt processing function reliably runs completely and recording correct node information;
S5: the system stops the execution of all auxiliary functions once the interrupt service routine is entered by the interrupt processing function to quickly respond to external signals, directly records the key data set by a user and backups, records the fault reason, and facilitates the fault analysis;
S6: through a flexible MRAM data protection mechanism, the user key data can be recorded accurately and reliably, and even if abnormal writing occurs, the backup data can be ensured to be accurate.
The MRAM data read-write mechanism part of the state machine is shown in fig. 7, in which MRAM is mainly used for writing data and recovering data after failure occurs, and the core thought of MRAM is to use the continuous operability and fast writing characteristics of MRAM addresses. The core of the design, which is different from the conventional operation, is that the design adopts 4-patch operation, and compared with the conventional double-patch operation, two backup patches are added. The conventional operation always divides the MRAM into two slices, namely, writing for the current A slice and writing for the next B slice, the scheme is simple in operation, but when faults occur, such as the A slice fails in the writing process, after the second power-on, the module cannot guide the acquisition of data from the slice. The design adopts two conventional writing areas and two backup writing areas, and introduces a hardware detection signal in the design, and once a fault is detected, the writing of data of the MRAM is stopped. In addition, the design introduces three variables of the read address, the write address and the last write OK mark to judge whether the data can be obtained, if any error exists in the read address, the write address and the last write OK mark, the program jumps into the backup area for data reading, the data of the backup area is written in a program running gap and updated in real time after the writing of the main data area is completed, and if the backup area writing failure program is found, the program is rewritten in the next running. Until the write is correct.
The key invention point of the scheme is to introduce the read address, the write address and the OK mark written last time and divide the MRAM into 4 areas, and introduce the hardware mark signal, cut off the write operation of the MRAM when the signal fails, and ensure the correctness of the written information.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (4)
1. The reliable power-down data maintaining and recovering method based on the FPGA is characterized by comprising the following steps of:
S1: the power failure detection part circuit is designed by utilizing hardware, and when an input power supply falls and falls, a subsequent system is rapidly identified and informed;
s2: filtering the signals in real time through an FPGA to filter out high-frequency components in the signals;
s3: fitting and matching the filtered signals through an FPGA, recording and searching a self-recorded curve library in real time by the FPGA, and accurately identifying whether the current fault is voltage drop or short-time interruption through matching;
S4: judging whether to switch the standby power supply or not through hardware, if the fault occurs, directly switching the hardware to the standby power supply, ensuring that the interrupt processing function reliably runs completely and recording correct node information;
S5: the system stops the execution of all auxiliary functions once the interrupt service routine is entered by the interrupt processing function to quickly respond to external signals, directly records the key data set by a user and backups, records the fault reason, and facilitates the fault analysis;
S6: through a flexible MRAM data protection mechanism, the user key data can be recorded accurately and reliably, and even if abnormal writing occurs, the backup data can be ensured to be accurate.
2. The method for maintaining and recovering reliable power-down data based on FPGA as claimed in claim 1, wherein the system is divided into 3 power domains in hardware in S1, wherein the 24V input part of the system is a first power domain, the FPGA part is a second power domain, and the main CPU part is a third power domain.
3. The reliable power-down data maintaining and recovering method based on the FPGA according to claim 1, wherein the FPGA in the S3 is used for carrying out fitting matching on the filtered signals by adopting the FPGA to record signals in real time, a reliable reset signal module is built in the FPGA, the signals are collected by adopting a high-speed ADC real-time sampling module in the early stage of judgment and the signal characteristics are recorded, the recorded signal characteristics are directly placed in NOR Flash through a bin file, and the signals are matched through table lookup in actual use.
4. The method for maintaining and recovering reliable power-down data based on FPGA as claimed in claim 1, wherein the MRAM data protection mechanism in S6 introduces the current read address, the current write address, the last write OK flag and divides the MRAM into 4 slices, and introduces a hardware flag signal, cuts off the write operation of the MRAM when the signal fails, and ensures the correctness of the written information.
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