CN117940783A - System and method for post-manufacturing repair of minimum delay violations - Google Patents

Abstract

A system and method of testing an integrated circuit provides a first clock signal to a first flip-flop having an output to a functional circuit; providing a second clock signal to a second flip-flop, the second flip-flop having an input from the functional circuit, wherein the second flip-flop has a minimum hold time; providing a test input to a first flip-flop; observing the signal propagation time through the functional circuit; determining that the signal propagation time is less than a minimum hold time of the second flip-flop; and increasing the timing interval by adding or subtracting the delay unit to or from the first clock signal.

Description

System and method for post-manufacturing repair of minimum delay violations

Related patent application

The present application claims priority from commonly owned U.S. provisional patent application 63/307,098 filed on 5/2/2022, which is hereby incorporated by reference.

Technical Field

The application relates to post-fabrication verification of integrated circuits.

Background

Integrated Circuits (ICs) are often tested after manufacture to ensure operability under normal and extreme conditions. Only ICs with setup violations may be downgraded and sold as part of lower performance. However, even an IC with a hold violation must be discarded.

Disclosure of Invention

In some examples, a method of testing an integrated circuit is provided, the method comprising: providing a first clock signal to a first flip-flop, the first flip-flop having an output to a functional circuit; providing a second clock signal to a second flip-flop, the second flip-flop having an input from the functional circuit, wherein the second flip-flop has a minimum hold time; providing a test input to a first flip-flop; observing the signal propagation time through the functional circuit; determining that the signal propagation time is less than a minimum hold time of the second flip-flop; and increasing the timing interval (timing separation) by adding or subtracting a delay unit to or from the first clock signal in response to determining that the signal propagation time is less than the minimum hold time of the second flip-flop. In some examples, the method includes: observing a second time of signal propagation time through the functional circuit after adding the delay element to the first clock signal; determining that the second signal propagation delay is less than a minimum hold time of the second flip-flop; and adding a second delay unit to the first clock signal. In some examples, the method includes determining a timing interval that cannot be further increased, and marking the integrated circuit to be discarded. In some examples, the method includes storing the delay cells in a non-volatile memory. In some examples, the functional circuit is a combinational logic path through a pipeline stage of the processor, and the method includes performing a static timing analysis of the pipeline stage and identifying the functional circuit as having a fastest signal propagation time in any path through the pipeline stage. In some examples, the method includes generating a first delayed clock signal by passing the master clock signal through a first delay circuit and generating a second delayed clock signal by passing the master clock signal through a second delay circuit, wherein adding the delay unit to the first clock signal includes selecting the first delayed clock signal as the first clock signal. In some examples, the second flip-flop has a minimum setup time, and the method includes observing a setup violation in the second flip-flop after increasing the timing interval, and degrading a maximum frequency of the integrated circuit.

In some examples, a system for testing an integrated circuit is provided, the system comprising: a first clock signal line to a first flip-flop having an output to the functional circuit; a second clock signal to a second flip-flop, the second flip-flop having an input from the function, wherein the second flip-flop has a minimum hold time; a test circuit coupled to an input of the first flip-flop and an output of the functional circuit to determine whether the signal has propagated through the function within a first propagation time that is less than a minimum hold time of the second flip-flop; and a first delay selection circuit coupled between the master clock signal line and the first clock signal line to selectively add or subtract delay cells; and a second delay selection circuit coupled between the master clock signal line and the second clock signal line. In some examples, the delay selection circuit selectively adds two delay cells to the first clock signal. In some examples, the test circuit includes a timer having a start input coupled to the first clock signal line and a stop input coupled to the output of the functional circuit. In some examples, the integrated circuit includes a non-volatile memory coupled to the delay selection circuit to store the cell delay count. In some examples, the functional circuit is a combinational logic path through a pipeline stage of the processor. In some examples, the delay selection circuit includes one unit clock delay buffer coupled to the master clock signal line, two unit clock delay buffers coupled to the master clock signal line, and a selector having an output coupled to the first clock signal line and a plurality of inputs coupled to each of the master clock signal, the output of the one unit clock delay buffer, and the output of the two unit clock delay buffers. In some examples, the test circuit includes: a timer for determining a signal propagation delay; an adder for adding a minimum setting time of the second flip-flop; and a comparator for signaling an unrepairable condition when the signal propagation delay plus a minimum setup time of the second flip-flop is greater than a cycle time of the clock signal on the second clock line.

In some examples, an integrated circuit includes: a first clock signal line to a first flip-flop having an output terminal to the functional circuit; a second clock signal to a second flip-flop, the second flip-flop having an input from the function, wherein the second flip-flop has a minimum hold time; a non-transitory memory for storing the delay amount; a first delay circuit that couples the master clock signal line to the first clock signal line to generate a first clock signal by delaying the master clock signal by an amount specified by the delay amount; and a second delay circuit coupling the master clock signal line to the second clock signal line. In some examples, the non-transitory memory is non-volatile. In some examples, the functional circuit is a combinational logic path through a pipeline stage of the processor. In some examples, the first delay circuit includes one unit clock delay buffer coupled to the master clock signal line, two unit clock delay buffers coupled to the master clock signal line, and a selector having an output coupled to the first clock signal line and a plurality of inputs coupled to the master clock signal, an output of the one unit clock delay buffer, and an output of each of the two unit clock delay buffers. In some examples, the integrated circuit includes a delay selection circuit coupled between the master clock signal line and the clock signal line at each pipeline stage of the processor. In some examples, the delay circuit includes a first clock delay buffer coupled to the master clock signal line and the intermediate line, a second clock delay buffer coupled to the first intermediate line and the second line, having an output coupled to the first clock signal line and a selector coupled to the first input of the master clock signal line, a second input coupled to the intermediate line, and a third input coupled to the second line.

Drawings

Fig. 1 is a diagram of an integrated circuit with controllable clock delay according to an example of the present disclosure.

Fig. 2 is an illustration of a circuit with controllable clock delay according to an example of the present disclosure.

Fig. 3 is a timing diagram according to an example of the present disclosure.

Fig. 4a and 4b are illustrations of a controllable clock delay buffer circuit according to examples of the present disclosure.

Fig. 5 is a flow chart of a method for correcting post-fabrication timing errors according to an example of the present disclosure.

Fig. 6 is a flow chart of a method for correcting post-fabrication timing errors according to an example of the present disclosure.

Fig. 7 is an illustration of an integrated circuit with controllable clock delay according to an example of the present disclosure.

Fig. 8 is an illustration of an integrated circuit with controllable clock delay according to an example of the present disclosure.

Fig. 9 is an illustration of an integrated circuit with controllable clock delay according to an example of the present disclosure.

Detailed Description

Fig. 1 is a diagram of an integrated circuit with controllable clock delay according to an example of the present disclosure. Integrated circuit 100 may be a pipeline processor having bus interface unit 130, functional circuits 101a-101f, followed by respective flip-flops 102 (shown as flip-flops 102a, 102b, 102c, 102d, 102e, and 102 f) that form boundaries between respective pipeline stages. The bus interface unit 130 provides an interface to a memory that stores instructions to be executed by the processor. The timing for integrated circuit 100 is driven by a master clock signal carried along master clock signal line 103 that is fed through respective clock buffers 104 (shown as clock buffers 104a, 104b, 104c, 104d, 104e, and 104 f) to separate clock signal lines coupled to corresponding flip-flops 102. In some examples, all flip-flops 102 in a given stage are driven by the same clock buffer, e.g., clock buffer 104a drives multiple flip-flops in 102a in the corresponding pipeline stage. Flip-flop 102 is a single bit memory arranged in an array to capture the result of a pipeline stage at each predetermined clock transition. For example, the flip-flop 102a may be a flip-flop array that stores processor instructions (e.g., 32-bit reduction instruction set instructions). For example, flip-flop 102b may store an operand value (e.g., a 32-bit value retrieved from memory) along with decoded instruction information. When triggered by, for example, a rising edge of a clock signal, the work done in the functional unit of each pipeline stage is propagated to the next stage. Values propagate along various paths in the functional unit, and some paths may be "shorter," meaning that values on one path may propagate faster than values on another path. In an impractical simple adder implementation, the Least Significant Bit (LSB) of the sum may reach flip-flop 102e much faster than the Most Significant Bit (MSB) of the sum, because any carried value must propagate from LSB to next bit, etc., until it reaches the MSB. The circuit must be clocked to ensure that the critical path signal (i.e., the slowest propagating signal) is calculated and valid before the next clock cycle to ensure that it is available to be read into the corresponding flip-flop before the next clock trigger. The circuit must also be clocked to ensure that the fastest propagating signal does not switch before the previous result is captured by the output flip-flop.

Each flip-flop has two timing requirements. First, each flip-flop has a minimum set time, which is the amount of time an input signal must remain stable before a clock triggers. Second, each flip-flop has a minimum hold time, which is the amount of time the input signal must remain stable after a clock trigger. If either requirement fails, the flip-flop may not capture the input signal. The flip-flop groups at each stage are typically clocked together and driven by a respective clock buffer assigned to the group.

Clock buffer 104 incorporates selectable delay circuitry to allow timing adjustment. If the signal propagation for a given execution stage is longer than designed or longer than expected, the clock buffers controlling the flip-flops before and/or after the stage may be adjusted to ensure that all signals are stable before the minimum setup time. Test circuit 110 generates a test pattern and observes the functional unit output to determine if clock buffer delay adjustment is required. In some examples, test circuitry 110 may emulate bus interface unit 130 to provide fetched instructions. In some examples, the test circuit 110 may set the value directly in one or more of the flip-flops 102a-102 e. In some examples, test circuit 110 may observe the functional unit output and the output of the flip-flop receiving the functional unit output. In these examples, if test circuit 110 observes a change in the functional unit output but does not observe a corresponding change in the receive flip-flop, test circuit 110 may determine that the timing is incorrect and adjust the clock buffer delay before and/or after the functional unit.

Fig. 2 is an illustration of a circuit with controllable clock delay according to an example of the present disclosure. This figure illustrates a 1-bit execution pipeline. Circuit 200 includes flip-flop 201 (shown as flip-flops 201a, 201b, and 201c, respectively), functional circuit 202 (shown as functional circuits 202b and 202c, respectively), master clock signal line 203, and controllable clock buffer 204 (shown as controllable clock buffers 204a, 204b, and 204c, respectively). The circuit 200 also includes test circuitry that provides inputs to the flip-flop 201a and observes the outputs of the functional circuits 202b and 202 c. Flip-flops 201a-c are clocked by signal lines labeled CLK1, CLK2, and CLK3, respectively, which are driven by clock buffers 204 a-c. Test circuit 210 provides a test input to flip-flop 201a at the beginning of the test and observes the output of functional circuit 202 b. If the output of functional circuit 202b changes too slowly to be captured by flip-flop 201b, test circuit 210 may decrease the delay value for clock buffer 204a or may increase the delay value for clock buffer 204b or may perform both. If the output of functional circuit 202b changes too fast and prevents the capture of the previous value by flip-flop 201b (i.e., the minimum hold time of violation flip-flop 201 b), then the portion may be degraded or marked as unrepairable. The degraded portion is designated to operate at a lower highest frequency than other portions of the same design.

Fig. 3 is a timing diagram according to an example of the present disclosure. Timing diagram 300 illustrates waveforms of CLK2, CLK3, and delayed CLK2 (illustrated as CLK2 (delayed)). This figure illustrates a situation in which the propagation time through the functional circuit 202c is short enough to violate the hold time at the flip-flop 201 c. In other words, the flip-flop 201c will capture new data one clock cycle in advance, rather than capturing it at t ₄. If CLK2 is instead delayed until t ₃, the hold violation will be prevented. However, this portion must be further tested to ensure that the delay of CLK2 does not violate the set requirement at flip-flop 201 c. If delay CLK2 causes a setup violation, then portions may be downgraded to a lower speed.

Fig. 4a and 4b are illustrations of a controllable clock delay buffer circuit according to examples of the present disclosure. In fig. 4a, delay selection circuit 400 includes a master clock input 403, a delay module 405, a delay selector 406, delay control logic 407, an enable 408, and a buffer clock output 409. The selector 406 includes an input with an increased amount of delay from one delay module to x delay modules (i.e., an increased number of serially connected delay modules 405), where x=5 in this example. Each delay module 405 introduces a single delayed element. The master clock input 403 receives a master clock signal, for example, from a master clock distribution network. In some examples, delay selection circuit 400 may include a plurality of delay modules 405 and a selector 406, the selector 406 being sized to select from a number of more inputs to provide an equal number of delay cells. Delay control logic 407 may read the fused memory location or register value to determine which of the inputs to selector 406 is selected to pass as the output clock signal. When the enable input is asserted, the enable 408 will pass the selected clock signal and the selected output clock signal will be output at clock signal 409. To add a delay unit, the delay control logic 407 may increment a register value, for example, and thereby change the select input to the selector 406 to select the next more delayed clock signal.

Fig. 4b illustrates another controllable clock buffer according to an example of the invention. Fig. 4b utilizes fewer delay blocks and may require less space in the circuit. In fig. 4b, circuit 420 includes a master clock input 403, a delay module 405, a selector 406, delay control logic 407, an enable 408, and a buffered clock output 409. The master clock input 403 is fed to a first input of a selector 406 through a series connection of delay modules 405. The output of a respective one of the delay modules 405 is tapped and fed to a respective input of a selector 406. The master clock input 403 is fed directly to a corresponding input of the selector 406. The operation of the delay control logic 407, the enable 408, and the buffered clock output 409 is as described above with respect to fig. 4 a. In this example, delay control 407 may select from zero to up to four delay cells. In some examples, delay selection circuit 420 may include a plurality of delay modules 405 and a selector 406, the selector 406 being sized to select from a number of more inputs to provide an equal number of delay cells.

Fig. 5 is a flow chart of a method for correcting post-fabrication timing errors according to an example of the present disclosure. The method may be performed to test and correct post-fabrication timing errors in a pipelined processor. The method may be aided by performing static timing analysis on the design to identify critical timing paths through functional circuit stages between sets of flip-flops for capturing and propagating pipeline states. Static analysis of the circuit may identify one or more fast paths through the pipeline stage that may cause hold time violations of flip-flops at the output of the stage. The static analysis of the circuit may also identify one or more slow paths through the pipeline stage that may cause setup time violations of flip-flops at the output of the stage. Such static analysis identification of fast and slow paths may be used to generate test inputs that trigger or isolate the paths. The method 500 begins by providing a first clock signal to a first flip-flop in a data path and providing a second clock to a second flip-flop in the data path, wherein a functional block connects an output of the first flip-flop and an input of the second flip-flop. In some examples, the first clock signal and the second clock signal are provided with a midpoint delay amount to allow each clock to be moved left (less delay) or right (more delay). At block 505, the test circuit provides a test input to the first flip-flop. In some embodiments, the test circuitry at block 505 observes and records inputs (e.g., instructions and/or operands fetched from memory) read from a memory coupled to the bus interface unit. At block 510, the test circuit observes signal propagation through the functional block. At block 515, the test circuit determines if the propagation is too fast to be properly acquired by the second flip-flop. This may be determined, for example, by observing the output of the second flip-flop. If the propagation is too fast at block 516, the test circuit determines if additional delay adjustments are possible. If all adjustments have been exhausted, then at block 540 the test circuitry marks that the device is to be discarded. If further adjustment is possible, at block 520, the delay control logic increases the timing interval by adding or subtracting a delay element to or from the first clock signal in response to determining that the signal propagation time is less than the minimum hold time of the second flip-flop. In some examples, the delay control logic delay may be added/subtracted in single unit increments, for example, by selecting paths through one more or one less delay module 405. In some examples, the second clock signal may be advanced by a single unit increment, e.g., to add a single delay module 405 to the path of the second clock signal instead of delaying the first clock signal.

If all applicable tests pass after adjusting the clock delay, then the adjusted delay settings for each controllable buffer are stored at block 525. In some examples, the self-test process may be repeated at intervals to adjust as environmental condition changes or aging effects (such as electromigration) occur. For example, temperature may change over time and affect propagation time. In some examples, the delay value may be stored in a register to allow adjustment over time. In some examples, the delay amount may be permanently stored in the circuit by burning fuses in the chip, for example. The permanently stored value may directly drive the clock buffer or may be read into a register at initialization. In some examples, the delay amount may be read into a register at initialization and further adjusted using the method 500. Further adjustments may be stored in the non-volatile memory by burning additional fuses. In some examples, the non-volatile memory is a set of flash memory cells.

However, shifting the clock delay to repair the hold violations may introduce setup violations elsewhere in the design. Thus, at block 526, the circuit is tested at the desired maximum frequency to determine if the timing remains correct. If the circuit passes these tests at block 530, then the portion may be marked as "good" and passed at block 535. At block 531, if the fix hold violation introduces a setup violation, the circuit may optionally be downgraded to a lower frequency. If the degradation is acceptable, the target frequency is lowered and the portion is retested at that frequency in block 532. The process continues until the device passes (535) or the lowest acceptable target frequency is not met and the portion is discarded (540).

Fig. 6 is a flow chart of a method for correcting post-fabrication timing errors according to an example of the present disclosure. The method 600 begins by providing a first clock signal to a first flip-flop in a data path and providing a second clock to a second flip-flop in the data path, wherein a functional block connects an output of the first flip-flop and an input of the second flip-flop. In some examples, the first clock signal and the second clock signal are provided with a midpoint delay amount to allow each clock to be moved left (less delay) or right (more delay). At block 605, the test circuit provides (or in some examples observes and records) a test input to the first flip-flop. At block 610, the test circuit observes signal propagation through the functional block. The test circuit may operate at a much higher clock rate than the first clock signal and the second clock signal. In some examples, the test circuit may sample twice in succession. At block 615, the test circuit determines whether the output of the functional block changed before the minimum hold time of the second flip-flop ended. If so, at block 620, the delay control logic adds a delay to the first clock signal. In some examples, the delay may be added in single unit increments, e.g., a single delay module 405 is added to the clock path. In some examples, the second clock signal may be advanced by a single unit increment by, for example, removing the single delay module 405 from the clock path instead of delaying the first clock signal.

Fig. 7 is an illustration of a circuit with controllable clock delay according to an example of the present disclosure. The circuit 700 includes flip-flops 701a and 701b, a functional circuit 702, a master clock input line 703 (which receives a master clock signal), and a clock buffer 704. The circuit 700 also includes a test circuit that provides an input to the flip-flop 701a and observes the output of the functional circuit 702. The input to flip-flop 701a may flow through other circuits before reaching flip-flop 701 a. Flip-flop 701a is clocked by clock buffer 704 and flip-flop 701b is clocked by the master clock signal received at master clock input line 703. Test circuit 710 provides a test input to flip-flop 701a at the beginning of the test and observes the output of functional circuit 702. If the output of functional circuit 702 changes too slowly to be captured by flip-flop 701b, test circuit 710 may reduce the delay value of clock buffer 704. If the output of functional circuit 702 changes too fast to be captured by flip-flop 701b, test circuit 710 may increase the delay value of clock buffer 704.

Fig. 8 is an illustration of a circuit with controllable clock delay according to an example of the present disclosure. Circuit 800 includes flip-flops 801a and 801b, functional circuit 802, master clock input line 803 (which receives a master clock signal), and clock buffers 804a and 804b. Flip-flop 801a is clocked by clock buffer 804a, and flip-flop 801b is clocked by clock buffer 804b. If the output of functional circuit 802 changes too slowly to be captured by flip-flop 801b, the tester may reduce the delay value of clock buffer 804. . The circuit 800 further comprises a non-transitory memory 811 for storing delay values. In some examples, memory 811 is a set of fuses used to form a non-volatile memory. In some examples, memory 811 is a register that can be modified by test circuitry 810 to adjust the delay of clock buffer 804. During operation, the delay value for the clock buffer 804 is responsive to the delay value stored in the non-transitory memory 811.

Fig. 9 is an illustration of a circuit with controllable clock delay according to an example of the present disclosure. The circuit 900 includes flip-flops 901a and 901b, a functional circuit 902, a master clock input line 903 (which, in turn, provides inputs to the flip-flop 901a and observes the output of the functional block 902. The circuit 900 also includes a test circuit that provides inputs to the flip-flop 901a that may flow through other circuits before reaching the flip-flop 901 a. The flip-flop 901a is clocked by the clock buffer 904a and the flip-flop 901b is clocked by the clock buffer 904b. The clock test circuit 910 provides a test input to the flip-flop 901a at the beginning of a test and observes the output of the functional circuit 902. If the output of the functional circuit 902 changes too slowly to be captured by the flip-flop 901b, the test circuit 910 may reduce the delay value of the clock buffer 904a or 904b.

In one example, test circuit 910 includes clock multiplier 920, counter 921, minimum setting 922, adder 923, cycle time value 924, comparator 925, indicator 926, observation input 927, and test case 928. The clock multiplier 920 may be a PLL or other clock multiplier to generate a higher frequency clock to use as a timer and may receive the output of the clock buffer 904a as an input. In some examples, clock multiplier 920 may be external to the integrated circuit. Counter 921 may be a digital counter configured to reset and count upon clock triggering from clock buffer 904a until the observation input 927 changes. The minimum setting 922 may be a representation of the minimum setting time of the trigger 901 b. Adder 923 may be a digital adder. The period time value 924 may be a representation of the master clock period time. The comparator 925 may be a digital comparator drive signal 926 to signal an unrepairable condition.

In operation, test case 928 provides an input to flip-flop 901a and counter 921 begins to multiply count the clock cycles provided by clock multiplier 920 in response to a predetermined edge of the clock signal provided by clock buffer 904 a. When the observation input 927 changes value, the counter 921 stops counting, and its output added to the minimum setting 922 is compared with the cycle time value 924 by the comparator 925. In the case where the output of the counter 921 plus the minimum setting 922 is less than the cycle time value 924, the comparator 925 does not indicate an unrepairable condition. In the case where the output of the counter 921 plus the minimum setting 922 is not less than the cycle time value 924, the comparator 925 indicates an unrepairable condition.

Although example embodiments have been described above, other variations and embodiments can be made by the present disclosure without departing from the spirit and scope of these embodiments.

Claims (20)

1. A method of testing an integrated circuit, the method comprising:

Providing a first clock signal to a first flip-flop, the first flip-flop having an output to a functional circuit,

Providing a second clock signal to a second flip-flop, the second flip-flop having an input from the functional circuit, wherein the second flip-flop has a minimum hold time,

Providing a test input to the first flip-flop,

Observing the signal propagation time through the functional circuit,

Determining that the signal propagation time is less than the minimum hold time of the second flip-flop, and

In response to determining that the signal propagation time is less than the minimum hold time of the second flip-flop, a timing interval is increased by adding a delay unit to the first clock signal or subtracting a delay unit from the second clock signal.

2. The method according to claim 1, the method comprising: after adding the delay unit to the first clock signal:

A second observation of the signal propagation time through the functional circuit,

Determining that the second signal propagation delay is less than the minimum hold time of the second flip-flop, and

A second delay unit is added to the first clock signal.

3. The method according to any one of claims 1 to 2, the method comprising:

determining that the timing interval cannot be further increased, and

The integrated circuit to be discarded is marked.

4. A method according to any one of claims 1 to 3, the method comprising:

The delay unit is stored in a non-volatile memory.

5. The method of any of claims 1 to 4, wherein the functional circuit is a combinational logic path through a pipeline stage of a processor, the method comprising:

A static timing analysis of the pipeline stage is performed and the functional circuit is identified as having the fastest signal propagation time in any path through the pipeline stage.

6. The method according to any one of claims 1 to 5, the method comprising:

Generating a first delayed clock signal by passing the master clock signal through a first delay circuit, an

Generating a second delayed clock signal by passing the master clock signal through a second delay circuit, wherein adding a delay unit to the first clock signal includes selecting the first delayed clock signal as the first clock signal.

7. The method of any of claims 1 to 6, wherein the second trigger has a minimum set time, the method comprising:

after increasing the timing interval, observing a setting violation in the second flip-flop, and

Reducing the maximum frequency of the integrated circuit.

8. A system for testing an integrated circuit, the system comprising:

A first clock signal line to a first flip-flop, the first flip-flop having an output to a functional circuit,

A second clock signal to a second flip-flop, the second flip-flop having an input from a function, wherein the second flip-flop has a minimum hold time,

A test circuit coupled to an input of the first flip-flop and an output of the functional circuit to determine whether a signal has propagated through the function within a first propagation time that is less than the minimum hold time of the second flip-flop;

A first delay selection circuit coupled between the main clock signal line and the first clock signal line to selectively increase or decrease the delay cells, an

A second delay selection circuit is coupled between the master clock signal line and the second clock signal line.

9. The system of claim 8, wherein the delay selection circuit is to selectively add two delay cells to the first clock signal.

10. The system of any of claims 8 to 9, the test circuit comprising:

A timer having a start input coupled to the first clock signal line and a stop input coupled to the output of the functional circuit.

11. The system of any of claims 8 to 10, comprising a non-volatile memory coupled to the delay selection circuit to store a cell delay count.

12. The system of any of claims 8 to 11, wherein the functional circuit is a combinational logic path through a pipeline stage of a processor.

13. The system of any of claims 8 to 12, the delay selection circuit comprising:

A unit clock delay buffer coupled to the master clock signal line,

Two unit clock delay buffers coupled to the master clock signal line, and

A selector having an output coupled to the first clock signal line and a plurality of inputs coupled to the master clock signal, the output of the one unit clock delay buffer, and each of the outputs of the two unit clock delay buffers.

14. The system of any of claims 8 to 13, the test circuit comprising:

a timer for determining a signal propagation delay,

An adder for adding a minimum setting time of the second flip-flop, an

And a comparator for issuing an unrepairable status signal when the signal propagation delay plus the minimum setup time of the second flip-flop is greater than a cycle time of a clock signal on the second clock line.

15. An integrated circuit, the integrated circuit comprising:

A first clock signal line to a first flip-flop, the first flip-flop having an output to a functional circuit,

A second clock signal to a second flip-flop, the second flip-flop having an input from a function, wherein the second flip-flop has a minimum hold time,

A non-transitory memory for storing a delay amount,

A first delay circuit coupling a master clock signal line to the first clock signal line to generate a first clock signal by delaying the master clock signal by an amount specified by the delay amount, and

A second delay circuit couples the master clock signal line to the second clock signal line.

16. The integrated circuit of claim 15, wherein the non-transitory memory is non-volatile.

17. The integrated circuit of any of claims 15 to 16, wherein the functional circuit is a combinational logic path through a pipeline stage of a processor.

18. The integrated circuit of any of claims 15 to 17, the first delay circuit comprising:

A unit clock delay buffer coupled to the master clock signal line,

Two unit clock delay buffers coupled to the master clock signal line, and

A selector having an output coupled to the first clock signal line and a plurality of inputs coupled to the master clock signal, the output of the one unit clock delay buffer, and each of the outputs of the two unit clock delay buffers.

19. An integrated circuit as claimed in any one of claims 15 to 18, comprising a delay selection circuit coupled between the master clock signal line and the clock signal line at each pipeline stage of a processor.

20. The integrated circuit of any of claims 15 to 19, the delay circuit comprising:

A first clock delay buffer coupled to the master clock signal line and the intermediate line,

A second clock delay buffer coupled to the first intermediate line and the second line, and

A selector having an output coupled to the first clock signal line and a first input coupled to the master clock signal line, a second input coupled to the intermediate line, and a third input coupled to the second line.