CN117938213A - Telescopic beamforming vector calculation circuit based on power iterative algorithm - Google Patents
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Abstract
The invention discloses a scalable beamforming vector calculation circuit based on a power iterative algorithm. The beamforming vector calculation circuit comprises a matrix RAM, a controller and an operation unit. The matrix RAM is used for storing the channel covariance matrix information, and the cost is reduced by nearly half according to the conjugate symmetry characteristic of the matrix. The controller is used for controlling the circulation of data according to the size of the matrix, and realizing the scalability of calculation. The operation unit is used for realizing a power iterative algorithm, and comprises operations such as matrix vector block multiplication, overflow detection, shift and the like. The invention is applicable to channel covariance matrixes with four sizes of 128×128, 256×256, 512×512 and 1024×1024, and can be applied to a large-scale millimeter wave MIMO communication system.
Description
Technical Field
The invention belongs to the technical field of wireless communication, and particularly relates to a scalable beamforming vector calculation circuit based on a power iterative algorithm.
Background
In a large-scale millimeter wave multiple-Input multiple-Output (MIMO) communication system widely adopted in the contemporary fifth-generation mobile communication (the 5th Generation,5G) and the future sixth-generation mobile communication (the 6th Generation,6G), a beamforming technique may concentrate radiation or reception gain of a signal to a specific direction of a user, thereby achieving enhanced signal strength and coverage at a target location, and further improving system performance.
Beamforming can be implemented by different methods, and is mainly divided into digital beamforming, analog beamforming, and hybrid beamforming. One major difference in these three beamforms is the difference in the number of radio chains. The rf chain is a key component connecting the antenna and the digital signal processor, including amplifiers, mixers, filters, and digital-to-analog converters, etc. In a digital beamforming system, each antenna needs to be equipped with one radio frequency chain, while in a massive MIMO system, the number of antennas is hundreds to thousands, so that the overhead of the radio frequency chain is high. Current research is often focused on analog beamforming that requires only one rf chain and hybrid beamforming that requires fewer rf chains than antennas.
In addition, the channels of millimeter wave MIMO are sparse, that is, only the direct path (LOS path) and a few first order reflection paths have enough energy to transmit, while the other reflection paths are too small to facilitate signal transmission. Therefore, when the millimeter wave MIMO channel is employed, only a small amount of data is transmitted simultaneously.
Based on the above-described limitations of the number of radio frequency chains and the sparsity of millimeter wave channels, consider that the communication system transmits only one data stream at a time. An optimal beamforming vector for such a communication system is proposed in article "Hybrid MIMO-OFDM Beamforming for Wideband mmWave Channels Without Instantaneous Feedback,"in IEEE Transactions on Signal Processing,vol.66,no.19,pp.5142-5151,1Oct.1,2018 of p.lin: the principal eigenvector of the channel covariance matrix (eigenvector corresponding to the largest amplitude eigenvalue). The conventional hardware implementation methods for calculating the feature vector include QR decomposition and Jacobi methods, and the methods can calculate all feature vectors of the matrix at one time, which can cause the waste of hardware.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide a scalable beamforming vector calculation circuit based on a power iterative algorithm; the communication system considered by the invention only transmits one data stream at a time, and only the main characteristic vector is needed in the beam forming method, so that the invention adopts a power iterative algorithm for only calculating the main characteristic vector to reduce hardware cost; the method is suitable for the channel covariance matrixes with four sizes of 128×128, 256×256, 512×512 and 1024×1024, and meets the requirements of the current large-scale millimeter wave MIMO communication system on performances such as delay, energy consumption and precision.
The technical scheme of the invention is specifically introduced as follows.
The invention provides a scalable beamforming vector calculation circuit based on a power iterative algorithm, which comprises a matrix Random Access Memory (RAM), a controller and an operation unit, wherein the matrix RAM is used for storing a plurality of beamforming vectors; wherein:
A matrix RAM for storing channel covariance matrix diagonal and 2×2 matrix block information thereabove; the matrix RAM is provided with four blocks, and the positions of the four elements at the upper left, the upper right, the lower left and the lower right in each matrix block are respectively stored;
The controller is used for controlling the circulation of data according to the size of the matrix to realize the scalability of calculation; the controller comprises an s counter for storing the column number of the current processing matrix block, an r counter for storing the line number of the current processing matrix block and an address control bit generator, wherein the address control bit generator generates a RAM read address and a control bit cb for judging whether the matrix to be read is stored in the RAM or not so as to facilitate the conjugate symmetrical conversion of the data of the matrix block after the matrix block is read out;
The operation unit is used for realizing a power iterative algorithm comprising matrix vector block multiplication, overflow detection and shift operation; assuming that the channel covariance matrix is sigma, in the power iterative algorithm, the initial vector v 0 is random first, and in the kth iteration, the matrix vector is multiplied
And shift
Two-step operation is constructed, where beta k is the number of shift bits provided to prevent overflow,After performing a plurality of iterations, the result vector v k obtained by the iteration approaches the main feature vector of the sigma;
The matrix vector product is carried out by adopting a method of multiplying a block matrix by a block vector; assuming that the size of the matrix is n×n, it is split into n×n 2×2 matrix blocks, where n=n/2; accordingly, the vector is divided into n 2×1 vector blocks; for matrix blocks in the (r, s) position, the completed block matrix vector multiplication is
Where Σ x,y is the element of Σ in the (x, y) position, v x is the x-th element of v k,Is/>The x-th element of (2)The sum of the s th part of (a)
In the present invention, the RAM read address addr r,s of the matrix block at the (r, s) position is read by the address control bit generator by the recursive formula
addrr,0＝r (5)
And
Generating;
The control bit cb is generated by the formula of
If the control bit is 1, the upper right corner element and the lower left corner element of the read matrix block are replaced with each other according to the conjugate symmetry characteristic of the channel covariance matrix, and the conjugate of each element is taken as the read matrix block element.
Compared with the prior art, the invention has the beneficial effects that:
The invention uses power iterative algorithm to carry out block multiplication iterative computation on the channel covariance matrix and the vector, and can directly obtain the main eigenvector of the channel covariance matrix instead of all eigenvectors, thereby carrying out beam forming and greatly reducing the cost of hardware. Meanwhile, the invention utilizes the conjugate symmetry characteristic of the channel covariance matrix, only about half of matrix data is stored in the RAM, and the area of the RAM is greatly reduced. Meanwhile, the invention improves the normalization operation of each iteration in the traditional power iterative algorithm into hardware-friendly shift operation, thereby greatly reducing the complexity of hardware.
Drawings
FIG. 1 is a graph of RAM address versus matrix block location in hardware of the present invention.
Fig. 2 is a general structural diagram of hardware of the present invention.
FIG. 3 is a block diagram of the generation of RAM read address and control bits in the hardware of the present invention.
FIG. 4 is a block diagram of a block matrix vector multiplication implemented in hardware in accordance with the present invention.
Fig. 5 is a block diagram of the real (or imaginary) part of the sum of the products of two pairs of complex numbers calculated in the hardware of the present invention.
FIG. 6 is a block diagram of an overflow detection module in hardware of the present invention.
Fig. 7 is a block diagram of the determination of the shift bit number from the vector protection bit data in the hardware of the present invention.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings. The embodiments described below by referring to the drawings are exemplary only for explaining the present invention and are not to be construed as limiting the present invention.
The invention provides a scalable beamforming vector calculation circuit based on a power iterative algorithm. The hardware implementation circuit of the invention comprises a matrix random access memory (Random Access Memory, RAM), a controller and an arithmetic unit. Wherein the matrix RAM is used to store channel covariance matrix information. The controller is used for controlling the circulation of data according to the size of the matrix, and realizing the scalability of calculation. The operation unit is used for realizing a power iterative algorithm, and comprises operations such as matrix vector block multiplication, overflow detection, shift and the like.
Let the channel covariance matrix be Σ. In the power iteration algorithm adopted by the invention, the initial vector v 0 is firstly random, and the matrix vector multiplication is carried out in the kth iteration
And shift
Two-step operation is constructed in which β k is the number of shift bits provided to prevent overflow. After several iterations, v k will approximate the principal eigenvector of Σ.
The invention adopts a method of multiplying the blocking matrix and the blocking vector to carry out matrix vector multiplication. Assuming that the size of the matrix is n×n, it can be split into n×n2×2 matrix blocks, where n=n/2. Accordingly, the vector may be divided into n2×1 vector blocks. For matrix blocks in the (r, s) position, the completed block matrix vector multiplication is
Where Σ x,y is the element of Σ in the (x, y) position, v x is the x-th element of v k,Is/>The x-th element of (2)The sum of the s th part of (a)
In order to reduce the RAM area, in the RAM of the present invention, only diagonal lines and matrix blocks above the diagonal lines are stored, as shown by gray matrix blocks of fig. 1. The invention stores the positions of the four elements of the upper left, the upper right, the lower left and the lower right in each matrix block through four RAMs respectively. When the matrix vector multiplication operation is performed, the read addresses of the four RAMs are the same, matrix blocks at corresponding positions are read, and the reading sequence is shown by a dotted arrow in FIG. 1. Reading a white matrix block is in fact reading a gray matrix block symmetrical to it about the main diagonal of the matrix of fig. 1, and constructing a white matrix block by conjugate symmetrical conversion of the data.
RAM read address addr r,s of the matrix block at the read (r, s) position can be represented by the recurrence formula
addrr,0＝r (5)
And
And (3) generating.
In addition, the circuit of the invention also generates a control bit cb for judging whether the matrix to be read is stored in the RAM or not so as to facilitate the conjugate symmetrical conversion of the data after the matrix block is read, and the formula for generating the control bit is as follows
Since matrix vector multiplication operations may produce overflows, the present invention is directed to product vectorsSetting p=log 2 n+1 bits of protection bits, the data structure of the vector is: b p+qbp-1+q…b1+q|bqbq-1…b1, wherein p bit guard bits are left of the vertical line and q bit data bits are right of the vertical line.
To prevent overflow, the vector should be moved to the rightAll the protection bits of all the elements are eliminated, so that the shift bit number beta k and the vector/>The maximum value of the guard bit data b p+qbp-1+q…b1+q of all elements in the table is correlated, and the relationship is shown in table 1. Since the shift operation can be directly performed by the shift register, the present invention applies the operation instead of the normalization operation requiring a large number of multiply-divide operations in the conventional power iterative algorithm to reduce hardware complexity.
Table 1: relationship between guard bit data b p+qbp-1+q…b1+q and shift bit number β k
| bp+qbp+q-1…bp+1 | βk |
| 1xx…xx | p+1 |
| 01x…xx | p |
| 001…xx | p-1 |
| … | … |
| 000…1x | 2 |
| 000…01 | 1 |
| 000…00 | 0 |
As shown in fig. 2, a scalable beamforming vector calculation circuit based on a power iterative algorithm. The hardware implementation circuit of the invention comprises a matrix RAM, a controller and an operation unit.
The matrix RAM is composed of four blocks of RAM, i.e., RAM0, RAM1, RAM2, and RAM3, and stores the positions of the four elements in each matrix block, upper left, upper right, lower left, and lower right, respectively.
The controller consists of an s counter, an r counter, an address control bit generator and other modules, and is used for controlling the circulation of data according to the size of the matrix, so as to realize the scalability of calculation. The s counter and the r counter store the number of columns and the number of rows of the current processing matrix block, i.e., s and r in equations (5) and (6), respectively.
The operation unit is composed of vector registers, 2 x2 multipliers, accumulators, first-in first-Out buffers (FIRST IN FIRST Out, FIFO), overflow detection and shift updating modules and the like, and is used for realizing power iterative algorithm, including matrix vector block multiplication, overflow detection, shift and other operations.
In performing power iterative operations, the circuit of the present invention performs the following operations:
the address control bit generator generates RAM read addresses and control bits according to formulas (5) and (6), the structure of which is shown in fig. 3. If the control bit is 1, it is indicated that the read matrix block is the white matrix block in fig. 1, and the upper right corner element and the lower left corner element of the read matrix block need to be replaced with each other according to the conjugate symmetry characteristic of the channel covariance matrix, and the conjugate of each element is taken as the read matrix block element. The corresponding vector block in the vector register is also read by the s counter.
For one layer of block matrix vector multiplication operation, sequentially reading matrix blocks from left to right, multiplying the matrix blocks and the vector blocks in a 2 multiplied by 2 multiplier, and accumulating the obtained partial sum product vectors in an accumulator to obtain a product vector result of the one layer, namely the operation in formulas (3) and (4). The hardware structure for completing one-layer block matrix vector multiplication operation is shown in fig. 4, wherein a multiplication and addition module is shown in fig. 5, and the hardware structure is composed of 4 pipeline real number multipliers, 2 subtraction (or addition) devices and 1 adder device, and can calculate the real part (or imaginary part) of the sum of the products of complex numbers a and b and the product of complex numbers c and d, wherein in the figure, a superscript R represents the real part of the complex number, and a superscript I represents the imaginary part of the complex number. The accumulator accumulates and serially outputs 4 paths of data, which are the real and imaginary parts of the first element and the real and imaginary parts of the second element of the 2x 1 product vector block of this layer, respectively.
After the block matrix vector multiplication operation of one layer is finished, reading the data of the next layer to carry out operation until the multiplication operation of all layers is finished, and storing 4 paths of output results of the accumulator, namely the real parts and the imaginary parts of two elements of the corresponding product vector block, in the FIFO.
When each calculation completes one layer of block matrix vector multiplication operation, the protection bit data of the real part and the imaginary part of two elements of the product vector are input into an overflow detection module, and the structure of the module is shown in fig. 6. The 4-way data are input in series n times. At each input, 4 β k generators in the overflow detection module generate corresponding shift bits according to table 1. The structure of the generator is shown in fig. 7, implemented by cascading of multiplexers. The resulting 4 shift bit numbers find the maximum value among them by 3 maximum value generators and compare with the shift bit numbers stored in the registers shown in fig. 6, if larger than the values in the registers shown in fig. 6, i.e., stored in the registers. After n times of serial input, the obtained shift bit number is the shift bit number corresponding to the element with the largest protection bit in the product vector, so that no data overflow is generated after shift.
The shift bit number is input into the shift update module, the real part and the imaginary part of the element of the product vector stored in the FIFO are serially input into the shift update module, all shift to the right by the same bit number, and the same bit number is stored back into the vector register.
The above operation completes one iteration operation. By repeating the above operations a plurality of times, the vector output by the shift update module will approximate the principal eigenvector of the channel covariance matrix stored in the matrix RAM.
The above embodiments are only preferred embodiments of the present invention, and it should be noted that: various modifications can be made by those skilled in the art based on the technical idea of the present invention, and these modifications also fall within the scope of the present invention.
Claims (7)
1. A scalable beamforming vector calculation circuit based on a power iterative algorithm is characterized by comprising a matrix Random Access Memory (RAM), a controller and an operation unit; wherein:
A matrix RAM for storing channel covariance matrix diagonal and 2×2 matrix block information thereabove; the matrix RAM is provided with four blocks, and the positions of the four elements at the upper left, the upper right, the lower left and the lower right in each matrix block are respectively stored;
The controller is used for controlling the circulation of data according to the size of the matrix to realize the scalability of calculation; the controller comprises an s counter for storing the column number of the current processing matrix block, an r counter for storing the line number of the current processing matrix block and an address control bit generator, wherein the address control bit generator generates a RAM read address and a control bit cb for judging whether the matrix to be read is stored in the RAM or not so as to facilitate the conjugate symmetrical conversion of the data of the matrix block after the matrix block is read out;
The operation unit is used for realizing a power iterative algorithm comprising matrix vector block multiplication, overflow detection and shift operation; assuming that the channel covariance matrix is sigma, in the power iterative algorithm, the initial vector v 0 is random first, and in the kth iteration, the matrix vector is multiplied
And shift
Two-step operation is constructed, where beta k is the number of shift bits provided to prevent overflow,After performing a plurality of iterations, the result vector v k obtained by the iteration approaches the main feature vector of the sigma;
The matrix vector product is carried out by adopting a method of multiplying a block matrix by a block vector; assuming that the size of the matrix is n×n, it is split into n×n 2×2 matrix blocks, where n=n/2; accordingly, the vector is divided into n 2×1 vector blocks; for matrix blocks in the (r, s) position, the completed block matrix vector multiplication is
Where Σ x,y is the element of Σ in the (x, y) position, v x is the x-th element of v k,Is/>The x-th element/>The sum of the s th part of (a)
2. The scalable power iterative algorithm-based beamforming vector calculation circuit according to claim 1, wherein RAM read addresses addr r,s of matrix blocks at address control bit generator read (r, s) positions are calculated by a recursive formula
addrr,0＝r (5)
And
Generating;
The control bit cb is generated by the formula of
If the control bit is 1, the upper right corner element and the lower left corner element of the read matrix block are replaced with each other according to the conjugate symmetry characteristic of the channel covariance matrix, and the conjugate of each element is taken as the read matrix block element.
3. The scalable power iterative algorithm-based beamforming vector calculation circuit according to claim 1, wherein the operation unit comprises a vector register, a 2 x2 multiplier, an accumulator, a first-in first-out buffer FIFO, an overflow detection module, and a shift update module; the operation unit realizes the steps of the power iterative algorithm as follows:
for the block matrix vector multiplication operation of one layer, sequentially reading matrix blocks from left to right, carrying out multiplication operation on the matrix blocks and the vector blocks in a2 multiplied by 2 multiplier, and accumulating the obtained partial sum product vectors in an accumulator to obtain a product vector result of the layer; the accumulator accumulates and serially outputs 4 paths of data, namely the real part and the imaginary part of the first element and the real part and the imaginary part of the second element of the 2 multiplied by 1 vector block of the layer; after the block matrix vector multiplication operation of one layer is finished, reading the data of the next layer to carry out operation until the multiplication operation of all layers is finished, and storing 4 paths of output results of the accumulator, namely the real parts and the imaginary parts of two elements of the corresponding product vector block, in the FIFO;
When each calculation completes one layer of block matrix vector multiplication operation, the protection bit data of the real parts and the imaginary parts of two elements of the product vector are input into an overflow detection module, and 4 beta k generators in the overflow detection module generate corresponding shift bit beta k when each input is performed; the generated 4 shift bit numbers beta k find the maximum value thereof through three maximum value generators, compare with the shift bit numbers stored in the register, and if the shift bit numbers are larger than the values in the register, the shift bit numbers are stored in the register; after n times of serial input, the obtained shift bit number is the shift bit number corresponding to the element with the largest protection bit in the product vector, so that no data overflow is generated after shift;
Then, the shift bit number is input into a shift update module, the real part and the imaginary part of the element of the product vector stored in the FIFO are serially input into the shift update module, all shift the same bit number to the right, and the shift bit number is stored back into the vector register;
The above operation completes one iteration operation; by repeating the above operations a plurality of times, the vector output by the shift update module approximates to the principal eigenvector of the channel covariance matrix stored in the matrix RAM.
4. A scalable power iterative algorithm based beamforming vector calculation circuit according to claim 3, wherein the multiply-add module in a2 x 2 multiplier consists of 4 pipelined real multipliers, 2 subtractions or adders and 1 adder.
5. A scalable power iterative algorithm based beamforming vector calculation circuit according to claim 3, wherein the β k generator is implemented by a cascade of multiplexers.
6. A scalable power iterative algorithm based beamforming vector calculation circuit according to claim 3, wherein for the product vectorSetting p=log 2 n+1 bits of protection bits, the data structure of the vector is: b p+qbp-1+q…b1+q|bqbq-1…b1, wherein p bit protection bits are left of the vertical line, and q bit data bits are right of the vertical line; the relationship between the guard bit data b p+qbp-1+q…b1+q and the shift bit number β k is as follows: data were 000 … 00, and β k was 0; data were 000 … 01, and β k was 1; data 000 … x, β k 2, and so on, data 001 … xx, β k p-1; data is 01x … xx, and beta k is p; the data is 1xx … xx, and β k is p+1.
7. The scalable power iterative algorithm-based beamforming vector calculation circuit according to claim 1, wherein the beamforming vector calculation circuit is adapted to four sizes of channel covariance matrices of 128×128, 256×256, 512×512, and 1024×1024.
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