CN117938165A

CN117938165A - Analog-digital conversion device, digital chip set and data acquisition device

Info

Publication number: CN117938165A
Application number: CN202410132604.5A
Authority: CN
Inventors: 魏强; 宗仙丽; 姚朋朋
Original assignee: Shenzhen Wanliyan Technology Co ltd
Current assignee: Shenzhen Wanliyan Technology Co ltd
Priority date: 2024-01-30
Filing date: 2024-01-30
Publication date: 2024-04-26

Abstract

The application provides an analog-digital conversion device, a digital chip set and a data acquisition device, wherein a pseudo-random sequence generation module is arranged in an analog-digital conversion unit and a digital chip in the data acquisition device, the pseudo-random sequence generated in the analog-digital conversion unit is triggered by a reset signal, a deterministic time delay relationship exists between the pseudo-random sequence generated in the digital chip and the reset signal of the analog-digital conversion unit, thus deterministic time delay exists between the pseudo-random sequence generated in the digital chip and the pseudo-random sequence, time delay calibration of the digital chip (a receiving end) and the mode conversion unit (a transmitting end) can be realized based on the pseudo-random sequence, synchronous acquisition of multipath data is realized, data synchronization is not required to be realized through a synchronous head, the data cost is reduced, the utilization rate of a transmission bandwidth is improved, and the transmission efficiency is improved. After time delay calibration, data acquisition is performed cooperatively through a plurality of synchronous digital chip sets, so that the sampling rate of the data acquisition is improved.

Description

Analog-digital conversion device, digital chip set and data acquisition device

Technical Field

The application relates to the technical field of data acquisition, in particular to an analog-to-digital conversion device, a digital chip set and a data acquisition device.

Background

With the continuous development of communication technology, requirements on bandwidth and sampling rate of data acquisition devices are also increasing. The sampling rate of the system is usually increased by means of synchronous acquisition and splicing of multiple ADCs (Analog-to-Digital Converter, analog-to-digital converters).

In the scenario of multi-ADC synchronous acquisition, in order to achieve data synchronization between multiple chips, the synchronization is usually accomplished through a synchronization header (Synchronization Header, SHR), which usually occupies a part of bandwidth, resulting in lower transmission efficiency and limited sample rate improvement. Taking the 64b/66b coding scheme in the JESD204C protocol as an example, this results in a 2bit sync header being added before every 64 bits of valid data, resulting in a loss of about 3% of the transmission bandwidth.

Therefore, it is desirable to provide a synchronous acquisition scheme with high transmission efficiency to support higher sampling rates.

Disclosure of Invention

The application provides an analog-digital conversion device, a digital chip set and a data acquisition device, which realize data synchronization based on a pseudo-random sequence, do not need to add a data head into data, improve the utilization rate of transmission bandwidth, further improve the transmission efficiency and support higher sampling rates, such as the sampling rate of tens of GSa/s to hundreds of GSa/s.

In a first aspect, the present application provides an analog-to-digital conversion apparatus, including at least one analog-to-digital conversion module, where different analog-to-digital conversion modules are configured to perform analog-to-digital conversion on analog signals of different input channels, and send the converted digital signals to a plurality of connected digital chip sets; the digital chip set comprises a plurality of digital chips;

the analog-to-digital conversion module comprises a plurality of analog-to-digital conversion units; the analog-to-digital conversion unit comprises a first sequence generation module, a sampling and holding module, an analog-to-digital conversion subunit, a mode selection module and a data transmission interface;

The first sequence generation module is used for generating a pseudo-random sequence under the triggering of a reset signal;

The sampling and holding module is used for sampling and holding the input analog signals based on the sampling clock signals;

The analog-to-digital conversion subunit comprises a plurality of analog-to-digital converters, and is used for performing analog-to-digital conversion on the signals output by the sample-and-hold module to obtain multi-channel digital signals;

the mode selection module is used for controlling the working mode of the analog-to-digital conversion unit;

When the working mode of the analog-to-digital conversion unit is a pseudo-random sequence sending mode, the pseudo-random sequence generated by the first sequence generating module is sent to a connected digital chip through the data sending interface so as to realize time delay calibration of different channels based on the pseudo-random sequence, and synchronous acquisition of multipath digital signals output by the multi-mode conversion unit is realized;

and when the working mode of the analog-to-digital conversion unit is a data acquisition mode, the multichannel digital signals output by the analog-to-digital conversion subunit are transmitted to a connected digital chip through the data transmission interface.

In one possible implementation, the mode selection module includes a selection switch, a programmable unit, and an exclusive or logic element;

The selection switch is used for selecting signal output of the analog-to-digital conversion subunit or the programmable unit;

the exclusive-or logic element is used for carrying out exclusive-or operation on the signal output by the selection switch and the pseudo-random sequence generated by the first sequence;

The signal output by the programmable unit is programmable; when the working mode of the analog-to-digital conversion unit is a pseudo-random sequence sending mode, the signal output by the programmable unit is a logic 0 signal, the signal output by the selection switch is a logic 0 signal output by the programmable unit, and the logic 0 signal and the generated pseudo-random sequence output the pseudo-random sequence after passing through the exclusive-or logic element and are sent to a connected digital chip through the data sending interface; when the working mode of the analog-to-digital conversion unit is a data acquisition mode, the selection switch selects multiple paths of digital signals output by the analog-to-digital conversion subunit to output, and the multiple paths of digital signals are sent to a connected digital chip through the data sending interface to realize data acquisition.

In a possible implementation manner, the working mode of the analog-to-digital conversion unit further includes a programmable mode, in which the programmable unit outputs a tag sequence, the tag sequence includes a tag of each analog-to-digital converter in the analog-to-digital conversion subunit, the tag of the analog-to-digital converter outputting a frame header in the multi-channel digital signal or pseudo-random sequence is 1, and the other tags are 0, so that the digital chip determines the position of the frame header based on the tag sequence, so as to realize frame header alignment of the serial-to-parallel converted signal.

In a possible implementation manner, the analog-to-digital conversion unit further comprises a phase detection module, configured to:

Dividing the sampling clock signal to obtain a 0-degree frequency division clock signal, a 90-degree frequency division clock signal, a 180-degree frequency division clock signal and a 270-degree frequency division clock signal;

Performing phase detection on the reset signal based on the 0 degree divided clock signal, the 90 degree divided clock signal, the 180 degree divided clock signal, and the 270 degree divided clock signal;

Based on the result of the phase detection, determining the synchronous clock signal of the reset signal from the 0 degree frequency division clock signal, the 90 degree frequency division clock signal, the 180 degree frequency division clock signal and the 270 degree frequency division clock signal, so as to realize synchronous reset of the multi-analog-digital conversion unit or the multi-analog-digital conversion module based on the synchronous clock signal of the reset signal.

In a second aspect, the present application provides a digital chipset, configured to receive a digital signal of a corresponding channel output by an analog-to-digital conversion module, where the digital chipset includes a plurality of digital chips, and the digital chips include a data receiving interface, a second sequence generating module, and a time delay calibration module; the analog-to-digital conversion module is provided in the first aspect of the present application;

The data receiving interface is used for receiving multipath digital signals or pseudo-random sequences sent by the connected analog-to-digital conversion units;

the second sequence generation module is used for generating a pseudo-random sequence under the triggering of the synchronous signal;

The time delay calibration module is used for time delay calibration of the digital chips based on the pseudo-random sequence generated by the second sequence generation module in each digital chip and the pseudo-random sequence received by the data receiving interface so as to synchronize multiple paths of digital signals received by each digital chip.

In one possible implementation, the digital chip further includes a periodic tag generation module for:

generating a periodic tag based on the pseudo-random sequence generated by the second sequence generation module;

The time delay calibration module is specifically configured to:

And performing time delay calibration on each digital chip based on the periodic tag.

In a possible implementation manner, the synchronization signal triggering the second sequence generating module is a reset signal triggering the first sequence generating module.

In one possible implementation manner, the digital chip and the analog-to-digital conversion unit are connected through a plurality of SerDes channels; the digital chip further comprises a plurality of shift adjustment modules, wherein the shift adjustment modules are used for performing time delay calibration on each SerDes channel.

In a possible implementation manner, the synchronization signal triggering the second sequence generating module is a signal output by a first shift adjusting module, and the second shift adjusting module is used for performing time delay calibration on the corresponding SerDes channel based on the pseudo-random sequence output by the second sequence generating module;

the first displacement adjustment module is any one of the plurality of displacement adjustment modules; the second shift adjustment module is a shift adjustment module remaining after the first shift module is removed from the plurality of shift adjustment modules.

In a third aspect, the present application provides a data acquisition device, including the analog-to-digital conversion device provided in the first aspect of the present application, and a digital chipset connected to each analog-to-digital conversion module in the analog-to-digital conversion device, where the digital chipset is a digital chipset provided in the second aspect of the present application.

According to the analog-to-digital conversion device, the digital chip set and the data acquisition device, which are provided by the embodiment, aiming at a multi-ADC synchronous acquisition scene, the analog-to-digital conversion device comprises at least one analog-to-digital conversion module, the analog-to-digital conversion module comprises a plurality of analog-to-digital conversion units, and one analog-to-digital conversion unit comprises a plurality of analog-to-digital converters, so that parallel conversion and acquisition of multi-channel data are realized, meanwhile, synchronization of digital signals output by different analog-to-digital conversion units or different analog-to-digital conversion modules is carried out through a pseudo-random sequence, a synchronization head is not required to be arranged when the digital signals are transmitted, the utilization rate of transmission bandwidth is improved, the transmission efficiency of the digital signals is improved, and the analog-to-digital conversion device can support higher sampling rate.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.

Fig. 1 is a schematic structural diagram of an analog-to-digital conversion device according to an embodiment of the present application;

FIG. 2 is a schematic diagram of an analog-to-digital conversion unit according to the embodiment of FIG. 1;

Fig. 3 is a schematic diagram of a frame header alignment procedure according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of another analog-to-digital conversion device according to an embodiment of the present application;

FIG. 5 is a schematic diagram of the frequency division result of the signal according to the embodiment of FIG. 4;

FIG. 6 is a schematic diagram of a digital chipset according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of a digital chip according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a periodic tag generation process in the embodiment of FIG. 7 in accordance with the present application;

FIG. 9 is a schematic diagram of another digital chip according to an embodiment of the present application;

Fig. 10 is a schematic structural diagram of a data acquisition device according to an embodiment of the present application;

fig. 11 is a flowchart of a time delay calibration method according to an embodiment of the present application.

Reference numerals:

10-a data acquisition device;

A 100-analog-to-digital conversion module; a 110-analog-to-digital conversion unit; 111-a first sequence generation module; 112-a sample-and-hold module; 113-an analog-to-digital conversion subunit; 114-a mode selection module; 115-data transmission interface; 116-a phase detection module;

200-digital chip sets; 210-a digital chip; 211-a data receiving interface; 212-a second sequence generation module; 213-a time delay calibration module; 214-a periodic tag generation module; 215-a shift adjustment module.

Specific embodiments of the present application have been shown by way of the above drawings and will be described in more detail below. The drawings and the written description are not intended to limit the scope of the inventive concepts in any way, but rather to illustrate the inventive concepts to those skilled in the art by reference to the specific embodiments.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims. It will be apparent that the described embodiments are some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

The data acquisition device provided by the embodiment of the application can be applied to equipment such as oscilloscopes, high-speed acquisition cards, frequency spectrographs and the like, has high transmission bandwidth utilization rate and transmission efficiency, and supports higher sampling rates, such as the sampling rate of tens of GSa/s to hundreds of GSa/s.

In order to make the above objects, features and advantages of the embodiments of the present application more comprehensible, the technical solutions of the embodiments of the present application will be described clearly and completely with reference to the accompanying drawings. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by a person skilled in the art based on the embodiments of the application without any inventive effort, are intended to fall within the scope of the application.

Fig. 1 is a schematic structural diagram of an analog-to-digital conversion device according to an embodiment of the present application, and referring to fig. 1, the analog-to-digital conversion device according to an embodiment of the present application includes at least one analog-to-digital conversion module 100, and in fig. 1, taking k analog-to-digital conversion modules 100 as an example, different analog-to-digital conversion modules 100 are used for performing analog-to-digital conversion on analog signals of different input channels (e.g., input channel 1 to input channel k), and sending the converted digital signals to a k digital chipset 200 connected thereto, so as to implement parallel acquisition of multi-channel signals.

The analog-to-digital conversion module 100 includes a plurality of analog-to-digital conversion units 110, and the number of analog-to-digital conversion units 110 included in different analog-to-digital conversion modules 100 may be different or the same. In fig. 1, the analog-to-digital conversion modules 100 each include n analog-to-digital conversion units 110 as an example.

With continued reference to fig. 1, the analog-to-digital conversion unit 110 includes a first sequence generation module 111, a sample-and-hold module 112, an analog-to-digital conversion subunit 113, a mode selection module 114, and a data transmission interface 115.

The first sequence generating module 111 is configured to generate a pseudo random sequence under the triggering of the reset signal; the sample-hold module 112 is configured to sample and hold an input analog signal based on a sampling clock signal; the analog-to-digital conversion subunit 113 includes a plurality of analog-to-digital converters ADCs, and the analog-to-digital conversion subunit 113 is configured to perform analog-to-digital conversion on the signal output by the sample-and-hold module 112, so as to obtain a plurality of channels of digital signals; the mode selection module 114 is used for controlling the operation mode of the analog-to-digital conversion unit 110; when the working mode of the analog-to-digital conversion unit 110 is a pseudo-random sequence sending mode, the pseudo-random sequence generated by the first sequence generating module 111 is sent to the connected digital chip 210 through the data sending interface 115 so as to realize time delay calibration of different channels based on the pseudo-random sequence, thereby realizing synchronous acquisition of multiple paths of digital signals output by the multiple analog-to-digital conversion unit 110; when the operation mode of the analog-to-digital conversion unit 110 is the data acquisition mode, the multiple digital signals output by the analog-to-digital conversion subunit 113 are sent to the connected digital chip 210 through the data sending interface 115.

A digital chipset 200 includes a plurality of digital chips 210, and an analog-to-digital conversion unit 110 is connected to one digital chip 210 for transmitting the output multiple digital signals to the connected digital chip 210.

In some embodiments, data transmission interface 115 is a high-speed data interface, and the rate of a single interface may be up to 32Gbps, such as a Lane interface.

A pseudo-random sequence is a periodic, random sequence that can be predetermined and repeatedly generated.

The first sequence generating modules 111 of different analog-to-digital converting units 110 in the same analog-to-digital converting module 100 may provide the reset signal by the same synchronizing module, so as to realize synchronous acquisition of multiple digital signals of corresponding channels.

The first sequence generating modules 111 of different analog-to-digital converting units 110 in the same analog-to-digital converting device may provide the reset signal by the same synchronizing module, so as to realize synchronous acquisition of multi-channel digital signals.

The setting of the operation mode of the analog-to-digital conversion unit 110 may be performed by a plurality of operation modes provided in the mode selection module 114.

The mode selection module 114 may be implemented by any structure, and the mode of operation of the analog-to-digital conversion unit 110 is controlled to select to output the multiple digital signals output by the analog-to-digital conversion subunit 113 or the pseudo random sequence output by the first sequence generation module 111 to the digital chip 210 through the data transmission interface 115.

The mode selection module 114 may be any kind of programmable logic device to output different logic signals, so that the operation mode of the analog-to-digital conversion unit 110 is controlled by the different logic signals, and the specific structure of the mode selection module 114 is not limited in the present application.

The number of analog-to-digital converters ADC in the analog-to-digital conversion unit 110 may be arbitrary, such as 64, 128, etc. Each ADC is used for carrying out analog-to-digital conversion on the input signal to obtain a one-bit digital signal.

The data transmission interface 115 may transmit multiple digital signals (in data acquisition mode) or pseudo-random sequences (in pseudo-random sequence transmission mode) to the digital chip 210 through multiple SerDes channels.

The digital chipset 200 is configured to store digital signals of corresponding channels output by the analog-to-digital conversion module 100, and the digital chipset 200 includes a plurality of digital chips 210 respectively connected to the analog-to-digital conversion units 110 of the analog-to-digital conversion module 100. In order to achieve synchronous acquisition of digital signals, the digital chipset 200 also needs to perform time delay calibration on different channels used for acquiring data based on a pseudo random sequence before data acquisition.

The analog-to-digital conversion apparatus or the analog-to-digital conversion module 100 may further include a clock module and a synchronization module, where the clock module is configured to generate a clock signal, i.e. a sampling clock signal, based on the reference clock, so as to trigger the synchronization module to generate a reset signal that triggers each of the first sequence generating modules.

According to the analog-to-digital conversion device provided by the embodiment, aiming at a multi-ADC synchronous acquisition scene, the analog-to-digital conversion device comprises at least one analog-to-digital conversion module, the analog-to-digital conversion module comprises a plurality of analog-to-digital conversion units, and one analog-to-digital conversion unit comprises a plurality of analog-to-digital converters, so that parallel conversion and acquisition of multi-channel data are realized, meanwhile, synchronization of digital signals output by different analog-to-digital conversion units or different analog-to-digital conversion modules is carried out through a pseudo-random sequence, a synchronization head is not required to be arranged when the digital signals are transmitted, the utilization rate of transmission bandwidth is improved, the transmission efficiency of the digital signals is improved, and the analog-to-digital conversion device can support higher sampling rate.

Fig. 2 is a schematic structural diagram of an analog-to-digital conversion unit according to the embodiment of the present application shown in fig. 1, and, in combination with fig. 1 and fig. 2, a mode selection module 114 in the analog-to-digital conversion unit 110 includes a selection switch, a programmable unit and an exclusive-or logic element, and the connection relationship between the components is shown in fig. 2.

The selection switch is used for selecting the signal output of the analog-to-digital conversion subunit 113 or the programmable unit; the exclusive-or logic element is configured to exclusive-or the pseudo-random sequence generated by the first sequence generating module 111 with respect to the signal output by the selection switch; the signal output by the programmable unit is programmable; the user can control the operation mode of the analog-to-digital conversion unit 110 by controlling the signal output by the programmable unit, i.e. programming the signal output by the programmable unit.

The operation modes of the analog-to-digital conversion unit 110 include a pseudo random sequence transmission mode and a data acquisition mode. In the pseudo-random sequence transmission mode, the analog-to-digital conversion unit 110 transmits the generated pseudo-random sequence to the connected digital chip 210 to perform time delay calibration, so as to realize multi-path data synchronous acquisition. After the time delay calibration, the analog-to-digital conversion unit 110 can be controlled to enter a data acquisition mode to realize digital conversion and acquisition of analog data, namely, multi-channel data acquisition of corresponding channels is performed.

The xor logic element is configured to xor the input data, where the data input by the xor logic element is a pseudo-random sequence generated by the first sequence generating module 111 and a signal output by the selection switch.

The signals output by the programmable unit comprise logic 0 signals and other digital signals, such as multi-bit digital signals consisting of logic 1 signals, 0 and 1, wherein the digital signals on each bit in the logic 0 signals are all 0, and the digital signals on each bit in the logic 1 signals are all 1.

When the operation mode of the analog-to-digital conversion unit 110 is the pseudo-random sequence transmission mode, the signal output by the programmable unit is a logic 0 signal, the signal output by the selection switch is a logic 0 signal output by the programmable unit, the logic 0 signal and the signal output by the first sequence generation module 111 after the pseudo-random sequence is passed through the exclusive-or logic element are the pseudo-random sequence itself, and the pseudo-random sequence is transmitted to the connected digital chip 210 through the data transmission interface 115.

When the operation mode of the analog-to-digital conversion unit 110 is the data acquisition mode, the selection switch selects the multiple paths of digital signals output by the analog-to-digital conversion subunit 113, and the multiple paths of digital signals are sent to the digital chip 210 through the data sending interface 115 after being subjected to exclusive-or operation with the output of the first sequence generation module 111. The digital chip 210 is also provided with a first sequence generating module and an exclusive or logic element, so that the received signal and the pseudo-random sequence output by the first sequence generating module are subjected to exclusive or operation, and the multi-channel digital signal output by the analog-digital conversion subunit 113 is obtained through reduction, thereby realizing data acquisition.

When the working mode of the analog-to-digital conversion unit 110 is the data acquisition mode, the output of the first sequence generation module 111 may be null, which is equivalent to that the logic 0 signal is xored with the multiple paths of digital signals, so that the signals output by the xored logic element are the multiple paths of digital signals, and the multiple paths of digital signals are sent to the connected digital chip through the data sending interface 115 to realize data acquisition.

In this embodiment, the control of the operation mode of the analog-to-digital conversion unit 110 is realized by three simple elements of the programmable unit, the exclusive-or logic unit and the selection switch, and the logic circuit is low in complexity and easy to implement.

The analog-to-digital conversion unit 110 converts parallel multiple digital signals into high-speed serial data when transmitting the multiple digital signals or pseudo-random sequences, and converts the high-speed serial data into parallel data at the receiving end of the digital chip 210 through transmission of high-speed wires. In order to solve the problem that the frame header positions may be random when the receiving end, i.e. the digital chip 210, performs serial-parallel conversion, the embodiment of the present application further provides a frame header alignment scheme, that is, the analog-to-digital conversion unit 110 is controlled to operate in a programmable mode, and frame header alignment is performed through a tag sequence output in the programmable mode.

Optionally, the operation mode of the analog-to-digital conversion unit 110 further includes a programmable mode, in which the programmable unit outputs a tag sequence including a tag of each analog-to-digital converter ADC in the analog-to-digital conversion subunit 113, and outputs a multi-channel digital signal or a tag of the analog-to-digital converter ADC of the frame header in the pseudo-random sequence as 1, and the other tags as 0, so that the digital chip 210 determines the position of the frame header based on the tag sequence, thereby implementing frame header alignment of the serial-to-parallel converted signal.

For example, fig. 3 is a schematic diagram of a frame header alignment process according to an embodiment of the present application, as shown in fig. 3, serial data (serial data or pseudo random sequence corresponding to multiple digital signals) output by the analog-to-digital conversion unit 110 is shown in fig. 3, where a reference number on each bit in the serial data is a serial number of the bit, and fig. 3 includes two frames of data (i.e. 1 st frame and 2 nd frame) as an example in the serial data; the receiving end, i.e. the digital chip 210, converts serial data into parallel data, and the position of a frame header (bit with reference number 1) is not at the first position of the parallel data due to the problem of random frame header positions, at this time, the analog-to-digital conversion unit 110 can be controlled to work in a programmable mode, and a tag sequence output by the programmable unit is sent to the digital chip 210, and the digital chip 210 determines the position of the frame header in the parallel data based on the position of a tag with value 0 in the tag sequence, so that the frame header alignment of the parallel data is realized based on the position of the frame header, and the aligned parallel data is shown in fig. 3.

The digital chip 210 may be provided with a shift adjustment module, through which the frame header and the data located behind the frame header in the parallel data are integrally moved based on the position of the tag with the value of 0 in the tag sequence, so that the moved frame header is located at the first position of the parallel data.

Taking the serial data output by the analog-to-digital conversion unit 110 as a pseudo-random sequence as an example, after the frame header alignment is achieved through the steps, the transmission delay can be determined based on the pseudo-random sequence after the frame header alignment and the pseudo-random sequence generated inside the digital chip 210, and the delay calibration is performed on the transmission delay, so that the multi-channel data synchronous acquisition is achieved based on the multiple analog-to-digital conversion units 110 and the digital chip 210 connected with the analog-to-digital conversion units.

The plurality of digital chips 210 in one digital chipset 200 may be located on the same circuit board or may be distributed on a plurality of circuit boards.

Fig. 4 is a schematic structural diagram of another analog-to-digital conversion unit according to an embodiment of the present application, and referring to fig. 2 and 4, in this embodiment, the analog-to-digital conversion unit 110 further includes a phase detection module 116.

The phase detection module 116 is configured to divide the sampling clock signal (provided by the clock module) input by the sample-and-hold module 112, so as to obtain a 0 ° divided clock signal, a 90 ° divided clock signal, a 180 ° divided clock signal, and a 270 ° divided clock signal; performing phase detection on the reset signal triggering the first sequence generation module 111 based on the 0 ° divided clock signal, the 90 ° divided clock signal, the 180 ° divided clock signal, and the 270 ° divided clock signal; based on the result of the phase detection, the synchronous clock signal of the reset signal is determined from the 0 ° divided clock signal, the 90 ° divided clock signal, the 180 ° divided clock signal, and the 270 ° divided clock signal to realize synchronous reset of the multi-analog-digital conversion unit 110 or the multi-analog-digital conversion module 100 based on the synchronous clock signal of the reset signal.

The phase detection module 116 takes the sampling clock signal and the reset signal input to the analog-to-digital conversion unit 110 as input, and divides the frequency of the clock signal to obtain four paths of low-speed clock signals, wherein the phases are respectively marked as 0 °, 90 °, 180 ° and 270 °, and the phase detection result detected by the phase detection module 116 is used for representing the phase of the reset signal, namely one of the phases of 0 °, 90 °, 180 ° and 270 °.

The phase detection result may be stored in a 4bit register, so that the phase of the reset signal is determined according to the value of each bit of the register, and further, the synchronous clock signal of the reset signal is determined from four low-speed clock signals of 0 °, 90 °, 180 ° and 270 °, thereby effectively avoiding the occurrence of metastable state and ensuring the deterministic timing relationship when the plurality of analog-digital conversion units 110 work cooperatively.

Fig. 5 is a schematic diagram of the frequency division result of the signal in the embodiment of fig. 4 according to the present application, as shown in fig. 5, the reset signal is a rising edge signal, and the sampling clock is frequency-divided to obtain four low-speed clock signals, the relative phases of which are respectively 0 °,90 °,180 ° and 270 °, and in fig. 5, the 0 °,90 °,180 ° and 270 ° frequency-divided clock signals are respectively represented by the 0 °,90 ° frequency-divided clock signal, the 180 ° frequency-divided clock signal and the 270 ° frequency-divided clock signal. The phase of the reset signal is detected every 1/2 sampling clock by the logical combination relation of the four low-speed clock signals.

A four-bit register (i.e., a reset signal phase detection register) may be used to store the phase detection result of the reset signal, and bits 0 to 3 of the register correspond to the 0 ° divided clock signal, the 90 ° divided clock signal, the 180 ° divided clock signal, and the 270 ° divided clock signal, respectively. The phase detection result of the reset signal may be represented by a bit with a value of 1 in the register, and a bit that is not adjacent to the bit with a value of 1 in the register, such as a bit with a farthest distance, may be selected, and the corresponding divided clock signal is the synchronous clock signal of the reset signal.

In fig. 5, taking the arrival of the reset signal at 0 ° to 90 ° as an example, the 0 th bit of the register is changed from 0 to 1, the synchronous clock signal of the reset signal may be selected to be the 270 ° divided clock signal.

If the reset signal arrives at 180 ° to 270 °, the 2 nd bit of the register is changed from 0 to 1, and the synchronous clock signal of the reset signal can be selected to be a frequency division clock signal of 0 °.

By frequency division of the clock, the uncertainty of the reset signal time sequence of the analog-to-digital conversion unit 110 caused by the fact that the edge time of the reset signal is too short to the edge time of the sampling clock and metastable state is effectively avoided, and the deterministic time sequence relation when the multimode-to-digital conversion unit 110 works cooperatively is ensured.

The analog-to-digital conversion device may be connected to a data storage device, where the data storage device includes a plurality of digital chipsets 200, and the number of digital chipsets 200 in the data storage device is consistent with the number of analog conversion modules 100 in the analog-to-digital conversion device, so as to store digital signals sent by each analog-to-digital conversion module 100 through a corresponding channel.

Fig. 6 is a schematic structural diagram of a digital chipset according to an embodiment of the present application, as shown in fig. 6, the digital chipset 200 includes a plurality of digital chips 210, where the digital chips 210 include a data receiving interface 211, a second sequence generating module 212, and a delay calibration module 213.

A digital chipset 200 corresponds to an analog-to-digital conversion module 100, and is configured to store multiple digital signals of corresponding channels output by the analog-to-digital conversion module 100. The digital chipset 200 includes a plurality of digital chips 210, which are respectively connected to or corresponding to the plurality of analog-to-digital conversion units 110 in the corresponding analog-to-digital conversion module 100. In fig. 6, the digital chipset 200 includes n digital chips 210 as an example.

The data receiving interface 211 is configured to receive multiple digital signals or pseudo random sequences sent by the connected analog-to-digital conversion unit 110; the second sequence generating module 212 is configured to generate a pseudo-random sequence under the triggering of the synchronization signal, which may be denoted as a second pseudo-random sequence; the delay calibration module is configured to perform delay calibration on the digital chip 210 based on the pseudo-random sequence generated by the second sequence generation module 212 in each digital chip 210 in the digital chipset 200, that is, the second pseudo-random sequence, and the pseudo-random sequence (denoted as the first pseudo-random sequence) sent by the analog-to-digital conversion unit 110 and received by the data receiving interface 211; thereby achieving time delay calibration of the transmission multi-channel digital signal channels so as to synchronize the multi-channel digital signals received by each digital chip 210.

In some embodiments, the digital chip 210 may further include a buffering unit for buffering the received multiple digital signals sent by the analog-to-digital conversion unit 110 after the time delay calibration.

The data receiving interface 211 in the digital chip 210 is connected to the data transmitting interface 115 of the corresponding analog-to-digital conversion unit 110, so as to receive multiple digital signals output by the data transmitting interface 115. The data receiving interface 211 in the digital chip 210 is connected to the data transmitting interface 115 of the corresponding analog-to-digital conversion unit 110 through a plurality of SerDes channels.

In other embodiments, the data receiving interface 211 in the digital chip 210 converts multiple digital signals, i.e. parallel data, into serial data, and the serial data is converted into parallel data through the data receiving interface 211 at the receiving end of the digital chip 210 through high-speed routing.

Because of the time error between the multiple channels through which the parallel data passes, in order to realize the correction of the time error, a shift adjustment module may be further disposed on each channel in the digital chip 210, and the time delay calibration of different channels is realized through the shift adjustment module.

In some embodiments, parameters of the shift adjustment module may be set in advance based on the length of the channel, so that the phase of the signal transmitted through the corresponding channel is adjusted by the shift adjustment module.

Optionally, the synchronization signal triggering the second sequence generation module 212 is a reset signal triggering the first sequence generation module 111.

Specifically, the first sequence generation module 111 and the second sequence generation module 212 may generate pseudo-random sequences simultaneously by starting from the same signal. The first sequence generation module 111 and the second sequence generation module 212 have the same structure, and the generated pseudo random sequences are the same. The delay calibration module 213 can obtain deterministic delay during digital signal transmission based on the pseudo random sequences generated by the first sequence generation module 111 and the second sequence generation module 212, and realize absolute delay calibration through compensation of the deterministic delay.

In other embodiments, the synchronization signal triggering the second sequence generating module 212 may not use the reset signal triggering the first sequence generating module 111, so that the delay calibration module 213 may obtain a deterministic delay when transmitting the digital signal based on the pseudo random sequences generated by the first sequence generating module 111 and the second sequence generating module 212, and implement the relative delay calibration through the compensation of the deterministic delay.

Fig. 7 is a schematic structural diagram of a digital chip according to an embodiment of the present application, and as can be seen in conjunction with fig. 6 and fig. 7, in this embodiment, the digital chip further includes a periodic tag generation module 214. The periodic tag generation module 214 is configured to generate a periodic tag based on the pseudo random sequence generated by the second sequence generation module 212; the delay calibration module 213 is specifically configured to perform delay calibration on the digital chip 210 based on the periodic tag.

The periodic tag is generated based on a pseudo-random sequence, and particularly, the numbers of the pseudo-random sequence can be latched through a synchronous signal, and the latched numbers are the tags of the pseudo-random sequence. Since the pseudo random sequence has periodicity, the tag also has periodicity, referred to as a periodic tag.

The delay calibration module 213 may measure deterministic delays of the channels between the two based on the periodic tags of the pseudo-random sequences generated within the digital chip 210 and based on the periodic tags of the pseudo-random sequences transmitted by the received analog-to-digital conversion unit 110. The time delay calibration of the different digital chips 210 may also be implemented based on periodic tags of pseudo-random sequences generated within the different digital chips 210.

Fig. 8 is a schematic diagram illustrating a periodic tag generation process according to the embodiment of the present application shown in fig. 7, where the synchronization signal is a rising edge signal, and the synchronization signal may be provided to each digital chipset 200 or different digital chips 210 in the same digital chipset 200 by the synchronization signal generation module as shown in fig. 8. The pseudo-random sequence comprises n different numbers, the pseudo-random sequences 1-n are pseudo-random sequences generated in n different digital chips 210 respectively, the corresponding labels are shown as labels 1-n in fig. 7, and the labels are latched based on the synchronous signals to obtain periodic labels corresponding to the pseudo-random sequences 1-n respectively; the time delay calibration module 213 determines time delays between the digital chips 210 based on the periodic tags and compensates the time delays, so that time delay calibration of different digital chips 210 is realized, data acquired by different digital chips 210 are synchronized, and multi-digital-chip collaborative acquisition is realized.

The delay calibration module 213 may also implement delay calibration between the digital chip 210 and the analog-to-digital conversion unit 110 based on the periodic tag.

The means for performing delay compensation may be any means, such as a shift adjustment module.

Optionally, fig. 9 is a schematic structural diagram of another digital chip according to an embodiment of the present application, as shown in fig. 9, a plurality of shift adjustment modules 215 are further disposed in the digital chip 210.

The digital chip 210 is connected to the analog-to-digital conversion unit 110 through a plurality of SerDes channels, and a plurality of shift adjustment modules 215 are used for performing time delay calibration on each SerDes channel.

Due to the difference in trace lengths, the delays of different SerDes channels are also different, so that when data arrives at the digital chip 210, there is a delay deviation due to the difference in SerDes channels. To correct for this delay skew, delay calibration may be performed on each SerDes channel of the data receiving interface 211 by a plurality of shift adjustment modules 215 immediately following the data receiving interface 211.

In some embodiments, the synchronization signal triggering the second sequence generating module 212 may be a signal output by the first shift adjusting module, where the second shift adjusting module is configured to perform time delay calibration on the corresponding SerDes channel based on the pseudo random sequence output by the second sequence generating module; the first shift adjustment module is any one shift adjustment module of the plurality of shift adjustment modules 215 in the digital chip 210, and in fig. 9, the first shift adjustment module is taken as an example of the first shift adjustment module 215; the second shift adjustment module is the shift adjustment module 215 remaining after the first shift module is removed from the plurality of shift adjustment modules 215 in the digital chip 210.

In the time delay calibration stage, the analog-to-digital conversion unit 110 may be controlled to operate in a pseudo-random sequence transmission mode, and the pseudo-random sequence generated by the first sequence generation module 111 (for distinguishing and marking as a first pseudo-random sequence) is transmitted to the digital chip 210, and the first pseudo-random sequence is transmitted to the time delay calibration module 213 after passing through the first shift adjustment module, and meanwhile, the first shift adjustment module triggers the second sequence generation module 212 to generate the pseudo-random sequence after receiving the first pseudo-random sequence (for distinguishing and marking as a second pseudo-random sequence). The delay calibration module 213 may implement delay calibration between different digital chips 210 based on the second pseudo-random sequences generated in different digital chips 210, and may implement delay calibration between different digital chips 210 and the analog-to-digital conversion unit 110 based on the second pseudo-random sequences generated in different digital chips 210 and the first pseudo-random sequences, so as to implement data synchronous acquisition.

Fig. 10 is a schematic structural diagram of a data acquisition device according to an embodiment of the present application, as shown in fig. 10, the data acquisition device 10 includes: analog-to-digital conversion means and a digital chipset 200 connected to each analog-to-digital conversion module 100 in the analog-to-digital conversion means.

In some embodiments, the data acquisition device 10 may be a device responsible for data acquisition in an oscilloscope acquisition system.

The embodiment of the application also provides a time delay calibration method, which is applied to the data acquisition device 10, and comprises the following steps:

The analog-to-digital conversion unit 110 is controlled to enter a pseudo-random sequence sending mode, and the first sequence generation module 111 is controlled to generate a pseudo-random sequence under the triggering of a reset signal; under the triggering of the synchronization signal, the second sequence generating module 212 is controlled to generate a pseudo-random sequence; the time delay calibration is performed based on the pseudo random sequences generated by the first sequence generation module 111 and the second sequence generation module 212.

Specifically, the second sequence generating module 212 may be triggered to generate the pseudo-random sequence by using the signal output by the first shift adjustment module or the reset signal as a synchronization signal.

Fig. 11 is a flowchart of a time delay calibration method according to an embodiment of the present application, where the method is applied to a data acquisition device 10, as shown in fig. 11, and the method includes:

in step S111, a reset signal is sent to each analog-to-digital conversion unit 110.

Specifically, a reset signal is sent to each analog-to-digital conversion unit 110 to ensure the operation timing between different analog-to-digital conversion units 110.

In step S112, the analog-to-digital conversion unit 110 is controlled to enter the pseudo random sequence transmission mode to generate the pseudo random sequence based on the first sequence generating module 111.

In step S113, the second sequence generating module 212 of the digital chip 210 is triggered to generate a pseudo random sequence.

The second sequence generation module 212 may be triggered to generate a pseudo-random sequence based on the reset signal, i.e. to generate a pseudo-random sequence in synchronization with the first sequence generation module 111, or may be triggered based on a signal sent by a certain analog-to-digital conversion unit 110.

In step S114, based on the shift adjustment module 215, the relative alignment of the plurality of transmission channels in the digital chip 210 is achieved.

Within the digital chip 210, the relative alignment of multiple data transmission channels within a piece of digital chip is achieved by multiple shift adjustment modules 215.

In step S115, the analog-to-digital conversion unit 110 is controlled to enter a programmable mode to output a tag sequence.

In step S116, frame header alignment of multiple transmission channels in the digital chip 210 is achieved based on the tag sequence output by the analog-to-digital conversion unit 110.

Step S117 generates a periodic label for each digital chip 210 based on the pseudo random sequence.

Step S118, based on the synchronization signal of the digital chips 210 and the periodic tag, the time delay calibration between the digital chips 210 is performed, so as to realize the multi-mode digital conversion unit 110 and multi-digital chip acquisition coordination.

The synchronization signal may be the aforementioned reset signal.

After the time delay calibration, the analog-to-digital conversion unit 110 is controlled to enter a data acquisition mode for normal data acquisition.

In describing embodiments of the present application, it should be noted that, unless explicitly stated or limited otherwise, the terms "mounted," "connected," and "coupled" should be construed broadly, and may be, for example, fixedly coupled, indirectly coupled through an intermediary, in communication between two elements, or in an interaction relationship between two elements. The specific meaning of the above terms in the embodiments of the present application will be understood by those of ordinary skill in the art according to specific circumstances.

In the description of the present application, it should be understood that the terms "center", "length", "width", "thickness", "top", "bottom", "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal", "inner", "outer", "axial", "circumferential", etc. are used to indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, merely to facilitate description of the present application and to simplify the description, and do not indicate or imply that the referred location or element must have a specific orientation, in a specific configuration and operation, and therefore should not be construed as limiting the present application.

The embodiments of the application may be implemented or realized in any number of ways, including as a matter of course, such that the apparatus or elements recited in the claims are not necessarily oriented or configured to operate in any particular manner. In the description of the embodiments of the present application, the meaning of "a plurality" is two or more unless specifically stated otherwise.

The terms first, second, third, fourth and the like in the description and in the claims and in the above-described figures, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be capable of being practiced otherwise than as specifically illustrated and described.

Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The term "plurality" herein refers to two or more. The term "and/or" is herein merely an association relationship describing an associated object, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship; in the formula, the character "/" indicates that the front and rear associated objects are a "division" relationship.

It will be appreciated that the various numerical numbers referred to in the embodiments of the present application are merely for ease of description and are not intended to limit the scope of the embodiments of the present application.

It should be understood that, in the embodiment of the present application, the sequence number of each process does not mean that the execution sequence of each process should be determined by the function and the internal logic, and should not limit the implementation process of the embodiment of the present application.

Claims

1. The analog-to-digital conversion device is characterized by comprising at least one analog-to-digital conversion module, wherein different analog-to-digital conversion modules are used for carrying out analog-to-digital conversion on analog signals of different input channels and sending the converted digital signals to a plurality of connected digital chip sets; the digital chip set comprises a plurality of digital chips;

2. The apparatus of claim 1, wherein the mode selection module comprises a selection switch, a programmable unit, and an exclusive or logic element;

3. The apparatus of claim 2, wherein the operation mode of the analog-to-digital conversion unit further comprises a programmable mode in which the programmable unit outputs a tag sequence including a tag of each of the analog-to-digital converters in the analog-to-digital conversion subunit, and the tags of the analog-to-digital converters outputting the frame header in the multiple digital signals or pseudo-random sequences are 1 and the remaining tags are 0, such that the digital chip determines the position of the frame header based on the tag sequence to achieve frame header alignment of the serial-to-parallel converted signals.

4. A device according to any one of claims 1-3, wherein the analog to digital conversion unit further comprises a phase detection module for:

5. The digital chip set is characterized by being used for receiving digital signals of corresponding channels output by the analog-to-digital conversion module, and comprises a plurality of digital chips, wherein each digital chip comprises a data receiving interface, a second sequence generating module and a time delay calibration module; the analog-to-digital conversion module is provided by any one of claims 1-4;

6. The digital chipset of claim 5, wherein the digital chip further comprises a periodic tag generation module for:

The time delay calibration module is specifically configured to:

7. The digital chipset of claim 5, wherein the synchronization signal triggering the second sequence generation module is a reset signal triggering the first sequence generation module.

8. The digital chipset of claim 5 wherein the digital chip and the analog to digital conversion unit are connected by a plurality of SerDes channels; the digital chip further comprises a plurality of shift adjustment modules, wherein the shift adjustment modules are used for performing time delay calibration on each SerDes channel.

9. The digital chipset of claim 8, wherein the synchronization signal triggering the second sequence generation module is a signal output by a first shift adjustment module, and the second shift adjustment module is configured to perform time delay calibration on a corresponding SerDes channel based on a pseudo random sequence output by the second sequence generation module;

10. A data acquisition device, comprising: the analog-to-digital conversion apparatus provided in any one of claims 1 to 4, and a digital chipset connected to each of the analog-to-digital conversion modules in the analog-to-digital conversion apparatus, the digital chipset being the digital chipset provided in any one of claims 5 to 9.