CN117938132A - Power-on reset circuit and chip - Google Patents

Abstract

The application relates to the technical field of semiconductors, and discloses a power-on reset circuit, which comprises: a detection voltage dividing circuit configured to detect a divided voltage of the power supply voltage; the reset signal generation circuit is connected with the detection voltage division circuit and comprises a high-voltage transistor circuit and a medium-voltage transistor circuit connected with the high-voltage transistor circuit, and is configured to turn over and output a primary power-on reset signal under the condition that the divided voltage of the power supply voltage is larger than a reset threshold voltage; wherein the reset threshold voltage is commonly determined according to the high voltage transistor circuit and the medium voltage transistor circuit; and the shaping delay circuit is connected with the reset signal generation circuit and is configured to shape and delay the primary power-on reset signal and output the power-on reset signal. The power-on reset circuit can ensure the normal operation of the band gap reference circuit before the power-on reset circuit resets in the power-on process of the power supply voltage, and effectively improves the reliability and the anti-interference performance of the system. The application also discloses a chip.

Description

Power-on reset circuit and chip

Technical Field

The present application relates to the field of semiconductor integrated circuits, and more particularly to a power-on reset circuit and a chip.

Background

At present, the improvement of the integration level of the chip application environment, the large power supply interference and the power supply judgment during the power on and power off of the chip are particularly important.

The related art discloses a traditional common power-on reset circuit, wherein a power supply VCC is connected to the grid electrodes of a plurality of high-voltage tubes in series through a resistor R1, when the power supply VCC is lower, an output reset signal POSH is low, the whole power supply system is reset, and the uncontrollable circuit or the error state caused by the excessively low power supply voltage is prevented; when the power supply VCC is high to the equivalent threshold value of the series high-voltage tube, the reset signal POSH releases the reset of the system and marks the normal state of the power supply voltage.

In the process of implementing the embodiments of the present disclosure, it is found that at least the following problems exist in the related art:

The traditional power-on reset circuit has the problem that the threshold value of the high-voltage MOS tube is changed greatly along with the change of temperature and process angle, so that the reset threshold value of the power-on reset circuit is also large in dispersion. Under the condition of lower threshold value, the power supply voltage is powered down, the normal work of the band gap reference circuit can not be ensured before the power-on reset circuit is reset, and the system reliability is not high.

It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the application and thus may include information that does not form the prior art that is already known to those of ordinary skill in the art.

Disclosure of Invention

The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview, and is intended to neither identify key/critical elements nor delineate the scope of such embodiments, but is intended as a prelude to the more detailed description that follows.

The embodiment of the disclosure provides a power-on reset circuit and a chip, which are used for reducing the influence of temperature and process angle change on reset threshold dispersion of the power-on reset circuit, effectively reducing the reset threshold dispersion, simplifying the structure, improving the performance stability, having a comparatively convergent threshold value, particularly ensuring the normal operation of a band gap reference circuit before reset of the power-on reset circuit in the power-on voltage power-on process, and effectively improving the reliability and anti-interference performance of a system.

In some embodiments, the power-on reset circuit includes: a detection voltage dividing circuit configured to detect a divided voltage of the power supply voltage; the reset signal generation circuit is connected with the detection voltage division circuit and comprises a high-voltage transistor circuit and a medium-voltage transistor circuit connected with the high-voltage transistor circuit, and is configured to turn over and output a primary power-on reset signal under the condition that the divided voltage of the power supply voltage is larger than a reset threshold voltage; wherein the reset threshold voltage is commonly determined according to the high voltage transistor circuit and the medium voltage transistor circuit; and the shaping delay circuit is connected with the reset signal generation circuit and is configured to shape and delay the primary power-on reset signal and output the power-on reset signal.

In some embodiments, the chip comprises: a chip body; the power-on reset circuit comprises a chip body.

The power-on reset circuit and the chip provided by the embodiment of the disclosure can realize the following technical effects:

the voltage division signal generated by the voltage division circuit is detected and input into a reset signal generating circuit comprising a high-voltage transistor circuit and a medium-voltage transistor circuit, a primary power-on reset signal is output, and if the voltage division of the power supply voltage is larger than a reset threshold voltage determined by the high-voltage transistor circuit and the medium-voltage transistor circuit together, the high-voltage transistor circuit turns over and outputs the primary power-on reset signal. The threshold value of the medium voltage transistor circuit has small change along with the temperature and the process angle, so that the dispersion of the reset threshold value is effectively reduced, the hysteresis of the power-on and power-off reset threshold value of the power supply is realized, and the anti-interference performance of the power-on reset circuit is improved. And after delaying and shaping the primary power-on reset signal output by the reset signal generating circuit, outputting a final power-on reset signal to the band gap reference circuit. The influence of temperature and process angle change on the reset threshold value dispersion of the power-on reset circuit is reduced, the reset threshold value dispersion is effectively reduced, the structure is simplified, the performance stability is improved, the power-on reset circuit has a convergent threshold value, and particularly, if the power supply is abnormally powered down in the power supply voltage power-on process, the power-on reset circuit in the system is not reset, the system reset can be controlled, the system is protected, the uncontrollable or error state is prevented, the normal work of the band gap reference circuit before the reset of the power-on reset circuit is maintained, and the reliability and the anti-interference performance of the system are effectively improved.

The foregoing general description and the following description are exemplary and explanatory only and are not restrictive of the application.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which like reference numerals refer to similar elements, and in which:

FIG. 1 is a schematic diagram of a power-on reset circuit provided in an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of another power-on reset circuit provided by an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of another power-on reset circuit provided by an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of another power-on reset circuit provided by an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of another power-on reset circuit provided by an embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of a chip according to an embodiment of the disclosure.

Reference numerals:

1: detecting a voltage dividing circuit; r1: a first resistor; r2: a second resistor;

2: a reset signal generating circuit;

21: a high voltage transistor circuit; NM1: a first high-voltage MOS tube; INV1: a first inverter;

22: a medium voltage transistor circuit; NMM1: a first medium voltage MOS tube; NMM2: a second medium voltage MOS tube; NMM3: a third medium voltage MOS tube;

23: resetting a threshold hysteresis circuit; r3: a third resistor; r4: a fourth resistor; PM1: a first PMOS tube;

3: shaping delay circuit;

31: a first shaping circuit; INV2: a second inverter; INV3: a third inverter;

32: a delay circuit;

INV4: a fourth inverter;

321: a transistor delay circuit;

3211: an equivalent delay resistance circuit; PM2: a second PMOS tube; PM3: a third PMOS tube; PM4: a fourth PMOS tube; PM5: a fifth PMOS tube; PM6: a sixth PMOS tube;

3213: a flipping device; NM2: a second high-voltage MOS tube;

3212: an equivalent delay capacitance circuit; NM3: a third high voltage MOS tube;

33: a second shaping circuit; INV5: a fifth inverter; INV6: a sixth inverter;

600: a chip body;

100: and a power-on reset circuit.

Detailed Description

So that the manner in which the features and techniques of the disclosed embodiments can be understood in more detail, a more particular description of the embodiments of the disclosure, briefly summarized below, may be had by reference to the appended drawings, which are not intended to be limiting of the embodiments of the disclosure. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may still be practiced without these details. In other instances, well-known structures and devices may be shown simplified in order to simplify the drawing.

The terms first, second and the like in the description and in the claims of the embodiments of the disclosure and in the above-described figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe embodiments of the present disclosure. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion.

In the embodiments of the present disclosure, the terms "upper", "lower", "inner", "middle", "outer", "front", "rear", and the like indicate an azimuth or a positional relationship based on that shown in the drawings. These terms are used primarily to better describe embodiments of the present disclosure and embodiments thereof and are not intended to limit the indicated device, element, or component to a particular orientation or to be constructed and operated in a particular orientation. Also, some of the terms described above may be used to indicate other meanings in addition to orientation or positional relationships, for example, the term "upper" may also be used to indicate some sort of attachment or connection in some cases. The specific meaning of these terms in the embodiments of the present disclosure will be understood by those of ordinary skill in the art in view of the specific circumstances.

In addition, the terms "disposed," "connected," "secured" and "affixed" are to be construed broadly. For example, "connected" may be in a fixed connection, a removable connection, or a unitary construction; may be a mechanical connection, or a connection; may be directly connected, or indirectly connected through intervening media, or may be in internal communication between two devices, elements, or components. The specific meaning of the above terms in the embodiments of the present disclosure may be understood by those of ordinary skill in the art according to specific circumstances.

The term "plurality" means two or more, unless otherwise indicated.

In the embodiment of the present disclosure, the character "/" indicates that the front and rear objects are an or relationship. For example, A/B represents: a or B.

The term "and/or" is an associative relationship that describes an object, meaning that there may be three relationships. For example, a and/or B, represent: a or B, or, A and B.

It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be combined with each other.

Referring to fig. 1, an embodiment of the present disclosure provides a power-on reset circuit, which includes a detection voltage division circuit 1, a reset signal generation circuit 2, and a shaping delay circuit 3. The detection voltage dividing circuit 1 is configured to detect the divided voltage of the power supply voltage. The reset signal generating circuit 2 is connected with the detection voltage dividing circuit 1, comprises a high-voltage transistor circuit 21 and a medium-voltage transistor circuit 22 connected with the high-voltage transistor circuit 21, and is configured to enable the reset signal generating circuit 2 to turn over and output a primary power-on reset signal under the condition that the divided voltage of the power supply voltage is larger than a reset threshold voltage. Wherein the reset threshold voltage is determined in accordance with the high voltage transistor circuit 21 and the medium voltage transistor circuit 22 together. And the shaping delay circuit 3 is connected with the reset signal generation circuit 2, and is configured to perform shaping delay on the primary power-on reset signal and output the power-on reset signal.

The reset signal generating circuit 2 inverts and outputs a primary power-on reset signal, and includes: in the case where the divided voltage of the power supply voltage is greater than the reset threshold voltage, the reset signal generation circuit 2 inverts and outputs the primary power-on instruction signal. In the case where the divided voltage of the power supply voltage is smaller than the threshold voltage, the reset signal generating circuit inverts and outputs the primary reset signal.

With the power-on reset circuit provided by the embodiment of the present disclosure, the voltage division signal generated by the voltage division circuit 1 is detected and input into the reset signal generating circuit 2 including the high voltage transistor circuit 21 and the medium voltage transistor circuit 22, and a primary power-on reset signal is output, and if the voltage division of the power supply voltage is greater than the reset threshold voltage determined by the high voltage transistor circuit 21 and the medium voltage transistor circuit 22 together, the high voltage transistor circuit 21 turns over and outputs the primary power-on reset signal. The threshold value of the medium voltage transistor circuit 22 has small change along with the temperature and the process angle, so that the dispersion of the reset threshold value is effectively reduced, the hysteresis of the power-on and power-off reset threshold value is realized, and the anti-interference performance of the power-on reset circuit is improved. And after delaying and shaping the primary power-on reset signal output by the reset signal generating circuit 2, outputting a final power-on reset signal to the band gap reference circuit. The influence of temperature and process angle change on the reset threshold value dispersion of the power-on reset circuit is reduced, the reset threshold value dispersion is effectively reduced, the structure is simplified, the performance stability is improved, the power-on reset circuit has a convergent threshold value, and particularly, if the power supply is abnormally powered down in the power supply voltage power-on process, the power-on reset circuit in the system is not reset, the system reset can be controlled, the system is protected, the uncontrollable or error state is prevented, the normal work of the band gap reference circuit before the reset of the power-on reset circuit is maintained, and the reliability and the anti-interference performance of the system are effectively improved.

Alternatively, as shown in connection with fig. 5, the high-voltage transistor circuit 21 includes: a first high voltage MOS transistor NM1 and a first inverter INV1. The source electrode of the first high-voltage MOS tube NM1 is connected with the medium-voltage transistor circuit 22, and the grid electrode of the first high-voltage MOS tube NM1 is connected with the detection voltage division circuit 1. The first inverter INV1 is connected to the drain of the first high voltage MOS transistor NM1 and configured to perform phase inversion when the divided voltage of the power supply voltage is greater than the reset threshold voltage.

In this way, the first high-voltage MOS transistor NM1 is beneficial to protecting the medium-voltage transistor circuit 22 connected with the first high-voltage MOS transistor NM1, avoiding the medium-voltage transistor circuit 22 from exceeding the withstand voltage, maintaining the stability of the reset threshold voltage, ensuring the normal operation of the band-gap reference circuit before the power-on reset circuit resets in the power-on voltage power-off process, and effectively improving the reliability and anti-interference performance of the system.

Optionally, the medium voltage transistor circuit 22 comprises a plurality of medium voltage MOS transistors connected in series in sequence, wherein: the grid electrode of the medium-voltage MOS tube NMM1 positioned at the head end of the medium-voltage transistor circuit 22 is connected with the detection voltage division circuit 1, the drain electrode is connected with the high-voltage transistor circuit 21, and the source electrode is connected with the drain electrode of the latter medium-voltage MOS tube in series. The grid electrode of the medium voltage MOS tube NMM2 positioned in the middle of the medium voltage transistor circuit 22 is connected with the detection voltage dividing circuit 1, the drain electrode is connected with the source electrode of the former medium voltage MOS tube connected in series, and the source electrode is connected with the drain electrode of the latter medium voltage MOS tube connected in series. The grid electrode of the medium-voltage MOS tube NMM3 positioned at the tail end of the medium-voltage transistor circuit 22 is connected with the detection voltage dividing circuit 1, the drain electrode is connected with the source electrode of the former medium-voltage MOS tube connected in series, and the source electrode is grounded.

Specifically, the number of the medium voltage MOS transistors connected in series in the medium voltage transistor circuit 22 may be 3, 4 or 5. The number of the medium-voltage MOS transistors can be adjusted and set according to the chip design. The type of medium voltage MOS transistors in series in the medium voltage transistor circuit 22 may be NMOS inverted ratio transistors.

When the number of the medium voltage MOS transistors connected in series in the medium voltage transistor circuit 22 is 3, the gate of the first medium voltage MOS transistor NMM1 is connected to the detection voltage dividing circuit 1, and the drain is connected to the high voltage transistor circuit 21. The grid electrode of the second medium-voltage MOS tube NMM2 is connected with the detection voltage dividing circuit 1, the drain electrode of the second medium-voltage MOS tube NMM2 is connected with the source electrode of the first medium-voltage MOS tube NMM1, the grid electrode of the third medium-voltage MOS tube NMM3 is connected with the detection voltage dividing circuit 1, the drain electrode of the third medium-voltage MOS tube NMM3 is connected with the source electrode of the second medium-voltage MOS tube NMM2, and the source electrode of the third medium-voltage MOS tube NMM3 is grounded.

In this way, the reset threshold voltage is determined according to the first high-voltage MOS transistor NM1 and the plurality of medium-voltage MOS transistors connected in series in sequence. The overall equivalent threshold voltage Vth of the first high-voltage MOS transistor NM1 and the medium-voltage MOS transistor is the VB-point voltage corresponding to the formed channel. The VB-point voltage increases with increasing supply voltage, as does the depletion layer width and the potential at the oxide-silicon interface. When the interface potential reaches a sufficiently high level, electrons flow from the source to the interface and ultimately to the drain. At this time, a carrier channel is formed under the gate oxide between the source and the drain while the transistor is turned on, the reset signal generating circuit 2 is turned over, and the voltage at the V1 point is changed from the high level to the low level, thereby determining the reset threshold voltage accordingly. The threshold value of the medium-voltage MOS tube is small in change along with the temperature and the process angle, so that the dispersion of the reset threshold value is effectively reduced, especially the minimum value can be converged, the normal operation of circuits such as a band gap reference circuit and the like under the reset voltage is effectively ensured, and the reliability and the anti-interference performance of the system are effectively improved.

Optionally, the detection voltage dividing circuit 1 includes: a first resistor R1 and a second resistor R2. The first resistor R1 has a first end connected to the reset signal generating circuit 2 and a second end grounded. The first end of the second resistor R2 is connected with the reset signal generating circuit 2 and the first end of the first resistor R1, and the second end is connected with the power supply voltage. Specifically, a first end of the first resistor R1 is connected to the reset signal generating circuit 2, including: the first terminal of the first resistor R1 is connected to the high-voltage transistor circuit and the medium-voltage transistor circuit 22. The first end of the second resistor R2 is connected to the reset signal generating circuit 2, and includes: the first terminal of the second resistor R2 is connected to the high-voltage transistor circuit and the medium-voltage transistor circuit 22. More specifically, the first end of the first resistor R1 is connected to the high-voltage transistor circuit, the medium-voltage transistor circuit 22, including: the first end of the first resistor R1 is connected to the gate of the first high-voltage MOS transistor NM1 and the gate of the medium-voltage MOS transistor connected in series in the medium-voltage transistor circuit 22. The first terminal of the second resistor R2 is connected to the high-voltage transistor circuit 21 and the medium-voltage transistor circuit 22, and includes: the first end of the second resistor R2 is connected to the gate of the first high-voltage MOS transistor NM1 and the gate of the medium-voltage MOS transistor connected in series in the medium-voltage transistor circuit 22.

Thus, the voltage division of the power supply voltage, namely VB point voltage, is better obtained, if the power supply voltage reaches the set threshold, the VB point voltage is the common overall equivalent threshold voltage Vth of the first high-voltage MOS tube NM1 and the medium-voltage MOS tube, and the reset threshold voltage is better determined.

Optionally, determining the reset threshold voltage from the high voltage transistor circuit 21 and the medium voltage transistor circuit 22 together includes: the overall equivalent threshold voltage Vth common to the medium voltage MOS transistors connected in series in the high voltage transistor circuit 21 and the medium voltage transistor circuit 22 is determined. The reset threshold voltage VP is determined from the overall equivalent threshold voltage Vth, the first resistor R1, and the second resistor R2. Specifically, determining the reset threshold voltage VP according to the overall equivalent threshold voltage Vth, the first resistor R1, and the second resistor R2 includes: vp= (1+r2/R3) Vth.

In this way, the reset threshold voltage is determined according to the first high-voltage MOS transistor NM1 and the plurality of medium-voltage MOS transistors connected in series in sequence. The overall equivalent threshold voltage Vth of the first high-voltage MOS transistor NM1 and the medium-voltage MOS transistor is the VB-point voltage corresponding to the formed channel. The VB-point voltage increases with increasing supply voltage, as does the depletion layer width and the potential at the oxide-silicon interface. When the interface potential reaches a sufficiently high level, electrons flow from the source to the interface and ultimately to the drain. At this time, a carrier channel is formed under the gate oxide between the source and the drain while the transistor is turned on, the reset signal generating circuit 2 is turned over, and the V1 point voltage of the output of the high voltage transistor circuit is changed from the high level to the low level, thereby determining the reset threshold voltage accordingly. And the threshold value of the medium voltage MOS tube is small along with the temperature and the process angle, so that the dispersion of the reset threshold value is effectively reduced, especially the minimum value can be converged, the normal operation of circuits such as a band gap reference circuit and the like under the reset voltage is effectively ensured, and the reliability and the anti-interference performance of the system are effectively improved.

Optionally, as shown in conjunction with fig. 2, the reset signal generating circuit 2 further includes: the threshold hysteresis circuit 23 is reset. A reset threshold hysteresis circuit 23 connected to the high voltage transistor circuit 21 and the shaping delay circuit 3 and configured to achieve hysteresis of the reset threshold voltage.

Therefore, if the power supply voltage is lower, the voltage division of the power supply voltage, namely the VB point voltage is also lower, the equivalent turning threshold of the reset signal generating circuit 2 is not reached, and at the moment, the hysteresis of the reset threshold voltage is realized through the reset threshold hysteresis circuit, so that the anti-interference performance of the power-on reset circuit is improved.

Optionally, as shown in connection with fig. 5, the reset threshold hysteresis circuit 23 includes: the third resistor R3, the fourth resistor R4 and the first PMOS tube PM1. And the first end of the third resistor R3 is connected with the high-voltage transistor circuit. And the first end of the fourth resistor R4 is connected with the second end of the third resistor R3, and the second end of the fourth resistor R4 is connected with the first power supply. The source of the first PMOS transistor PM1 is connected to the first end of the fourth resistor R4, the gate is connected to the high voltage transistor circuit 21 and the shaping delay circuit 3, and the drain is connected to the first end of the third resistor R3.

Under the condition that the power supply voltage is smaller than the power-on reset threshold, the first PMOS tube PM1 is turned off, and the third resistor R3 is not short-circuited. Or under the condition that the power supply voltage is larger than the power-on reset threshold, the first PMOS tube PM1 is conducted, and the third resistor R3 is short-circuited. Specifically, the power-on reset threshold is less than the power-on reset threshold set threshold difference. More specifically, the threshold difference is set to have a value in the range of [100mV,200mV ].

Thus, if the power supply voltage is smaller than the power-on reset threshold, the divided voltage of the power supply voltage, that is, the voltage at the point VB is also lower, and the equivalent inversion threshold of the reset signal generating circuit 2 is not reached, so that the output voltage V1 of the medium voltage transistor circuit 22 outputs a high level, the primary power-on reset signal V2 output by the reset signal generating circuit 2 outputs a low level, at this time, the first PMOS transistor PM1 is turned off, and the third resistor R3 is not shorted. If the power supply voltage is greater than the power-on reset threshold, the divided voltage of the power supply voltage, namely the voltage at the point VB, is also higher, and reaches the equivalent inversion threshold of the reset signal generating circuit 2, so that the output voltage V1 of the medium voltage transistor circuit 22 outputs a low level, the primary power-on reset signal V2 output by the reset signal generating circuit 2 outputs a high level, and at this time, the first PMOS tube PM1 is turned on, and the third resistor R3 is shorted. When the power supply voltage is low to be low to a power-down reset threshold, the resistance is high during overturning, the required power supply voltage division is small, and the power-down threshold is smaller than the power-on threshold by 100-200 mV, so that the hysteresis of the power supply voltage power-on and power-off reset threshold is realized, and the anti-interference performance of the power-on reset circuit is improved.

Optionally, as shown in connection with fig. 3, the shaping delay circuit 3 comprises: a first shaping circuit 31, a delay circuit 32 and a second shaping circuit 33. The first shaping circuit 31 is connected to the high-voltage transistor circuit 21, and is configured to shape the primary power-on reset signal and output a first shaped signal. And a delay circuit 32 connected to the first shaping circuit 31 and configured to delay the first shaped signal and output a first delayed signal. The second shaping circuit 33 is connected to the delay circuit 32 and configured to shape the first delay signal and output a power-on reset signal.

Therefore, the primary power-on reset signal is shaped to output a first shaping signal at the V3 point, then delayed to output a first delay signal at the V4 point, finally shaped to output a power-on reset signal, if the power supply is abnormally powered down, the power-on reset circuit in the system is not reset, the system reset can be controlled, the system is protected, the uncontrollable or error state is prevented, the normal work of the band gap reference circuit before the power-on reset circuit is maintained, and the reliability and the anti-interference performance of the system are effectively improved.

Optionally, as shown in connection with fig. 4, the delay circuit 32 includes: a fourth inverter INV4 and a transistor delay circuit 321. The fourth inverter INV4 is connected to the first shaping circuit 31 and is configured to invert the first shaped signal and output a third inverted signal. The transistor delay circuit 321 is connected to the fourth inverter INV4 and the second power supply, and is configured to delay the third inverse phase output from the fourth inverter INV4, and output a first delay signal.

Therefore, the first shaping signal is favorably delayed, if the power supply is abnormally powered down, the power-on reset circuit in the system is not reset, the system reset can be controlled, the system is protected, uncontrollable or error states are prevented, the normal work of the band gap reference circuit before the power-on reset circuit is maintained, and the reliability and the anti-interference performance of the system are effectively improved.

Optionally, as shown in connection with fig. 4, the transistor delay circuit 321 includes: an equivalent delay resistance circuit 3211, a flip device 3213 and an equivalent delay capacitance circuit 3212. The equivalent delay resistor circuit 3211 is connected to the second power supply and the fourth inverter INV4, respectively. The flip-flop 3213 is connected to the fourth inverter INV4 of the equivalent delay resistor circuit. The equivalent delay capacitance circuit 3212 is connected to the equivalent delay resistance circuit 3211, the inverting device 3213, and the fourth inverter INV4, respectively. The delay time of the first delay signal is determined by the equivalent resistance of the equivalent delay resistor circuit 3211 and the equivalent capacitance of the equivalent delay capacitor circuit 3212.

In this way, the delay time of the first delay signal can be better adjusted and adjusted according to the equivalent resistance of the equivalent delay resistance circuit 3211 and the equivalent capacitance of the equivalent delay capacitance circuit 3212. Therefore, the first shaping signal is delayed more accurately, if the power supply is abnormally powered down, the power-on reset circuit in the system is not reset, the system reset can be controlled, the system is protected, uncontrollable or error states are prevented, normal operation of the band gap reference circuit before the power-on reset circuit is maintained, and the reliability and anti-interference performance of the system are effectively improved.

Optionally, as shown in fig. 5, the equivalent delay resistor circuit 3211 includes a plurality of PMOS transistors connected in series. Wherein: the PMOS tube positioned at the head end of the equivalent delay resistor circuit 3211 has a grid connected with the fourth inverter INV4, a source connected with the second power supply and a drain connected with the source of the subsequent PMOS tube connected in series. The grid electrode of the PMOS tube positioned in the middle of the equivalent delay resistor circuit 3211 is connected with the fourth inverter INV4, the source electrode of the PMOS tube is connected with the drain electrode of the former PMOS tube connected in series, and the drain electrode of the PMOS tube is connected with the source electrode of the latter PMOS tube connected in series. The PMOS tube positioned at the tail end of the equivalent delay resistor circuit 3211 has a grid connected with the fourth inverter INV4, a source connected with the drain of the former serially connected fourth inverter INV4, and a drain connected with the equivalent delay capacitor circuit. Specifically, the number of PMOS transistors connected in series in the equivalent delay resistor circuit 3211 may be 3,4 or 5. The number of the PMOS tubes can be adjusted and set according to the chip design. The equivalent resistance of the equivalent delay resistance circuit can be adjusted by adjusting the number of PMOS tubes which are sequentially connected in series. The type of PMOS transistors connected in series in the equivalent delay resistor circuit 3211 may be PMOS inverted ratio transistors.

In the case that the number of PMOS transistors connected in series in the equivalent delay resistor circuit 321 is 5, the gate of the second PMOS transistor PM2 is connected to the fourth inverter INV4, and the source is connected to the second power supply. The grid electrode of the third PMOS tube PM3 is connected with the fourth inverter INV4, and the source electrode of the third PMOS tube PM3 is connected with the drain electrode of the second PMOS tube PM2 in series. The grid electrode of the fourth PMOS tube PM4 is connected with the fourth inverter INV4, and the source electrode of the fourth PMOS tube PM4 is connected with the drain electrode of the third PMOS tube PM3 in series. The grid electrode of the fifth PMOS tube PM5 is connected with the fourth inverter INV4, and the source electrode of the fifth PMOS tube PM4 is connected with the drain electrode of the fourth PMOS tube PM4 in series. The gate of the sixth PMOS PM6 is connected to the fourth inverter INV4, the source is connected to the drain of the fifth PMOS PM5, and the drain is connected to the equivalent delay capacitor 3212.

Therefore, the linear region resistors of the PMOS tubes which are sequentially connected in series are adopted to replace the actual resistor, and layout area is saved. And the equivalent resistance of the equivalent delay resistance circuit can be adjusted by adjusting the number of the PMOS tubes which are sequentially connected in series, so that the delay time can be more accurately determined.

Optionally, the flipping device 3213 includes: and a second high-voltage MOS transistor NM2. The gate of the second high-voltage MOS transistor NM2 is connected to the fourth inverter INV4, the source is grounded, and the drain is connected to the equivalent delay resistor circuit 3211.

Optionally, the equivalent delay capacitance circuit 3212 includes: and a third high-voltage MOS transistor NM3. The gate of the third high voltage MOS transistor NM3 is connected to the fourth inverter INV4, and the source and drain are grounded.

In this way, the second high-voltage MOS tube NM2 and the third high-voltage MOS tube NM3 are adopted, so that the equivalent capacitance of the equivalent delay capacitance circuit 3212 can be adjusted, and the delay time can be determined more accurately.

Optionally, the first shaping circuit includes: the second inverter INV2 and the third inverter INV3. And the input end of the second inverter INV2 is connected with the reset signal generating circuit 2 and is configured to perform inversion operation on the primary power-on reset signal to obtain a first inversion signal. And the input end of the third inverter INV3 is connected with the output end of the second inverter INV2, and the output end of the third inverter INV3 is connected with the delay circuit 32 and is configured to perform inversion operation on the first inversion signal to obtain a first shaping signal. And/or the number of the groups of groups,

The second shaping circuit 33 includes: a fifth inverter INV5 and a sixth inverter INV6. The fifth inverter INV5, an input terminal of which is connected to the delay circuit 32, is configured to perform an inverting operation on the first delayed signal to obtain a second inverted signal. The sixth inverter INV6 has an input terminal connected to the output terminal of the fifth inverter INV5, and is configured to invert the second inversion signal and output a power-on reset signal.

Therefore, the shaping of the primary power-on reset signal and the first delay signal is facilitated, if the power supply is abnormally powered down, the power-on reset circuit in the system is not reset, the system reset can be controlled, the system is protected, the uncontrollable or error state is prevented, the normal work of the band gap reference circuit before the power-on reset circuit is maintained, and the reliability and the anti-interference performance of the system are effectively improved.

Actual test data show that under different process angles and temperature conditions, the deviation of the minimum reset threshold voltage and the typical condition of the reset threshold voltage is reduced by 10% compared with the traditional structure by adopting the power-on reset circuit provided by the embodiment of the disclosure.

Referring to fig. 6, an embodiment of the disclosure provides a chip including a chip body 600 and a power-on reset circuit 100. The power-on reset circuit 100 includes a chip body 600. The power-on reset circuit 100 includes a detection voltage division circuit 1, a reset signal generation circuit 2, and a shaping delay circuit 3. The detection voltage dividing circuit 1 is configured to detect the divided voltage of the power supply voltage. The reset signal generating circuit 2, connected to the detection voltage dividing circuit 1, includes a high voltage transistor circuit 21 and a medium voltage transistor circuit 22 connected to the high voltage transistor circuit 21, and is configured to invert and output a primary power-on reset signal in the case where the divided voltage of the power supply voltage is greater than a reset threshold voltage. Wherein the reset threshold voltage is determined in accordance with the medium voltage transistor circuit 22. And the shaping delay circuit 3 is connected with the reset signal generation circuit 2, and is configured to perform shaping delay on the primary power-on reset signal and output the power-on reset signal.

With the chip provided in the embodiment of the present disclosure, the voltage division signal generated by the voltage division detection circuit 1 is input into the reset signal generation circuit 2 including the high voltage transistor circuit and the medium voltage transistor circuit 22, and outputs the primary power-on reset signal, and if the voltage division of the power supply voltage is greater than the reset threshold voltage determined by the medium voltage transistor circuit, the high voltage transistor circuit turns over and outputs the primary power-on reset signal. The threshold value of the medium voltage transistor circuit 22 has small change along with the temperature and the process angle, so that the dispersion of the reset threshold value is effectively reduced, the hysteresis of the power-on and power-off reset threshold value is realized, and the anti-interference performance of the power-on reset circuit is improved. And after delaying and shaping the primary power-on reset signal output by the reset signal generating circuit 2, outputting a final power-on reset signal to the band gap reference circuit. The influence of temperature and process angle change on reset threshold dispersion of the power-on reset circuit is reduced, the reset threshold dispersion is effectively reduced, the structure is simplified, the performance stability is improved, the power-on reset circuit has a convergent threshold, and particularly, if the power supply is abnormally powered down in the power-on process, the power-on reset circuit in the system is not reset, the system reset can be controlled, the system is protected, uncontrollable or error states are prevented, the normal work of the band gap reference circuit before the reset of the power-on reset circuit is maintained, and the reliability and anti-interference performance of the system are effectively improved.

The above description and the drawings illustrate embodiments of the disclosure sufficiently to enable those skilled in the art to practice them. Other embodiments may include structural and other modifications. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in, or substituted for, those of others. The embodiments of the present disclosure are not limited to the structures that have been described above and shown in the drawings, and various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims (10)

1. A power-on reset circuit, comprising:

a detection voltage dividing circuit configured to detect a divided voltage of the power supply voltage;

The reset signal generation circuit is connected with the detection voltage division circuit and comprises a high-voltage transistor circuit and a medium-voltage transistor circuit connected with the high-voltage transistor circuit, and is configured to turn over and output a primary power-on reset signal under the condition that the divided voltage of the power supply voltage is larger than a reset threshold voltage; wherein the reset threshold voltage is commonly determined according to the high voltage transistor circuit and the medium voltage transistor circuit;

and the shaping delay circuit is connected with the reset signal generation circuit and is configured to shape and delay the primary power-on reset signal and output the power-on reset signal.

2. The power-on reset circuit of claim 1, wherein the high voltage transistor circuit comprises:

the source electrode of the first high-voltage MOS tube is connected with the medium-voltage transistor circuit, and the grid electrode of the first high-voltage MOS tube is connected with the detection voltage division circuit;

the first inverter is connected with the drain electrode of the first high-voltage MOS tube and is configured to generate phase inversion under the condition that the divided voltage of the power supply voltage is larger than the reset threshold voltage.

3. The power-on reset circuit of claim 1, wherein the medium voltage transistor circuit comprises a plurality of medium voltage MOS transistors connected in series in sequence, wherein:

The grid electrode of the medium-voltage MOS tube is connected with the detection voltage dividing circuit, the drain electrode of the medium-voltage MOS tube is connected with the high-voltage transistor circuit, and the source electrode of the medium-voltage MOS tube is connected with the drain electrode of the latter medium-voltage MOS tube in series;

the grid electrode of the medium-voltage MOS tube is connected with the detection voltage dividing circuit, the drain electrode of the medium-voltage MOS tube is connected with the source electrode of the former medium-voltage MOS tube in series, and the source electrode of the medium-voltage MOS tube is connected with the drain electrode of the latter medium-voltage MOS tube in series;

the grid electrode of the medium-voltage MOS tube is connected with the detection voltage dividing circuit, the drain electrode of the medium-voltage MOS tube is connected with the source electrode of the former medium-voltage MOS tube in series, and the source electrode is grounded.

4. The power-on reset circuit of claim 1 wherein the reset signal generation circuit further comprises:

And the reset threshold hysteresis circuit is connected with the high-voltage transistor circuit and the shaping delay circuit and is configured to realize hysteresis of the reset threshold voltage.

5. The power-on reset circuit of claim 4, wherein the reset threshold hysteresis circuit comprises:

The first end of the third resistor is connected with the high-voltage transistor circuit;

The first end of the fourth resistor is connected with the second end of the third resistor, and the second end of the fourth resistor is connected with the first power supply;

and the source electrode of the first PMOS tube is connected with the first end of the fourth resistor, the grid electrode of the first PMOS tube is connected with the high-voltage transistor circuit and the shaping delay circuit, and the drain electrode of the first PMOS tube is connected with the first end of the third resistor.

6. A power-on reset circuit as claimed in any one of claims 1 to 5, wherein the shaping delay circuit comprises:

the first shaping circuit is connected with the high-voltage transistor circuit and is configured to shape the primary power-on reset signal and output a first shaping signal;

The delay circuit is connected with the first shaping circuit and is configured to delay the first shaping signal and output a first delay signal;

And the second shaping circuit is connected with the delay circuit and is configured to shape the first delay signal and output a power-on reset signal.

7. The power-on reset circuit of claim 6, wherein the delay circuit comprises:

a fourth inverter connected to the first shaping circuit and configured to invert the first shaped signal and output a third inverted signal;

And the transistor delay circuit is respectively connected with the fourth inverter and the second power supply and is configured to delay the third inverse phase output by the fourth inverter and output a first delay signal.

8. The power-on reset circuit of claim 7, wherein the transistor delay circuit comprises:

The equivalent delay resistance circuit is respectively connected with the second power supply and the fourth inverter;

the turnover device is respectively connected with the equivalent delay circuit and the fourth inverter;

The equivalent delay capacitor circuit is respectively connected with the equivalent delay resistor circuit, the turnover device and the fourth inverter;

The delay time of the first delay signal is determined by the equivalent resistance of the equivalent delay resistance circuit and the equivalent capacitance of the equivalent delay capacitance circuit.

9. The power-on reset circuit of claim 6, wherein,

The first shaping circuit includes:

The input end of the second inverter is connected with the reset signal generating circuit and is configured to perform inversion operation on the primary power-on reset signal to obtain a first inversion signal;

The input end of the third inverter is connected with the output end of the second inverter, the output end of the third inverter is connected with the delay circuit and is configured to perform inversion operation on the first inversion signal to obtain a first shaping signal;

And/or the number of the groups of groups,

The second shaping circuit includes:

a fifth inverter, the input end of which is connected with the delay circuit and is configured to perform an inverting operation on the first delay signal to obtain a second inverted signal;

and the input end of the sixth inverter is connected with the output end of the fifth inverter and is configured to perform inversion operation on the second inversion signal and output a power-on reset signal.

10. A chip, comprising:

A chip body;

The power-on reset circuit of any one of claims 1 to 9, comprising a chip body.