CN117935902A - Detection device, method and system with synchronous SRAM wafer device - Google Patents
Detection device, method and system with synchronous SRAM wafer device Download PDFInfo
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Abstract
The embodiment of the invention discloses a detection device, a detection method and a detection system for a wafer device with a synchronous SRAM (static random Access memory), and relates to the technical field of synchronous SRAM detection. The detection device comprises a programmable memory detection module, a control module, an open-short circuit test module, a connection interface and a communication module; the programmable memory detection module and the communication module are both connected with the control module, the open-short circuit test module is connected with the control module through a connection interface, and the control module and the programmable memory detection module are both connected with the piece to be tested through the connection interface; the control module is used for acquiring a first detection instruction through the communication module and determining the connection state of the connection interface and the piece to be tested according to the first detection instruction; the control module is also used for obtaining a second detection instruction through the communication module according to the connection state, and controlling the programmable memory detection module to detect the to-be-detected piece according to the second detection instruction so as to obtain a detection result. The scheme can realize the programming test of any March algorithm on the piece to be tested.
Description
Technical Field
The embodiment of the invention relates to the technical field of synchronous SRAM detection, in particular to a detection device, method and system with synchronous SRAM wafer devices.
Background
For the test of synchronous SRAM, no specific test solution exists in the market, and the demand side basically adopts a universal tester to realize the read-write test of the SRAM by programming preset write data of each period. The programming scheme of the universal tester requires that the tester has a large capacity for preset writing data along with the increase of the address depth of the SRAM to be tested. The scheme simply realizes the read-write operation of the SRAM with different capacities by continuously increasing the preset write data capacity supported by the testing machine, but is almost impossible to realize any March algorithm. With the increase of algorithm operands, the depth of the preset write data is correspondingly increased. Moreover, different preset write data are needed for the SRAMs with different sizes, so that the synchronous SRAMs cannot be tested by any March algorithm.
Disclosure of Invention
The embodiment of the invention provides a detection device, a detection method and a detection system for a synchronous SRAM wafer device, which are used for realizing the test of any March algorithm on a synchronous SRAM.
In a first aspect, an embodiment of the present invention provides a detection apparatus with a synchronous SRAM wafer device, where the detection apparatus with a synchronous SRAM wafer device includes a programmable memory detection module, a control module, an open/short circuit test module, a connection interface, and a communication module;
The programmable memory detection module and the communication module are both connected with the control module, the open-short circuit test module is connected with the control module through the connection interface, and the control module and the programmable memory detection module are both connected with a piece to be tested through the connection interface;
The control module is used for acquiring a first detection instruction through the communication module and determining the connection state of the connection interface and the piece to be detected according to the first detection instruction; the control module is further used for obtaining a second detection instruction through the communication module according to the connection state, and controlling the programmable memory detection module to detect the to-be-detected piece according to the second detection instruction to obtain a detection result.
Optionally, the connection interface includes a multiplexing end and an open-short circuit test end;
The open-short circuit test module is connected with the control module through the open-short circuit test end, and the control module and the programmable memory detection module are connected with the piece to be tested through the multiplexing end.
Optionally, the detecting device with the synchronous SRAM wafer device further comprises a voltage monitoring module; the connection interface also comprises a voltage signal input end;
The voltage monitoring module is connected with the control module through the voltage signal input end, and the control module is used for controlling the voltage monitoring module to acquire a voltage signal of the piece to be detected according to the first detection instruction, and determining the connection state of the connection interface and the piece to be detected according to the voltage signal.
Optionally, the detecting device with the synchronous SRAM wafer device further comprises a clock module and a voltage control module; the connection interface also comprises a voltage signal output end;
the clock module is connected with the control module, and the voltage control module is connected with the control module through the voltage signal output end;
The clock module is used for generating a clock signal, and the control module is used for acquiring the clock signal according to the second detection instruction and configuring a scanning voltage and a scanning frequency according to the clock signal; the voltage control module is used for adjusting the voltage signal of the to-be-detected piece according to the scanning voltage; the control module is used for controlling the programmable memory detection module to detect the piece to be detected according to the second detection instruction and the scanning frequency to obtain a detection result.
Optionally, the programmable memory detection module includes a storage unit, a memory detection unit, an address generation unit, a write data generation unit, an expected data generation unit, and a data comparison unit;
The storage unit is connected with the memory detection unit, the address generation unit, the write data generation unit and the expected data generation unit are all connected with the memory detection unit, the expected data generation unit is connected with the data comparison unit, and the address generation unit, the write data generation unit and the data comparison unit are all connected with the to-be-detected piece through the multiplexing end.
Optionally, the detecting device with the synchronous SRAM wafer device further comprises a storage module;
the programmable memory detection module is connected with the storage module, and the storage module is connected with the communication module; the storage module is used for storing the detection result and sending the detection result to external control equipment through the communication module.
Optionally, the detecting device with synchronous SRAM wafer device further comprises a data arbitration module;
The data arbitration module is connected with the control module, the data arbitration module is connected with the programmable memory detection module, and the data arbitration module is connected with the storage module.
In a second aspect, an embodiment of the present invention further provides a method for detecting a wafer device with a synchronous SRAM, where the method for detecting a wafer device with a synchronous SRAM is performed by the apparatus for detecting a wafer device with a synchronous SRAM provided by any embodiment of the present invention. The detection method of the wafer device with the synchronous SRAM comprises the following steps:
acquiring a first detection instruction;
Determining the connection state of the connection interface and the to-be-detected piece according to the first detection instruction;
Acquiring a second detection instruction according to the connection state;
and detecting the to-be-detected piece according to the second detection instruction, and obtaining a detection result.
Optionally, the detection device with synchronous SRAM wafer devices further comprises a voltage monitoring module; the connection interface comprises a voltage signal input end;
The voltage monitoring module is connected with the control module through the voltage signal input end;
The determining, according to the first detection instruction, a connection state of the connection interface and the to-be-detected member includes:
Acquiring a voltage signal of the to-be-detected piece according to the first detection instruction;
and determining the connection state of the connection interface and the to-be-detected piece according to the voltage signal.
Optionally, the detection device with the synchronous SRAM wafer device further comprises a clock module and a voltage control module; the connection interface also comprises a voltage signal output end;
the clock module is connected with the control module, and the voltage control module is connected with the control module through the voltage signal output end;
the detecting the piece to be detected according to the second detection instruction to obtain a detection result includes:
Acquiring a clock signal according to the second detection instruction;
Configuring a scanning voltage and a scanning frequency according to the clock signal;
adjusting a voltage signal of the to-be-detected piece according to the scanning voltage;
and detecting the to-be-detected piece according to the second detection instruction and the scanning frequency, and obtaining a detection result.
In a third aspect, an embodiment of the present invention further provides a detection system with a synchronous SRAM wafer device, where the detection system with a synchronous SRAM wafer device includes an external control device, a part to be tested, and a detection apparatus with a synchronous SRAM wafer device provided in any embodiment of the present invention.
The control module of the detection device with the synchronous SRAM wafer device provided by the embodiment of the invention can acquire the first detection instruction through the communication module, determine the connection state of the connection interface and the to-be-detected piece according to the first detection instruction, and control the programmable memory detection module to detect the to-be-detected piece according to the second detection instruction acquired by the communication module according to the connection state to obtain a detection result. Therefore, the scheme can perform efficient data transmission and command interaction in a command recognition mode so as to realize programming test of any March algorithm on the piece to be tested.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a detecting device with synchronous SRAM wafer devices according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of another embodiment of a detecting device with synchronous SRAM wafer devices;
FIG. 3 is a schematic diagram of a programmable memory detection module according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of another embodiment of a test apparatus with synchronous SRAM wafer devices;
FIG. 5 is a schematic diagram of another embodiment of a test apparatus with synchronous SRAM wafer devices;
FIG. 6 is a flowchart of another method for inspecting a wafer device with synchronous SRAM according to an embodiment of the present invention;
fig. 7 is a flowchart illustrating a step of determining a connection state of a connection interface and a to-be-tested piece according to a first detection instruction according to an embodiment of the present invention;
Fig. 8 is a flowchart illustrating steps for detecting a workpiece according to a second detection instruction and obtaining a detection result according to an embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The detection device with the synchronous SRAM wafer device provided by the invention is realized on an FPGA of xilinux, and can efficiently realize the programming test of any March algorithm. Fig. 1 is a schematic structural diagram of a testing apparatus with synchronous SRAM wafer devices according to an embodiment of the present invention, and as shown in fig. 1, the testing apparatus 100 with synchronous SRAM wafer devices includes a programmable memory testing module 110, a control module 120, an open/short circuit testing module 130, a connection interface 140, and a communication module 150; the programmable memory detection module 110 and the communication module 150 are both connected with the control module 120, the open-short circuit test module 130 is connected with the control module 120 through the connection interface 140, and the control module 120 and the programmable memory detection module 110 are both connected with the piece 300 to be tested through the connection interface 140;
The control module 120 is configured to obtain a first detection instruction through the communication module 150, and determine a connection state of the connection interface 140 and the to-be-tested piece 300 according to the first detection instruction; the control module 120 is further configured to obtain a second detection instruction according to the connection state through the communication module 150, and control the programmable memory detection module 110 to detect the part 300 to be detected according to the second detection instruction to obtain a detection result.
The programmable memory detection module 110 can test the synchronous SRAM by any March algorithm, and the programmable memory detection module 110 builds a microkernel capable of identifying micro instructions by using the concept of a traditional microcontroller. Wherein the microinstruction is a binary sequence recognizable by the microkernel. The microkernel is an operation and control unit operated in a single cycle, and the microkernel mainly functions to fetch, decode and execute microinstructions in the programmable ROM. Through the microkernel of the programmable memory detection module 110, the implementation of any March algorithm only needs to download the corresponding microinstruction code to the corresponding ROM, and the microkernel can analyze the microinstruction to generate the corresponding address vector and data vector, thereby realizing the test of any March algorithm on the synchronous SRAM.
The control module 120 can implement interaction with external serial logic and control over serial interface devices, and the control module 120 is a Microblaze soft core 121 embedded in xlinx. The open/short circuit test module 130 can detect the connection state of the test device 100 with the synchronous SRAM wafer device and the test piece 300, that is, detect the connection state of the connection interface 140 and the test piece 300, thereby confirming that any March algorithm test is performed on the test piece 300 under the condition that the connection interface 140 and the test piece 300 are connected to be qualified. The connection interface 140 is a connection port between the control module 120 and the device such as the dut 300. The communication module 150 is a bridge for information interaction with external control devices (devices or apparatuses having independent information processing, such as a single-chip microcomputer, an industrial personal computer, a computer, etc.), and may transmit an instruction sent by the external control device to the control module 120, or transmit a detection result of the programmable memory detection module 110 for detecting the to-be-detected piece 300 to the external control device. Illustratively, the communication module 150 includes gigabit Ethernet transmission circuitry to meet the requirements of high-speed read-write error data transmission and command interaction. The part to be inspected refers to a device or apparatus having a synchronous SRAM wafer configuration.
According to the above connection relationship, the process of inspecting the part 300 by the inspection apparatus 100 having the synchronous SRAM wafer device will be described: the external control device generates a first detection instruction and transmits the first detection instruction to the control module 120 through the communication module 150. After the control module 120 takes the first detection instruction, the connection state of the connection interface 140 and the to-be-tested piece 300 is determined according to the first detection instruction. If the connection state indicates that the connection between the connection interface 140 and the to-be-tested device 300 is normal, the control module 120 sends a demand instruction for obtaining the second detection instruction to the external control device through the communication module 150. The external control device generates a second detection command according to the demand command, and sends the second detection command to the control module 120 through the communication module 150. After the second detection finger is obtained by the control module 120, the programmable memory detection module 110 is controlled to implement the test of any March algorithm on the to-be-tested piece 300 according to the second detection instruction, and a detection result is obtained.
The control module 120 of the inspection apparatus 100 with synchronous SRAM wafer devices provided in the embodiments of the present invention may obtain a first inspection instruction through the communication module 150, determine a connection state of the connection interface 140 and the piece 300 to be inspected according to the first inspection instruction, and control the programmable memory inspection module 110 to inspect the piece 300 to be inspected according to a second inspection instruction obtained by the communication module 150 according to the connection state, so as to obtain an inspection result. Therefore, the scheme can perform efficient data transmission and command interaction in a command recognition mode so as to realize programming test of any March algorithm on the piece 300 to be tested.
Based on the above embodiment, optionally, fig. 2 is a schematic structural diagram of another inspection apparatus with synchronous SRAM wafer devices according to the embodiment of the present invention, as shown in fig. 2, the connection interface 140 includes a multiplexing end 141 and an open-short circuit test end 142; the open-short circuit test module 130 is connected with the control module 120 through an open-short circuit test end 142, and the control module 120 and the programmable memory detection module 110 are both connected with the to-be-tested piece 300 through a multiplexing end 141.
When determining the connection state between the connection interface 140 and the to-be-tested piece 300, the control module 120 starts the open-short circuit test module 130 through the open-short circuit test terminal 142 according to the first detection command, and the open-short circuit test module 130 generates a first test signal and transmits the first test signal to the control module 120 through the open-short circuit test terminal 142. The control module 120 adjusts the functional mode of the multiplexing end 141 to an output mode and a signal output by the multiplexing end 141 according to the first test signal, so as to assist in determining the connection state of the connection interface 140 and the to-be-tested piece 300 (for example, determining the connection state of the multiplexing end 141 and the to-be-tested piece 300). After determining the connection state between the connection interface 140 and the to-be-tested device 300, the control module 120 further adjusts the function mode of the multiplexing terminal 141 to be an input/output mode. The programmable memory inspection module 110 can test the part 300 to be inspected through the multiplexing terminal 141 and obtain the inspection result.
Optionally, with continued reference to fig. 2, the inspection apparatus 100 with synchronous SRAM wafer devices further includes a voltage monitor module 160; the connection interface 140 further includes a voltage signal input 143;
the voltage monitoring module 160 is connected to the control module 120 through the voltage signal input end 143, and the control module 120 is configured to control the voltage monitoring module 160 to obtain a voltage signal of the to-be-tested piece 300 according to the first detection instruction, and determine a connection state of the connection interface 140 and the to-be-tested piece 300 according to the voltage signal.
The voltage monitoring module 160 is connected to the to-be-tested device 300, and the voltage monitoring module 160 can monitor a voltage signal of the to-be-tested device 300, so as to confirm a connection state of the detecting device 100 with the synchronous SRAM wafer device and the to-be-tested device 300, i.e. a connection state of the connection interface 140 and the to-be-tested device 300 according to the voltage signal.
For example, if the voltage signal detected by the voltage monitoring module 160 is outside the preset threshold voltage range, it is indicated that the connection state between the connection interface 140 and the to-be-tested device 300 is an open circuit state or a short circuit state; if the voltage signal detected by the voltage monitoring module 160 is within the preset threshold voltage range, it is indicated that the connection state between the connection interface 140 and the to-be-tested device 300 is a normal state.
It should be noted that: the above embodiment is merely illustrative of a determination process of determining the connection state of the control module 120 and the to-be-tested piece 300 by the control module 120 according to the electrical signal, and the specific determination process may be designed according to the actual situation, which is not limited in this case.
Optionally, with continued reference to fig. 2, the inspection apparatus 100 with synchronous SRAM wafer devices further comprises a clock module 170 and a voltage control module 180; the connection interface 140 further includes a voltage signal output 144; the clock module 170 is connected with the control module 120, and the voltage control module 180 is connected with the control module 120 through the voltage signal output end 144;
The clock module 170 is configured to generate a clock signal, and the control module 120 is configured to obtain the clock signal according to the second detection instruction, and configure the scan voltage and the scan frequency according to the clock signal; the voltage control module 180 is used for adjusting the voltage signal of the to-be-measured piece 300 according to the scanning voltage; the control module 120 is configured to control the programmable memory detection module 110 to detect the part 300 to be detected according to the second detection command and the scanning frequency to obtain a detection result.
The clock module 170 is a dynamic clock, a static clock, and a dynamic phase generating circuit, and can generate any frequency and phase below 800 Mhz. Clock module 170 includes a xilinx mixed mode clock manager unit that can dynamically reconfigure clock primitives determined by multiplication, division, phase shift/offset, or duty cycle, automatically calculates the voltage controlled oscillator frequency of the primitive using an oscillator, and outputs a stable and valid clock signal. The control module 120 obtains the clock signal after receiving the second detection command, and determines the scan voltage and the scan frequency according to the clock signal. The voltage control module 180 may adjust the voltage signal of the dut 300 according to the scan voltage. The control module 120 configures the programmable memory detection module 110 according to the configuration data and the scanning frequency included in the second detection instruction, stores the test instruction included in the second detection instruction in the programmable memory detection module 110, and controls the programmable memory detection module 110 to analyze the stored test instruction to detect the to-be-detected component 300 with different voltages (for example, -5V to +5v), so as to obtain a detection result.
Optionally, fig. 3 is a schematic structural diagram of a programmable memory detection module 110 according to an embodiment of the present invention. As shown in fig. 3, the programmable memory detection module 110 includes a storage unit 111, a memory detection unit 112, an address generation unit 113, a write data generation unit 114, a desired data generation unit 115, and a data comparison unit 116; the memory unit 111 is connected to the memory detection unit 112, the address generation unit 113, the write data generation unit 114, and the expected data generation unit 115 are connected to the memory detection unit 112, the expected data generation unit 115 is connected to the data comparison unit 116, and the address generation unit 113, the write data generation unit 114, and the data comparison unit 116 are connected to the test piece 300 through the multiplexing terminal 141.
The control module 120 writes the micro-command of the March algorithm to be executed in the storage unit 111 according to the micro-command of the March algorithm included in the second detection command, opens the clock gate after the test is enabled, releases the reset signal, the memory detection unit 112 starts decoding the micro-command of the March algorithm and controls the address generation unit 113 to generate an address vector, the write data generation unit 114 generates a write data vector, the expected data generation unit 115 generates an expected data vector, and the data comparison unit 116 performs data comparison on the expected data vector and the feedback data after obtaining the feedback data of the workpiece 300 to be tested. Therefore, according to the above process, the corresponding March algorithm test logic, that is, any March algorithm can be implemented only by configuring the corresponding March algorithm microinstruction to the programmable memory detection module 110.
Based on the above embodiments, fig. 4 is a schematic structural diagram of another inspection apparatus with synchronous SRAM wafer devices according to an embodiment of the present invention. As shown in fig. 4, the inspection apparatus 100 with synchronous SRAM wafer devices further includes a memory module 190;
The programmable memory detection module 110 is connected with the storage module 190, and the storage module 190 is connected with the communication module 150; the storage module 190 is used to store the detection result and transmit the detection result to the external control device through the communication module 150.
The communication module 150 includes an ethernet communicator, which can implement gigabit ethernet data transmission, and can meet the requirements of high-speed read-write error data transmission and command interaction. The storage module 190 is connected with the communication module 150, adopts RTL hardware to realize UDP protocol, adopts xilinx's three-speed IP to realize ethernet physical layer, and adopts fixed priority to arbitrate data and command interaction. The time delay of command interaction is greatly reduced while high-speed data transmission is ensured. The memory module 190 comprises a DDR3 read-write circuit of 2GB, and can effectively record the multiple detection results of SRAM with common capacity in the market.
Optionally, with continued reference to fig. 4, the inspection apparatus 100 with synchronous SRAM wafer devices further includes a data arbitration module 200;
The data arbitration module 200 is connected with the control module 120, the data arbitration module 200 is connected with the programmable memory detection module 110, and the data arbitration module 200 is connected with the storage module 190.
The detection result in the test process is recorded in the buffer memory module 190 (DDR 3 of 2 GB), and the data transmitted by the gigabit ethernet fixed priority arbitration data arbitration module 200 and the interleaved mutual command can greatly reduce the time delay of command interaction while ensuring the high-speed data transmission.
Based on the above embodiments, fig. 5 is a schematic structural diagram of another inspection apparatus with synchronous SRAM wafer devices according to an embodiment of the present invention. As shown in fig. 5, the logic is integrally implemented on the FPGA, specifically, an ethernet control 151 part, a programmable memory detection module 110 part, a DDR3 read/write control 191 part, a Microblaze soft core 121 part, a clock part (an MMCM dynamic clock 171 and an MMCM static clock 172), a multiplexing terminal 141 part, a data arbitration 201 part, and the like. The detection device of the synchronous SRAM wafer device, which can support programming test of any March algorithm, can perform high-efficiency data transmission and command interaction, and can integrate high-capacity test data storage, multi-voltage test, current monitoring and open-short circuit test, can be formed by combining logic on the FPGA with external hardware (voltage control module 180, current monitoring module 220, debug210 and the like).
The Microblaze soft core 121 of xilinux embedded in the FPGA system can efficiently expand the control of multiple external serial devices through the standard IP mounted on the core. After the Mcriolaze cores are embedded in the FPGA system, external 10-way control units i2c master (standard IIC MASTER × 10 14141), 4-way GPIO control unit (standard gpio×4 1431) and 2-way UART serial port unit (standard uart×2 1451) can all mount peripheral registers on the Microblaze soft core 121 (exchange information with the Microblaze soft core 121 through the AXI4-Lite interface 122). The user side can control and monitor related functions through C programming, so that the flexibility and usability of the whole system are greatly enhanced. In addition, the voltage control module 180 and the current monitoring module 220 are both connected to the device under test 300, and the ethernet control 151 is connected to the logic connection channel 123, which is not shown in fig. 5.
The operation of the inspection apparatus with synchronous SRAM wafer device will be described with reference to fig. 5: the external control device 400 sends a first detection instruction to the Microblaze soft core 121 through the ethernet control 151, the logical connection channel 123, the ethernet interrupt IP and control, and the AXI4-Lite interface 122. Microblaze soft core 121 controls open-short test module 130 to modify the working mode of multiplexing terminal 141 into output voltage of multiplexing terminal 141 and output voltage of output module through AXI4-Lite interface 122 and open-short control IP. At the same time, the Microblaze soft core 121 controls the voltage control module 180 to detect the voltage signal of the to-be-detected piece 300 through the AXI4-Lite interface 122 and the standard IIC MASTER x 10 14141, so as to determine the connection state of the multiplexing end 141 and the to-be-detected piece 300. After determining the connection state between the multiplexing end 141 and the to-be-tested piece 300, the Microblaze soft core 121 controls the open-short circuit test module 130 to modify the working mode of the multiplexing end 141 into the input/output mode through the AXI4-Lite interface 122 and the open-short circuit control IP.
If the connection state between the multiplexing end 141 and the to-be-tested device 300 is a normal state, the Microblaze soft core 121 obtains a second detection instruction from the external control device 400 through the AXI4-Lite interface 122, the ethernet interrupt IP and control, and the ethernet control 151, the Microblaze soft core 121 obtains a clock signal from the MMCM dynamic clock 171 or the MMCM static clock 172 through the second detection instruction, and the Microblaze soft core 121 generates a scan voltage and a scan frequency according to the clock signal, and controls the voltage control module 180 to perform voltage configuration on the to-be-tested device 300 through the standard IIC MASTER × 10 1441. The Microblaze soft core 121 sends the second detection instruction to the programmable memory detection module 110 through PMBIST data flow control IP to test the to-be-tested device 300, and the detection result output by the programmable memory detection module 110 is stored in the DDR3 read/write control 191 after passing through the data arbitration module 200.
In addition, the Microblaze soft core 321 may further control the current monitoring module 220 to detect a current signal of the to-be-measured device 300 through the AXI4-Lite interface 122 and the standard GPIO x 4 1431, so as to determine whether the to-be-measured device 300 works normally or not and perform power consumption statistics on the to-be-measured device 300 according to the current signal.
Fig. 6 is a flowchart of another method for detecting a synchronous SRAM wafer device according to an embodiment of the present invention. As shown in fig. 6, the method for inspecting a wafer device with synchronous SRAM is performed by the apparatus for inspecting a wafer device with synchronous SRAM according to any embodiment of the present invention.
The detection method of the synchronous SRAM wafer device specifically comprises the following steps:
S110, acquiring a first detection instruction.
S120, determining the connection state of the connection interface and the to-be-tested piece according to the first detection instruction.
S130, acquiring a second detection instruction according to the connection state.
S140, detecting the to-be-detected piece according to the second detection instruction, and obtaining a detection result.
The embodiment of the invention obtains the first detection instruction. And determining the connection state of the connection interface and the to-be-detected piece according to the first detection instruction. And acquiring a second detection instruction according to the connection state. And detecting the to-be-detected piece according to the second detection instruction, and obtaining a detection result. Therefore, the scheme can perform efficient data transmission and command interaction in a command recognition mode so as to realize programming test of any March algorithm on the piece to be tested.
Optionally, the detecting device with the synchronous SRAM wafer device further comprises a voltage monitoring module; the connection interface also comprises a voltage signal input end;
The voltage monitoring module is connected with the control module through a voltage signal input end;
Optionally, fig. 7 is a flowchart illustrating a step of determining a connection state of the connection interface and the to-be-tested device according to the first detection instruction according to the embodiment of the present invention. As shown in fig. 7, the steps of determining the connection state of the connection interface and the to-be-tested piece according to the first detection instruction are described:
S210, acquiring a voltage signal of the to-be-detected piece according to the first detection instruction.
S220, determining the connection state of the connection interface and the to-be-tested piece according to the voltage signal.
Optionally, the detecting device with the synchronous SRAM wafer device further comprises a clock module and a voltage control module; the connection interface also comprises a voltage signal output end;
the clock module is connected with the control module, and the voltage control module is connected with the control module through a voltage signal output end;
Optionally, fig. 8 is a flowchart illustrating a step of detecting the workpiece according to the second detection instruction and obtaining the detection result according to the embodiment of the present invention. As shown in fig. 8, the steps of detecting the workpiece according to the second detection instruction and obtaining the detection result will be described:
s310, acquiring a clock signal according to the second detection instruction.
S320, configuring the scanning voltage and the scanning frequency according to the clock signal.
S330, adjusting the voltage signal of the to-be-tested piece according to the scanning voltage.
S340, detecting the to-be-detected piece according to the second detection instruction and the scanning frequency to obtain a detection result.
The embodiment of the invention also provides a detection system with the synchronous SRAM wafer device, which comprises external control equipment, a piece to be detected and the detection device with the synchronous SRAM wafer device provided by any embodiment of the invention, so that the detection device with the synchronous SRAM wafer device provided by the embodiment of the invention has the beneficial effects and is not repeated.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.
The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.
Claims (11)
1. The detection device with the synchronous SRAM wafer device is characterized by comprising a programmable memory detection module, a control module, an open-short circuit test module, a connection interface and a communication module;
The programmable memory detection module and the communication module are both connected with the control module, the open-short circuit test module is connected with the control module through the connection interface, and the control module and the programmable memory detection module are both connected with a piece to be tested through the connection interface;
The control module is used for acquiring a first detection instruction through the communication module and determining the connection state of the connection interface and the piece to be detected according to the first detection instruction; the control module is further used for obtaining a second detection instruction through the communication module according to the connection state, and controlling the programmable memory detection module to detect the to-be-detected piece according to the second detection instruction to obtain a detection result.
2. The inspection apparatus with synchronous SRAM wafer device of claim 1, wherein said connection interface comprises a multiplexing end and an open-short test end;
The open-short circuit test module is connected with the control module through the open-short circuit test end, and the control module and the programmable memory detection module are connected with the piece to be tested through the multiplexing end.
3. The inspection apparatus with synchronous SRAM wafer device of claim 1, further comprising a voltage monitor module; the connection interface also comprises a voltage signal input end;
The voltage monitoring module is connected with the control module through the voltage signal input end, and the control module is used for controlling the voltage monitoring module to acquire a voltage signal of the piece to be detected according to the first detection instruction, and determining the connection state of the connection interface and the piece to be detected according to the voltage signal.
4. The inspection apparatus with synchronous SRAM wafer device of claim 1, further comprising a clock module and a voltage control module; the connection interface also comprises a voltage signal output end;
the clock module is connected with the control module, and the voltage control module is connected with the control module through the voltage signal output end;
The clock module is used for generating a clock signal, and the control module is used for acquiring the clock signal according to the second detection instruction and configuring a scanning voltage and a scanning frequency according to the clock signal; the voltage control module is used for adjusting the voltage signal of the to-be-detected piece according to the scanning voltage; the control module is used for controlling the programmable memory detection module to detect the piece to be detected according to the second detection instruction and the scanning frequency to obtain a detection result.
5. The inspection apparatus with synchronous SRAM wafer device according to claim 2, wherein the programmable memory inspection module comprises a memory unit, a memory inspection unit, an address generation unit, a write data generation unit, an expected data generation unit, and a data comparison unit;
The storage unit is connected with the memory detection unit, the address generation unit, the write data generation unit and the expected data generation unit are all connected with the memory detection unit, the expected data generation unit is connected with the data comparison unit, and the address generation unit, the write data generation unit and the data comparison unit are all connected with the to-be-detected piece through the multiplexing end.
6. The inspection apparatus with synchronous SRAM wafer device of claim 1, further comprising a memory module;
the programmable memory detection module is connected with the storage module, and the storage module is connected with the communication module; the storage module is used for storing the detection result and sending the detection result to external control equipment through the communication module.
7. The inspection apparatus with synchronous SRAM wafer device of claim 6, further comprising a data arbitration module;
The data arbitration module is connected with the control module, the data arbitration module is connected with the programmable memory detection module, and the data arbitration module is connected with the storage module.
8. A method of inspecting a wafer device having a synchronous SRAM, performed by the inspection apparatus having a synchronous SRAM wafer device according to any one of claims 1 to 7, comprising:
acquiring a first detection instruction;
Determining the connection state of the connection interface and the to-be-detected piece according to the first detection instruction;
Acquiring a second detection instruction according to the connection state;
and detecting the to-be-detected piece according to the second detection instruction, and obtaining a detection result.
9. The method of claim 8, wherein the device further comprises a voltage monitor module; the connection interface comprises a voltage signal input end;
The voltage monitoring module is connected with the control module through the voltage signal input end;
The determining, according to the first detection instruction, a connection state of the connection interface and the to-be-detected member includes:
Acquiring a voltage signal of the to-be-detected piece according to the first detection instruction;
and determining the connection state of the connection interface and the to-be-detected piece according to the voltage signal.
10. The method of claim 8, wherein the device further comprises a clock module and a voltage control module; the connection interface also comprises a voltage signal output end;
the clock module is connected with the control module, and the voltage control module is connected with the control module through the voltage signal output end;
the detecting the piece to be detected according to the second detection instruction and obtaining a detection result includes:
Acquiring a clock signal according to the second detection instruction;
Configuring a scanning voltage and a scanning frequency according to the clock signal;
adjusting a voltage signal of the to-be-detected piece according to the scanning voltage;
and detecting the to-be-detected piece according to the second detection instruction and the scanning frequency to obtain a detection result.
11. A test system with synchronous SRAM wafer devices, comprising an external control apparatus, a part to be tested, and a test device with synchronous SRAM wafer devices according to any one of claims 1-7.
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| CN202410323747.4A CN117935902A (en) | 2024-03-21 | 2024-03-21 | Detection device, method and system with synchronous SRAM wafer device |
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| CN202410323747.4A CN117935902A (en) | 2024-03-21 | 2024-03-21 | Detection device, method and system with synchronous SRAM wafer device |
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