CN117935898A - Reliability testing device and reliability testing method - Google Patents
Reliability testing device and reliability testing method Download PDFInfo
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- CN117935898A CN117935898A CN202211259936.7A CN202211259936A CN117935898A CN 117935898 A CN117935898 A CN 117935898A CN 202211259936 A CN202211259936 A CN 202211259936A CN 117935898 A CN117935898 A CN 117935898A
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Abstract
The disclosure relates to a reliability testing device and a reliability testing method, and relates to the technical field of integrated circuits. The reliability test device includes: test chip and test board; at least part of the chip metal pads of the test chip and the corresponding test board metal pads of the test board are connected into a serial link, and the serial link is used for monitoring the connection reliability of at least part of the chip metal pads and the test board metal pads. The present disclosure provides a method for board-level reliability evaluation of a chip.
Description
Technical Field
The disclosure relates to the technical field of integrated circuits, and in particular relates to a reliability testing device and a reliability testing method.
Background
LPDDR (Low Power Double Data Rate Synchronous Dynamic Random Access Memory, double data rate synchronous dynamic random access memory) is a synchronous DRAM memory that has lower power consumption and smaller size than contemporary DDR memories.
Generally, chips such as LPDDR are mainly applied in a non-standard board-level application scenario, and therefore, it is required to perform board-level reliability evaluation on such chips in the non-standard board-level application scenario.
It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The disclosure aims to provide a reliability testing device and a reliability testing method, so as to provide a method for evaluating the board-level reliability of a chip.
Other features and advantages of the present disclosure will be apparent from the following detailed description, or may be learned in part by the practice of the invention.
According to a first aspect of the present disclosure, there is provided a reliability testing apparatus, the apparatus comprising: test chip and test board; at least part of the chip metal pads of the test chip and the corresponding test board metal pads of the test board are connected into a serial link, and the serial link is used for monitoring the connection reliability of the at least part of the chip metal pads and the test board metal pads.
In an exemplary embodiment of the present disclosure, the apparatus further includes: the chip end connecting wire is arranged on the test chip, and the test board end connecting wire is arranged on the test board; the chip end connecting wire is connected with one chip metal pad and the adjacent first side chip metal pad, the test board end connecting wire is connected with the test board metal pad opposite to the chip metal pad and the adjacent second side test board metal pad, and the first side chip metal pad and the second side test board metal pad are not corresponding.
In an exemplary embodiment of the present disclosure, the apparatus further includes: at least two test ports; the test ports are arranged at two ends of the serial link or any position inside the serial link, and are used for monitoring impedance of the serial link.
In one exemplary embodiment of the present disclosure, the chip metal pads and the corresponding test board metal pads are connected by intermetallic bonding.
In one exemplary embodiment of the present disclosure, the chip metal pads and the corresponding test board metal pads are connected by a solder.
In one exemplary embodiment of the present disclosure, a plurality of the weldments are divided into different weldment groups, the weldments within each of the weldment groups being connected in series; the weldments within adjacent weldment groups are connected in series.
In one exemplary embodiment of the present disclosure, the test chip is consistent with the package characteristics of a general chip.
In one exemplary embodiment of the present disclosure, the encapsulation characteristics include at least an encapsulation material and an encapsulation mode.
In an exemplary embodiment of the present disclosure, the test chip removes the Layout line corresponding to the normal chip.
In one exemplary embodiment of the present disclosure, the test plate includes: a silicon board or a PCB.
In one exemplary embodiment of the present disclosure, the PCB employs an FR4 substrate, an OSP surface treatment process, and employs non-solder-resist pads.
In an exemplary embodiment of the present disclosure, the solder member is a solder ball.
In an exemplary embodiment of the present disclosure, a plurality of the test chips are disposed on one of the test boards.
According to a second aspect of the present disclosure, there is provided a reliability test method, the method comprising: connecting at least part of chip metal pads of the test chip and test board metal pads of the corresponding test board into a serial link; and monitoring the connection reliability of the at least part of chip metal pads and the test board metal pads through the serial links.
In an exemplary embodiment of the present disclosure, the monitoring connection reliability of the at least part of the chip metal pads and the test board metal pads through the serial link includes: the connection reliability is monitored by monitoring the impedance of the series link.
The technical scheme provided by the disclosure can comprise the following beneficial effects:
According to the reliability testing device provided by the exemplary embodiment of the disclosure, at least part of chip metal pads of a test chip and the corresponding test board metal pads of the test board are connected into a serial link, the connection reliability of the at least part of chip metal pads and the test board metal pads can be monitored through the serial link, and the purpose of monitoring the connection reliability of the chip metal pads and the test board metal pads in real time can be achieved due to the fact that the serial link is measurable in real time, so that the board-level connection reliability of the chip is monitored in real time.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort. In the drawings:
FIG. 1 schematically illustrates a schematic distribution diagram of a signal plane of an LPDDR chip in an exemplary embodiment in accordance with the disclosure;
FIG. 2 schematically illustrates a structural schematic of a reliability testing apparatus according to an exemplary embodiment of the present disclosure;
FIG. 3 schematically illustrates a cross-sectional schematic view of a reliability testing apparatus according to an exemplary embodiment of the present disclosure;
FIG. 4 schematically illustrates a schematic structure of a circuit board with a plurality of test chips disposed thereon according to an exemplary embodiment of the present disclosure;
fig. 5 schematically illustrates a flow chart of a reliability test method according to an exemplary embodiment of the present disclosure.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and thus a repetitive description thereof will be omitted.
Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the disclosed aspects may be practiced without one or more of the specific details, or with other methods, components, devices, steps, etc. In other instances, well-known structures, methods, devices, implementations, materials, or operations are not shown or described in detail to avoid obscuring aspects of the disclosure.
The block diagrams depicted in the figures are merely functional entities and do not necessarily correspond to physically separate entities. That is, these functional entities may be implemented in software, or in one or more software-hardened modules, or in different networks and/or processor devices and/or microcontroller devices.
With the advancement of integrated circuit manufacturing technology, integrated circuits with relatively complex circuit structures, high integration, and various functions have been manufactured. However, these highly integrated, multifunctional integrated circuits are connected to external circuits only through a limited number of pins, which makes it difficult to determine whether the integrated circuit is good or bad.
Any integrated circuit is a monolithic module designed to perform a function of a certain electrical characteristic, and testing of the integrated circuit is performed by various methods to detect undesirable samples caused by physical defects during the manufacturing process.
For chips, from design to use, the chip is typically subjected to multiple steps such as tape-out, packaging, testing, etc. The test is an essential link in the chip manufacturing process, and only the tested chip can ensure certain reliability and can be put into the market for use.
Generally, testing of chips is largely divided into three main categories: functional testing, performance testing, and reliability testing. The functional test mainly tests parameters, indexes, functions and the like of the chip. The performance test is mainly used for screening defects of chips in the production and manufacturing processes. The reliability test is to evaluate the reliability, service life and the like of the chip in the use process after the chip passes the function and performance test.
Among the tests of the chip, a board level test is included, wherein the board level test belongs to a functional test, mainly a 'simulated' chip working environment is built by using a PCB (Printed Circuit Board ) board and the chip, interfaces of the chip are led out, and the function of the chip is detected, or whether the chip can work normally is checked under various severe environments.
In the existing chip packaging structure, a Ball Grid Array (BGA) is generally used to fix components such as a circuit board and a chip. However, with the development trend of miniaturization of the chip packaging structure component, the diameters of the solder balls are smaller and smaller, and in the use process of the chip packaging structure component, the solder balls are extremely easy to repeatedly stretch or compress to generate fatigue failure due to larger difference of thermal expansion coefficients between the packaging substrate and the circuit board, so that the welding points are broken, and the reliability of the chip packaging structure component is affected.
In addition, in practical applications, for example, in the signal Plane of the LPDDR chip shown in fig. 1, for example, the signal of VDD1, there are many solder balls VDD1, and the solder balls of VDD1 may form the same signal Plane. When there is a bad soldering of a single or a few solder balls on the same signal Plane, there may be no effect on the function of the chip, but the performance and reliability of the chip may be affected. And along with the lengthening of the service time of the chip, the function of the chip is inevitably influenced, but if the function of the chip is detected only when the function of the chip is problematic, the monitoring and the maintenance of the chip are inevitably unfavorable.
In addition, for the signal chip metal pads of the chip, for example, the power supply chip metal pad, the ground chip metal pad, and the like, there are often more than one, and if there is an abnormality in the soldering of one of the power supply chip metal pad or the ground chip metal pad, it may be difficult to detect using the method of the detection function.
Therefore, the test method and the test device for monitoring the board-level welding reliability of the chip in real time are provided, and the test method and the test device have a critical effect on the use reliability of the chip.
Based on this, the exemplary embodiments of the present disclosure provide a reliability test device that can be applied not only to LPDDR chips, but also to any DDR (Double Data Rate Synchronous Dynamic Random Access Memory, double rate synchronous dynamic random access memory) chips that require board level solder reliability monitoring.
Referring to fig. 2, a schematic structural diagram of a reliability testing apparatus according to an exemplary embodiment of the present disclosure is shown. As shown in fig. 2, the reliability testing apparatus includes a test chip 210 and a test board 220, wherein at least part of the chip metal pads of the test chip 210 and the corresponding test board metal pads of the test board 220 are connected to form a serial link, specifically, after at least part of the chip metal pads are connected to the corresponding test board metal pads, a plurality of pairs of connected chip metal pads and the corresponding test board metal pads form a serial link. The serial link can be used to monitor the connection reliability of at least part of the chip metal pads and the corresponding test board metal pads.
According to the reliability testing device provided by the exemplary embodiment of the disclosure, at least part of chip metal pads of a test chip and the corresponding test board metal pads of the test board are connected into a serial link, the connection reliability of the at least part of chip metal pads and the test board metal pads can be monitored through the serial link, and the purpose of monitoring the connection reliability of the chip metal pads and the test board metal pads in real time can be achieved due to the fact that the serial link is measurable in real time, so that the board-level connection reliability of the chip is monitored in real time.
It should be noted that, in the actual testing process, all the die metal pads of the test die 210 and the corresponding test board metal pads on the test board 220 are often connected in a serial link to monitor the connection reliability of all the die metal pads and the test board metal pads, so the following description will be mainly based on the serial link formed by connecting all the die metal pads and the test board metal pads of the test board 220.
In practical applications, monitoring the connection reliability of the chip metal pads and the test board metal pads can be achieved by detecting the impedance of the serial link. In particular, the impedance tester may be connected to the serial link to monitor the impedance change of the serial link by the impedance tester. When the impedance change is large, for example, the impedance is infinite, it is indicated that the series link is open, and at this time, it is indicated that there is a problem with the connection of at least one chip metal pad to the test board metal pad.
It should be noted that, in practical application, the chip metal pad and the test board metal pad may be structural members for performing electrical connection, and in addition, the chip metal pad may also be a pin of the test chip 210, and the specific structure and materials of the chip metal pad and the test board metal pad are not particularly limited in the exemplary embodiment of the present disclosure.
In the reliability test apparatus provided in the exemplary embodiment of the present disclosure, the connection reliability of the test chip 210 and the test board 220 may be inter-metal bonding reliability between Die (integrated circuit Die) and Die, soldering reliability between Die and substrate, or soldering reliability between chip particles and PCB.
Based on this, in the exemplary embodiment of the present disclosure, the connection between the chip metal pads of the test chip 210 and the test board metal pads of the corresponding test board 220 may be a connection through intermetallic bonding or a connection through a solder. That is, the connection relationship between the chip metal pad and the test board metal pad is an intermetallic bonding connection or a soldering connection.
Specifically, when the chip metal pads of the test chip 210 are soldered to the corresponding test board metal pads of the test board 220, the following two methods are generally adopted: firstly, each chip metal pad is directly soldered to the test board metal pad of the test board 220, that is, the solder joint is heated to a molten state by fusion welding, and the soldering is completed without pressurization. Under the heating condition, the atomic kinetic energy of the metal is enhanced, the inter-diffusion among atoms is promoted, and when the welded metal is heated to a molten state to form a liquid molten pool, the atoms can be fully diffused and closely contacted, so that a firm welding piece is formed after cooling and solidification. Secondly, after the solder paste is drawn on the metal pads of the chip, the element and the test board 220 are put into a high-temperature oven to be baked so as to melt the solder paste, and then the soldering is realized after the solder paste is solidified.
The first method has the defects that when the number of the chip metal pads is large and the density of the chip metal pads is high, the difficulty of welding one by one is high, and the operation of personnel is difficult, so that the welding effect is affected. The second method has the defect that the baking temperature in the oven is higher, usually up to three and four hundred ℃, so that the abnormal part of the element or the circuit board which is not resistant to the high temperature occurs to influence the product quality, and the product cost is greatly increased if the part which is not resistant to the high temperature is replaced by the high temperature resistant material.
Besides the two welding connection modes, the automatic welding mode of the laser solder paste can be adopted, and the method specifically comprises the following steps: step one: the die pad to be tested is placed on the test board 220 at the position to be soldered, the position is fixed by using a special soldering fixture, and then the tray with the material is placed on the right jig of the machine. Step two: and servo-moving the test board 220 and the chip metal pad to be tested to a visual starting point position, capturing the welding position by self definition by a height measurement system and a visual positioning system to take a picture, entering a solder paste station at the next step after all products on the material tray are photographed, and drawing solder paste strips on the chip metal pad along the direction perpendicular to the arrangement direction of the chip metal pad of the element. Step three: the tray on which the solder paste strips are drawn is moved to a laser welding station in a servo manner, and the solder paste is melted by high-energy continuous laser, so that the element chip metal pads are welded on the test board 220 until all the products on the tray are welded, and the tray is moved to a blanking station for blanking. In addition, another welding connection mode is called a laser tin wire automatic welding mode, and is not repeated here.
In practical applications, the solder member may be a solder ball, and in particular, the solder ball may be a solder ball, regardless of the above-mentioned soldering method. Among them, tin ball is an indispensable important material in a new type of encapsulation, it is a new type of connection that meets the electrical interconnection and mechanical interconnection requirement. With the rapid development of BGA and CSP (CHIP SCALE PACKAGE, chip size package) in recent years, solder balls replace the conventional pin package and lead frame package forms, thereby playing an important role in electrical interconnection and mechanical support in terms of solder balls. The packaging devices such as BGA and CSP connected by solder balls are used in a large number of notebook computers, mobile phones, PDAs (Personal DIGITAL ASSISTANT, palm computers), DSCs (DIGITAL STILL CAMERA, digital cameras), LCDs (Liquid CRYSTAL DISPLAY, liquid crystal displays) and 3C products.
Common solder ball (Sn content is from 2[% ] -100[% ], melting point temperature range is 182-316 ℃); ag-containing solder balls (common products contain 1.5[% ], 2[% ] or 3[% ] of Ag, and the melting point temperature is 178-189 ℃); low temperature solder ball (containing bismuth or indium, melting point temperature is 95-135 ℃); high temperature solder ball (melting point 186-309 ℃); fatigue-resistant high-purity solder balls (the melting points of common products are 178 ℃ and 183 ℃); lead-free solder balls (lead content in the composition is less than 0.1[% ]).
The solder balls are applied in two types, one type is that a Flip Chip (FC) with first-level interconnection is directly installed on the occasion, the solder balls are directly jointed on the bare Chip after the wafer is cut into chips, and the function of electrically interconnecting the chips and the packaging substrate is achieved in FC-BGA packaging; another type of application is secondary interconnect bonding, which implants tiny solder balls, one by one, onto a package substrate by special equipment, and bonds the solder balls to lands on the substrate by heating. In IC packages (BGA, CSP, etc.), the chip is soldered to the motherboard by heating in a reflow oven.
In the exemplary embodiment of the present disclosure, the chip metal pads of the test chip 210 of the test chip and the test board metal pads of the corresponding test board 220 are mainly described as examples by connecting the solder balls. As shown in the schematic cross-sectional view of the reliability testing apparatus provided by the exemplary embodiment of the present disclosure shown in fig. 3, the circular structure shown in fig. 3 represents a solder ball, i.e., a solder 330.
It should be noted that, the connection manner between the metal pads of the test chip 210 and the metal pads of the test board 220 is simulated by the connection manner between the solder balls and the circuit board, and the connection reliability between the metal pads of the test chip 210 and the metal pads of the test board 220, that is, the connection reliability between the common chip and the circuit board, is monitored by monitoring the connection reliability between the metal pads of the test chip 210 and the metal pads of the test board 220. The purpose of monitoring the connection reliability of each chip metal pad and the test board metal pad, that is, the purpose of monitoring the connection reliability of the solder balls, can be achieved by testing the impedance of the serial link formed by the chip metal pad of the chip 210 and the test board metal pad of the test board 220.
Because in the actual solder ball soldering process, there may be problems in that soldering voids, temperature cycles, mechanical vibrations, electromigration, etc. have an influence on board-level reliability. Therefore, the monitoring of the connection reliability of the solder balls has important significance for the board-level connection reliability of the chip.
In the exemplary embodiment of the present disclosure, in addition to ensuring that the above-mentioned manner of connecting the chip metal pads of the test chip 210 with the test board metal pads of the test board 220 through solder balls is the same as the manner of connecting the normal chip with the circuit board, it is also necessary to ensure that the package characteristics of the test chip 210 and the normal chip are consistent, so as to ensure that the manner of connecting the test chip 210 and the test board 220 can completely represent the manner of connecting the normal chip with the circuit board.
In practical applications, the chip package is to put the produced integrated circuit Die (Die) on a substrate with a bearing function, then lead out the pins, and then fix and package the pins into a whole. The chip can be protected by the chip protection device, which is equivalent to a shell of the chip, and can not only fix and seal the chip, but also enhance the electrothermal performance of the chip.
The chip package plays roles in mounting, fixing, sealing, protecting the chip, enhancing electrothermal performance and the like. Meanwhile, the pins are connected to pins of the packaging shell through wires by contacts on the chip, and the pins are connected with other devices through wires on the printed circuit board, so that the connection between the internal chip and an external circuit is realized.
Through the encapsulation of chip, can keep apart the chip with external world to can prevent that the impurity in the air from causing the electrical property to drop to the corruption of chip circuit. And the packaged chip is more convenient to install and transport.
In practical applications, common packaging materials include: plastic, ceramic, glass, metal, etc., are now basically encapsulated with plastic. The main packaging modes comprise: DIP package (Dual in-LINE PACKAGE ), PQFP package (Plastic Quad FLAT PACKAGE, plastic Quad Flat package), QFN package (Quad Flat No-LEADS PACKAGE, quad Flat No-lead package), BGA package (Ball GRID ARRAY PACKAGE ), PGA package (PIN GRID ARRAY PACKAGE, pin grid array package), and the like.
The DIP package is a package mode of an integrated circuit, the shape of the integrated circuit is rectangular, and two parallel rows of metal pins are arranged on two sides of the integrated circuit, which is called pin header. The DIP packaged components may be soldered into plated through holes in a printed circuit board or plugged into DIP sockets. The PQFP package is a chip package form, pins are arranged around the PQFP package chip, the total number of the pins is generally more than 100, the distance between the pins is small, the pins are also very thin, and a large-scale or very large-scale integrated circuit adopts the package form. The chip packaged by PQFP must be soldered with the motherboard by SMT (Surface Mount Technology ), the chip mounted by SMT does not need to be punched on the motherboard, and the motherboard surface is generally provided with soldered points of corresponding pins. And (3) aligning each pin of the chip with a corresponding welding spot, so that the welding with the main board can be realized. The PQFP package is suitable for mounting wiring on a PCB (Printed Circuit Board, a printed circuit board) by using an SMT surface mounting technology, is suitable for high-frequency use, and has the advantages of convenient operation, high reliability, mature process, low price and the like.
The I/O terminals of the BGA package are distributed under the package in the form of circular or columnar solder dots in an array, and the BGA technology has the advantages that the number of I/O pins is increased, but the pin pitch is not reduced but increased, thereby improving the assembly yield. The PGA packaged chip has multiple square pins, each square pin is arranged at a certain distance along the periphery of the chip, and can be enclosed into 2-5 circles according to the number of pins, and the chip is inserted into a special PGA socket during installation.
In practical application, the packaging characteristics include packaging materials and packaging modes, and also include packaging design methods, packaging processes and the like, that is, the packaging materials, the packaging modes, the packaging design methods, the packaging processes and the like of the test chip and the common chip are required to be consistent, so that the packaging characteristics of the test chip and the common chip are ensured to be consistent.
In the exemplary embodiment of the disclosure, the test chip can remove the Layout circuit corresponding to the common chip on the basis of ensuring that the package characteristics of the test chip are consistent with those of the common chip. The Layout refers to wiring on a circuit board, and is also a Layout design, and various factors such as external connection Layout, optimized Layout of internal electronic elements, optimized Layout of metal wires and through holes, electromagnetic protection, heat dissipation and the like need to be considered. The excellent layout design can save the production cost and achieve good circuit performance and heat dissipation performance.
In practical applications, the wiring may mainly include: right angle routing, differential routing, serpentine routing, etc. The right-angle routing generally changes the line width of the transmission line, resulting in discontinuous impedance, which is generally required to be avoided as much as possible in PCB routing. The differential wires are the pair of wires carrying differential signals, the differential signals are signals with equal value and opposite phase sent by the driving end, and the receiving end judges whether the logic state is 0 or 1 by comparing the difference value of the two voltages. The differential wiring has strong anti-interference capability, can effectively inhibit EMI (Electromagnetic Interference ) and has accurate time sequence positioning. The serpentine is a wiring mode frequently used in the Layout, and the main purpose of the serpentine is to adjust delay and meet the design requirement of a system time sequence.
In the exemplary embodiment of the present disclosure, for the test chip 210, the Layout line on the circuit board plays no substantial role in the connection reliability between the chip metal pad of the test chip 210 and the test board 220, and therefore, in the connection reliability test, the Layout line on the circuit board corresponding to the normal chip may be deleted, so as to avoid the influence on the serial link formed by the chip metal pad of the test chip 210 and the test board 220.
In practical application, in order to form the above-mentioned serial link, as shown in fig. 3, the reliability testing apparatus provided in the exemplary embodiment of the present disclosure further includes: chip-side connection lines 340 and test board-side connection lines 350, wherein chip-side connection lines 340 are disposed on test chip 210 and test board-side connection lines 350 are disposed on test board 220. The chip-side connection wire 340 connects a chip metal pad 360 and its adjacent first side chip metal pad 370, the test board-side connection wire 350 connects a test board metal pad 380 opposite to the chip metal pad 360 and its adjacent second side test board metal pad 390, and the first side chip metal pad 370 does not correspond to the second side test board metal pad 390. In this way, the chip metal pads 360 on the test chip 210 and the corresponding test board metal pads 380 on the test board 220 can be connected in a serial link.
Referring to fig. 3, the shown solder 330 is numbered from No.1 to No. 4, and when the first chip-side connecting wire 340 connects the chip metal pads corresponding to the No.1 solder and the No. 2 solder, the second chip-side connecting wire 340 connects the chip metal pads corresponding to the No. 3 solder and the No. 4 solder; at this time, the test board terminal connection wire 350 is connected to the test board metal pad corresponding to the number 2 solder and the number 3 solder. Finally, the test board terminal connection lines 350 and the chip terminal connection lines 340 for connecting the solder 330 are staggered, so that all the solder 330 form a series link, and since the solder 330 is connected with the chip metal pads of the test chip 210, all the chip metal pads of the test chip 210 form a series link, the series link can be used for connection reliability test of the chip metal pads and the test board 220, that is, connection reliability test of the solder 330 and the test chip 210 and the test board 220.
In practical application, since the chip-side connection lines 340 are connected to adjacent chip metal pads and the test board-side connection lines 350 are connected to adjacent test board metal pads, the chip-side connection lines 340 and the test board-side connection lines 350 can be arranged in a straight line, and the length of wiring can be reduced.
In practical application, the chip-end connecting wire 340 and the test board-end connecting wire 350 may be gold wires or copper wires, where the gold wires have a density greater than that of the copper wires, and copper wires with a smaller density may be arranged thicker, which is beneficial to processing, and at the same time, the conductivity of the chip-end connecting wire 340 and the test board-end connecting wire 350 may be increased, so that the impedance detection in the serial link is beneficial to through a larger current, so that the copper wires are preferentially selected in the exemplary embodiment of the present disclosure, and the effect of reducing the cost may be also achieved.
In practical applications, any connection wires that can perform a connection and conduction function may be used as the chip-side connection wires 340 and the test board-side connection wires 350 in the exemplary embodiment of the present disclosure, and specific materials of the chip-side connection wires 340 and the test board-side connection wires 350 are not particularly limited herein.
In the exemplary embodiment of the disclosure, the reliability testing apparatus for forming a serial link further includes at least two testing ports 230, where the testing ports 230 are mainly used for monitoring the impedance of the serial link, that is, the testing ports 230 may be used for connecting an impedance tester or other devices for monitoring the impedance, or for connecting a device for monitoring parameters such as current, and the exemplary embodiment of the disclosure is not limited thereto.
IN practical applications, at least two test ports 230 need to be disposed at two ends of the serial link, and can be used as an input end IN and an output end OUT of the serial link, where the input end IN and the output end OUT can be used for accessing a power signal, so as to generate a current signal IN the serial link, so as to be finally used for detecting the impedance of the serial link, etc.
In addition, the test port 230 provided by the exemplary embodiment of the present disclosure may also be disposed at any position inside the serial link, for example, any of positions T1, T2, T3, T4, T5, and T6 as shown in fig. 2. By providing the test port 230 at any position inside the serial link, impedance, current, or the like on a part of the serial link can be tested, so that connection reliability of a part of the chip metal pads of the test chip 210 and the test board 220 can be monitored.
In the exemplary embodiments of the present disclosure, by providing the test port 230 inside the serial link, it can be further used to locate chip metal pads where connection problems may occur. For example, if an impedance tester is connected across the series link, the impedance tester shows that the impedance of the series link is infinite and there may be an open circuit in the series link, then this indicates that there is a problem with the connection of the die metal pads to the test board 220 in at least one of the series links. At this time, an impedance tester may be connected to the test port 230 inside the serial link, for testing the impedance of different sections in the serial link to determine the minimum section where the open circuit occurs, so that the chip metal pad where the connection problem actually occurs may be further determined in the minimum section for subsequent processing, such as repair or replacement, and the exemplary embodiment of the present disclosure is not limited in particular to the specific content of the subsequent processing.
It should be noted that, in addition to monitoring the connection reliability of the chip of the test chip and the circuit board by monitoring the impedance of the serial link, the connection reliability of the chip of the test chip and the circuit board may also be monitored by monitoring the current, the voltage, etc. of the serial link, which is not particularly limited in the exemplary embodiments of the present disclosure.
In the exemplary embodiment of the present disclosure, as shown in fig. 2, the weldments 330 for connecting the test chip 210 and the test board 220 may be further divided into different weldment groups, the weldments 330 within each of the weldment groups are connected in series, and each of the weldment groups may individually perform the detection of the impedance, the current, etc. For example, the test ports 230 described above may be provided at both ends of the weldment set.
As can be seen in connection with fig. 2, the weldment 330 shown in fig. 2 is divided into four blocks, which corresponds to four weldment groups. The series link formed by each set of weldments is provided with test ports 230 at both ends that can be used to monitor the reliability of the connection of the weldments within the weldment set.
In an exemplary embodiment of the present disclosure, the weldments 330 within adjacent weldment groups may be connected in series, forming one large series link, i.e., a series link that includes all die metal pads of the test die 210, to facilitate initial monitoring of connection reliability of all die metal pads. The exemplary embodiments of the present disclosure are not particularly limited as to the specific number of connection chip metal pads of the serial link, the arrangement position of the test port 230, and the like.
In practical applications, the test chip 210 may be an LPDDR chip, or any DDR chip that needs to perform board-level solder reliability monitoring, or a DRAM (Dynamic Random Access Memory ) chip, etc.
In an exemplary embodiment of the present disclosure, the test board 220 may be a silicon board or a PCB, wherein the PCB is an important electronic component, is a support for electronic components, and is a carrier for electrically interconnecting the electronic components. The PCB may employ an FR4 substrate, an OSP surface treatment process, and employ non-solder-resist pads. The FR4 substrate is a glass cloth substrate, and is a plate-shaped pressed product which is formed by immersing special electronic cloth in epoxy novolac epoxy resin and performing high-temperature, high-pressure and hot-pressing, namely an epoxy glass fiber cloth substrate (commonly known as an epoxy board, a glass fiber board, a fiber board and FR 4). The epoxy glass fiber cloth substrate is a substrate which uses epoxy resin as an adhesive and uses electronic grade glass fiber cloth as a reinforcing material, and the epoxy glass fiber cloth substrate copper-clad plate has high strength, good heat resistance and good dielectric property, through holes of the substrate can be metallized to realize circuit conduction between double-sided multilayer printed layers and layers, and the epoxy glass fiber cloth substrate copper-clad plate is the most widely used and largest-used substrate copper-clad plate in all qualities.
OSP is a process for surface treatment of copper foil of printed circuit board, which meets RoHS instruction requirement. OSP is a abbreviation of Organic Solderability Preservatives, which is translated into an organic solder mask, also called copper-protecting agent, also called Preflux in English. Briefly, OSP is a chemical process for growing an organic film on a clean bare copper surface. The film has oxidation resistance, heat shock resistance and moisture resistance, and is used for protecting the copper surface from further rusting (oxidation or vulcanization and the like) in a normal environment; however, in the subsequent soldering temperatures, the protective film must be readily removed by the flux, in such a way that the exposed clean copper surface is immediately bonded to the molten solder in a very short period of time to form a strong solder joint.
In practical applications, a plurality of test chips 210 may be further disposed on one test board 220, for monitoring the soldering reliability of a plurality of identical test chips 210, and for monitoring the soldering reliability of a plurality of different test chips 210. Four test chips 210 are provided on the test board 220 as shown in fig. 4, each test chip 210 forming a separate serial link with the test board 220.
In the exemplary embodiment of the disclosure, by connecting at least part of the chip metal pads of the test chip and the corresponding test board metal pads of the test board into a serial link, the impedance, the current, and the like of the serial link can be monitored by arranging the test port on the serial link, so that the connection reliability between the test chip and the circuit board, that is, the welding reliability of the welding piece for connecting the chip and the circuit board, is monitored.
In addition, the exemplary embodiment of the disclosure also provides a reliability test method. The reliability test method is used for the reliability test device. Referring to fig. 5, the reliability test method may specifically include the steps of:
Step S510, connecting at least part of chip metal pads of the test chip and corresponding test board metal pads of the test board into a serial link;
step S520, monitoring connection reliability of at least part of the chip metal pads and the test board metal pads through the serial link.
In an exemplary embodiment of the present disclosure, the monitoring connection reliability of at least part of the chip metal pads and the test board metal pads through the serial link includes: the reliability of the connection is monitored by monitoring the impedance of the link.
The specific details of each step in the above-mentioned reliability testing method are already described in detail in the corresponding reliability testing apparatus, and thus are not described here again.
In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using a software program, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in accordance with the embodiments of the present disclosure are produced in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device including one or more servers, data centers, etc. that can be integrated with the medium. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid State Disk (SSD)), etc. In embodiments of the present disclosure, a computer may include the apparatus described previously.
Although the disclosure has been described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed disclosure, from a review of the figures, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
Although the present disclosure has been described in connection with specific features and embodiments thereof, it will be apparent that various modifications and combinations thereof can be made without departing from the spirit and scope of the disclosure. Accordingly, the specification and drawings are merely exemplary illustrations of the present disclosure as defined in the appended claims and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the present disclosure without departing from the spirit or scope of the disclosure. Thus, the present disclosure is intended to include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (15)
1. A reliability testing apparatus, the apparatus comprising: test chip and test board; wherein,
At least part of the chip metal pads of the test chip and the corresponding test board metal pads of the test board are connected into a serial link, and the serial link is used for monitoring the connection reliability of the at least part of the chip metal pads and the test board metal pads.
2. The apparatus of claim 1, wherein the apparatus further comprises: the chip end connecting wire is arranged on the test chip, and the test board end connecting wire is arranged on the test board; wherein,
The chip end connecting wire is connected with one chip metal pad and the adjacent first side chip metal pad, the test board end connecting wire is connected with the test board metal pad opposite to the chip metal pad and the adjacent second side test board metal pad, and the first side chip metal pad is not corresponding to the second side test board metal pad.
3. The apparatus of claim 1, wherein the apparatus further comprises: at least two test ports; wherein,
The test ports are arranged at two ends of the serial link or any position inside the serial link, and are used for monitoring the impedance of the serial link.
4. The device of claim 1 or 2, wherein the chip metal pads and their corresponding test board metal pads are connected by intermetallic bonding.
5. The device of claim 1 or 2, wherein the die metal pads and their corresponding test board metal pads are connected by solder.
6. The apparatus of claim 5 wherein a plurality of said weldments are divided into different weldment groups, said weldments within each of said weldment groups being connected in series;
the weldments within adjacent weldment groups are connected in series.
7. The apparatus of claim 1, wherein the test chip is consistent with package characteristics of a normal chip.
8. The apparatus of claim 7, wherein the encapsulation characteristics include at least an encapsulation material and an encapsulation means.
9. The apparatus of claim 7, wherein the test chip removes a Layout line corresponding to the normal chip.
10. The apparatus of claim 1, wherein the test plate comprises: a silicon board or a PCB.
11. The apparatus of claim 10 wherein the PCB is formed using an FR4 substrate, an OSP surface treatment process, and using non-solder-resist pads.
12. The apparatus of claim 5, wherein the solder members are solder balls.
13. The apparatus of claim 1, wherein a plurality of said test chips are disposed on one of said test boards.
14. A method of reliability testing, the method comprising:
connecting at least part of chip metal pads of the test chip and test board metal pads of the corresponding test board into a serial link;
and monitoring the connection reliability of the at least part of chip metal pads and the test board metal pads through the serial links.
15. The method of claim 14, wherein monitoring connection reliability of the at least a portion of the die metal pads and the test board metal pads through the serial link comprises:
The connection reliability is monitored by monitoring the impedance of the series link.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211259936.7A CN117935898A (en) | 2022-10-14 | 2022-10-14 | Reliability testing device and reliability testing method |
| PCT/CN2022/130392 WO2024077695A1 (en) | 2022-10-14 | 2022-11-07 | Reliability test apparatus and reliability test method |
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| CN202211259936.7A CN117935898A (en) | 2022-10-14 | 2022-10-14 | Reliability testing device and reliability testing method |
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| CN202211259936.7A Pending CN117935898A (en) | 2022-10-14 | 2022-10-14 | Reliability testing device and reliability testing method |
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| US6788092B2 (en) * | 2002-04-15 | 2004-09-07 | Advanced Semiconductor Engineering, Inc. | Test assembly for integrated circuit package |
| JPWO2010050133A1 (en) * | 2008-10-28 | 2012-03-29 | 株式会社アドバンテスト | Test apparatus, circuit module, and manufacturing method |
| CN105203852B (en) * | 2014-06-10 | 2019-07-02 | 中国科学院微电子研究所 | Test board and testing scheme for integrated passive devices |
| CN204389644U (en) * | 2015-02-11 | 2015-06-10 | 中芯国际集成电路制造(北京)有限公司 | Test board device |
| CN113540039B (en) * | 2021-07-09 | 2022-10-11 | 中国人民解放军国防科技大学 | TSV multi-stress reliability test chip structure and device based on flip chip bonding |
| CN113495189B (en) * | 2021-09-08 | 2022-11-15 | 深圳荣耀智能机器有限公司 | Test method for evaluating reliability of electronic assembly material |
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