CN117933169A

CN117933169A - Chip design file generation method, device, system and related equipment

Info

Publication number: CN117933169A
Application number: CN202311770163.3A
Authority: CN
Inventors: 于立波
Original assignee: Chengdu Haiguang Integrated Circuit Design Co Ltd
Current assignee: Chengdu Haiguang Integrated Circuit Design Co Ltd
Priority date: 2023-12-20
Filing date: 2023-12-20
Publication date: 2024-04-26

Abstract

The embodiment of the invention provides a method, a device, a system and related equipment for generating a chip design file, wherein the method comprises the following steps: acquiring a logic view of a chip design including various logic modules combined according to logic design requirements of the chip design; acquiring a physical view of a chip design including physical modules formed by combining logic modules in the logic view according to physical implementation requirements of the chip design; adjusting the logic view based on the physical view so as to enable the logic level of each logic module in the logic view to be consistent with the physical level of the corresponding logic module in the physical view, wherein the physical level is a physical setting position corresponding to the logic module in the physical realization requirement, and the logic level is a logic setting position corresponding to the logic module in the logic design requirement; and generating a standard design file of the chip design based on the adjusted logic view. The technical scheme provided by the embodiment of the invention can facilitate the generation of the standard design file and reduce the design time consumption of chip design.

Description

Chip design file generation method, device, system and related equipment

Technical Field

The embodiment of the application relates to the technical field of computers, in particular to a method, a device, a system and related equipment for generating a chip design file.

Background

Along with the expansion of the scale of the chip design, the number of the integrated physical modules in the chip design is increased sharply, and when the chip design is performed on a large scale, the error rate and the time consumption for realizing the layout of the physical layer are increased correspondingly according to the standard design file containing the design codes obtained by the function of the chip design. Therefore, in this context, how to provide a technical solution, which facilitates the generation of standard design files, reduces the design time consumption of chip design, and becomes a technical problem to be solved by those skilled in the art.

Disclosure of Invention

In view of this, the embodiments of the present invention provide a method, a system and a related device for generating a chip design file, so as to improve the data security of high-performance computing.

In order to achieve the above purpose, the embodiment of the present invention provides the following technical solutions.

In a first aspect, an embodiment of the present invention provides a method for generating a chip design file, including:

Obtaining a logic view of a chip design, wherein the logic view comprises all logic modules of the chip design, and all logic modules are combined according to logic design requirements of the chip design;

Acquiring a physical view of a chip design, wherein the physical view comprises all physical modules, and all the physical modules are formed by combining logic modules in the logic view according to the physical realization requirements of the chip design;

Adjusting the logic view based on the physical view so that the logic level of each logic module in the logic view is consistent with the physical level of the corresponding logic module in the physical view, wherein the physical level is a physical setting position corresponding to the logic module in the physical implementation requirement of chip design, and the logic level is a logic setting position corresponding to the logic module in the logic design requirement of chip design;

and generating a standard design file of the chip design based on the adjusted logic view.

In a second aspect, an embodiment of the present invention provides a chip design file generating apparatus, including:

The logic view acquisition module is used for acquiring a logic view of the chip design, wherein the logic view comprises all logic modules of the chip design, and all logic modules are combined according to logic design requirements of the chip design;

The system comprises a physical view acquisition module, a physical view generation module and a physical view generation module, wherein the physical view acquisition module is used for acquiring a physical view of a chip design, the physical view comprises all physical modules, and all the physical modules are formed by combining logic modules in the logic view according to the physical realization requirements of the chip design;

The logic level adjustment module is used for adjusting the logic view based on the physical view so that the logic level of each logic module in the logic view is consistent with the physical level of the corresponding logic module in the physical view, wherein the physical level is a physical setting position corresponding to the logic module in the physical implementation requirement of the chip design, and the logic level is a logic setting position corresponding to the logic module in the logic design requirement of the chip design;

And the standard design file generation module is used for generating a standard design file of the chip design based on the adjusted logic view.

In a third aspect, an embodiment of the present invention provides a chip design file generating system, including:

the first reading module is used for reading the interface protocol type definition file;

the second reading module is used for reading the module assembled file;

The third reading module is used for reading the physical hierarchy configuration form of the module;

The chip design file generating apparatus according to the second aspect generates the standard design file of the chip design based on the respective logical modules and the respective interface protocol types read by the interface protocol type definition file reading module and the physical layer layout read by the module physical hierarchy configuration table reading module.

In a fourth aspect, an embodiment of the present invention provides an electronic device, including a memory and a processor, where the memory stores a program, and the processor invokes the program stored in the memory to execute the chip design file generating method according to the first aspect.

In a fifth aspect, an embodiment of the present invention provides a storage medium storing a program that when executed implements the chip design file generation method according to the first aspect.

Firstly, obtaining a logic view of a chip design, wherein the logic view comprises logic modules of the chip design, and the logic modules are combined according to logic design requirements of the chip design; meanwhile, a physical view of the chip design is obtained, the physical view comprises all physical modules, and all the physical modules are formed by combining logic modules in the logic view according to the physical realization requirements of the chip design; then, adjusting the logic view based on the physical view so as to enable the logic level of each logic module in the logic view to be consistent with the physical level of the corresponding logic module in the physical view, wherein the physical level is a physical setting position corresponding to the logic module in the physical implementation requirement of chip design, and the logic level is a logic setting position corresponding to the logic module in the logic design requirement of chip design; and finally, generating a standard design file of the chip design based on the adjusted logic view. It can be seen that, according to the method for generating the chip design file provided by the embodiment of the invention, the logic view corresponding to the logic design requirement of the chip design is obtained, meanwhile, the physical view corresponding to the physical implementation requirement of the chip design is obtained, and the physical modules in the physical view are formed by combining all the logic modules in the logic view, so that when all the logic modules in the logic view are adjusted based on the physical view in the follow-up process, the logic levels of all the logic modules in the logic view can be directly adjusted to be consistent with the physical levels of the corresponding logic modules in the physical view, thereby realizing the direct conversion from the logic design requirement to the physical implementation requirement, enabling the generated standard design file of the chip design to meet the physical layer layout of the chip design, avoiding the repartition and modification of the standard design file of the chip design according to the physical layer layout, facilitating the generation of the standard design file, thereby reducing the error rate in the process of generating the standard design file, and improving the generation efficiency of the standard design file of the chip design.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.

FIG. 1 is a flow chart of a method for generating a chip design file according to an embodiment of the present application;

FIG. 2 is another flow chart of a method for generating a chip design file according to an embodiment of the present application;

FIG. 3 is a diagram illustrating a logic view in a method for generating a chip design file according to an embodiment of the present application;

FIG. 4 is a schematic diagram illustrating a process of adjusting a logic view in a method for generating a chip design file according to an embodiment of the present application;

FIG. 5 is a schematic diagram of an adjustment command sequence in a method for generating a chip design file according to an embodiment of the present application;

FIG. 6 is another flow chart of a method for generating a chip design file according to an embodiment of the present application;

FIG. 7 is a schematic diagram of an implementation process of post-processing in the method for generating a chip design file according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a chip design file generating apparatus according to an embodiment of the present application;

fig. 9 is a schematic diagram of a chip design file generating system according to an embodiment of the application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

With the dramatic increase in the design scale of Chip designs, the entire System can be integrated into a single Chip during the design process of Chip designs, which are referred to as System on Chip (SoC). For example, a typical SoC system may integrate CPU processor cores, DDR memory controllers, various high-speed interfaces such as universal serial bus (USB, universal Serial Bus) interfaces, ethernet interfaces, high-speed serial computer expansion bus (PCI-E, PERIPHERAL COMPONENT INTERCONNECT EXPRESS) interfaces, etc., data networks on chip, data bridges, power management systems, etc.

Verification of chip design is one of the links in the chip manufacturing process. After the chip design is completed, a standard design file of the chip design is obtained, wherein the standard design file is a code file written based on a hardware description language (such as verilog coding language) and used for describing a logic circuit of the chip design. In the verification process of the chip design, the verification of the standard design file aiming at the chip design is mainly performed, namely, the verification of the design code in the standard design file is performed.

With further expansion of the design scale of chip design, the complexity of the logic circuit integrated in the SoC system increases dramatically, and thus the number of physical modules integrated in one SoC for implementing the logic circuit increases accordingly. One SoC system, even subsystem and a class of intellectual property cores (IP, intellectual Property), may contain hundreds or thousands of physical modules (instantiation of logic modules based on logic function design of chip design, which are formed by verilog meter code describing logic functions), while the verilog/vhdl language describing logic circuits formed by each logic module, the description of interfacing information of each logic module is supported too low. For example, a group of AXI interfaces is generally composed of more than ten signals, and when programming the interface design code corresponding to the AXI interface, the corresponding requirements are defined for the more than ten signals respectively and are used in a large amount. Therefore, in the large-scale chip design, the description of the interface connection information of each logic module and the number of the interface design codes corresponding to the interface connection information of each logic module are huge, and the time and the error are taken, so that the maintenance is difficult.

In addition, another problem with the expansion of the design scale of the chip design is that in the process of integrating and laying out the large-scale chip design, the SoC system needs to be divided into a plurality of small physical layers according to the physical implementation requirements of the chip design (for example, the SoC system), each physical layer is independently integrated and laid out for winding, and finally, the splicing and combination of the top physical layers of the SoC system are performed. The logic level of the logic module in the logic development of the IP and SoC systems is divided according to the functions of the chip design, and the physical level corresponding to the division of the physical implementation requirements is inconsistent. Therefore, a designer is required to manually modify the design code in the standard design file to conform to the physical layer layout corresponding to the physical layer, redefinition of the logic module and connection adjustment of the logic module are required in the process of modifying the design code, so that the design time consumption of chip design is increased, and errors are easy to occur in the process of dividing and reorganizing.

In order to solve the above-mentioned problems, the embodiment of the application provides a method for generating a chip design file, so as to facilitate the generation of a standard design file and reduce the design time consumption of the chip design.

Referring to fig. 1, fig. 1 is a flow chart illustrating a method for generating a chip design file according to an embodiment of the application.

As shown in fig. 1, the process may include the steps of:

step S100, obtaining a logic view of the chip design, wherein the logic view comprises all logic modules of the chip design, and all logic modules are combined according to logic design requirements of the chip design.

The logic design requirement of the chip design starts from the logic function realization of the chip design, and corresponding codes are designed according to each logic function of the chip design, so that each logic module of the chip design can be obtained. Meanwhile, the logic design requirement describes the combination relation of each logic module (namely the corresponding logic setting position of each logic module in the logic design requirement) on a logic level so as to meet the logic function realization of the chip design. Therefore, after each logic module is obtained, each logic module can be combined according to logic design requirements to form a logic view.

Step S101, a physical view of the chip design is obtained, the physical view comprises all physical modules, and all the physical modules are formed by combining logic modules in the logic view according to the physical realization requirements of the chip design.

The physical implementation requirements correspond to the physical layer layout of the chip design, for example, the physical layer layout of the chip design may cover the physical area of the chip design and the area of each physical module in the physical area, and the interface connection relationship between each physical module is the routing. Therefore, the combination mode of each physical module in the physical view can embody the physical layer layout of the chip design and accords with the actual construction of the chip design; further, because the physical modules in the physical view are formed based on the logic modules in the logic view, on the basis that the combination mode of the physical modules accords with the actual structure of the chip design, the corresponding combination mode of the logic modules forming the physical modules also accords with the actual structure of the chip design, so that the subsequent corresponding adjustment of the combination of the logic modules in the logic view according to the combination of the logic modules in the logic view can be facilitated, the combination of the logic modules in the logic view accords with the actual structure of the chip design, and the manual adjustment of the combination of the logic modules is avoided.

It should be noted that, one physical module in the physical view may be formed by one logical module in the logical view, or may be formed by a plurality of logical modules in the logical view (for example, two logical modules are combined to form one physical module), so as to ensure that the physical module formed by the combination of the logical modules in the physical view meets the physical implementation requirement.

Each physical module in the physical view is divided and combined according to the layout of the physical layer of the chip design, so that EDA tools are convenient to realize, and different chip designs adopt different dividing modes according to different manufacturing processes of the chip designs and different configurations of the chip designs. Meanwhile, each physical module is formed based on the logic modules in the logic view, so that the combination of each logic module in the physical view corresponds to the planning of the physical layer layout, and further, the division of one or more logic modules corresponding to each physical module, namely, the combination mode of the logic modules in the physical view is suitable for EDA tool processing, and the time and the optimization realization effect are reduced.

Step S102, the logical view is adjusted based on the physical view so that the logical level of each logical module in the logical view is consistent with the physical level of the corresponding logical module in the physical view.

The physical hierarchy is a physical setting position of the logic module in the physical implementation requirement of the chip design, and the logic hierarchy is a logic setting position of the logic module in the logic design requirement of the chip design.

And determining the logic setting position of each logic module according to the logic functions and logic design requirements which can be realized by each logic module, thereby determining the logic level of each logic module. For example, if the functions implemented by the logic module a and the logic module B are similar, the logic module a and the logic module B are connected and combined together to form a logic module AB, wherein the logic hierarchy corresponding to the logic module AB in the logic design requirement is upper logic, and the logic hierarchy corresponding to the logic module a and the logic module B in the logic design requirement is lower logic; therefore, the logic view can be generated according to the interface connection information of each logic module and the corresponding logic level of each logic module in the logic design requirement, so that the logic view can be used for carrying out the level division of the logic modules from the logic design level, the interface connection information and the logic level between each logic module are displayed, the change of the logic functions corresponding to different chip designs is small, and the description of the logic view from the logic design requirement aspect is more stable.

The physical view meets the physical realization requirement of the chip design and meets the actual manufacturing requirement of the chip design, so that the combination mode of each logic module forming each physical module can be determined according to the combination mode of each physical module in the physical view to obtain the physical level of each logic module in the physical view, and then the logic level of each logic module in the logic view is adjusted according to the physical level of each logic module in the physical view, namely, the combination mode of the logic modules in the logic view is adjusted, so that the combination mode of each logic module in the adjusted logic view meets the physical realization requirement of the chip design.

Step S103, generating a standard design file of the chip design based on the adjusted logic view.

The logic level of each logic module in the adjusted logic view is consistent with the physical level of the corresponding logic module in the physical view of the chip design, so that the combination mode of each logic module in the adjusted logic view meets the physical realization requirement of the chip design, and further, the standard design file of the chip design is generated based on the adjusted logic view, so that the physical realization requirement of the chip can be met, and readjustment of the standard design file based on the physical realization requirement of the chip is avoided.

It can be seen that, according to the method for generating the chip design file provided by the embodiment of the application, the logic view corresponding to the logic design requirement of the chip design is obtained, meanwhile, the physical view corresponding to the physical implementation requirement of the chip design is obtained, and the physical modules in the physical view are formed by combining all the logic modules in the logic view, so that when all the logic modules in the logic view are adjusted based on the physical view in the follow-up process, the logic levels of all the logic modules in the logic view can be directly adjusted to be consistent with the physical levels of the corresponding logic modules in the physical view, thereby realizing the direct conversion from the logic design requirement to the physical implementation requirement, enabling the generated standard design file of the chip design to meet the physical layer layout of the chip design, avoiding the repartition and modification of the standard design file of the chip design according to the physical layer layout, facilitating the generation of the standard design file, thereby reducing the error rate in the process of generating the standard design file, and improving the generation efficiency of the standard design file of the chip design.

In order to be able to accurately generate a logical view, in an embodiment, the method may further comprise a step of generating a logical view of the chip design, the step of generating the logical view of the chip design comprising:

Determining each logic module of the chip design and an external port of each logic module according to logic design requirements of the chip design;

Forming interface connection information based on interface design function information corresponding to the external ports of each logic module;

determining logic setting positions of each logic module in logic design requirements of chip design, and forming logic layers of each logic module;

And correspondingly connecting the logic modules with the same interface connection information, and combining the connected logic modules based on the logic layers corresponding to the logic modules to generate the logic view.

The logic design requirement corresponds to the realization of the logic function of the chip design, so that each logic module and the interface connection information and the logic level corresponding to each logic module can be determined according to the realization flow of the logic function.

For example, the logic function implementation flow is to transfer data from a logic module implementing a storage function to a logic module implementing a data operation function, and for the logic module (e.g., a memory) implementing the storage function, further includes a logic module a (e.g., a memory DRAM) and a logic module B (e.g., a cache) capable of performing data storage therein, and each logic module corresponding to the determination may be a logic module AB implementing the data storage function, a logic module a and a logic module B lower inside the logic module AB, and a logic module C (e.g., a processor) implementing the data operation function.

The interface connection information of the logic module AB may be interface design function information (i.e., instance information of an interface type) implemented corresponding to an external port of the logic module AB, and the interface connection information of the logic module C may be interface design function information implemented corresponding to an external port of the logic module C, and interface design function information implemented corresponding to an external port of the logic module a in an inner lower layer of the logic module AB and interface design function information implemented corresponding to an external port of the logic module B in a lower layer.

The logic level of the logic module AB may be a corresponding logic setting position of the logic module AB according to a logic design requirement of the chip design, for example, the logic module AB is formed by the logic module a and the logic module B, so in the logic design requirement of the chip design, the logic module AB is an upper layer logic of the logic module a and the logic module B, that is, an upper layer logic package, the logic module a and the logic module B are a lower layer logic, the logic level of the logic module C is the same as the logic level of the logic module AB, which means that the logic module C is the same as the upper layer logic of the logic module AB, and the logic module C and the logic module AB are packaged in the same layer on the logic design requirement.

It should be noted that, the interface design function information (i.e., instance information of an interface type) is function information of an interface protocol type corresponding to an interface type, which is implemented correspondingly when physical instantiation (hardware implementation) is performed.

For example, according to the logic design requirement of the chip design, it is determined that the logic module a includes 2 external ports, i.e. the external port 1 and the external port 2, and the interface types corresponding to the 2 external ports are interface protocol types of advanced extensible interface protocols (AXI, advanced Microcontroller Bus Architecture), so that according to the interface design function information corresponding to the two external ports, interface connection information of each interface can be formed, for example, the interface design function information corresponding to the external port 1 is an interface for connecting a memory and a cache, the interface connection information can be defined as AXItype, the interface design function information corresponding to the external port 2 is a connection cache and a memory, and the interface connection information can be defined as AXItype2. Therefore, the design function actually realized by the external port under the interface protocol type of the same high-level extensible interface protocol can be shown.

In order to facilitate the generation of the logic view, in one embodiment, the logic modules are defined in a module assembly file, and instantiation information, interface connection information and logic hierarchy of the logic modules are correspondingly defined for each logic module in the module assembly file.

The module assembly file is an interconnection design file of the logic modules on the logic layer and is used for describing the connection relation and the logic level between each logic module, so that each logic module can be conveniently interconnected based on the interface connection information and the logic level.

For the convenience of understanding the definition content of the module assembly file, the following expression form may be considered as an implementation manner of the record content in the module assembly file based on which the chip design file generating method provided by the embodiment of the present application is based.

< Module > Module name

Instantiation information of logic modules

Port portion

Instantiation information port connection of underlying logic modules

Instantiation information of# more logic modules

< End >;

Wherein "< module >" indicates a logical module, and "module name" indicates the name of the logical module, for example, the logical module AB described in the foregoing embodiment, and "AB" is the name of the logical module; the instantiation information of the logic module represents a physical module corresponding to the logic module in physical realization; the "port portion" includes interface connection information of the logic module (i.e., interface design function information corresponding to an external port of the logic module, example information of an interface protocol type described in the foregoing embodiment) and an input or output direction of the external port; the instantiation information of the lower-layer logic module represents the lower-layer referenced logic module of the logic module, and comprises the module name of the lower-layer logic module, the interface connection information of the lower-layer logic module and a logic level.

It should be noted that, each module assembly design file corresponds to an IP, that is, corresponds to a function of implementing a chip design, so that a plurality of logic modules capable of implementing the corresponding function are included under an IP, and thus, a definition of each logic module under the IP is included in one module assembly design file, where a definition content of each logic module may be defined with reference to a content defined by the above < module >.

In one embodiment, in order to enable each logic module in the logic view to meet the logic design requirement of the chip design, the logic module further includes interface connection information of the logic module, so that each logic module in the logic view can be combined based on the logic design requirement and meanwhile connection of the logic module can be performed according to the interface connection relation of each logic module.

Referring to fig. 2, fig. 2 is another flow chart of a method for generating a chip design file according to an embodiment of the application.

As illustrated in fig. 2, the process may include the steps of:

Step S200, obtaining a logic view of the chip design, wherein the logic view comprises all logic modules of the chip design, and all logic modules are combined according to logic design requirements of the chip design.

Step S201, obtaining a physical view of the chip design, where the physical view includes each physical module, and each physical module is formed by combining logic modules in the logic view according to the physical implementation requirement of the chip design.

Step S202, adjusting the logical view based on the physical view, so that the logical hierarchy of each logical module in the logical view is consistent with the physical hierarchy of the corresponding logical module in the physical view.

Step S203, generating a corresponding module standard design file based on each logic module in the adjusted logic view.

Step S204, determining the interface protocol type corresponding to the interface connection information of each logic module, and generating an interface design code according to the interface composition information of the determined interface protocol type.

Step S205, writing the interface design code into the corresponding module standard design file to generate the standard design file of the chip design.

Because each logic module in the logic view has been correspondingly adjusted according to the physical view, the combination of the adjusted logic modules accords with the physical module in the physical implementation requirements of the chip design, and when the corresponding module standard design file is generated based on the adjusted logic modules, the module standard design file correspondingly accords with the physical implementation requirements of the chip design, namely, each module standard design file corresponds to the physical module of the chip design, and the subsequent manual division of the standard design file row of the chip design is avoided.

Further, an interface design code is generated according to the interface protocol type corresponding to the interface connection information, and the interface design code is written into a module standard design file generated by the logic module corresponding to the interface connection information, so that the finally generated standard design file of the chip design can correspond to the connection of each physical module in the physical layer layout of the chip design, and the physical realization requirement of the chip design is met.

To facilitate the generation of the interface design code, in one embodiment, the generating the interface design code according to the interface composition information of the determined interface protocol type may include:

Acquiring each component signal corresponding to the determined interface protocol type, bit width corresponding to each component signal and driving type corresponding to each component signal, and forming interface component information of the interface protocol type;

And generating the interface design code of the determined interface protocol type according to the interface composition information of the interface protocol type and the language coding format corresponding to the standard design file.

The interface connection information is formed by interface design function information corresponding to the external ports of the logic modules, the external ports of the logic modules are determined by logic design requirements of chip design, and the interface protocol type of the external port of each logic module is defined in the logic design requirements of chip design, so that the interface protocol type of the external port of the logic module can be determined according to the interface connection information.

And further, based on the determined interface protocol type, acquiring predefined information under the interface protocol type, expanding the interface composition under the interface protocol type based on the predefined information according to a language coding format corresponding to the standard design file, and obtaining an interface design code corresponding to the external port of the logic module, so as to accurately describe the design function of the external port based on the interface design code.

The interface connection information of each logic module described in the above embodiment may be directly written in real time according to the interface protocol type corresponding to the interface connection information.

For example, when generating a standard design file of a chip design, interface composition information is defined in real time in the standard design file according to the interface protocol type corresponding to the determined interface connection information in the current chip design so as to generate an interface design code, thereby obtaining the standard design file of the chip design; when the standard design file of other chip designs is generated again, interface composition information needs to be redefined in the standard design file in real time according to the interface protocol type corresponding to the determined interface connection information in the new chip design.

Because the scale of chip design is continuously increased, the number of interfaces connected with each logic module is correspondingly increased, so that the code quantity of the interface design codes for describing the interface composition information is greatly increased, and the interface composition information is repeatedly defined when a standard design file of the chip design is generated each time so as to generate the corresponding interface design codes, thereby causing the problems of long programming time consumption, increased programming error rate and increased maintenance difficulty of the interface design codes. Thus, in other embodiments, the interface protocol type may be defined in an interface protocol type definition file, where the interface protocol type definition file includes respective interface protocol types, and predefined information of each interface protocol type, where the predefined information of an interface protocol type is defined correspondingly according to protocol content of each interface protocol type, and includes respective constituent signals corresponding to each interface protocol type, bit widths of the respective constituent signals, and driving types of the respective constituent signals, where the interface protocol type defined in the interface protocol type definition file corresponds to an interface protocol type of interface connection information of a logic module defined in a module assembly file.

The embodiment of the application predefines the interface composition information corresponding to the interface protocol type and stores the interface composition information in the interface protocol type definition file, thereby avoiding manual writing of a large number of interface design codes in large-scale chip design, facilitating the conversion according to the predefine information directly when the interface design codes are generated, reducing the error rate and the writing time consumption when the interface design codes are written, improving the generating efficiency of the standard design file and reducing the error rate in the generating process of the standard design file.

In the interface protocol type definition file, the data structure of each interface protocol type is defined, one interface protocol type is used for representing a group of signals, and the external port of the logic module is defined in a structured mode, so that the direct reference of the interface design code can be conveniently generated subsequently.

For example, the following description may be considered as an implementation manner of the record content in the interface protocol type definition file on which the chip design file generating method provided by the embodiment of the present application is based.

Interface name

Signal name width direction

# More signal definition

< End >;

Wherein "< interface protocol type >" indicates an interface protocol type corresponding to an external port of the logic module; "interface name" means the name of the interface protocol type, defined in terms of the specific interface protocol, which is a variable; the "signal name width direction" is interface composition information, and the "signal name" indicates a group of signals included under the interface protocol type, i.e., composition signals, for example, ten groups of signals included under the AXI interface protocol type; the "width" indicates the bit width corresponding to each constituent signal in the set of signals, and the bit is taken as a basic unit; the "direction" is the drive type corresponding to each constituent signal in the set of signals, and indicates whether to transmit or receive.

The interface protocol type definition file may correspondingly define each interface protocol type and an interface name based on different interface protocol types, for example, based on an interface protocol type AHB interface protocol or an AXI interface protocol, and may define a corresponding interface name, where predefined information may be defined as each signal name under the interface name according to each signal field in the corresponding interface protocol type, for example, a write address, a read address, write data, read data, etc., so that a set of signals may be represented by one interface name.

For example, according to the basic format of the interface protocol type definition file, the content defining a plurality of different interface protocol types may be expressed as:

< interface protocol type > AXI

Signal name width direction

# More signal definition

< End >

< Interface protocol type > AHB

Signal name width direction

# More signal definition

< End >;

Since one interface protocol type can be instantiated based on the difference of interface design function information corresponding to the external port of the logic module, the instance information of the interface type, which is the interface connection information of multiple types of external ports, can be correspondingly used in the module assembly file to represent the external port of the logic module, namely, the interface protocol type of the external interface of the logic module is represented by the interface name defined in the interface type definition file, so as to facilitate the direct acquisition and reference of the subsequent predefined information.

In order to facilitate understanding of the structure of representing the logic view based on the module assembly file and the definition description of the external ports of each logic module based on the interface protocol type definition file, please refer to fig. 3, fig. 3 is a diagram illustrating a structure of the logic view in the chip design file generating method according to the embodiment of the present application.

As shown in fig. 3, a logic view is constructed according to the interface connection information and the logic hierarchy of each logic module described by the module assembly file, where the interface connection information of each logic module corresponds to an external port of the logic module, the external port corresponds to an interface protocol type to which the port belongs, and the interface protocol type is defined and described by using an interface protocol type definition file.

To implement adjustment of a logical view based on a physical view, implementing a direct conversion of a logical layer to a physical layer, in one embodiment, the adjusting the logical view based on the physical view includes:

Correspondingly comparing the logic level of each logic module in the logic view with the physical level of each logic module in the physical view, and generating an adjustment command sequence according to the comparison result;

And executing the adjustment command sequence, and adjusting the logic level of each logic module in the logic view so as to enable the logic level of each logic module in the logic view to be consistent with the physical level of the corresponding logic module in the physical view.

The physical view is established according to the physical implementation requirements of the chip design, so that the physical layer layout corresponding to the physical implementation requirements can be described, the physical layer layout is an actual design structure of the chip design, the physical layer can be determined according to the physical setting positions of all the physical modules in the physical layer layout, and the physical layer can further determine the physical setting positions corresponding to all the logic modules because the physical modules are based on the logic module composition in the logic view, thereby determining the physical layer of all the logic modules. Therefore, according to the physical view, the logic levels of all logic modules in the logic view are adjusted, so that the logic levels of all logic modules in the adjusted logic view can meet the physical levels in physical realization demands, and further, when corresponding module standard design files are generated based on all adjusted logic modules, manual readjustment according to physical layer layout can be avoided, the module standard design files generated through conversion can be directly used, and the design and manufacturing efficiency of chip design are improved.

Referring to fig. 4, fig. 4 is a schematic process diagram of adjusting a logic view in the method for generating a chip design file according to an embodiment of the application.

As shown in fig. 4, based on the logic design requirement of the chip design, the logic module a and the logic module B in the generated logic view are the lower layer logic of the logic module AB, while in the generated physical view, the logic module B and the logic module C in the generated physical view are the lower layer logic of the logic module BC (actual physical module in the physical layer layout) according to the physical implementation requirement of the chip design, so after the logic view and the physical view are acquired, the logic levels of the logic modules in the logic view can be adjusted according to the physical levels of the logic modules in the physical layer layout corresponding to the physical view, so that the logic levels of the logic modules in the adjusted logic view conform to the physical levels, and the physical implementation requirement of the chip design is satisfied.

In adjusting the logical view, the connection interface information is not changed for adjusting the logical hierarchy of the logical module.

In order to automatically implement adjustment of the logic levels of each logic module in the logic view, in one embodiment, the comparing the logic levels of each logic module in the logic view with the physical levels corresponding to each logic module in the physical view, and generating an adjustment command sequence according to the comparison result includes:

Generating a command of a dismissal module for a logic module with a logic level different from a physical level in the physical view in the logic view so as to dismiss the logic module corresponding to the logic level different from the physical level;

Generating a combination module command according to a combination mode of each logic module in the physical view aiming at the logic module after being disassembled so as to combine the logic modules after being disassembled;

Generating a module creation command aiming at the physical module information of each logic module corresponding to the physical layer in the physical view so as to create a corresponding logic layer for the combined and disassembled logic modules, so that the created logic layer is consistent with the physical layer;

an adjustment command sequence is generated based on the dismissal module command, the combine module command, and the create module command.

Because the logic levels of the logic modules in the logic view correspond to the logic design requirements, and the physical implementation requirements need to be designed according to the actual layout of the chip design, the logic modules originally combined together in the logic design requirements may have a situation of separate setting in the physical implementation requirements, so that the composition structure of the logic modules corresponding to the physical levels and the composition structure of the logic modules corresponding to the logic levels are different.

The final implementation of the chip design is mainly based on the structural form of physical layer layout, so that in order to meet the physical implementation requirement, the physical layers of all logic modules in a physical view are utilized to carry out corresponding comparison with the logic layers of all logic modules in the logic view, a command for disassembling the module is generated aiming at the logic modules with the layer difference, the corresponding logic layers are disassembled, and the lower logic modules included in the logic modules corresponding to the logic layers are displayed; then, generating a combined module command for the disassembled logic modules according to the composition structure of each logic module corresponding to the physical layer so as to combine the disassembled logic modules; and finally, generating a module creation command according to the name of the physical hardware structure correspondingly realized by the physical layer, so as to generate a new physical module name for the combined and disassembled logic module, thereby creating a corresponding new logic layer so as to be convenient for conforming to the physical layer.

Referring to fig. 5, fig. 5 is a schematic diagram of an adjustment command sequence in a method for generating a chip design file according to an embodiment of the application.

As shown in fig. 5, the command names are the respective commands included in the adjustment command sequence, such as the break-up module command, the combine module command, and the create module command; the parameters represent the specific implementation of each command in the instruction description for each command execution.

In order to describe the physical layer layout, so as to generate a physical view, in one embodiment, the physical layer is described in a module physical layer configuration table, the module physical layer configuration table is established according to the physical implementation requirement of the chip design, the module physical layer configuration table includes each physical module of the chip design and instantiation information of each physical module, and each physical module includes each logic module and instantiation information of each logic module, where each logic module is the same as a logic module in the logic module assembly file.

In the module physical layer configuration table, the user describes the physical layer of each logic module in the physical layer layout of the physical view, and the module physical layer configuration table can be placed under the configuration file directory corresponding to the interface type definition file and the module assembly file to be used as an input file in the process of converting the logic layer into the physical layer.

The module physical hierarchy configuration table comprises names of all physical modules and instantiation names of the physical modules under the top layer of the SoC, and names of logic modules and instantiation names of the logic modules under the physical modules.

For example, the following description of the expression form may be considered as an implementation manner of the record content in the module physical hierarchy configuration table based on which the chip design file generating method provided by the embodiment of the present application is based.

< SoC Top-level name >

< Physical Module name instantiation name >

Instantiation information of logical module name logical module

# Other physical Module

< End >;

Wherein "< SoC top-level name >" represents the name of the chip system; "< physical module name instantiation name >" indicates the name of the physical hardware structure of the chip design; the "instantiation information of a logical module name logical module" indicates that the logical module corresponding to the physical module is formed according to the physical implementation requirement of the chip design, corresponds to the logical module defined in the module assembly file, and is name information of a physical structure implemented corresponding to the logical module, and corresponds to instantiation information of the logical module under the logical module defined in the module assembly file.

The module physical layer configuration table can automatically realize adjustment and conversion from the logical view to the physical view, so that each logical module conforming to the physical view is obtained, and the adjustment of the logical layer of each logical module is facilitated.

Referring to fig. 6, fig. 6 is another flow chart of the method for generating a chip design file according to the embodiment of the application.

As shown in fig. 6, the process may include the steps of:

step S300, obtaining a logic view of the chip design, wherein the logic view comprises all logic modules of the chip design, and all logic modules are combined according to logic design requirements of the chip design.

Step S301, obtaining a physical view of the chip design, where the physical view includes each physical module, and each physical module is formed by combining logic modules in the logic view according to the physical implementation requirement of the chip design.

Step S302, adjusting the logical view based on the physical view, so that the logical hierarchy of each logical module in the logical view is consistent with the physical hierarchy of the corresponding logical module in the physical view.

Step S303, generating a corresponding module standard design file based on each logic module in the adjusted logic view.

Step S304, determining the interface protocol type corresponding to the interface connection information of each logic module, and generating an interface design code according to the interface composition information of the determined interface protocol type.

Step S305, writing the interface design code into the corresponding module standard design file to generate the standard design file of the chip design.

Step S306, according to the physical realization requirement of the chip design, the instantiation information of the physical module is obtained, and the physical module exceeding the threshold value of the instantiation times is determined.

Step S307, determining a logic module corresponding to the determined physical module, and obtaining a corresponding target module standard design file from the module standard design files.

Step S308, the obtained standard design file of the target module is subjected to copying processing so as to instantiate a physical module based on the copied standard design file of the module.

The adjusted logic module corresponds to the physical implementation requirement of the chip design, so that the adjusted logic module can be determined according to the corresponding of the instantiated physical module, and further, a module standard design file generated based on the adjusted logic module is obtained.

And the module standard design file of the logic module corresponding to the physical module exceeding the threshold of the instantiation times is duplicated (post-processing of the module standard design file), so that the use flexibility of standard module design codes can be enhanced, and the iteration with a physical realization team can be accelerated. Based on the module standard design file, the exclusive operation of part of physical modules is realized quickly, namely, the module standard design file of the logic module corresponding to the physical module exceeding the threshold of the instantiation times is copied, so that the time sequence of physical realization can be improved.

For example, please refer to fig. 7 for implementation of the post-processing, fig. 7 is a schematic diagram illustrating an implementation process of the post-processing in the method for generating a chip design file according to an embodiment of the present application.

As shown in fig. 7, the implementation process may include the following stages:

stage 1, loading interface protocol type definition file and module assembly file.

Reading in all interface protocol types and logic modules defined.

And 2, analyzing and checking the read interface protocol type and the read logic module.

Judging whether the logic module and the interface protocol type are missing or not, and judging the interconnection conflict between the logic modules.

Stage 3, hierarchical adjustment.

And reading in the physical hierarchy configuration table of the module, automatically converting the physical hierarchy configuration table into a basic operation command combination (namely an adjustment command sequence) for adjusting the logic hierarchy of the internal logic module, and completing the adjustment of the logic hierarchy of the logic module.

And 4, generating a standard design file of the chip design.

For each IP of the chip design, a design file and a file list needle in a standard verilog format are written.

Stage 5, post-treatment.

According to the physical realization requirement, a physical module exceeding the threshold of the instantiation times determines a corresponding logic module, and copies the generated verilog module standard design file to realize the exclusive processing of the physical module. In the case that multiple instantiations exist in the same physical module, the self-unique physical module is automatically created for each instantiation, so that time sequence can be better in physical implementation. This is done in a post-processing step, making the process simpler and more flexible.

The embodiment of the application also provides a device for generating the chip design file, please refer to fig. 8, fig. 8 is a schematic structural diagram of the device for generating the chip design file provided by the embodiment of the application.

As shown in fig. 8, the chip design file generating apparatus 40 may include:

A logic view obtaining module 400, configured to obtain a logic view of a chip design, where the logic view includes each logic module of the chip design, and each logic module is combined according to logic design requirements of the chip design;

A physical view obtaining module 401, configured to obtain a physical view of a chip design, where the physical view includes each physical module, and each physical module is formed by combining logic modules in the logic view according to a physical implementation requirement of the chip design;

A logic level adjustment module 402, configured to adjust the logic view based on the physical view, so that a logic level of each logic module in the logic view is consistent with a physical level of a corresponding logic module in the physical view, where the physical level is a physical setting position corresponding to the logic module in a physical implementation requirement of a chip design, and the logic level is a logic setting position corresponding to the logic module in a logic design requirement of the chip design;

the standard design file generating module 403 is configured to generate a standard design file of the chip design based on the adjusted logic view.

It can be seen that, in the chip design file generating device 40 provided in the embodiment of the present application, the logic view corresponding to the logic design requirement of the chip design is obtained, and the physical view corresponding to the physical implementation requirement of the chip design is obtained at the same time, and the physical modules in the physical view are formed by combining all the logic modules in the logic view, so when all the logic modules in the logic view are adjusted based on the physical view in the following process, the logic levels of all the logic modules in the logic view can be directly adjusted to be consistent with the physical levels of the corresponding logic modules in the physical view, thereby the direct conversion from the logic design requirement to the physical implementation requirement can be realized, so that the generated standard design file of the chip design meets the physical layer layout of the chip design, the repartition and modification of the standard design file of the chip design according to the physical layer layout are avoided, the generation of the standard design file is convenient, and the error rate in the process of generating the standard design file can be reduced, and the generation efficiency of the standard design file of the chip design is improved.

In one embodiment, the logic module further includes interface connection information of the logic module, and the standard design file generating module 403 is configured to generate a standard design file of the chip design based on the adjusted logic view, including:

Generating a corresponding module standard design file based on each logic module in the adjusted logic view;

determining interface protocol types corresponding to the interface connection information of each logic module, and generating interface design codes according to the interface composition information of the determined interface protocol types;

writing the interface design code into the corresponding module standard design file to generate a standard design file of the chip design.

In one embodiment, the chip design file generating device 40 further includes a logic view generating module, where the logic view generating module is configured to generate a logic view of a chip design, and includes:

In one embodiment, the logic level adjustment module 402 is configured to adjust the logic view based on the physical view, and includes:

In one embodiment, the logic level adjustment module 402 is configured to compare a logic level of each logic module in the logic view with a physical level corresponding to each logic module in the physical view, and generate an adjustment command sequence according to a comparison result, where the adjustment command sequence includes:

In one embodiment, the standard design file generating module 403 is configured to obtain target predefined information corresponding to the determined interface protocol type, and generate an interface design code based on the target predefined information, including:

acquiring each component signal corresponding to the determined interface protocol type, bit width of each component signal and driving type of each component signal to obtain target predefined information;

And generating the interface design code of the determined interface protocol type according to the language coding format corresponding to the standard design file based on the target predefined information.

In one embodiment, the design file generating apparatus 40 may further include:

the post-processing module is used for determining a physical module exceeding the threshold value of the instantiation times according to the physical realization requirement of the chip design; and obtaining a module standard design file corresponding to the determined physical module from the module standard design files, and copying the obtained module standard design file to instantiate the physical module based on the copied module standard design file.

The embodiment of the application also provides a system for generating the chip design file, please refer to fig. 9, fig. 9 is a schematic structural diagram of the system for generating the chip design file provided by the embodiment of the application.

As shown in fig. 9, the chip design file generation system may include:

a first reading module 10 for reading the interface protocol type definition file;

a second reading module 20 for reading module assembly files;

a third reading module 30 for reading the module physical hierarchy configuration table;

the design file generating apparatus 40 according to any one of the foregoing embodiments generates a standard design file of a chip design based on each logic module read by the second reading module 20, each interface protocol type read by the first reading module 10, and the physical layer layout read by the third reading module 30.

The interface type definition file and the module assembly file may be located under the directory of the configuration file, and after being read by the first reading module 10 and the second reading module 20, the interface type definition file and the module assembly file are sent to the logic view generating module 400 of the design file generating device 40, so that the design file generating device 40 scans the files one by one, extracts the logic module, the interface connection information of the logic module (design function information of the external port), the logic hierarchy of the logic module (interface connection information of the logic module of the lower layer and the logic module of the lower layer), and the corresponding interface protocol type, and stores the extracted interface type definition file and module assembly file into an internal module data structure (e.g., a storage structure) to generate a logic view. The design file generating apparatus 40 may further check whether all the parsed information has a corresponding definition, and whether the interface protocol types corresponding to the interface connection information of all the logic modules are the same.

The third reading module 30 may transmit the read module physical hierarchy configuration table to the physical view generating module 401 of the design file generating apparatus 40, and further transmit the logical view and the physical view to the logical hierarchy adjusting module 402 of the design file generating apparatus 40, so as to generate an adjustment command sequence, and control adjustment of the logical hierarchy of the logical view.

Finally, the standard design file generating module 403 in the design file generating device 40 generates a module standard design file described by verilog for each adjusted logic module, then determines an interface protocol type for an external port corresponding to the interface connection information of each logic module, obtains predefined information formed by each signal name, width and direction in the interface name (interface protocol type) from the interface protocol type definition file, and expands and writes the definition information into the output module standard design file according to the verilog coding language format.

It can be seen that, in the design file generating system provided by the embodiment of the application, on one hand, based on the logic design requirement of the chip design, a corresponding logic view is generated, and meanwhile, based on the physical implementation requirement of the chip design, a corresponding physical view is generated, and the physical modules in the physical view are formed based on the combination of each logic module in the logic view, so that when the interface connection information and the logic hierarchy of each logic module in the logic view are adjusted based on the physical layer layout corresponding to the physical view, the connection and the combination of each logic view in the logic view can be directly adjusted to be the same as the connection and the combination of the physical layer layout corresponding to the physical view, thereby realizing the direct conversion from the logic design requirement to the physical implementation requirement, enabling the generated standard design file of the chip design to meet the physical layer layout of the chip design, avoiding the repartitioning and modifying the standard design file of the chip design according to the physical layer layout, and facilitating the generation of the standard design file, and further reducing the error rate in the process of generating the standard design file; on the other hand, when the standard design file of the chip design is generated, the interface design code is generated based on the predefined information of the interface protocol type corresponding to the interface connection information, so that the repeated writing workload of a large number of interface design codes can be reduced, and the time consumption and the error rate of writing the interface design codes in a large number can be further reduced.

An embodiment of the present application provides an electronic device, including a memory and a processor, where the memory stores a program, and the processor invokes the program stored in the memory to execute the chip design file generating method according to any one of the foregoing embodiments.

An embodiment of the present application provides a storage medium storing a program that when executed implements the chip design file generation method according to any one of the foregoing embodiments.

The foregoing describes several embodiments of the present application, and the various alternatives presented by the various embodiments may be combined, cross-referenced, with each other without conflict, extending beyond what is possible embodiments, all of which are considered to be embodiments of the present application disclosed and disclosed.

Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the application, and the scope of the application should be assessed accordingly to that of the appended claims.

Claims

1. A method for generating a chip design file, comprising:

Adjusting the logic view based on the physical view so as to enable the logic level of each logic module in the logic view to be consistent with the physical level of the corresponding logic module in the physical view; the physical layer is a physical setting position corresponding to a logic module in the physical implementation requirement of chip design, and the logic layer is a logic setting position corresponding to the logic module in the logic design requirement of chip design;

2. The chip design file generation method of claim 1, wherein the logic module further comprises interface connection information of the logic module, and the generating the standard design file of the chip design based on the adjusted logic view comprises:

3. The chip design file generation method according to claim 2, wherein the generating an interface design code according to the interface composition information of the determined interface protocol type comprises:

4. The chip design file generation method of claim 3, wherein the interface protocol type is defined in an interface protocol type definition file, the interface protocol type definition file includes respective interface protocol types, and interface composition information of each interface protocol type, wherein the interface composition information of the interface protocol type is defined according to protocol content correspondence of each interface protocol type, and includes respective composition signals corresponding to each interface protocol type, bit widths corresponding to the respective composition signals, and driving types corresponding to the respective composition signals, wherein the interface protocol type defined in the interface protocol type definition file corresponds to an interface protocol type of interface connection information of a logic module defined in a module assembly file.

5. The chip design file generation method according to any one of claims 1 to 4, further comprising a step of generating a logical view of the chip design, the step of generating the logical view of the chip design comprising:

6. The chip design file generation method according to claim 5, wherein the logic modules are defined in a module assembly file, and instantiation information, interface connection information, and a logic hierarchy of the logic modules are defined for each logic module in the module assembly file.

7. The chip design file generation method of claim 6, wherein the adjusting the logical view based on the physical view comprises:

8. The method for generating a chip design file according to claim 7, wherein the comparing the logic level of each logic module in the logic view with the physical level corresponding to each logic module in the physical view, and generating the adjustment command sequence according to the comparison result, comprises:

9. The chip design file generation method of claim 8, wherein the physical hierarchy is described in a module physical hierarchy configuration table, the module physical hierarchy configuration table being established according to physical implementation requirements of the chip design, the module physical hierarchy configuration table including respective physical modules of the chip design and instantiation information of the respective physical modules, and respective logic modules and instantiation information of the respective logic modules included in each physical module, wherein the respective logic modules are identical to logic modules in the logic module assembly file.

10. The chip design file generation method of claim 9, further comprising:

according to the physical realization requirement of chip design, obtaining the instantiation information of a physical module, and determining the physical module exceeding the threshold value of the instantiation times;

determining a logic module corresponding to the determined physical module, and acquiring a corresponding target module standard design file from each module standard design file;

and copying the obtained standard design file of the target module to instantiate the physical module based on the copied standard design file of the module.

11. A chip design file generation apparatus, comprising:

12. The chip design file generation apparatus of claim 11, wherein the logic module further comprises interface connection information of the logic module, the standard design file generation module for generating a standard design file of the chip design based on the adjusted logic view, comprising:

13. The chip design file generation apparatus of claim 12, further comprising a logic view generation module for generating a logic view of a chip design, comprising:

14. The chip design file generation apparatus of claim 13, wherein the logic hierarchy adjustment module to adjust the logic view based on the physical view comprises:

15. The chip design file generating apparatus according to claim 14, wherein the logic level adjustment module is configured to compare a logic level of each logic module in the logic view with a physical level corresponding to each logic module in the physical view, and generate the adjustment command sequence according to the comparison result, and includes:

16. The chip design file generation apparatus of claim 15, wherein the standard design file generation module for generating an interface design code according to the interface composition information of the determined interface protocol type comprises:

17. The chip design file generation apparatus according to any one of claims 11 to 16, further comprising:

18. A chip design file generation system, comprising:

the second reading module is used for reading the module assembled file;

The chip design file generating apparatus according to any one of claims 11 to 17, wherein the standard design file of the chip design is generated based on the respective logical modules and interface protocol type definition file read by the module assembly file reading module, the respective interface protocol types read by the interface protocol type definition file reading module, and the physical layer layout read by the module physical hierarchy configuration table reading module.

19. An electronic device comprising a memory in which a program is stored and a processor that invokes the program stored in the memory to execute the chip design file generation method according to any one of claims 1 to 10.

20. A storage medium storing a program which, when executed, implements the chip design file generation method according to any one of claims 1 to 10.