CN117915450A - Signal processing circuit and electronic equipment - Google Patents

Abstract

The application provides a signal processing circuit and electronic equipment, which are applied to the technical field of wireless communication and applied to a base station, and are used for reducing the cost of base station clock synchronization and improving the applicability of base station clock synchronization and the convenience of base station clock synchronization control. The signal processing circuit includes: a transmit link, a receive link, a synchronization link, and a switch assembly; the transmitting link is used for transmitting downlink signals, the receiving link is used for receiving uplink signals, and the synchronous link is used for receiving synchronous signals from adjacent base stations; wherein at least one device in the synchronization link multiplexes at least one device in the transmit link and/or at least one device in the receive link; the switch assembly is used for: in a first period, the synchronous link is conducted, and the receiving link is blocked; and/or, in a second period, switching on the receiving link and blocking the synchronous link.

Description

Signal processing circuit and electronic equipment

Technical Field

The present application relates to the field of wireless communications technologies, and in particular, to a signal processing circuit and an electronic device.

Background

The integrated base station is arranged outdoors, and the traditional method for realizing clock synchronization adopts an external global positioning system (English: global Positioning System, abbreviated as GPS), but the GPS has higher cost, higher construction requirement and influence of an antenna; or a precision clock synchronization protocol standard of a network measurement and control system, namely an Institute of Electrical and Electronics Engineers (IEEE) 1588 standard synchronization ethernet, there are transmission network nodes which do not support the IEEE1588 standard synchronization ethernet in some scenarios.

In addition, in the integrated base station in the frequency division duplex mode, the clock synchronization of the base station can be realized by independently adding a set of air interface synchronization unit circuits. However, the method has high hardware cost, occupies more resources of the circuit board and has larger product size.

Therefore, how to reduce the cost of the base station clock synchronization and improve the applicability of the base station clock synchronization and the convenience of the base station clock synchronization control are needed to be solved.

Disclosure of Invention

The embodiment of the application provides a signal processing circuit and electronic equipment, which can reduce the cost of base station clock synchronization and simultaneously improve the applicability of base station clock synchronization and the convenience of base station clock synchronization control.

In a first aspect, the present application provides a signal processing circuit for use in a base station, the signal processing circuit comprising: a transmit link, a receive link, a synchronization link, and a switch assembly; the transmitting link is used for transmitting downlink signals, the receiving link is used for receiving uplink signals, and the synchronizing link is used for receiving synchronizing signals from adjacent base stations;

wherein at least one device in the synchronization link multiplexes at least one device in the transmit link and/or at least one device in the receive link;

the switch assembly is used for: in a first period, a synchronous link is conducted to block a receiving link; and/or, in the second period, switching on the receiving link and blocking the synchronous link.

In the signal processing circuit provided by the application, the synchronous link is realized by multiplexing at least one device of the transmitting link and/or at least one device of the receiving link in the base station, so that the hardware cost required by clock synchronization of the base station can be reduced, and the product volume is reduced; moreover, the switch component is used for realizing the switching between the synchronous link and the receiving link (a clock synchronous mode and a normal working mode), so that the synchronous signal only passes through the synchronous link, and the convenience of clock synchronous control of the base station can be improved; in addition, by adding a switch component to realize the switching of the synchronous link and the receiving link, the added devices are easy to obtain, and the method is suitable for most base stations based on frequency division duplex modes, and the scheme has strong applicability.

Optionally, the signal processing circuit further comprises a controller; the controller is connected with the transmitting link, the receiving link and the synchronous link; the controller is used for: transmitting a first control signal to the switching assembly before or at the beginning of the first period of time; the switch assembly is used for: according to the first control signal, a synchronous link is conducted to block a receiving link; and/or the number of the groups of groups,

The controller is used for: transmitting a second control signal to the switching assembly before or at the beginning of the second period; the switch assembly is used for: and according to the second control signal, the receiving link is conducted to block the synchronous link.

Optionally, the switch assembly includes a first switch, the synchronization link includes a first link, and the first link is connected to at least one device in the transmission link through the first switch;

The first switch is used for: conducting a path between the first link and at least one device in the transmit chain for a first period of time; and/or blocking a path between the first link and at least one device in the transmit chain during the second period.

Optionally, the switch assembly further comprises a second switch disposed on the transmit link, the second switch for: blocking the transmission link during a first period of time; and/or, in the second time period, switching on the transmitting link.

Optionally, the transmitting chain comprises an antenna, a filter, a circulator and a power amplifier which are connected one by one in the following order, and further comprises a load connected with the circulator; the first switch is arranged between the load and the circulator; at least one device in the synchronous link multiplexed transmit chain comprises: antenna, filter, circulator.

Optionally, the switch assembly includes a third switch, the synchronization link includes a first link, and the first link is connected to at least one device in the receiving link through the third switch;

The third switch is used for: conducting a path between at least one device in the first link and the receive link for a first period of time; and/or blocking a path between at least one device in the first link and the receiving link during the second period.

Optionally, the third switch is further configured to: blocking the receive link during a first period of time; and/or, in the second period, switching on the receiving link.

Optionally, the switch assembly further comprises a fourth switch disposed on the receiving link, the fourth switch being configured to: blocking the receive link during a first period of time; and/or, in the second period, switching on the receiving link.

Optionally, the receiving link includes an antenna, a filter, a receiving amplifier, a sound table filter, and a broadband low noise amplifier connected one by one in the following order; the third switch is arranged between the sound surface filter and the broadband low-noise amplifier; at least one device in the receive chain of the synchronous link multiplex comprises: an antenna, a filter, a broadband low noise amplifier.

Optionally, the receive chain and the transmit chain share an antenna and a filter.

Optionally, the signal processing circuit further comprises a processor, and the processor is connected with the controller, the receiving link, the transmitting link and the synchronizing link; the controller is further configured to: transmitting a first control instruction to the processor in a first period; the processor is used for: according to the first control instruction, setting the signal receiving frequency point of the base station as the frequency point which is the same as the transmitting frequency point of the adjacent base station; and/or the number of the groups of groups,

The controller is further configured to: transmitting a second control instruction to the processor in a second period; the processor is used for setting the signal receiving frequency point of the base station and the signal transmitting frequency point of the base station based on the working frequency bands of all cells of the base station according to the second control instruction.

In a second aspect, the present application provides a base station comprising the optional signal processing circuit of the first aspect or any one of the first aspects.

In a third aspect, the present application provides a control method, applied to a controller, including: before or at the beginning of the first period, sending a first control signal to the switch assembly, so that the switch assembly conducts the synchronous link according to the first control signal to block the receiving link; and/or, before or at the beginning of the second period, sending a second control signal to the switch assembly, so that the switch assembly conducts the receiving link according to the second control signal to block the synchronous link.

Optionally, the method further comprises: in a first period, a first control instruction is sent to the processor, so that the processor sets the signal receiving frequency point of the base station to be the same frequency point as the transmitting frequency point of the adjacent base station according to the first control instruction; and/or, in the second period, sending a second control instruction to the processor, so that the processor sets the signal receiving frequency point of the base station and the signal transmitting frequency point of the base station based on the working frequency bands of all cells of the base station according to the second control instruction.

In a fourth aspect, the application provides a computer readable storage medium for storing instructions that, when executed, cause a method as in the third aspect or an optional implementation of any of the third aspects to be carried out.

In a fifth aspect, the application provides a computer program product comprising computer program code which, when run on a computer, causes the computer to perform the method as in the third aspect or any of the alternative embodiments of the third aspect.

The technical effects or advantages of one or more of the second, third, fourth and fifth aspects of the embodiments of the present application may be correspondingly explained by the technical effects or advantages of the corresponding one or more of the technical aspects provided in the first aspect.

Drawings

FIG. 1 is an exemplary diagram of a time division duplex mode air interface synchronization circuit;

FIG. 2 is an exemplary diagram of an air interface synchronization unit circuit;

Fig. 3 is an exemplary diagram of a frequency division duplex base station circuit;

fig. 4 is a block diagram of a signal processing circuit according to an embodiment of the present application;

Fig. 5 is a diagram illustrating a structure of a switch according to an embodiment of the present application;

fig. 6 is a diagram illustrating a structure of an optional switch according to an embodiment of the present application;

Fig. 7 is a diagram illustrating a structure of a controller according to an embodiment of the present application;

FIG. 8 is a diagram illustrating a structure of a processor according to an embodiment of the present application;

fig. 9 is an exemplary diagram of a signal processing circuit according to an embodiment of the present application;

Fig. 10 is an exemplary diagram of normal operation of a signal processing circuit according to an embodiment of the present application;

fig. 11 is a flowchart of a control method according to an embodiment of the present application.

Detailed Description

The following detailed description of the technical solutions of the present application is made by the accompanying drawings and specific embodiments, and it should be understood that the specific features of the embodiments of the present application are detailed descriptions of the technical solutions of the present application, and not limiting the technical solutions of the present application, and that the technical features of the embodiments of the present application and the technical features of the embodiments of the present application may be combined with each other without conflict.

It should be understood that the term "plurality" as used in the embodiments of the present application refers to two or more. The term "and/or" in the embodiment of the present application is merely an association relationship describing the association object, and indicates that three relationships may exist, for example, a and/or B may indicate: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the associated object is an "or" relationship.

A base station refers to a device in an access network that communicates over the air with wireless terminal devices via one or more cells. The base station may be configured to convert received air frames to and from Internet Protocol (IP) packets, english: internet Protocol, abbreviated as IP, as a router between the terminal device and the rest of the access network, which may include the IP network. The network device may also coordinate attribute management for the air interface. For example, the base station may include an evolved node B (english: long term evolution-advanced, abbreviated LTE-A) in A long term evolution (english: long term evolution, abbreviated LTE) system or an evolved node B (english: advanced node B, abbreviated NodeB or eNB or e-NodeB) in an advanced long term evolution (english: long term evolution, abbreviated LTE) system, or may also include A next generation node B (english: next generation node B, abbreviated gNB) in A new air interface (english: new radio, abbreviated NR) system or A next generation evolved node B (english: next generation evolved nodeB, abbreviated ng-eNB), en-gNB (english: enhanced next generation node B, abbreviated gNB) in A fifth generation mobile communication technology (english: the 5 ^th generation, abbreviated 5G) system: enhanced next generation base stations; centralized units (english: centralized unit, abbreviated CU) and Distributed Units (DU) in a cloud access network (english: cloud radio access network, abbreviated cloud RAN) system may also be included, or relay devices may also be included, and embodiments of the present application are not limited. In some embodiments, a base station may also be referred to by other names, such as network device or access network device.

An integrated base station: the functions of an indoor baseband processing unit (English: building Base band Unit, abbreviated BBU) and a remote radio unit (English: radio Remote Uinte, abbreviated RRU) are integrated into a base station in one product. Because of the multiple backhaul modes and flexible installation modes, the product is often used as a supplement to macro stations, such as blind supplements in rural areas, residential areas, etc. where bombing can also be performed with weak coverage, or hot spot absorption in local high traffic areas.

The air interface synchronization means that the integrated base station searches surrounding macro station signals through an air interface to realize clock synchronization with the macro station. Wherein, the air interface refers to an air interface. The air interface synchronization can be a powerful complement to the integrated base station clock synchronization.

Referring to fig. 1, an exemplary diagram of an air interface synchronization circuit in a time division duplex mode is shown, and air interface synchronization of an integrated base station in a time division duplex (english: time Division Duplex, TDD) mode can only support synchronization with neighboring macro stations in the same frequency band. In the TDD mode, the transmitting link and the receiving link adopt the same frequency band, the transmitting link and the receiving link share the antenna, the transmitting link and the receiving link work in a time-sharing mode, and the transmitting mode and the receiving mode are switched through a high-power radio frequency switch. When the base station starts the air interface synchronization, the base station is configured into a receiving mode, the radio frequency switch is switched to an uplink receiving link to receive the downlink broadcast signals of the macro station in the adjacent area, and the received signals are demodulated to realize the synchronization with the adjacent base station. After the synchronization is completed, the operation mode is switched to a normal time slot operation mode (namely, a receiving mode and a transmitting mode are switched according to a preset time slot), and the time slot configuration is the same as that of the TDD time slots of the adjacent base stations, and the TDD time slots are transmitted and received simultaneously.

However, the air interface synchronization circuit can only support the integrated base station in the TDD mode, is not suitable for the integrated base station synchronization in the frequency division duplex (Frequency Division Duplex is called FDD for short), and has a larger limitation.

Referring to fig. 2, an exemplary diagram of an air interface synchronization unit circuit is shown. And the air interface synchronization is realized by adding a set of air interface synchronization unit circuits. The circuit comprises an air interface synchronous radio frequency link, a baseband demodulation circuit and an independent antenna, has no multiplexing relation with an integrated base station service channel, and can realize an FDD mode or a TDD mode. Besides supporting the synchronization of the adjacent base station with the same frequency as the integrated base station, the adjacent base station with different frequency from the integrated base station can also be selected for synchronization.

However, the hardware cost of adding the air interface synchronization unit circuit is high, the occupied area of a printed circuit board (English: printed Circuit Board, abbreviated as PCB) is large, and the antenna port is added, so that the size of the product is large, and although the air interface synchronization of different frequency bands can be supported, the cost is also increased.

Referring to fig. 3, an exemplary diagram of a frequency division duplex base station circuit including a transmit chain, a receive chain, and a synchronization chain is shown.

The transmit chain includes two processors (field programmable gate array (Field Programmable GATE ARRAY, FPGA) and transceiver (transmitter)), power Amplifier (PA), circulator, diplexer and service antenna connected one by one in this order, and a load connected to the circulator.

The transmitting signal of the transmitting link flows unidirectionally and sequentially passes through FPGA, transceiver, PA, the circulator and the duplexer to reach the service antenna.

The receiving link includes a service antenna, a duplexer, a first low noise amplifier, a watch filter, a second low noise amplifier, and two processors connected one by one in this order.

The receiving signal of the receiving link flows unidirectionally and sequentially passes through the service antenna, the duplexer, the first low noise amplifier, the sound table filter, the second low noise amplifier and the transmitter to reach the FPGA.

Wherein the transmit and receive chains share a traffic antenna, a duplexer (TX (transmit x) filter and an RX (receive x) filter, each implemented by a duplexer), and two processors.

The synchronous link is an independent link and comprises a GPS, a clock phase-locked loop and a constant temperature crystal oscillator, and synchronous signals are received through the GPS.

In the circuit, the clock synchronization of the base station in the FDD mode is realized through external GPS reception, but the GPS has higher cost, higher construction requirement and weather influence.

In view of this, the technical solution of the embodiment of the present application is provided, which is improved on the circuit structure of the frequency division duplex base station shown in fig. 3, so as to reduce the cost of base station clock synchronization and improve the applicability of base station clock synchronization and the convenience of base station clock synchronization control.

The embodiment of the application can be applied to clock synchronization scenes in any FDD mode. For example: the above-mentioned air interface synchronization of the integrated base station in FDD mode.

An embodiment of the present application provides a signal processing circuit, which is applied to an integrated base station in FDD mode, as shown in fig. 4, and includes:

A transmitting link 01, a receiving link 02, a synchronizing link 03 and a switch assembly (it will be understood that two switches are taken as an example in fig. 4, and the invention is not limited thereto); the transmitting link 01 is used for transmitting downlink signals, the receiving link 02 is used for receiving uplink signals, and the synchronizing link 03 is used for receiving synchronizing signals from adjacent base stations; wherein at least one device in the synchronization link 03 multiplexes at least one device in the transmission link 01 and/or at least one device in the reception link 02.

The switch assembly is used for: during a first period, the synchronous link 03 is conducted, and the receiving link 02 is blocked; and/or, in the second period, the receiving link 02 is turned on, and the synchronous link 03 is blocked.

For example, the switch assembly may have a plurality of switches.

The first period may be a period in which the base station is started for the first time, or a period in which traffic of all cells of the base station is less than a preset value; the second period may be a period in which the base station is clock synchronized with the neighboring base station, i.e., a period in which the base station is operating normally (the receiving link and the transmitting link are operating normally).

It can be understood that the period of starting the synchronization circuit of the base station is usually performed under the condition of not affecting the user service when all cells of the base station have no active users or less service requirements, for example, the 1-5-point low service period in the early morning, and generally, the time for performing one air interface synchronization is 2-3 minutes, that is, the duration of one first period is about 2-3 minutes; after the air interface synchronization is completed, the base station clock enters a hold mode, and can be maintained in a clock range required by service operation within 24 hours generally, namely, the duration of a second period is about 24 hours; the above are examples only, and the practice is not limited thereto.

In this embodiment, the synchronization link 03 is implemented by multiplexing at least one device of the transmitting link 01 and/or at least one device of the receiving link 02 in the base station, so that the hardware cost required for clock synchronization of the base station can be reduced, and the product volume can be reduced; moreover, the switching between the synchronous link 03 and the receiving link 02 is realized through the switch component, so that the synchronous signal only passes through the synchronous link 03, and the convenience of clock synchronous control of the base station can be improved; in addition, by adding a switch component to realize the switching between the synchronous link 03 and the receiving link 02, the added devices are easy to obtain, and the scheme is suitable for most base stations based on the frequency division duplex mode and has strong applicability.

In a possible embodiment, as shown in fig. 4, the switch assembly comprises a first switch 04, the synchronization link 03 comprises a first link 06, and the first link 06 is connected to at least one device in the transmission link 01 through the first switch 04.

The first switch 04 is for: conducting a path between the first link 06 and at least one device in the transmission link 01 during a first period; and/or, in the second period, blocking the path between the first link 06 and at least one device in the transmission link 01.

It will be appreciated that since the first switch 04 is connected to the transmission link 01, the first switch 04 may be a high power radio frequency switch, requiring a pass through carrying a transmission signal, i.e. a pass through carrying a high power signal.

Illustratively, as shown in fig. 5, the transmission link 01 is the link from the device 07 to the device 09 above fig. 5 and the link from the device 07 through the first switch 04 to the load 08, and one or more circuit devices other than the device 07, the device 09, the first switch 04, and the load 08 may be further included on the transmission link 01.

The receiving link 02 is a link from the device 09 to the device 07 through the third switch 05 in fig. 5, and one or more circuit devices other than the device 09, the device 07, and the third switch 05 may be further included on the receiving link 02.

The synchronization link 03 is a link from the device 09 to the device 07 through the first switch 04 and the third switch 05 in fig. 5, and may further include one or more circuit devices other than the device 09, the device 07, the first switch 04, and the third switch 05.

The first link 06 is a link from a2 of the first switch 04 to b3 of the third switch 05, and the first link 06 may further include one or more circuit devices other than the first switch 04 and the third switch 05.

It will be appreciated that devices 09 and 07 in fig. 5 are merely an identification of one device and are not intended to represent only two devices, one or more circuit devices may be included in device 09, and one or more circuit devices may also be included in device 07.

Alternatively, the first switch 04 may be a single pole double throw switch or a double pole double throw switch, having three interfaces, where the a1 interface of the first switch 04 is connected to the transmitting link 01, the a2 interface is connected to the first link 06, and the a3 interface is connected to the load 08 of the transmitting link 01.

During a first period, the first switch 04 turns on the path between a1 and a2, i.e. between the first link 06 and at least one device of the transmission link 01; during the second period, the first switch 04 opens the path between a1 and a2, i.e. blocks the path between the first link 06 and at least one device of the transmission link 01.

In an alternative embodiment, the switch assembly further comprises a second switch 10, the second switch 10 being arranged on the transmission link 01, the second switch 10 being arranged to: blocking the transmission link 01 during a first period; and/or, in the second period, the transmission link 01 is turned on.

As shown in fig. 6, the second switch 10 is located on the transmission link 01, the first switch 04 has three interfaces, the a1 interface of the first switch 04 is connected with the transmission link 01, the a2 interface is connected with the first link 06, and the a3 interface is connected with the load 08 of the transmission link 01. In the first period, the first switch 04 turns on the path between a1 and a2, that is, the path between the first link 06 and at least one device of the transmission link 01, and the second switch 10 turns off to block the transmission link 01; in the second period, the first switch 04 opens the path between a1 and a2, turns on the path between a1 and a3, i.e., blocks the path between the first link 06 and at least one device of the transmission link 01, and the second switch 10 is closed, turning on the transmission link 01.

In this way, the two switches (the first switch 04 and the second switch 10) can respectively control and conduct the path between the first link 06 and at least one device of the transmitting link 01, and can also block the transmitting link 01, so that the transmitting link 01 is prevented from influencing the clock synchronization.

In a possible embodiment, the switch assembly comprises a third switch 05, the synchronization link 03 comprises a first link 06, and the first link 06 is connected to at least one device in the receiving link 02 via the third switch 05.

The third switch 05 is for: conducting a path between at least one device in the first link 06 and the receiving link 02 during a first period; and/or, in the second period, blocking the path between the first link 06 and at least one device in the receiving link 02.

It can be understood that, since the third switch 05 is connected with the receiving link 02, a high-power signal does not need to be carried, so that the third switch 05 can be a low-power radio frequency switch, and the cost is saved; the first switch 04 and the third switch 05 may be the same type of switch, and the first switch 04 and the second switch 05 may be adjusted according to practical situations, which is not limited in the embodiment of the present application.

As shown in fig. 5, the third switch 05 may be a single pole double throw switch or a double pole double throw switch, and has three interfaces, wherein the b1 interface of the third switch 05 is connected to one end of the receiving link 02, the b2 interface is connected to the other end of the receiving link 02, and the b3 interface is connected to the first link 06.

During the first period, the third switch 05 turns on the path between b2 and b3, i.e. between the first link 06 and at least one device of the receiving link 02; during the second period, the third switch 05 opens the path between b2 and b3, i.e. blocks the path between the first link 06 and at least one device of the receiving link 02.

Optionally, the third switch 05 is further configured to: blocking the receive link 02 during a first period; and/or, in the second period, the reception link 02 is turned on.

Illustratively, during the first period, the third switch 05 opens the path between b1 and b2, i.e., blocks the receive link 02; in the second period, the path between b1 and b2, i.e., the reception link 02 is turned on.

In this way, the switching on of the path between the first link 06 and at least one device of the receiving link 02 and the blocking of the receiving link 02 can be achieved by one switch (third switch 05), and the hardware amount can be further reduced.

Optionally, the switch assembly further includes a fourth switch 11, the fourth switch 11 being disposed on the receiving link 02, the fourth switch 11 being configured to: blocking the receive link 02 during a first period; and/or, in the second period, the reception link 02 is turned on.

As shown in fig. 6, the fourth switch 11 is located on the receiving link 02, the third switch 05 has only two interfaces, the b2 interface of the third switch 05 is connected to the receiving link 02, and the b3 interface is connected to the first link 06.

In the first period, the third switch 05 turns on the path between b2 and b3, that is, the path between the first link 06 and at least one device of the receiving link 02, and the fourth switch 11 turns off to block the receiving link 02; during the second period, the third switch 05 opens the path between b2 and b3, i.e. blocks the path between the first link 06 and at least one device of the receiving link 02, and the fourth switch 11 is closed, turning on the receiving link 02.

In this way, the two switches (the third switch 05 and the fourth switch 11) can respectively control the path between the first link 06 and at least one device of the receiving link 02 and block the receiving link 02, so that the complexity of control logic can be reduced.

In a possible design, the signal processing circuit further comprises a controller 12, as shown in fig. 7, the controller 12 being connected to the transmitting link 01, the receiving link 02 and the synchronization link 03.

The controller 12 is configured to send a first control signal to the switching assembly before or at the beginning of the first time period, the switching assembly being configured to: according to the first control signal, the synchronous link 03 is conducted, and the receiving link 02 is blocked; and/or the controller 12 is configured to send a second control signal to the switching assembly before or at the beginning of the second time period, the switching assembly being configured to: according to the second control signal, the reception link 02 is turned on, and the synchronization link 03 is blocked.

It will be appreciated that the first control signal may comprise one signal which is sent to all switches in the switch assembly, i.e. the one signal may control all switches in the switch assembly; or the first control signal may comprise a plurality of different signals, which are sent to corresponding switches in the switch assembly, i.e. each signal in the plurality of signals controls a corresponding switch in the switch assembly (each signal corresponds to each switch one-to-one).

The second control signal is similar to the first control signal, and the embodiments of the present application will not be repeated.

As illustrated in fig. 6, in an exemplary embodiment, the controller 12 detects all cell service usage of the base station when the base station is first started, or at preset time intervals, and generates a first control signal when the traffic volume is lower than a preset value (i.e., before or at the beginning of a first period of time), and sends the first control signal to the first switch 04 and the third switch 05, where the first control signal may be a low level signal or a high level signal.

The time interval for detecting the service usage conditions of all cells of the base station may be a fixed period, for example, 1 day, 1 hour, etc.; the method can also be set according to actual service demands, for example, the detection time interval is shortened in a low service period (for example, 1-5 a.m.), and the detection time interval is increased in a service peak period; the embodiments of the present application are not limited in this regard.

After receiving the first control signal, the first switch 04 turns on the path between a1 and a2, and turns off the path between a1 and a3, that is, turns on the path between the first link 06 and at least one device of the transmission link 01.

After receiving the first control signal, the third switch 05 turns on the path between b2 and b3, and turns off the path between b1 and b2, that is, turns on the path between the first link 06 and at least one device of the receiving link 02, and blocks the receiving link 02.

In another possible embodiment, the controller 12 detects clock synchronization between the base station and the neighboring base station at preset time intervals, and generates a second control signal if the base station has completed clock synchronization with the neighboring base station (i.e. before or when the second period starts), and sends the second control signal to the first switch and the third switch, where the second control signal may be a high level signal or a low level signal.

The time interval for detecting the clock synchronization condition of the base station and the adjacent base station may be a fixed period, for example, 1 hour; the method can also be determined according to actual service requirements, for example, detection is performed only after the air interface synchronization is started, and the completion condition of the air interface synchronization is detected every 1 minute. The time interval for detecting the clock synchronization condition of the base station and the adjacent base station may be the same or different from the time interval for detecting the service usage condition of all cells of the base station, which is not limited in the embodiment of the present application.

After receiving the second control signal, the first switch 04 blocks the path between a1 and a2, and turns on the path between a1 and a3, that is, blocks the path between the first link 06 and at least one device of the transmission link 01.

After receiving the second control signal, the third switch 05 blocks the path between b2 and b3, and turns on the path between b1 and b2, that is, blocks the path between the first link 06 and at least one device of the receiving link 02, and turns on the receiving link 02.

In particular implementations, the controller 12 may be any device having control capabilities, including, for example, but not limited to, a central processing unit (English: central Processing Unit, abbreviated CPU), an FPGA, and the like. In some embodiments, the controller 12 is located in a baseband module of the base station, such as a baseband processor.

In this embodiment, the controller 12 detects the actual service condition of the base station cell, so that the air interface synchronization function (that is, the synchronization link is turned on) can be determined to be started according to the actual condition, and the flexibility of clock synchronization of the base station can be improved; the controller 12 sends a control signal to switch on the synchronous link 03 and switch off the receiving link 02, so that the operation mode is simple, and the convenience of clock synchronization of the base station can be improved.

In a possible design, the signal processing circuit may further include a processor 13, where the processor 13 is connected to the controller 12, the receiving link 02, the transmitting link 01, and the synchronization link 03, as shown in fig. 8.

The controller 12 is also configured to: transmitting a first control instruction to the processor 13 during a first period; the processor 13 is configured to: according to the first control instruction, setting the signal receiving frequency point of the base station as the frequency point which is the same as the transmitting frequency point of the adjacent base station; and/or, the controller 12 is further configured to: during a second period, a second control instruction is sent to the processor 13, the processor 13 being configured to: and setting a signal receiving frequency point of the base station and a signal transmitting frequency point of the base station based on the working frequency bands of all cells of the base station according to the second control instruction.

For example, during the first period, the processor 13 may further stop sending the transmission signal according to the first control instruction, so that the transmission link 01 stops operating.

In particular implementations, the Processor 13 may be any device having processing, including, for example, but not limited to, a digital signal Processor (English: DIGITAL SIGNAL Processor, abbreviated as DSP), a transceiver, and the like. In some embodiments, the processor 13 is located in a baseband module of the base station, for example, a baseband processor.

It will be appreciated that the controller 12 and the processor 13 may be integrated on the same device (e.g. as different software modules in the same processor) or may be implemented by two different devices (e.g. as two different processors), respectively.

In this embodiment, in the first period (i.e., the synchronization period), the processor 13 sets the signal receiving frequency point of the base station to the transmitting frequency point of the adjacent base station according to the first control instruction sent by the controller 12, that is, the synchronization signal of the adjacent base station can be received, so that the clock of the base station can be adjusted according to the synchronization signal of the adjacent base station; in the second period (i.e. the normal working period of the base station), the processor 13 sets the signal receiving frequency point of the base station and the signal transmitting frequency point of the base station based on the working frequency bands of all cells of the base station according to the second control instruction sent by the controller 12, so as to be convenient for meeting the service demands of the cell users.

In addition, the signal processing circuit provided by the embodiment of the application can also be used for searching information of the neighboring cell base station in the same-frequency FDD mode, such as information of physical cell identification (English: PHYSICAL CELL IDENTIFIER, abbreviated as PCI), carrier frequency point, bandwidth and the like of the neighboring cell base station, and performing signal processing such as demodulation and the like on the received neighboring cell base station through the controller 12 and the processor 13 to realize the neighboring cell self-configuration of the integrated base station.

In a possible embodiment, the device 09 may comprise at least one antenna and at least one filter and the device 07 may comprise the processor 13.

The transmission link 01 may include a controller 12, a device 07, a power amplifier 19 (PA), a circulator 17, and a device 09 connected one by one in this order, and further include a load 08 connected to the circulator 17; a high power radio frequency switch (first switch 04) is arranged between the load 08 and the circulator 17; the at least one device in the synchronous link 03 multiplexed transmission link 01 includes: device 09, circulator 17 and device 07.

The transmission signal is unidirectionally transmitted according to the devices of the transmission links connected one by one in sequence.

The circulator is used for conducting the path from the PA to the device 09 in one direction and blocking the path from the device 09 to the PA; and unidirectional conduction device 09 to the first switch 04 direction path, blocking the first switch 04 to device 09 direction path.

It will be appreciated that in the first period (i.e. the synchronization period), the synchronization signal received by the device 09 is sent to the first switch 04 via the circulator 17 without passing through the PA19; the transmit signal may be sent from the PA19 to the device 09 through the circulator 17 without passing through the first switch 04, i.e. the transmit chain 01 is not affected by the switching of the first switch 04; thus, in the first period, the transmission link 01 may also be conductive. If the transmission link 01 is to be blocked, the output of the transmission signal may be turned off by the processor 13, or by opening the second switch 10 as shown in the above embodiment.

Illustratively, the filters in device 09 may be pulse filters, gaussian filters, etc., as embodiments of the present application are not limited in this regard.

It will be appreciated that the circuit devices in the transmission link 01 are just one possible example, and the circuit devices in the transmission link 01 may be replaced or increased or decreased according to the actual base station circuit requirements, which is not limited by the embodiment of the present application.

In a possible embodiment, the device 09 may comprise at least one antenna and at least one filter and the device 07 may comprise the processor 13.

The receiving link 02 includes a device 09, a receiving amplifier 18 (english: receive Low Noise Amplifier, abbreviated as RX LNA), a sound table filter 20 (english: surface Acoustic Wave, abbreviated as SAW), and a broadband low noise amplifier 22 (broadband LNA), a device 07, and a controller 12, which are connected one by one in this order; a low power radio frequency switch (third switch 05) is provided between the watch filter 20 and the broadband low noise amplifier 22; the at least one device in the synchronous link 03 multiplexed reception link 02 includes: device 09, device 07 and broadband low noise amplifier 22.

The received signal is unidirectionally transmitted according to the devices of the reception links connected one by one in sequence as described above.

Illustratively, the filters in device 09 may be intermediate frequency filters, band pass filters, etc., as embodiments of the present application are not limited in this regard.

It will be appreciated that the circuit devices in the receiving link 02 are just one possible example, and the circuit devices in the receiving link 02 may be replaced or increased or decreased according to the actual base station circuit requirements, which is not limited by the embodiment of the present application.

In a possible embodiment, the device 09 comprises only one antenna and one filter, i.e. the transmitting chain 01 and the receiving chain 02 share the antenna and the filter, which may be a diplexer (filtering the transmitted signal and the received signal separately).

In this way, the receiving link 02 and the transmitting link 01 share the device 09, and the cost can be further reduced.

It will be appreciated that the receiving link 02 and the transmitting link 01 may share one or more antennas and one or more filters, and the above embodiment is merely exemplified by the receiving link 02 and the transmitting link 01 sharing one antenna and one filter, and is not limited thereto.

In another possible embodiment, the device 09 comprises two antennas and two filters, one for each of the transmit chain 01 and the receive chain 02, and the synchronization chain 03 and the receive chain 02 share only the device 07 and the broadband low noise amplifier.

Therefore, the transmitting link 01 and the receiving link 02 are independent in transmitting and receiving signals, the problem that the two links are influenced due to the occurrence of an antenna or a filter can be avoided, and the stability of a circuit can be improved.

It will be appreciated that the transmitting chain 01 and the receiving chain 02 may each include one or more antennas and one or more filters, and the above embodiment is merely exemplified by the transmitting chain 01 and the receiving chain 02 each including one antenna and one filter, which is not limited thereto.

It will be appreciated that the above embodiments may be implemented separately or in combination with each other. For a better understanding of the above scheme, several detailed examples are set forth below.

Exemplary, as shown in fig. 9, the embodiment of the present application provides a specific example in a signal processing circuit:

The transmission link 01 includes a service antenna 14, a TX filter 25 in a duplexer 15, a circulator 17, a power amplifier 19 (PA), and a load 08 connected to the circulator 17, which are connected one by one in this order; a high power radio frequency switch (first switch 04) is arranged between the load 08 and the circulator 17; the at least one device in the synchronous link 03 multiplexed transmission link 01 includes: an antenna 14, a TX filter 25 and a circulator 17. The antenna 14 is used for sending a transmission signal, the TX filter 25 is used for filtering the transmission signal, the circulator 17 is used for conducting a path between the power amplifier 19 and the duplexer 15 and a path between the duplexer 15 and the high-power radio frequency switch 04, the power amplifier 19 is used for amplifying the power of the transmission signal, and the load 08 is used for converting electric energy into other needed energy.

The reception link 02 includes a service antenna 14, an RX filter 26 in a duplexer 15, a reception amplifier 18, a watch filter 20, and a broadband low noise amplifier 22 (broadband LNA) connected one by one in this order; a low power radio frequency switch (third switch 05) is provided between the watch filter 20 and the broadband low noise amplifier 22; the at least one device in the synchronous link 03 multiplexed reception link 02 includes: an antenna 14, an RX filter 26, and a wideband low noise amplifier 22.

The antenna 14 is used for receiving signals of all cells of the base station, the RX filter 26 is used for filtering the received signals, the receiving amplifier 18 is used for amplifying the received signals, the sound table filter 20 is used for filtering the signal frequencies, and the broadband low noise amplifier 22 is used for amplifying the signals.

The receive chain 02 and the transmit chain 01 share a service antenna 14 (i.e., both the receive signal and the transmit signal are implemented by the service antenna 14) and a diplexer 15.

It can be understood that the duplexer 15 is a different frequency duplex radio station, and is configured to couple weak received signals, and feed the transmission signals with larger transmission power to the service antenna 14, so as to ensure that both receiving and transmitting can work simultaneously without mutual influence; it is made up of two sets of stop band filters of different frequencies (i.e., TX filter 25 and RX filter 26, and the frequency ranges of the signals passing through TX filter 25 and RX filter 26 are different).

In the first period (i.e., the synchronization period), the base station receives the transmission signal (i.e., the synchronization signal) of the base station having the same transmission frequency band as the base station, and the synchronization signal has the same frequency band as the transmission signal of the base station, i.e., the frequency band of the signal received by the TX filter 25, so that the received synchronization signal is received by the TX filter 25 and is subjected to filtering.

In the second period (i.e., the normal operation period of the base station), the base station receives the traffic signal of the cell, and the frequency band of the traffic signal is the same as the frequency band of the signal received by the RX filter 26, so that the traffic signal is received by the RX filter 26 and subjected to filtering.

The synchronization link 03 includes a first link 06, and the first link 06 includes a low noise amplifier 21 for amplifying a synchronization signal, for example, an air_sync LNA shown in fig. 9.

The processor 13 is a Transceiver transmitter, and is configured to set a signal transmitting frequency point and a signal receiving frequency point of the base station, and send control signals 05 to the high-power radio frequency switch 04 and the low-power radio frequency switch.

The controller 12 includes a control unit 12a and an FPGA12b, the control unit 12a may be configured to generate control instructions (indicating to generate control signals, set signaling frequency points and signal receiving frequency points of the base station), and the FPGA12b is configured to generate control signals according to the control instructions, and send the control signals and the control instructions to the processor 13; the control unit 12a and the FPGA12b may be integrated on the same device, or may be disposed on two different devices, where a communication connection exists between the two devices; the control unit may be software or hardware, such as a central processing unit.

The devices in fig. 9 are merely one possible example, and the devices of the actual circuit may be replaced or increased or decreased, which is not a limitation of the embodiments of the present application.

Based on the exemplary diagram of the signal processing circuit shown in fig. 9, two possible examples of the signal processing circuit in practical applications are described below.

Example 1: when the base station opens a service for the first time, or when the controller 12 detects that the service requirements of all cell users of the base station are smaller than a preset value, in the controller 12, the control unit 12a generates a first control instruction, sends the first control instruction to the Transceiver transmitter 13, the FPGA12b generates a first control signal (for example, a high level signal), and sends the first control signal to the Transceiver13.

The transmitter 13 receives the first control instruction and the first control signal, sets the signal receiving frequency point of the base station to be the same frequency point as the transmitting frequency point of the adjacent base station according to the first control instruction, and sends the first control signal to the high-power radio frequency switch (the first switch 04) and the low-power radio frequency switch (the third switch 05).

Optionally, the transmitter 13 may further stop sending the transmission signal according to the first control instruction, so that the transmission link 01 stops working.

The high-power rf switch 04 switches to the air_sync interface of the high-power rf switch 04 according to the first control signal, and disconnects the TX interface (interface between the high-power rf switch 04 and the load), i.e. turns on the path between the first link 06 and the circulator 17.

The low-power radio frequency switch 05 is switched to the air_sync interface of the low-power radio frequency switch 05 according to the first control signal, and the RX interface is disconnected, namely the path between the first link 06 and the broadband low-noise amplifier 22 is conducted, and the path between the sound table filter 20 and the broadband low-noise amplifier 22 is disconnected.

The service antenna 14 receives the synchronization signal of the adjacent base station, sends the synchronization signal to the duplexer 15 for filtering processing, then sends the synchronization signal to the air_sync LNA21 through the high-power radio frequency switch 04 by the circulator 17, and sends the amplified synchronization signal to the broadband LNA22 for amplifying processing through the low-power radio frequency switch 05, the broadband LNA22 sends the amplified synchronization signal to the Transceiver13, the Transceiver13 converts the synchronization signal into a digital signal and sends the digital signal to the FPGA12b, the FPGA12b processes the digital signal (including searching the synchronization signal, demodulating a physical broadcast channel, obtaining a field indication, a system frame number and the like), and outputs a clock synchronization signal of 1pps as a clock source and sends the clock synchronization signal to the clock phase-locked loop 23; the clock phase-locked loop 23 performs phase discrimination based on the local oven controlled crystal oscillator 24 (english: oven Controlled Crystal Oscillator, abbreviated OCXO) clock and a clock source of 1 pps; the base station adjusts the local clock according to the phase discrimination result of the clock phase-locked loop 23 to realize the synchronization with the clock source of 1pps (i.e. the synchronization with the adjacent base station), and records what frequency point the clock synchronization searches for the synchronization signal, so that the signal receiving frequency point is convenient to set in the next synchronization.

In example 2, when the controller 12 detects that the air interface synchronization is finished (i.e., the local clock is synchronized with the clock of the neighboring base station), the control unit 12a generates a second control instruction in the controller, sends the second control instruction to the transmitter 13, and the FPGA12b generates a second control signal (e.g., a low level signal) and sends the second control signal to the transmitter 13.

The Transceiver13 receives the second control instruction and the second control signal, sets a signal receiving frequency point of the base station and a signal transmitting frequency point of the base station based on the working frequency bands of all cells of the base station according to the second control instruction (for example, sets the signal receiving frequency point and the signal transmitting frequency point as frequency points where the cells of the base station work), and sends the second control signal to the high-power radio frequency switch 04 and the low-power radio frequency switch 05.

The high-power radio frequency switch 04 is switched to a TX interface according to a second control signal, and an air_sync interface of the high-power radio frequency switch 04 is disconnected, namely, a passage between the circulator 17 and the load 08 is conducted, and the passage between the circulator 17 and the air_sync LNA21 is blocked.

The low-power radio frequency switch 05 is switched to an RX interface according to the second control signal, and the air_sync interface of the low-power radio frequency switch 05 is disconnected, namely, the channel between the sound table filter 20 and the broadband LNA22 is conducted, and the channel between the air_sync LNA21 and the broadband LNA22 is blocked.

The clock of the base station enters a hold mode (according to the clock hold algorithm of the base station, the clock of the base station can be maintained within a clock range required for the operation of the cell service for 24 hours), the base station enters a normal operation mode, as shown by a dotted line in fig. 10, and the base station simultaneously receives and transmits signals according to a route shown by the dotted line.

The above are only possible embodiments and are not limited thereto in practice.

Based on the same technical concept, the embodiment of the present application also provides an electronic device, which includes the signal processing circuit in any one of the above embodiments.

Based on the same technical concept, the embodiment of the present application further provides a control method, as shown in fig. 11, where the method includes:

s101, before or at the beginning of a first period of time, sending a first control signal to a switch assembly; so that the switching assembly turns on the synchronization link 03 and blocks the receiving link 02 according to the first control signal.

And/or, S102, before or at the beginning of the second period, sending a second control signal to the switch assembly; so that the switching assembly turns on the receiving link 02 and blocks the synchronization link 03 according to the second control signal.

In the method, the switch component is controlled by the control signal to realize the switching of the synchronous link 03 and the receiving link 02, so that the synchronous signal only passes through the synchronous link 03, and the convenience of the synchronous control of the base station clock can be improved.

Optionally, the method further comprises: in the first period, a first control instruction is sent to the processor 13, so that the processor 13 sets the signal receiving frequency point of the base station to be the same frequency point as the transmitting frequency point of the adjacent base station according to the first control instruction; and/or, in the second period, sending a second control instruction to the processor 13, so that the processor 13 sets the signal receiving frequency point of the base station and the signal transmitting frequency point of the base station based on the working frequency bands of all cells of the base station according to the second control instruction.

In the method, the processor 13 adjusts the signal receiving frequency point and the signal transmitting frequency point of the base station through the control instruction, so that the switching between the synchronous mode (receiving synchronous signals) and the normal working mode (receiving and transmitting cell service signals) of the base station is realized, and the convenience of clock synchronous control of the base station can be improved.

The specific implementation of the method may refer to the relevant content of the embodiment of the apparatus and will not be described in detail.

Based on the same technical concept, the embodiments of the present application also provide a computer-readable storage medium, where the computer-readable storage medium is used to store instructions that, when executed, cause a computer to perform the method steps performed by any one or more modules in the above method embodiments.

Based on the same technical idea, an embodiment of the present application also provides a computer program product, comprising computer program code, which when run on a computer, causes the computer to perform the method steps performed by the apparatus of any of the above-mentioned method embodiments.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims (15)

1. A signal processing circuit for use in a base station, the signal processing circuit comprising: a transmit link, a receive link, a synchronization link, and a switch assembly; the transmitting link is used for transmitting downlink signals, the receiving link is used for receiving uplink signals, and the synchronous link is used for receiving synchronous signals from adjacent base stations;

wherein at least one device in the synchronization link multiplexes at least one device in the transmit link and/or at least one device in the receive link;

The switch assembly is used for: in a first period, the synchronous link is conducted, and the receiving link is blocked; and/or, in a second period, switching on the receiving link and blocking the synchronous link.

2. The signal processing circuit of claim 1, wherein the signal processing circuit further comprises: a controller; the controller is connected with the transmitting link, the receiving link and the synchronous link;

The controller is used for: transmitting a first control signal to the switch assembly before or at the beginning of the first period of time; the switch assembly is used for: according to the first control signal, the synchronous link is conducted to block the receiving link; and/or the number of the groups of groups,

The controller is used for: transmitting a second control signal to the switch assembly before or at the beginning of the second period; the switch assembly is used for: and according to the second control signal, the receiving link is conducted to block the synchronous link.

3. The signal processing circuit of claim 1 or 2, wherein the to switch assembly comprises a first switch, the synchronization link comprising a first link, the first link being connected with at least one device in the transmit chain through the first switch;

The first switch is used for: conducting a path between the first link and at least one device in the transmit link during the first period; and/or blocking a path between the first link and at least one device in the transmit link during the second period.

4. The signal processing circuit of claim 3, wherein the switch assembly further comprises a second switch disposed on the transmit link, the second switch to: blocking the transmit chain during the first period; and/or, in the second time period, switching on the transmitting link.

5. The signal processing circuit of claim 3, wherein the transmit chain comprises an antenna, a filter, a circulator, a power amplifier, and a load connected to the circulator, connected one by one in that order;

The first switch is arranged between the load and the circulator;

at least one device in the transmit chain of the synchronous link multiplex comprises: the antenna, the filter, the circulator.

6. The signal processing circuit of claim 1 or 2, wherein the switch assembly comprises a third switch, the synchronization link comprising a first link, the first link being connected to at least one device in the receive link through the third switch;

The third switch is used for: conducting a path between at least one device in the first link and the receive link during the first period; and/or blocking a path between at least one device in the first link and the receiving link during the second period.

7. The signal processing circuit of claim 6, wherein the third switch is further to: blocking the receive link during the first period of time; and/or, in the second period, switching on the receiving link.

8. The signal processing circuit of claim 6, wherein the switch assembly further comprises a fourth switch disposed on the receive link, the fourth switch to: blocking the receive link during the first period of time; and/or, in the second period, switching on the receiving link.

9. The signal processing circuit of claim 6, wherein the receive chain comprises an antenna, a filter, a receive amplifier, a watch filter, and a wideband low noise amplifier connected one to the other in that order;

The third switch is arranged between the sound surface filter and the broadband low-noise amplifier;

at least one device in the receive chain of the synchronous link multiplex comprises: the antenna, the filter, a broadband low noise amplifier.

10. The signal processing circuit of claim 9, wherein the receive chain and the transmit chain share the antenna and the filter.

11. The signal processing circuit of claim 2, further comprising a processor coupled to the controller, the transmit link, the receive link, the synchronization link;

the controller is further configured to: transmitting a first control instruction to the processor in the first period; the processor is configured to: according to the first control instruction, setting the signal receiving frequency point of the base station as the frequency point which is the same as the transmitting frequency point of the adjacent base station; and/or the number of the groups of groups,

The controller is further configured to: transmitting a second control instruction to the processor within the second period of time; the processor is configured to set, according to the second control instruction, a signal receiving frequency point of the base station and a signal transmitting frequency point of the base station based on working frequency bands of all cells of the base station.

12. A base station comprising a signal processing circuit as claimed in any one of claims 1 to 11.

13. A control method, applied to a controller, comprising:

before or when a first period starts, sending a first control signal to a switch assembly, so that the switch assembly conducts a synchronous link according to the first control signal to block a receiving link; and/or the number of the groups of groups,

And before or at the beginning of a second period, sending a second control signal to the switch assembly, so that the switch assembly conducts the receiving link according to the second control signal to block the synchronous link.

14. The method of claim 13, wherein the method further comprises:

In the first period, a first control instruction is sent to a processor, so that the processor sets a signal receiving frequency point of a base station to be the same frequency point as a transmitting frequency point of an adjacent base station according to the first control instruction; and/or in a second period, sending a second control instruction to the processor, so that the processor sets a signal receiving frequency point of the base station and a signal transmitting frequency point of the base station based on the working frequency bands of all cells of the base station according to the second control instruction.

15. A computer readable storage medium for storing instructions that, when executed, cause the method of any of claims 13-14 to be implemented.