CN117914142A - Dual-output rectifying voltage-stabilizing circuit - Google Patents
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Abstract
The invention provides a double-output rectifying voltage-stabilizing circuit, which relates to the technical field of wireless charging and comprises an inductor, a first capacitor, a second capacitor, a third capacitor, a first field effect transistor, a second field effect transistor, a first switch, a second switch, a first comparator, a second comparator, a first hysteresis comparator, a second hysteresis comparator, a self-starting circuit, a clock generator, a first voltage-dividing circuit, a second voltage-dividing circuit, a reference voltage source, a linear voltage stabilizer and a digital controller. The double-output rectifying and voltage stabilizing circuit optimally designs the rectifying and voltage stabilizing circuit in the traditional wireless charging technology based on a voltage doubling topological structure, adopts two field effect transistors, is combined with a digital control circuit, realizes single-stage voltage doubling double-output rectifying and voltage stabilizing, has higher voltage conversion ratio, provides larger output power, and can realize two paths of different output voltages.
Description
Technical Field
The invention relates to the technical field of wireless charging, in particular to a double-output rectifying and voltage stabilizing circuit.
Background
With the development of implantable medical electronics, implantable medical devices (Implantable MEDICAL DEVICE, IMD) are widely used clinically. In practical clinical application, IMD requires long-term stable power, and the use of disposable batteries is limited by battery capacity and life, requiring periodic surgical replacement of the battery, which can cause great pain and even life-threatening to the patient. The development of wireless charging technology opens up a new channel for the energy supply of the IMD, and in order to further improve the charging efficiency and the effective distance of wireless charging, a wireless charging mode (MAGNETICALLY-Coupled Resonant Wireless Power Transfer, MCR-WPT) of magnetic coupling resonance is widely applied to the IMD. The MCR-WPT establishes an energy transmission channel by using the principle of coupling resonance between coils, and efficiently transfers energy from a transmitting end to a receiving end.
In a wireless charging system for an implantable device, it is generally desirable that the energy receiving circuit be small and capable of providing two or more output voltages. Under the condition that the system needs two paths of output, the energy receiving end can adopt a scheme of a rectifier two-stage cascade single-inductor multi-output power converter generally, and can generate two paths of different direct-current voltage output. However, the single-inductor multi-output power converter introduces more off-chip components, the circuit cost is high, and the system efficiency is lower due to the two-stage cascading scheme. In order to simplify the structure of the energy receiving end circuit, a rectifying and voltage stabilizing circuit structure based on a full-bridge rectifier topological structure is generally adopted at present. However, this configuration can achieve a voltage conversion ratio of less than 1, and can provide lower output power when a weak coupling condition occurs between the energy emitting end and the energy receiving end due to misalignment, a long distance, or a barrier by other objects. In addition, due to the limitation of the topology structure of the full-bridge rectifier, the circuit generally uses more power field effect transistors, and the two output voltages are relatively similar.
Disclosure of Invention
The invention provides a double-output rectifying voltage-stabilizing circuit, which can overcome the technical problems in the prior art, has higher voltage conversion ratio, provides larger output power and can realize two paths of different output voltages.
In order to achieve the above purpose, the technical scheme adopted by the invention is as follows: the double-output rectifying and voltage stabilizing circuit is characterized by comprising an inductor, a first capacitor, a second capacitor, a third capacitor, a first field effect transistor, a second field effect transistor, a first switch, a second switch, a first comparator, a second comparator, a first hysteresis comparator, a second hysteresis comparator, a self-starting circuit, a clock generator, a first voltage dividing circuit, a second voltage dividing circuit, a reference voltage source, a linear voltage stabilizer and a digital controller.
After the inductor is connected with the first capacitor in parallel, one end of the inductor is an alternating current signal input end, the source electrode of the first field effect transistor and the source electrode of the second field effect transistor are connected, and the other end of the inductor is connected to a second direct current voltage output end; the drain electrode of the first field effect transistor is connected to the first direct-current voltage output end, and the drain electrode of the second field effect transistor is grounded; one end of the second capacitor is connected to the first direct-current voltage output end, and the other end of the second capacitor is connected to the second direct-current voltage output end; one end of the third capacitor is connected to the second direct-current voltage output end, and the other end of the third capacitor is grounded; the first switch is connected in parallel between the gate and the drain of the field first effect transistor, and the second switch is connected in parallel between the gate and the drain of the second field effect transistor; the non-inverting input end of the first comparator is connected to the drain electrode of the first field effect transistor, the inverting input end of the first comparator is connected to the source electrode of the first field effect transistor, and the output end of the first comparator is connected to the grid electrode of the first field effect transistor; the non-inverting input end of the second comparator is grounded, the inverting input end of the second comparator is connected to the source electrode of the second field effect transistor, and the output end of the second comparator is connected to the grid electrode of the second field effect transistor.
The input end of the self-starting circuit is connected to the first direct-current voltage output end, and the output end of the self-starting circuit is connected to the input end of the digital controller; the input end of the first voltage dividing circuit is connected to the first direct-current voltage output end, and the output end of the first voltage dividing circuit is connected to the non-inverting input end of the first hysteresis comparator; the input end of the second voltage dividing circuit is connected to the second direct-current voltage output end, and the output end of the second voltage dividing circuit is connected to the non-inverting input end of the second hysteresis comparator; the input end of the reference voltage source is connected to the first direct-current voltage output end, and the output end of the reference voltage source is connected to the input end of the linear voltage stabilizer; the output end of the linear voltage stabilizer is respectively connected to the inverting input end of the first hysteresis comparator and the inverting input end of the second hysteresis comparator; the output end of the first hysteresis comparator and the output end of the second hysteresis comparator are both connected to the input end of the digital controller; the input end of the clock generator is connected to the input end of the alternating current signal, and the output end of the clock generator is connected to the input end of the digital controller; four output ends of the digital controller are respectively connected to the enabling end of the first switch, the enabling end of the second switch, the enabling end of the first comparator and the enabling end of the second comparator.
Further, the first field effect transistor is a P-channel power field effect transistor, and the second field effect transistor is an N-channel power field effect transistor.
Optionally, the dual-output rectifying and voltage stabilizing circuit further comprises a third switch, wherein one end of the third switch is connected with the alternating current signal input end, and the other end of the third switch is connected to the second direct current voltage output end.
Further, the first switch and the second switch are field effect transistors, and the third switch is a field effect transistor or a CMOS transmission gate.
The dual-output rectifying and voltage stabilizing circuit provided by the embodiment of the invention optimally designs the rectifying and voltage stabilizing circuit in the traditional wireless charging technology based on the voltage doubling topological structure, adopts two field effect transistors and is combined with a digital control circuit, so that single-stage voltage doubling dual-output rectifying and voltage stabilizing is realized, the voltage doubling dual-output rectifying and voltage stabilizing circuit has higher voltage conversion ratio, larger output power is provided, and two paths of different output voltages can be realized.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it will be obvious that the drawings in the following description are some embodiments of the present invention, and that other drawings can be obtained according to these drawings without inventive effort to a person skilled in the art.
Fig. 1 is a schematic diagram of a dual-output rectifying and voltage stabilizing circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of the dual output rectifying and voltage stabilizing circuit shown in FIG. 1, wherein both outputs are charged;
Fig. 3 is a schematic diagram of the dual-output rectifying and voltage stabilizing circuit shown in fig. 1, in which only the first dc voltage output terminal is charged;
fig. 4 is a schematic diagram of the dual-output rectifying and voltage stabilizing circuit shown in fig. 1, in which only the second dc voltage output terminal is charged;
FIG. 5 is a schematic diagram of the dual output rectifying and voltage stabilizing circuit shown in FIG. 1, wherein neither output is charged;
FIG. 6 is a schematic diagram of another dual-output rectifying and voltage stabilizing circuit according to an embodiment of the present invention;
fig. 7 is a schematic diagram of the principle that two outputs of the dual-output rectifying and voltage stabilizing circuit shown in fig. 6 are not charged.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Fig. 1 is a schematic diagram of a dual-output rectifying and voltage stabilizing circuit according to an embodiment of the present invention. As shown in fig. 1, the circuit includes an inductance L, a first capacitor C 1, a second capacitor C 2, a third capacitor C 3, a first field effect transistor M 1, a second field effect transistor M 2, a first switch S 1, a second switch S 2, a first comparator CMP 1, a second comparator CMP 2, a first hysteresis comparator CMP 3, a second hysteresis comparator CMP 4, a self-starting circuit, a clock generator, a first voltage divider circuit, a second voltage divider circuit, a reference voltage source, a linear regulator LDO, and a digital controller.
After the inductor L is connected in parallel with the first capacitor C 1, one end is an alternating current signal input end V AC, the source electrode of the first field effect transistor M 1 and the source electrode of the second field effect transistor M 2 are connected, and the other end is connected to a second direct current voltage output end V DC2; the drain electrode of the first field effect transistor M 1 is connected to the first direct-current voltage output end V DC1, and the drain electrode of the second field effect transistor M 2 is grounded; one end of the second capacitor C 2 is connected to the first direct-current voltage output end V DC1, and the other end of the second capacitor C 2 is connected to the second direct-current voltage output end V DC2; one end of the third capacitor C 3 is connected to the second direct-current voltage output end V DC2, and the other end of the third capacitor C 3 is grounded; the first switch S 1 is connected in parallel between the gate and the drain of the first field effect transistor M 1, and the second switch S 2 is connected in parallel between the gate and the drain of the second field effect transistor M 2; the non-inverting input end of the first comparator CMP 1 is connected to the drain electrode of the first field effect transistor M 1, the inverting input end is connected to the source electrode of the first field effect transistor M 1, and the output end is connected to the grid electrode of the first field effect transistor M 1; the non-inverting input terminal of the second comparator CMP 2 is grounded, the inverting input terminal is connected to the source of the second field effect transistor M 2, and the output terminal is connected to the gate of the second field effect transistor M 2.
The input end of the self-starting circuit is connected to the first direct-current voltage output end V DC1, and the output end is connected to the input end of the digital controller; the input end of the first voltage dividing circuit is connected to the first direct-current voltage output end V DC1, and the output end of the first voltage dividing circuit is connected to the non-inverting input end of the first hysteresis comparator CMP 3; the input end of the second voltage dividing circuit is connected to the second direct-current voltage output end V DC2, and the output end of the second voltage dividing circuit is connected to the non-inverting input end of the second hysteresis comparator CMP 4; the input end of the reference voltage source is connected to the first direct-current voltage output end V DC1, and the output end is connected to the input end of the linear voltage regulator LDO; the output end of the linear voltage regulator LDO is respectively connected to the inverting input end of the first hysteresis comparator CMP 3 and the inverting input end of the second hysteresis comparator CMP 4; the output end of the first hysteresis comparator CMP 3 and the output end of the second hysteresis comparator CMP 4 are both connected to the input end of the digital controller; the input end of the clock generator is connected to the alternating current signal input end V AC, and the output end of the clock generator is connected to the input end of the digital controller; the four output terminals of the digital controller are respectively connected to the enable terminal of the first switch S 1, the enable terminal of the second switch S 2, the enable terminal of the first comparator CMP 1 and the enable terminal of the second comparator CMP 2.
The whole circuit comprises two parts, wherein one part is a power stage circuit consisting of an inductor L, a first capacitor C 1, a second capacitor C 2, a third capacitor C 3, a first field effect transistor M 1, a second field effect transistor M 2, a first comparator CMP 1 and a second comparator CMP 2; the other part is a control stage circuit consisting of a first switch S 1, a second switch S 2, a first hysteresis comparator CMP 3, a second hysteresis comparator CMP 4, a self-starting circuit, a clock generator, a first voltage dividing circuit, a second voltage dividing circuit, a reference voltage source, a linear voltage stabilizer LDO and a digital controller. The control stage circuit is powered by the second dc voltage output terminal V DC2 with lower voltage, so that the overall power consumption of the control circuit can be reduced, and the bias currents of the first comparator CMP 1, the second comparator CMP 2, the first hysteresis comparator CMP 3 and the second hysteresis comparator CMP 4 are all provided by the reference voltage source module. The input signal of the reference voltage source is a first direct current voltage output end V DC1, the reference voltage source outputs a voltage signal, and the voltage is stabilized by the linear voltage stabilizer LDO to form a reference voltage V ref, and the reference voltage V ref can quickly reach a stable state.
The clock generator generates a synchronous clock signal CLK from the input ac signal at the ac signal input V AC to the digital controller, so that the switching of the operation mode of the circuit occurs at the time point V AC =0. The operation modes include 4 operation modes described below: both dc voltage outputs are charged, only the first dc voltage output V DC1 is charged, only the second dc voltage output V DC2 is charged, and both dc voltage outputs are not charged.
When an ac signal is introduced into the ac signal input terminal V AC, the whole circuit just starts to operate, the output voltages of the first dc voltage output terminal V DC1 and the second dc voltage output terminal V DC2 are smaller, and the first comparator CMP 1, the second comparator CMP 2 and part of the modules of the control stage circuit cannot operate normally. The self-starting circuit can detect the output voltage of the first direct-current voltage output end V DC1, when detecting that the output voltage signal of the first direct-current voltage output end V DC1 is smaller, the digital controller can send an enabling signal to the first switch S 1 and the second switch S 2 to enable the first switch S 1 and the second switch S 2 to be closed, so that the first field-effect transistor M 1 and the second field-effect transistor M 2 can work in a passive mode, namely the first field-effect transistor M 1 and the second field-effect transistor M 2 are in a diode connection mode, and the second capacitor C 2 is continuously charged until the output voltage signal of the first direct-current voltage output end V DC1 reaches a certain preset voltage value.
When the output voltage signal of the first dc voltage output terminal V DC1 reaches the preset voltage value, all the modules in the first comparator CMP 1, the second comparator CMP 2 and the control stage circuit can work normally, and the digital controller sends an enable signal to the first switch S 1 and the second switch S 2 to disconnect them. At this time, the first field effect transistor M 1 and the second field effect transistor M 2 operate in an active mode, which are controlled by the first comparator CMP 1 and the second comparator CMP 2, respectively.
In practical application, output voltage may be unstable due to various factors such as large fluctuation of input power supply, quality problem of charging equipment, overload problem and the like. In the embodiment of the invention, the upper limit and the lower limit of comparison are set through the first hysteresis comparator CMP 3 and the second hysteresis comparator CMP 4, and the first feedback voltage V fb1 output by the first voltage dividing circuit and the second feedback voltage V fb2 output by the second voltage dividing circuit are respectively judged in real time, so that the magnitudes of the first feedback voltage V fb2 and the reference voltage V ref provided by the linear voltage stabilizer LDO are obtained, and more stable output voltage is obtained.
Specifically, when the first feedback voltage V fb1 is lower than the lower limit voltage of the first hysteresis comparator CMP 3 and the second feedback voltage V fb2 is lower than the lower limit voltage of the second hysteresis comparator CMP 4, the first enable signal EN 1 and the second enable signal EN 2 output by the first hysteresis comparator CMP 3 and the second hysteresis comparator CMP 4 to the digital controller are both low-level signals, and then the digital controller sends the enable signals to the first comparator CMP 1 and the second comparator CMP 2 to enable the first comparator CMP 1 and the second comparator CMP 2 to operate normally, and the first dc voltage output terminal V DC1 and the second dc voltage output terminal V DC2 of the rectifying voltage regulator are both in the charging operation mode. Fig. 2 is a schematic diagram of the dual-output rectifying and voltage stabilizing circuit shown in fig. 1, in which the first dc voltage output terminal V DC1 and the second dc voltage output terminal V DC2 are both in a charging operation mode. As shown in fig. 2, when the input ac signal V AC is in the positive half-cycle, if the input ac voltage V AC is greater than the first output voltage V DC1, the first field effect transistor M 1 is turned on and the circuit charges the second capacitor C 2 through the upper half-loop. When the input ac signal at the ac signal input terminal V AC is in the negative half-cycle, if the input ac voltage V AC is less than 0, the second field effect transistor M 2 is turned on, and the circuit charges the third capacitor C 3 through the lower half-loop. The first output voltage V DC1 and the second output voltage V DC2 both perform the charging operation during the whole period. In this way, when the circuit reaches a steady state, the voltage amplitude of the output voltage of the first dc voltage output terminal V DC1 is theoretically twice the input ac signal amplitude of the ac signal input terminal V AC, and the voltage amplitude of the output voltage of the second dc voltage output terminal V DC2 is theoretically the same as the input ac signal amplitude of the ac signal input terminal V AC. Therefore, the circuit has higher voltage conversion ratio, provides larger output power and can realize two paths of different output voltages.
When the first feedback voltage V fb1 is lower than the lower limit voltage of the first hysteresis comparator CMP 3 and the second feedback voltage V fb2 is higher than the upper limit voltage of the second hysteresis comparator CMP 4, the first enable signal EN 1 output by the first hysteresis comparator CMP 3 to the digital controller is a low level signal, the second enable signal EN 2 output by the second hysteresis comparator CMP 4 to the digital controller is a high level signal, the digital controller sends enable signals to the first comparator CMP 1 and the second comparator CMP 2 to enable the first comparator CMP 1 to work normally, and the output of the second comparator CMP 2 controls the second field effect transistor M 2 to be in a cut-off state. Fig. 3 is a schematic diagram of the dual-output rectifying and voltage stabilizing circuit shown in fig. 1, in which only the first dc voltage output terminal V DC1 is in the charging mode. As shown in fig. 3, when the input ac signal at the ac signal input terminal V AC is in the positive half-cycle, if the input ac voltage V AC is greater than the first output voltage V DC1, the first field effect transistor M 1 is turned on, and the circuit charges the second capacitor C 2.
When the first feedback voltage V fb1 is higher than the upper limit voltage of the first hysteresis comparator CMP 3 and the second feedback voltage V fb2 is lower than the lower limit voltage of the second hysteresis comparator CMP 4, the first enable signal EN 1 output by the first hysteresis comparator CMP 3 to the digital controller is a high level signal, the second enable signal EN 2 output by the second hysteresis comparator CMP 4 to the digital controller is a low level signal, and the digital controller sends enable signals to the first comparator CMP 1 and the second comparator CMP 2, so that the output of the first comparator CMP 1 controls the first field effect transistor M 1 to be in a cut-off state, and the second comparator CMP 2 works normally. Fig. 4 is a schematic diagram of the dual-output rectifying and voltage stabilizing circuit shown in fig. 1, in which only the second dc voltage output terminal V DC2 is in the charging mode. As shown in fig. 4, when the input ac signal at the ac signal input terminal V AC is in the negative half-cycle, if the input ac voltage V AC is less than the output voltage 0, the second field effect transistor M 2 is turned on, and the circuit charges the third capacitor C 3.
When the first feedback voltage V fb1 is higher than the upper limit voltage of the first hysteresis comparator CMP 3 and the second feedback voltage V fb2 is higher than the upper limit voltage of the second hysteresis comparator CMP 4, the first enable signal EN 1 and the second enable signal EN 2 output by the first hysteresis comparator CMP 3 and the second hysteresis comparator CMP 4 to the digital controller are both high-level signals, and then the digital controller sends the enable signals to the first comparator CMP 1 and the second comparator CMP 2 to enable the output of the first comparator CMP 1 and the second comparator CMP 2 to respectively control the first field effect transistor M 1 and the second field effect transistor M 2 to be in the off state, and the first direct current voltage output terminal V DC1 and the second direct current voltage output terminal V DC2 of the rectifying voltage stabilizer are both in the non-charging operation mode. Fig. 5 is a schematic diagram of the dual-output rectifying and voltage stabilizing circuit shown in fig. 1, in which the first dc voltage output terminal V DC1 and the second dc voltage output terminal V DC2 are both in a non-charging operation mode. At this time, as shown in fig. 5, the circuit does not charge the first dc voltage output terminal V DC1 and the second dc voltage output terminal V DC2, so as to perform overvoltage protection and reduce damage to the device components.
The first hysteresis comparator CMP 3 and the second hysteresis comparator CMP 4 can control the upper and lower limits of the comparison between the first feedback voltage V fb1, the second feedback voltage V fb2 and the reference voltage V ref, so as to form a hysteresis window, and further make the output voltage more stable.
The dual-output rectifying and voltage stabilizing circuit provided by the embodiment of the invention optimally designs the rectifying and voltage stabilizing circuit in the traditional wireless charging technology based on the topological structure of the voltage doubling rectifying and voltage stabilizing circuit, adopts two field effect transistors and is combined with a digital control circuit, so that single-stage voltage doubling dual-output rectifying and voltage stabilizing is realized, the voltage doubling rectifying and voltage stabilizing circuit has higher voltage conversion ratio, larger output power is provided, and two paths of different output voltages can be realized.
Preferably, the first field effect transistor M 1 is a P-channel power field effect transistor, and the second field effect transistor M 2 is an N-channel power field effect transistor. The power field effect transistor has higher voltage resistance and current passing capability than the common field effect transistor, thereby improving the working performance of the circuit.
Fig. 6 is a schematic diagram of another dual-output rectifying and voltage stabilizing circuit according to an embodiment of the present invention. As shown in fig. 6, the dual-output rectifying and voltage stabilizing circuit is added with a third switch S 3 on the basis of the circuit shown in fig. 1, wherein one end of the third switch S 3 is connected with an ac signal input end V AC, and the other end is connected with a second dc voltage output end V DC2.
The third switch S 3 is controlled to be turned on and off by the digital controller, and the digital controller controls the third switch S 3 to be always turned on during the period when the first feedback voltage V fb1 or the second feedback voltage V fb2 is lower than the base reference voltage V ref, that is, during the period when the circuit just starts to operate and the circuit is in the charging operation mode, so that the charging operation of the circuit is not affected. The charging process of the circuit is described above and will not be described in detail herein.
Fig. 7 is a schematic diagram of the dual-output rectifying and voltage stabilizing circuit shown in fig. 6, in which the first dc voltage output terminal V DC1 and the second dc voltage output terminal V DC2 are both in a non-charging operation mode. As shown in fig. 7, when the first feedback voltage V fb1 and the second feedback voltage V fb2 are both higher than the base reference voltage V ref, the digital controller sends an enable signal to the first comparator CMP 1 and the second comparator CMP 2 to turn off the first field effect transistor M 1 and the second field effect transistor M 2, and also sends an enable signal to the third switch S 3 to turn on the first and second field effect transistors M 1 and M 2, so that the receiving terminal is in a short-circuit state. According to the reflection load theory, the receiving end after short circuit is a large reflection impedance in the transmitting end, and the current of the transmitting end is small, so that the power loss of the circuit in a zero-mode working mode can be reduced.
In the dual-output rectifying and voltage stabilizing circuit provided in the above embodiment, in order to reduce the size of the whole circuit, the first switch S 1 and the second switch S 2 are small-sized field effect transistors, and the third switch S 3 is a field effect transistor or a CMOS transmission gate.
Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
It is to be understood that the invention is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the invention is limited only by the appended claims.
Claims (4)
1. The double-output rectifying and voltage stabilizing circuit is characterized by comprising an inductor, a first capacitor, a second capacitor, a third capacitor, a first field effect transistor, a second field effect transistor, a first switch, a second switch, a first comparator, a second comparator, a first hysteresis comparator, a second hysteresis comparator, a self-starting circuit, a clock generator, a first voltage dividing circuit, a second voltage dividing circuit, a reference voltage source, a linear voltage stabilizer and a digital controller;
After the inductor is connected with the first capacitor in parallel, one end of the inductor is an alternating current signal input end, the source electrode of the first field effect transistor and the source electrode of the second field effect transistor are connected, and the other end of the inductor is connected to a second direct current voltage output end; the drain electrode of the first field effect transistor is connected to the first direct-current voltage output end, and the drain electrode of the second field effect transistor is grounded; one end of the second capacitor is connected to the first direct-current voltage output end, and the other end of the second capacitor is connected to the second direct-current voltage output end; one end of the third capacitor is connected to the second direct-current voltage output end, and the other end of the third capacitor is grounded; the first switch is connected in parallel between the gate and the drain of the field first effect transistor, and the second switch is connected in parallel between the gate and the drain of the second field effect transistor; the non-inverting input end of the first comparator is connected to the drain electrode of the first field effect transistor, the inverting input end of the first comparator is connected to the source electrode of the first field effect transistor, and the output end of the first comparator is connected to the grid electrode of the first field effect transistor; the non-inverting input end of the second comparator is grounded, the inverting input end of the second comparator is connected to the source electrode of the second field effect transistor, and the output end of the second comparator is connected to the grid electrode of the second field effect transistor;
The input end of the self-starting circuit is connected to the first direct-current voltage output end, and the output end of the self-starting circuit is connected to the input end of the digital controller; the input end of the first voltage dividing circuit is connected to the first direct-current voltage output end, and the output end of the first voltage dividing circuit is connected to the non-inverting input end of the first hysteresis comparator; the input end of the second voltage dividing circuit is connected to the second direct-current voltage output end, and the output end of the second voltage dividing circuit is connected to the non-inverting input end of the second hysteresis comparator; the input end of the reference voltage source is connected to the first direct-current voltage output end, and the output end of the reference voltage source is connected to the input end of the linear voltage stabilizer; the output end of the linear voltage stabilizer is respectively connected to the inverting input end of the first hysteresis comparator and the inverting input end of the second hysteresis comparator; the output end of the first hysteresis comparator and the output end of the second hysteresis comparator are both connected to the input end of the digital controller; the input end of the clock generator is connected to the input end of the alternating current signal, and the output end of the clock generator is connected to the input end of the digital controller; four output ends of the digital controller are respectively connected to the enabling end of the first switch, the enabling end of the second switch, the enabling end of the first comparator and the enabling end of the second comparator.
2. The rectifying and voltage regulating circuit of claim 1, wherein said first field effect transistor is a P-channel power field effect transistor and said second field effect transistor is an N-channel power field effect transistor.
3. The rectifying and voltage stabilizing circuit according to claim 1 or 2, further comprising a third switch, wherein one end of said third switch is connected to said ac signal input terminal, and the other end is connected to said second dc voltage output terminal.
4. The rectifying and voltage regulating circuit of claim 3, wherein said first switch and said second switch are field effect transistors and said third switch is a field effect transistor or a CMOS transmission gate.
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| CN202311656637.1A CN117914142A (en) | 2023-12-05 | 2023-12-05 | Dual-output rectifying voltage-stabilizing circuit |
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| CN202311656637.1A CN117914142A (en) | 2023-12-05 | 2023-12-05 | Dual-output rectifying voltage-stabilizing circuit |
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|---|---|
| CN (1) | CN117914142A (en) |
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2023
- 2023-12-05 CN CN202311656637.1A patent/CN117914142A/en active Pending
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