CN117913092A

CN117913092A - Integrated circuit device and method of forming the same

Info

Publication number: CN117913092A
Application number: CN202311346753.3A
Authority: CN
Inventors: 朴金锡; 白在职; 朴修永; 徐康一
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2022-10-19
Filing date: 2023-10-17
Publication date: 2024-04-19

Abstract

An integrated circuit device and a method of forming the same are provided. An integrated circuit device may include a substrate and a transistor stack on the substrate, the transistor stack including a first transistor and a second transistor on the first transistor. The first transistor may be between the substrate and the second transistor, and the first transistor may include first and second source/drain regions, a first channel region between the first and second source/drain regions, and first gate structures on upper and lower surfaces of the first channel region. The lower surface of the first source/drain region may be higher than the lower surface of the first gate structure with respect to the substrate.

Description

Integrated circuit device and method of forming the same

Technical Field

The present disclosure relates generally to the field of integrated circuit devices, and more particularly, to integrated circuit devices including stacked Field Effect Transistors (FETs).

Background

Various structures of integrated circuit devices and methods of forming the same have been proposed to increase the integration density of the integrated circuit devices and/or to improve the performance of the integrated circuit devices. In particular, integrated circuit devices comprising 3D stacked FETs have been proposed.

Disclosure of Invention

An integrated circuit device according to some embodiments may include a substrate and a transistor stack on the substrate, the transistor stack including a first transistor and a second transistor on the first transistor. The first transistor may be between the substrate and the second transistor, and the first transistor may include first and second source/drain regions, a first channel region between the first and second source/drain regions, and first gate structures on upper and lower surfaces of the first channel region. The lower surface of the first source/drain region may be higher than the lower surface of the first gate structure with respect to the substrate.

An integrated circuit device according to some embodiments may include a substrate and a transistor stack on the substrate, the transistor stack including a first transistor and a second transistor on the first transistor. The first transistor may be between the substrate and the second transistor, and may include first and second source/drain regions, a first channel region between the first and second source/drain regions, and first gate structures on upper and lower surfaces of the first channel region. The uppermost end of the second source/drain region may be spaced apart from the substrate by a first distance, and the upper surface of the first gate structure may be spaced apart from the substrate by a second distance equal to or greater than the first distance.

A method of forming an integrated circuit device according to some embodiments may include: forming an initial transistor stack on a substrate, the initial transistor stack including an upper channel region and a lower channel region between the substrate and the upper channel region; forming a bottom insulating layer on the substrate and adjacent to the first side surface of the lower channel region; and forming a first source/drain region on the bottom insulating layer, the first source/drain region contacting a first side surface of the lower channel region.

Drawings

Fig. 1 is a layout of an integrated circuit device according to some embodiments.

Fig. 1A illustrates a cross-sectional view of an integrated circuit device, taken along line X-X' in fig. 1, in accordance with some embodiments.

FIG. 1B illustrates a cross-sectional view of an integrated circuit device, taken along line Y1-Y1' in FIG. 1, according to some embodiments.

Fig. 1C illustrates a cross-sectional view of an integrated circuit device, taken along line Y2-Y2' in fig. 1, in accordance with some embodiments.

Fig. 1D is an enlarged view of region R1 in fig. 1A, according to some embodiments.

Fig. 2 is a layout of an integrated circuit device according to some embodiments.

Fig. 2A illustrates a cross-sectional view of an integrated circuit device, taken along line X-X' in fig. 2, in accordance with some embodiments.

Fig. 2B illustrates a cross-sectional view of the integrated circuit device, taken along line Y1-Y1' in fig. 2, in accordance with some embodiments.

Fig. 2C illustrates a cross-sectional view of the integrated circuit device, taken along line Y2-Y2' in fig. 2, in accordance with some embodiments.

Fig. 3 is a layout of an integrated circuit device according to some embodiments.

Fig. 3A illustrates a cross-sectional view of an integrated circuit device, taken along line X-X' in fig. 3, in accordance with some embodiments.

Fig. 3B illustrates a cross-sectional view of an integrated circuit device, taken along line Y1-Y1' in fig. 3, in accordance with some embodiments.

Fig. 3C illustrates a cross-sectional view of an integrated circuit device, taken along line Y2-Y2' in fig. 3, in accordance with some embodiments.

Fig. 4 is a flow chart of a method of forming an integrated circuit device according to some embodiments.

Fig. 5-15 are cross-sectional views illustrating methods of forming integrated circuit devices according to some embodiments.

Detailed Description

Parasitic capacitance between the gate electrode and the source/drain regions may degrade the performance (e.g., AC performance) of the integrated circuit device, which may be varied by various factors. For example, the parasitic capacitance may increase as the portion of the gate electrode overlapping the source/drain regions increases. According to some embodiments, an integrated circuit device may include a gate electrode including a portion that does not overlap with a source/drain region, such that parasitic capacitance between the gate electrode and the source/drain region can be reduced. In some embodiments, an insulating layer (e.g., a bottom insulating layer) may be formed under the source/drain regions and may overlap with a lower portion of the gate electrode such that the lower portion of the gate electrode may not overlap with the source/drain regions. In this case, the thickness of the source/drain region may be reduced in the lower portion due to the insulating layer, and source/drain contacts (e.g., top contacts) may be connected to the upper surface of the source/drain region. In some other embodiments, an insulating layer (e.g., a top insulating layer) may be formed over the source/drain regions and may overlap an upper portion of the gate electrode such that the upper portion of the gate electrode does not overlap the source/drain regions. In this case, the thickness of the source/drain region may be reduced in the upper portion due to the insulating layer, and source/drain contacts (e.g., bottom contacts) may be connected to the lower surface of the source/drain region.

Example embodiments will be described in more detail with reference to the accompanying drawings.

Fig. 1 is a layout of a first integrated circuit device 100 according to some embodiments. For simplicity of illustration, fig. 1 shows only selected elements. Fig. 1A illustrates a cross-sectional view of a first integrated circuit device 100, taken along line X-X' in fig. 1, in accordance with some embodiments. Fig. 1B illustrates a cross-sectional view of the first integrated circuit device 100, taken along line Y1-Y1' in fig. 1, in accordance with some embodiments. Fig. 1C illustrates a cross-sectional view of the first integrated circuit device 100, taken along line Y2-Y2' in fig. 1, in accordance with some embodiments. Referring to fig. 1, 1A, 1B, and 1C, the first integrated circuit device 100 may include first and second lower source/drain regions 110 and 112 on a substrate 122 and first and second upper source/drain regions 114 and 116 on the first and second lower source/drain regions 110 and 112. The first and second lower source/drain regions 110 and 112 may be between the first and second upper source/drain regions 114 and 116 and the substrate 122 in a third direction Z (also referred to as a vertical direction). The first integrated circuit device 100 may also include a lower channel region 102, an upper channel region 104, a lower gate structure 106, an upper gate structure 108, and first and second dummy gate structures 118a and 118b. As used herein, a lower element/surface refers to an element/surface that is closer to the substrate 122 than an upper element/surface.

The first and second lower source/drain regions 110 and 112, the lower channel region 102, and the lower gate structure 106 may form a lower transistor (e.g., a first transistor). The first and second upper source/drain regions 114 and 116, the upper channel region 104, and the upper gate structure 108 may form an upper transistor (e.g., a second transistor). The lower and upper transistors may comprise a transistor stack of the first integrated circuit device 100. The substrate 122 and the upper transistor may be spaced apart in the third direction Z with the lower transistor between the substrate 122 and the upper transistor. In some embodiments, the lower and upper transistors may be different types of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), but are not limited thereto. For example, depending on the specifications of the first integrated circuit device 100, the lower transistor may be a PMOS transistor of a transistor stack, the upper transistor may be an NMOS transistor of a transistor stack, or vice versa. In some embodiments, the lower and upper transistors may be formed as Complementary Metal Oxide Semiconductor (CMOS) structures. The lower and upper transistors may be stacked on the substrate 122 in the third direction Z.

The first and second dummy gate structures 118a and 118b may be non-electrically active gate structures (e.g., non-active gate structures) and may be formed as physical structures that replicate the lower and upper gate structures 106 and 108. The first and second dummy gate structures 118a and 118b may be connected to various elements. For example, the first and second dummy gate structures 118a and 118b may be connected to the first and second dummy gate spacers 117a and 117b, respectively, of the first integrated circuit device 100.

In some embodiments, the substrate 122 may extend in a first direction X (also referred to as a first horizontal direction) and a second direction Y (also referred to as a second horizontal direction). In some embodiments, the first direction X may be perpendicular to the second direction Y. The substrate 122 may include one or more semiconductor materials, such as Si, ge, siGe, gaP, gaAs, siC, siGeC and/or InP. In some embodiments, the substrate 122 may be a bulk substrate (e.g., a bulk silicon substrate) or a semiconductor-on-insulator (SOI) substrate. For example, the substrate 122 may be a silicon wafer. The thickness of the substrate 122 in the third direction Z may be in the range of 50nm to 100 nm. In some embodiments, the substrate 122 may include an insulating material, such as silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, and/or low-k materials. For example, the substrate 122 may include a plurality of insulating layers (e.g., a silicon oxide layer and a silicon nitride layer) stacked in the third direction Z. In some embodiments, the third direction Z may be perpendicular to the first direction X and/or the second direction Y.

The lower channel region 102 may be, for example, a semiconductor layer having a nano-scale thickness in the third direction Z. The lower channel region 102 may be between the first lower source/drain region 110 and the second lower source/drain region 112 in the first horizontal direction X. The first lower source/drain region 110 and the second lower source/drain region 112 may be electrically connected to the lower channel region 102. In some embodiments, a plurality of lower channel regions 102 may be stacked in the third direction Z, and the plurality of lower channel regions 102 may be spaced apart from each other in the third direction Z, as shown in fig. 1A. For example, the lower channel region 102 may be implemented by a plurality of nano-sheets or nano-wires extending between the first lower source/drain region 110 and the second lower source/drain region 112, for example. In some other embodiments, only a single lower channel region 102 may be present between the first lower source/drain region 110 and the second lower source/drain region 112.

The lower gate structure 106 may include a lower gate insulator and a lower gate electrode. The lower channel region 102 may extend through the lower gate structure 106 in the first direction X, and a lower gate insulator may be provided between the lower gate electrode and the lower channel region 102 for electrical isolation therebetween. The lower gate insulator may contact the lower channel region 102. In some embodiments, the lower gate electrode may include a metal layer including, for example, tungsten (W), aluminum (Al), copper (Cu), molybdenum (Mo), and/or ruthenium (Ru). The lower gate electrode may additionally include a work function layer (e.g., tiN layer, taN layer, tiAl layer, tiC layer, tiAlC layer, tiAlN layer, and/or WN layer). A work function layer may be provided between the metal layer and the lower gate insulator. In some embodiments, the work function layer may separate the metal layer from the lower gate insulator.

The first and second lower source/drain regions 110 and 112 may be spaced apart from each other in the first direction X, and the lower gate structure 106 may be provided between the first and second lower source/drain regions 110 and 112.

The upper channel region 104 may be, for example, a semiconductor layer having a nano-scale thickness in the third direction Z. The upper channel region 104 may be between the first upper source/drain region 114 and the second upper source/drain region 116 in the first horizontal direction X. The first upper source/drain region 114 and the second upper source/drain region 116 may be electrically connected to the upper channel region 104. In some embodiments, a plurality of upper channel regions 104 may be stacked in the third direction Z, and the plurality of upper channel regions 104 may be spaced apart from each other in the third direction Z, as shown in fig. 1A. For example, the upper channel region 104 may be implemented by, for example, a plurality of nanoplates or nanowires extending between the first upper source/drain region 114 and the second upper source/drain region 116. In some other embodiments, only a single upper channel region 104 may be present between the first upper source/drain region 114 and the second upper source/drain region 116.

The upper gate structure 108 may include an upper gate insulator and an upper gate electrode. The upper channel region 104 may extend through the upper gate structure 108 in the first direction X, and an upper gate insulator may be provided between the upper gate electrode and the upper channel region 104 for electrical isolation therebetween. The upper gate insulator may contact the upper channel region 104. In some embodiments, the upper gate electrode may include a metal layer including, for example, tungsten (W), aluminum (Al), copper (Cu), molybdenum (Mo), and/or ruthenium (Ru). The upper gate electrode may additionally include a work function layer (e.g., tiN layer, taN layer, tiAl layer, tiC layer, tiAlC layer, tiAlN layer, and/or WN layer). A work function layer may be provided between the metal layer and the upper gate insulator. In some embodiments, the work function layer may separate the metal layer from the upper gate insulator.

The first integrated circuit device 100 may further include a first gate isolation layer 132 provided between the lower gate structure 106 and the upper gate structure 108. In some embodiments, the first gate isolation layer 132 may completely separate the lower gate structure 106 from the upper gate structure 108, and the lower gate structure 106 may not contact the upper gate structure 108. For example, the first gate isolation layer 132 may be an insulating layer. In other embodiments, the first gate isolation layer 132 may be omitted.

The first upper source/drain region 114 and the second upper source/drain region 116 may be spaced apart from each other in the first direction X, and the upper gate structure 108 may be provided between the first upper source/drain region 114 and the second upper source/drain region 116. In some embodiments, the first lower source/drain region 110 and the first upper source/drain region 114 may overlap each other in the third direction Z, and the second lower source/drain region 112 and the second upper source/drain region 116 may overlap each other in the third direction Z, as shown in fig. 1, 1B, and 1C. As used herein, "element a overlaps element B in direction X" (or similar language) means that there is at least one line extending in direction X and intersecting both element a and element B.

Although the first and second lower source/drain regions 110, 112 are shown in fig. 1A as single layer source/drain regions, in some embodiments they may comprise multiple semiconductor layers. Similarly, although the first and second upper source/drain regions 114 and 116 are shown in fig. 1B and 1C, respectively, as single-layer source/drain regions, in some embodiments they may comprise multiple semiconductor layers. Accordingly, the first and second lower source/drain regions 110 and 112 and the first and second upper source/drain regions 114 and 116 may be single-layer or multi-layer source/drain regions.

Each of the lower channel region 102 and the upper channel region 104 may comprise a semiconductor material (e.g., si, ge, siGe, gaP, gaAs, siC, siGeC and/or InP). In some embodiments, the lower channel region 102 and the upper channel region 104 may comprise the same material. In some embodiments, each of the lower channel region 102 and the upper channel region 104 may be a nano-sheet that may have a thickness in the range from 1nm to 100nm in the third direction Z, or may be a nano-wire that may have a circular cross-section with a diameter in the range from 1nm to 100 nm.

Each of the lower gate insulator and the upper gate insulator may include a single layer or multiple layers (e.g., silicon oxide layers and/or high-k material layers). For example, the high-k material layer may include Al₂O₃、HfO₂、ZrO₂、HfZrO₄、TiO₂、Sc₂O₃、Y₂O₃、La₂O₃、Lu₂O₃、Nb₂O₅ and/or Ta ₂O₅. In some embodiments, the lower gate insulator and the upper gate insulator may comprise the same material. In some embodiments, the lower gate electrode and the upper gate electrode may comprise the same material.

In some embodiments, the first and second lower source/drain regions 110, 112 may comprise the same material as the first and second upper source/drain regions 114, 116. The first and second lower source/drain regions 110, 112 and the first and second upper source/drain regions 114, 116 may comprise one or more semiconductor materials, such as Si, ge, siGe, gaP, gaAs, siC, siGeC and/or InP. In other embodiments, the first and second upper source/drain regions 114, 116 may comprise a semiconductor material that is different from the semiconductor material of the first and second lower source/drain regions 110, 112. For example, the first and second upper source/drain regions 114, 116 may comprise silicon germanium, and the first and second lower source/drain regions 110, 112 may comprise silicon carbide, or vice versa.

The first integrated circuit device 100 may include an insulating layer 142, with first and second lower source/drain regions 110 and 112 and first and second upper source/drain regions 114 and 116 provided in the insulating layer 142.

The first integrated circuit device 100 may include upper gate spacers 128 (also referred to as inter-gate spacers). For simplicity of illustration, the cross-sectional view of fig. 1A is not taken along a line intersecting the first upper source/drain region 114 and the second upper source/drain region 116. However, it will be appreciated that upper gate spacers 128 may be provided between the upper gate structure 108 and the first and second upper source/drain regions 114, 116 for electrical isolation therebetween. A lower gate spacer 126 may be provided between the lower gate structure 106 and the first and second lower source/drain regions 110 and 112 for electrical isolation therebetween. In some embodiments, opposite side surfaces of the upper gate spacer 128 may contact the upper gate structure 108 and one of the first and second upper source/drain regions 114, 116, respectively, and opposite side surfaces of the lower gate spacer 126 may contact the lower gate structure 106 and one of the first and second lower source/drain regions 110, 112, respectively.

In some embodiments, the upper channel region 104 may extend through the upper gate spacer 128 in the first direction X and may contact the first upper source/drain region 114 and the second upper source/drain region 116. The lower channel region 102 may extend through the lower gate spacer 126 in the first direction X and may contact the first lower source/drain region 110 and the second lower source/drain region 112, as shown in fig. 1 and 1A. The lower gate spacer 126 and the upper gate spacer 128 may comprise, for example, silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, and/or low-k materials. For example, the low-k material may include fluorine doped silicon oxide, organosilicate glass, carbon doped oxide, porous silicon dioxide, porous organosilicate glass, spin-on organic polymer dielectric, and/or spin-on silicon-based polymer dielectric.

In some embodiments, the second gate spacer 134 may be between an upper surface of the first gate spacer 132 and the upper gate structure 108 and/or between a lower surface of the first gate spacer 132 and the lower gate structure 106.

The second spacer 138 may be on a sidewall of an upper portion of the upper gate structure 108, and the first spacer 136 may be between the second spacer 138 and the upper portion of the upper gate structure 108.

The first and second gate insulation layers 132 and 134, the insulating layer 142, and/or the first and second spacers 136 and 138 may include, for example, silicon oxide, silicon oxynitride, silicon nitride, or a low-k dielectric material.

A bottom insulating layer 124 may be formed between the substrate 122 and the lower surface of the first lower source/drain region 110. The bottom insulating layer 124 may comprise, for example, silicon oxide, silicon oxynitride, silicon nitride, or a low-k dielectric material.

A top contact 144 may be provided on the first lower source/drain region 110 and in the insulating layer 142. The top contact 144 may electrically connect the first lower source/drain region 110 to a conductive element (e.g., a conductive line or conductive via plug) of a back end of line (BEOL) structure 146, which BEOL structure 146 is formed by the BEOL portion of the device fabrication. In some embodiments, the top contact 144 may contact the first lower source/drain region 110 (e.g., may contact an upper surface of the first lower source/drain region 110).

The BEOL structure 146 may include a conductive line (e.g., a metal line) and a conductive via plug (e.g., a metal via plug) stacked in the third direction Z, each of which may electrically connect two conductive lines spaced apart from each other in the third direction Z.

Bottom contact 148 may be provided in substrate 122. In some embodiments, the bottom contact 148 may extend through the substrate 122 in the third direction Z, and the bottom contact 148 may contact the second lower source/drain region 112 (e.g., may contact a lower surface of the second lower source/drain region 112), as shown in fig. 1A. In some embodiments, the width of the bottom contact 148 in the horizontal direction (e.g., the first direction X or the second direction Y) may increase with increasing distance from the second lower source/drain region 112 in the third direction Z, as shown in fig. 1A. The bottom contact 148 may include a conductive layer, which may include a metallic element (e.g., W, al, cu, mo and/or Ru).

The bottom contact 148 may electrically connect the second lower source/drain region 112 to a conductive element (e.g., a conductive line or conductive via plug) of the backside distribution network (BSPDN) structure 150. In some embodiments, the second lower source/drain region 112 may be electrically connected to a power source having a predetermined voltage (e.g., drain voltage or source voltage). BSPDN structure 150 may include a plurality of insulating layers stacked on a lower surface of substrate 122 and conductive elements provided in the insulating layers.

Referring to fig. 1B and 1C, shallow Trench Isolation (STI) structures 121 may be formed in the substrate 122 and adjacent to side surfaces of the first and second lower source/drain regions 110 and 112. STI structures 121 may electrically insulate transistors of first integrated circuit device 100 from each other. The portion of the substrate 122 between the STI structures 121 (e.g., the portion of the substrate 122 on which the first lower source/drain regions 110 and the second lower source/drain regions 112 are formed) may be referred to as an active region of the first integrated circuit device 100.

Fig. 1D is an enlarged view of region R1 in fig. 1A, according to some embodiments. Referring to fig. 1D, a bottom insulating layer 124 may be formed between the lower surface of the first lower source/drain region 110 and the substrate 122. An upper surface of the bottom insulating layer 124 may contact a lower surface of the first lower source/drain region 110. The first lower source/drain region 110 may be formed such that an upper surface of the first lower source/drain region 110 is at a height relative to the substrate 122 that will be electrically connected to the top contact 144. The top contact 144 may contact an upper surface of the first lower source/drain region 110. By forming the first lower source/drain region 110 on the bottom insulating layer 124, the first lower source/drain region 110 may have a reduced thickness in the third direction Z.

The lower surface of the first lower source/drain region 110 may be higher than the lower surface of the lower gate structure 106 with respect to the substrate 122. The lower surface of the lower gate structure 106 may be coplanar with the lower surface of the bottom insulating layer 124. In some embodiments, a lower surface of the first lower source/drain region 110 may be coplanar with a lower surface of a lowermost lower channel region 102 of the plurality of lower channel regions 102 (e.g., may be coplanar with a lower surface of the lower channel region 102). A lower portion of the lower gate structure 106 may be between the substrate 122 and a lowermost lower channel region 102 of the plurality of lower channel regions 102. In some embodiments, a lower portion of the lower gate structure 106 may partially overlap the first lower source/drain region 110 in the first direction X. In other embodiments, the entire lower portion of the lower gate structure 106 may not overlap the first lower source/drain region 110 in the first direction X. The bottom insulating layer 124 may completely or partially overlap a lower portion of the lower gate structure 106 in the first direction X, which may reduce parasitic capacitance between the first lower source/drain region 110 and the lower gate structure 106. In some embodiments, as used herein, "surface a is coplanar with surface B" (or similar language) means that surface a and surface B are equidistant from substrate 122.

Accordingly, parasitic capacitance between the first lower source/drain region 110 and the lower gate structure 106 may be reduced by forming the first lower source/drain region 110 with a reduced thickness (e.g., a reduced thickness in the third direction Z). By forming the first lower source/drain region 110 on the bottom insulating layer 124, the thickness of the first lower source/drain region 110 may be reduced in a lower portion thereof.

The second lower source/drain region 112 may have a reduced thickness at an upper portion thereof (e.g., a reduced thickness in the third direction Z). For example, an upper surface of the first lower source/drain region 110 and/or an upper surface of the lower gate structure 106 may be higher than an upper surface of the second lower source/drain region 112 with respect to the substrate 122. The lower surface of the first lower source/drain region 110 may be higher than the lower surface of the second lower source/drain region 112 with respect to the substrate 122. The second lower source/drain region 112 may be formed such that a lower surface of the second lower source/drain region 112 is on the substrate 122 and contacts the bottom contact 148. Bottom contact 148 may be in substrate 122 and may be electrically connected to second lower source/drain region 112. An upper portion of the lower gate structure 106 may be between the upper gate structure 108 (or the first gate spacer 132 and/or the second gate spacer 134) and an uppermost lower channel region 102 of the plurality of lower channel regions 102. In some embodiments, an upper portion of the lower gate structure 106 may overlap with a portion of the insulating layer 142 formed on the second lower source/drain region 112 in the first direction X entirely or partially.

Accordingly, parasitic capacitance between the second lower source/drain region 112 and the lower gate structure 106 may be reduced by forming the second lower source/drain region 112 with a reduced thickness (e.g., a reduced thickness in the third direction Z). The thickness of the second lower source/drain regions 112 may be reduced in an upper portion thereof.

In some embodiments, the upper surface of the second lower source/drain region 112 may have a flat portion 113a and an inclined portion 113b. The flat portion 113a may be coplanar with an upper surface of the lower gate structure 106 or lower than the upper surface of the lower gate structure 106. In some embodiments, the inclined portion 113b may extend between a lower surface of an uppermost one of the lower gate spacers 126 and the flat portion 113 a. In other embodiments, the inclined portion 113b may extend between a sidewall of an uppermost one of the lower gate spacers 126 and the flat portion 113 a. The uppermost end (e.g., the flat portion 113 a) of the second lower source/drain region 112 may be spaced apart from the substrate 122 by a first distance d1. The upper surface of the lower gate structure 106 may be spaced apart from the substrate 122 by a second distance d2. In some embodiments, the second distance d2 may be equal to the first distance d1. In other embodiments, the second distance D2 may be greater than the first distance D1, as shown in fig. 1D. The uppermost end of the first lower source/drain region 110 may be spaced apart from the substrate 122 by a third distance d3 greater than the first distance d1. In some embodiments, a lowermost end of the upper surface of the second lower source/drain region 112 may be spaced apart from the substrate 122 by a fourth distance d4, and an upper surface of an uppermost lower channel region 102 of the plurality of lower channel regions 102 (e.g., an upper surface of the lower channel region 102) may be spaced apart from the substrate 122 by a fifth distance d5 that may be equal to the fourth distance d 4.

In fig. 1D, the first lower source/drain region 110 may be electrically connected to the top contact 144 and the second lower source/drain region 112 may be electrically connected to the bottom contact 148. The first lower source/drain region 110 may be formed on the bottom insulating layer 124 and may have a reduced thickness at a lower portion thereof. The second lower source/drain region 112 may have a reduced thickness at an upper portion thereof. Accordingly, the first lower source/drain region 110 and the second lower source/drain region 112 may each have a reduced parasitic capacitance relative to the lower gate structure 106.

Fig. 2 is a layout of a second integrated circuit device 200 according to some embodiments. Fig. 2A illustrates a cross-sectional view of the second integrated circuit device 200, taken along line X-X' in fig. 2, in accordance with some embodiments. Fig. 2B illustrates a cross-sectional view of the second integrated circuit device 200, taken along line Y1-Y1' in fig. 2, in accordance with some embodiments. Fig. 2C illustrates a cross-sectional view of the second integrated circuit device 200, taken along line Y2-Y2' in fig. 2, in accordance with some embodiments. Referring to fig. 2, 2A, 2B, and 2C, the second integrated circuit device 200 is similar to the first integrated circuit device 100, with the primary difference being that the second integrated circuit device 200 includes a second lower source/drain region 212, the second lower source/drain region 212 being on a second bottom insulating layer 224 and electrically connected to a second top contact 244. The lower surface of the second lower source/drain region 212 may be higher than the lower surface of the lower gate structure 106 with respect to the substrate 122. The second lower source/drain region 212 may be similar to the first lower source/drain region 110, and thus a further description will be omitted. The second bottom insulating layer 224 may be similar to the bottom insulating layer 124 (e.g., the first bottom insulating layer 124) except that the second bottom insulating layer 224 is between the lower surface of the second lower source/drain region 212 and the substrate 122. The second top contact 244 may be similar to the top contact 144 (e.g., the first top contact 144) except that the second top contact 244 may contact and electrically connect with an upper surface of the second lower source/drain region 212.

The first lower source/drain region 110 and the second lower source/drain region 212 may be electrically connected to the first top contact 144 and the second top contact 244, respectively. The first and second lower source/drain regions 110 and 212 may be formed on the first and second bottom insulating layers 124 and 224, respectively, and may each have a reduced thickness at a lower portion thereof. Accordingly, the first lower source/drain region 110 and the second lower source/drain region 212 may each have a reduced parasitic capacitance relative to the lower gate structure 106.

Fig. 3 is a layout of a third integrated circuit device 300 according to some embodiments. Fig. 3A illustrates a cross-sectional view of a third integrated circuit device 300, taken along line X-X' in fig. 3, in accordance with some embodiments. Fig. 3B illustrates a cross-sectional view of the third integrated circuit device 300, taken along line Y1-Y1' in fig. 3, in accordance with some embodiments. Fig. 3C illustrates a cross-sectional view of the third integrated circuit device 300, taken along line Y2-Y2' in fig. 3, in accordance with some embodiments. Referring to fig. 3, 3A, 3B, and 3C, a third integrated circuit device 300 is similar to the first integrated circuit device 100, with the primary difference being that the third integrated circuit device 300 includes a first lower source/drain region 310 electrically connected to a first bottom contact 348. The first lower source/drain region 310 may be similar to the second lower source/drain region 112, and thus a further description will be omitted. The first bottom contact 348 may be similar to the bottom contact 148 (e.g., the second bottom contact 148) except that the first bottom contact 348 may contact the first lower source/drain region 310 (e.g., may contact a lower surface of the first lower source/drain region 310) and be electrically connected to the first lower source/drain region 310.

The first lower source/drain region 310 and the second lower source/drain region 112 may be electrically connected to the first bottom contact 348 and the second bottom contact 148, respectively. The first lower source/drain region 310 and the second lower source/drain region 112 may each have a reduced thickness at an upper portion thereof. Accordingly, the first lower source/drain region 310 and the second lower source/drain region 112 may each have a reduced parasitic capacitance relative to the lower gate structure 106.

Fig. 4 is a flow chart of a method of forming the first integrated circuit device 100, according to some embodiments. Fig. 5-15 are cross-sectional views illustrating those methods of forming the first integrated circuit device 100, according to some embodiments. Referring to fig. 4 and 5, the method may include forming an initial transistor stack PTS on a substrate 122 (block 410). The initial transistor stack PTS may include an upper channel region 104 and a lower channel region 102 between a substrate 122 and the upper channel region 104. The initial transistor stack PTS may further include a lower sacrificial layer 506 and an upper sacrificial layer 508 stacked on the lower sacrificial layer 506. The lower sacrificial layer 506 and the upper sacrificial layer 508 may comprise different materials than the lower channel region 102 and the upper channel region 104 such that the lower sacrificial layer 506 and the upper sacrificial layer 508 may be selectively removed from the initial transistor stack PTS to form a lower gate structure and an upper gate structure (e.g., the lower gate structure 106 and the upper gate structure 108 of fig. 1 and 1A). For example, lower sacrificial layer 506 and upper sacrificial layer 508 may comprise a semiconductor material (e.g., silicon germanium).

The lower gate spacer 126 may be formed on sidewalls of the lower sacrificial layer 506 and the upper gate spacer 128 may be formed on sidewalls of the upper sacrificial layer 508. In some embodiments, the first gate isolation layer 132 may be formed between the upper sacrificial layer 508 and the lower sacrificial layer 506. The second gate spacer 134 may be formed on upper and lower surfaces of the first gate spacer 132. According to some embodiments, the first and second dummy gate structures 118a and 118b may be formed on sidewalls of the lower and upper channel regions 102 and 104 and sidewalls of the lower and upper sacrificial layers 506 and 508. The first dummy gate spacer 117a may be formed on a sidewall of the first dummy gate structure 118 a. The second dummy gate spacers 117b may be formed on sidewalls of the second dummy gate structure 118 b.

The initial first spacers 536, the sacrificial layers 552, 554 and 556, and the initial second spacers 538 may be formed on the initial transistor stack PTS. For example, the sacrificial layers 552, 554, and 556 may be insulating layers. According to some embodiments, the sacrificial layers 552, 554, and 556 may be part of a multi-layer mask. The sacrificial layers 552, 554, and 556, the initial first spacers 536, and the initial second spacers 538 may comprise, for example, silicon oxide, silicon oxynitride, silicon nitride, or a low-k dielectric material. The sacrificial layers 552, 554, and 556, the initial first spacers 536, and the initial second spacers 538 may be used as an etch mask when forming the initial transistor stack PTS. The first opening 558 and the second opening 560 may be formed on opposite side surfaces of the initial transistor stack PTS.

Referring to fig. 4 and 5, an initial insulating layer 562 (also referred to as a first initial insulating layer) may be formed in the first opening 558 and the second opening 560 (block 412). An initial insulating layer 562 may be formed in the first and second openings 558 and 560 and on sidewalls of the initial second spacers 538. For example, the initial insulating layer 562 can include the same insulating material as the initial second spacers 538 (and/or the same insulating material as the initial first spacers 536). The initial insulating layer 562 may cover sidewalls of the lower channel region 102 and the upper channel region 104 and sidewalls of the lower sacrificial layer 506 and the upper sacrificial layer 508, or on sidewalls of the lower channel region 102 and the upper channel region 104 and sidewalls of the lower sacrificial layer 506 and the upper sacrificial layer 508. The first mask 564 may be formed on the sacrificial layers 552, 554, and 556 and may cover the first opening 558 and the second opening 560. The initial insulating layer 562 may comprise, for example, silicon oxide, silicon oxynitride, silicon nitride, or a low-k dielectric material.

Referring to fig. 4 and 6, a portion of the initial insulating layer 562 in the first opening 558 may be removed, thereby forming a first lower portion 662 of the initial insulating layer 562 (block 414). For example, the second mask 664 may be formed by removing a portion of the first mask 564 covering the first opening 558, and then an etching process may be performed on the initial insulating layer 562 to remove an upper portion thereof in the first opening 558. The second mask 664, the sacrificial layers 552, 554, and 556, and the initial second spacers 538 may be used as an etch mask for an etching process. After removing portions of the initial insulating layer 562, an upper surface of a first lower portion 662 of the initial insulating layer 562 in the first opening 558 may be coplanar with or higher than an upper surface of an uppermost lower sacrificial layer 506 (e.g., an upper surface of the lower sacrificial layer 506) with respect to the substrate 122. First and second thin layers 666 and 668 may be formed on sidewalls of first opening 558, sidewalls of initial second spacers 538, and an upper surface of first lower portion 662 of initial insulating layer 562 in first opening 558. For example, the first and second thin layers 666 and 668 may include silicon oxide, silicon oxynitride, silicon nitride, or a low-k dielectric material. In some embodiments, first sheet 666 and second sheet 668 may include different materials. For example, the first thin layer 666 may be a layer including an oxide material and the second thin layer 668 may be a layer including a nitride material.

Referring to fig. 4 and 7, the first and second thin spacers 766 and 768 may be formed by removing portions of the first and second thin layers 666 and 668 formed on the upper surface of the first lower portion 662 of the initial insulating layer 562. Further, a portion of the first lower portion 662 of the initial insulating layer 562 in the first opening 558 may be removed to form the bottom insulating layer 124 (block 416). For example, the second mask 664, the first thin spacer 766 and the second thin spacer 768, and/or the sacrificial layers 552, 554, and 556 may be used as an etching mask when etching the first lower portion 662 of the initial insulating layer 562. The etching process may be performed such that the upper surface of the bottom insulating layer 124 is coplanar with or lower than the lower surface of the lower channel region 102 (e.g., the lower surface of the lowermost lower channel region 102) with respect to the substrate 122. A bottom insulating layer 124 may be formed on the substrate 122 adjacent to the first side surface of the lower channel region 102.

Referring to fig. 4 and 8, a first lower source/drain region 110 may be formed (block 420). The first lower source/drain region 110 may be epitaxially grown from the lower channel region 102 in the first opening 558. In some embodiments, the lower channel region 102 may comprise silicon and the first lower source/drain region 110 may comprise silicon, silicon carbide, or silicon germanium. However, the present disclosure is not limited thereto, and the lower channel region 102 and/or the first lower source/drain region 110 may include one or more semiconductor materials, such as Si, ge, siGe, gaP, gaAs, siC, siGeC and/or InP. The first lower source/drain region 110 may be formed on the bottom insulating layer 124. The first lower source/drain region 110 may contact a first side surface of the lower channel region 102. The lower surface of the first lower source/drain region 110 may be higher than the lower surface of the lower sacrificial layer 506 with respect to the substrate 122. When the first lower source/drain region 110 is formed, the side surfaces of the upper channel region 104 are covered by the first thin spacer 766 and the second thin spacer 768. Thus, the epitaxial layer may not grow from those side surfaces of the upper channel region 104.

Referring to fig. 9, after forming the first lower source/drain region 110, a second initial insulating layer 962 may be formed in the first opening 558. The second initial insulating layer 962 may be formed on side surfaces of the first and second thin spacers 766 and 768 and on an upper surface of the first lower source/drain region 110. A third mask 964 may be formed to cover the second initial insulating layer 962.

Referring to fig. 4 and 10, a portion of the initial insulating layer 562 in the second opening 560 may be removed, thereby forming a second lower portion 1062 of the initial insulating layer 562 in the second opening 560 (block 422). For example, the fourth mask 1064 may be formed by removing a portion of the second mask 664, and then an etching process may be performed on the initial insulating layer 562 to remove an upper portion thereof in the second opening 560. The fourth mask 1064, the sacrificial layers 552, 554, and 556, and the initial second spacers 538 may be used as an etch mask for an etching process. After removing portions of the initial insulating layer 562 in the second opening 560, an upper surface of the second lower portion 1062 of the initial insulating layer 562 may be coplanar with an upper surface of the uppermost lower sacrificial layer 506 (e.g., an upper surface of the lower sacrificial layer 506) or higher than an upper surface of the uppermost lower sacrificial layer 506 (e.g., an upper surface of the lower sacrificial layer 506). Third and fourth thin layers 1066 and 1068 may be formed on sidewalls of the second opening 560, sidewalls of the initial second spacers 538, and upper surfaces of the second lower portion 1062 of the initial insulating layer 562 in the second opening 560.

Referring to fig. 4 and 11, the third thin spacers 1166 and the fourth thin spacers 1168 may be formed by removing portions of the third thin layer 1066 and the fourth thin layer 1068 formed on the upper surface of the second lower portion 1062 of the initial insulating layer 562. Further, the second lower portion 1062 of the initial insulating layer 562 in the second opening 560 may be removed (block 424). For example, an etching process may be performed on the second lower portion 1062 of the initial insulating layer 562 using the fourth mask 1064, the third thin spacers 1166, and the fourth thin spacers 1168, and/or the sacrificial layers 552, 554, and 556 as etching masks for the etching process.

Referring to fig. 4 and 12, an initial second lower source/drain region 1270 may be formed (block 426). An initial second lower source/drain region 1270 may be epitaxially grown from the lower channel region 102 in the second opening 560. In some embodiments, the lower channel region 102 may comprise silicon and the initial second lower source/drain region 1270 may comprise silicon, silicon carbide, or silicon germanium. However, the present disclosure is not so limited, and the lower channel region 102 and/or the initial second lower source/drain region 1270 may comprise one or more semiconductor materials, such as Si, ge, siGe, gaP, gaAs, siC, siGeC and/or InP. An initial second lower source/drain region 1270 may be formed on the substrate 122 and may contact a second side surface of the lower channel region 102 opposite the first side surface of the lower channel region 102. When forming the initial second lower source/drain regions 1270, side surfaces of the upper channel region 104 are covered by the third thin spacers 1166 and the fourth thin spacers 1168. Thus, the epitaxial layer may not grow from those side surfaces of the upper channel region 104.

Referring to fig. 4 and 13, a second lower source/drain region 112 may be formed (block 430). The second lower source/drain regions 112 may be formed in the second openings 560 by removing an upper portion of the initial second lower source/drain regions 1270. For example, an etching process may be performed on the initial second lower source/drain region 1270 to remove an upper portion thereof. The fourth mask 1064, the third thin spacers 1166 and the fourth thin spacers 1168 and/or the sacrificial layers 552, 554 and 556 may be used as etching masks for the etching process. The second lower source/drain region 112 may be formed on the substrate 122 and may contact a second side surface of the lower channel region 102 opposite to the first side surface of the lower channel region 102. The uppermost end of the second lower source/drain region 112 may be lower than the uppermost end of the first lower source/drain region 110 with respect to the substrate 122. In some embodiments, the initial second lower source/drain region 1270 may have an upper surface (or uppermost) that is lower than the upper surface (or uppermost) of the uppermost lower sacrificial layer 506, and thus may serve as the second lower source/drain region 112. Accordingly, an etching process for removing the upper portion of the initial second lower source/drain region 1270 may be omitted.

Referring to fig. 14, after forming the second lower source/drain regions 112, a third initial insulating layer 1462 may be formed in the second openings 560. A third preliminary insulating layer 1462 may be formed on side surfaces of the third and fourth thin spacers 1166 and 1168 and an upper surface of the second lower source/drain region 112. The fourth mask 1064 may be removed to expose the second preliminary insulating layer 962 formed in the first opening 558.

Referring to fig. 15, a fourth initial insulating layer 1562 may be formed on the first and second lower source/drain regions 110 and 112. The fourth initial insulating layer 1562 may be formed by removing an upper portion of the second initial insulating layer 962 and an upper portion of the third initial insulating layer 1462. For example, an etching process may be performed on the second and third initial insulating layers 962 and 1462. After forming the fourth initial insulating layer 1562, the first, second, third, and fourth thin spacers 766, 768, 1166, and 1168 may be removed to expose side surfaces of the upper channel region 104.

Referring to fig. 1A, 1B, 1C, and 4, upper source/drain regions (e.g., first upper source/drain region 114 and second upper source/drain region 116) may be formed (block 440). The first and second upper source/drain regions 114 and 116 may be formed on the fourth initial insulating layer 1562 (shown in fig. 15) by performing an epitaxial growth process using the upper channel region 104 as a seed layer. After forming the first upper source/drain regions 114 and the second upper source/drain regions 116, an insulating layer (e.g., insulating layer 142) may be formed (block 442). In some embodiments, the insulating layer 142 may be formed on the fourth initial insulating layer 1562. The insulating layer 142 and the fourth initial insulating layer 1562 may comprise the same material and may be collectively referred to as an insulating layer. In some other embodiments, fourth initial insulating layer 1562 may be removed and insulating layer 142 may then be formed.

Upper gate structure and lower gate structure (e.g., upper gate structure 108 and lower gate structure 106) may be formed by replacing upper sacrificial layer 508 and lower sacrificial layer 506 with upper gate structure 108 and lower gate structure 106, respectively (block 450). After forming the upper and lower gate structures 108 and 106, the sacrificial layers 552, 554, and 556 may be removed, and the initial first and second spacers 536 and 538 may be converted to the first and second spacers 136 and 138, respectively.

A top contact (e.g., top contact 144) may be formed (block 460). A top contact 144 may be formed in the insulating layer 142 over the first lower source/drain region 110, as shown in fig. 1A and 1B. The top contact 144 may be electrically connected to the first lower source/drain region 110.

A process line Back End (BEOL) structure (e.g., BEOL structure 146) may be formed (block 470). The top contacts 144 may electrically connect the first lower source/drain regions 110 to conductive elements (e.g., conductive lines or conductive via plugs) of the BEOL structure 146, which BEOL structure 146 is formed by BEOL portions of device fabrication, as shown in fig. 1A and 1B.

A bottom contact (e.g., bottom contact 148) may be formed (block 480). Bottom contact 148 may be formed in substrate 122 as shown in fig. 1A and 1C. For example, an etching process may be performed on a lower surface of the substrate 122 to form an opening in the substrate 122, and the bottom contact 148 may be formed in the opening formed in the substrate 122. In some embodiments, a process (e.g., a grinding process and/or an etching process) may be performed on the lower surface of the substrate 122 to reduce the thickness of the substrate 122 prior to forming the bottom contact 148.

A backside power distribution network (BSPDN) structure (e.g., BSPDN structure 150) may be formed (block 490). BSPDN structures 150 may be formed on the lower surface of the substrate 122, as shown in fig. 1A, 1B, and 1C. In some embodiments, BSPDN structures 150 may contact bottom contact 148.

Example embodiments are described herein with reference to the accompanying drawings. Many different forms and embodiments are possible without departing from the teachings of the present disclosure, and thus the present disclosure should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like numbers refer to like elements throughout.

Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments and intermediate structures of the example embodiments. Thus, variations in the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Therefore, embodiments herein should not be construed as limited to the particular shapes illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. Although an element is shown as a single layer in the figures, the element may comprise multiple layers.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," "including," "containing," "including," "includes", "including," "including" when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof.

It will be understood that when an element is referred to as being "coupled," connected "or" responsive "to" another element, it can be directly coupled, connected or responsive to the other element or on the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly coupled," "directly connected," or "directly responsive to" or "directly on" another element, there are no intervening elements present. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. Furthermore, the symbol "/" (e.g., when used in the term "source/drain") will be understood to be equivalent to the term "and/or".

It will be understood that, although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element could be termed a second element without departing from the teachings of the present embodiment.

For ease of description, spatial relationship terms such as "under," "above," "upper," and the like may be used herein to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "under" or "under" other elements or features would then be oriented "over" the other elements or features. Thus, the term "below" can encompass both an orientation of above and below. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Many different embodiments have been disclosed herein in connection with the above description and the accompanying drawings. It will be understood that each combination and sub-combination of these embodiments, literally described and illustrated, will be overly repeated and confusing. Accordingly, the specification (including the drawings) should be construed to constitute a complete written description of all combinations and subcombinations of the embodiments described herein, as well as of the manner and process of making and using them, and should support claims to any such combination or subcombination.

The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the scope of the present invention. Thus, to the maximum extent allowed by law, the scope is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.

The disclosure of U.S. provisional application serial No. 63/3801717 entitled "method of forming stacked field effect transistors" filed on USPTO at 10/19 of 2022 and U.S. patent application serial No. 18/171754 filed on USPTO at 21 of 2023 is hereby incorporated by reference in its entirety.

Claims

1. An integrated circuit device, comprising:

A substrate; and

A transistor stack on the substrate, the transistor stack including a first transistor and a second transistor on the first transistor,

Wherein the first transistor is between the substrate and the second transistor, and wherein the first transistor comprises:

a first source/drain region and a second source/drain region;

A first channel region between the first source/drain region and the second source/drain region; and

A first gate structure on upper and lower surfaces of the first channel region,

Wherein a lower surface of the first source/drain region is higher than a lower surface of the first gate structure with respect to the substrate.

2. The integrated circuit device of claim 1, further comprising a bottom insulating layer between the lower surface of the first source/drain region and the substrate.

3. The integrated circuit device of claim 2, wherein an upper surface of the bottom insulating layer contacts the lower surface of the first source/drain region.

4. The integrated circuit device of claim 2, wherein the lower surface of the first gate structure is coplanar with a lower surface of the bottom insulating layer.

5. The integrated circuit device of claim 1, further comprising a top contact contacting an upper surface of the first source/drain region.

6. The integrated circuit device of claim 1, wherein the substrate and the second transistor are spaced apart from each other in a direction,

The first transistor includes a plurality of first channel regions stacked in the direction, and

The lower surface of the first source/drain region is coplanar with a lower surface of a lowermost first channel region of the plurality of first channel regions.

7. The integrated circuit device of claim 1, wherein the substrate and the second transistor are spaced apart from each other in a direction,

A lower portion of the first gate structure is between the substrate and a lowermost first channel region of the plurality of first channel regions.

8. The integrated circuit device of claim 1, wherein a lower surface of the second source/drain region is higher than the lower surface of the first gate structure relative to the substrate.

9. The integrated circuit device of claim 8, further comprising:

a first bottom insulating layer between the lower surface of the first source/drain region and the substrate; and

A second bottom insulating layer between the lower surface of the second source/drain region and the substrate.

10. The integrated circuit device of claim 8, further comprising:

a first top contact contacting an upper surface of the first source/drain region; and

A second top contact contacts an upper surface of the second source/drain region.

11. The integrated circuit device of claim 1, wherein the lower surface of the first source/drain region is higher than a lower surface of the second source/drain region relative to the substrate.

12. The integrated circuit device of claim 11, further comprising a bottom contact in the substrate and electrically connected to the second source/drain region.

13. An integrated circuit device, comprising:

A substrate; and

Wherein the first transistor is between the substrate and the second transistor and includes:

a first source/drain region and a second source/drain region;

A first gate structure on upper and lower surfaces of the first channel region,

Wherein an uppermost end of the second source/drain region is spaced apart from the substrate by a first distance, and an upper surface of the first gate structure is spaced apart from the substrate by a second distance equal to or greater than the first distance.

14. The integrated circuit device of claim 13, wherein an uppermost end of the first source/drain region is spaced apart from the substrate by a third distance, the third distance being greater than the first distance.

15. The integrated circuit device of claim 13, wherein the substrate and the second transistor are spaced apart from each other in a direction,

The lowermost end of the upper surface of the second source/drain region is spaced apart from the substrate by a fourth distance, and the upper surface of an uppermost first channel region of the plurality of first channel regions is spaced apart from the substrate by a fifth distance equal to the fourth distance.

16. The integrated circuit device of claim 13, further comprising a bottom contact in the substrate and electrically connected to the second source/drain region.

17. A method of forming an integrated circuit device, the method comprising:

Forming an initial transistor stack on a substrate, the initial transistor stack including an upper channel region and a lower channel region between the substrate and the upper channel region;

forming a bottom insulating layer on the substrate and adjacent to a first side surface of the lower channel region; and

A first source/drain region is formed on the bottom insulating layer, the first source/drain region contacting the first side surface of the lower channel region.

18. The method of claim 17, further comprising:

forming an insulating layer on the first source/drain region; and

A top contact is formed in the insulating layer, wherein the top contact is electrically connected to the first source/drain region.

19. The method of claim 17, further comprising forming a second source/drain region on the substrate and contacting a second side surface of the lower channel region,

Wherein the first side surface of the lower channel region is opposite the second side surface of the lower channel region, and

The uppermost end of the second source/drain region is lower than the uppermost end of the first source/drain region with respect to the substrate.

20. The method of claim 19, wherein forming the second source/drain regions comprises:

Forming an initial second source/drain region on the substrate and contacting the second side surface of the lower channel region; and

The second source/drain region is formed by removing an upper portion of the initial second source/drain region.