CN117912401A

CN117912401A - Pixel circuit, driving method thereof and display device

Info

Publication number: CN117912401A
Application number: CN202211282917.6A
Authority: CN
Inventors: 秦斌; 曲燕; 牛亚男; 彭锦涛; 滕万鹏; 高志坤; 任锦宇; 王玮
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2022-10-19
Filing date: 2022-10-19
Publication date: 2024-04-19

Abstract

The embodiment of the disclosure provides a pixel circuit, a driving method thereof and a display device. The pixel circuit includes: a driving module configured to provide a driving electrical signal to the first node; the first bias module is configured to provide a signal of a second power supply end for the first node under the control of the second control signal end; the second bias module is configured to provide a signal of the first power supply end for the second node under the control of the second control signal end; the switching module is configured to be conducted under the control of the first control signal end under the condition that the driving electric signal is provided for the first node, and the switching module is used for providing a signal of the second power end for the second node; in the case of providing the signal of the second power supply terminal to the first node, providing the signal of the first power supply terminal to the second node, the switching module is configured to be disconnected under the control of the first control signal terminal, cutting off the coupling between the second power supply terminal and the second node; and the light emitting module is respectively coupled with the first node and the second node.

Description

Pixel circuit, driving method thereof and display device

Technical Field

The disclosure relates to the technical field of display, and in particular relates to a pixel circuit, a driving method thereof and a display device.

Background

Liquid Crystal Displays (LCDs) are the earliest popular, more mature display technology, but with the increasing performance requirements of panels, LCDs are difficult to meet future demands. Organic light emitting diode display (OLED) is a new generation of display technology following LCD, and technology is already mature. Mini LEDs (sub-millimeter light emitting diode chips) and Micro LEDs (Micro light emitting diode chips) have excellent performances of lower power consumption, faster reaction, longer service life, better color saturation contrast and the like. With technological breakthroughs, mini LEDs and Micro LEDs will become the next generation display technology following LCDs, OLEDs.

However, the LED display product has some problems that the brightness of the LED device is reduced in the case of maintaining high brightness for a long time, resulting in brightness difference between adjacent positions of the display screen, and thus the quality of the display screen is reduced.

Disclosure of Invention

Embodiments of the present disclosure provide a pixel circuit, a driving method thereof, and a display device, so as to solve or alleviate one or more technical problems in the prior art.

As a first aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a pixel circuit including:

The driving module is coupled with the first power supply end, the data signal end, the scanning signal end, the reset signal end, the first control signal end, the initial signal end and the first node respectively, and is configured to provide driving electric signals for the first node based on the first power supply end, the data signal end and the initial signal end under the control of the scanning signal end, the reset signal end and the first control signal end;

The first bias module is coupled with the first node, the second control signal end and the second power end respectively and is configured to provide signals of the second power end for the first node under the control of the second control signal end;

the second bias module is coupled with the second node, the second control signal end and the first power end respectively and is configured to provide signals of the first power end for the second node under the control of the second control signal end;

The switching module is respectively coupled with the second node, the first control signal end and the second power end, and is configured to be conducted under the control of the first control signal end under the condition that a driving electric signal is provided for the first node, and a signal of the second power end is provided for the second node; in the case of providing the signal of the second power supply terminal to the first node, providing the signal of the first power supply terminal to the second node, the switching module is configured to be disconnected under the control of the first control signal terminal, cutting off the coupling between the second power supply terminal and the second node;

And the light emitting module is respectively coupled with the first node and the second node.

In some embodiments, the pixel circuit includes at least one of:

The first bias module comprises a seventh transistor, a grid electrode of the seventh transistor is coupled with the second control signal end, and a first pole and a second pole of the seventh transistor are respectively coupled with the first node and the second power supply end;

the second bias module comprises a ninth transistor, a grid electrode of the ninth transistor is coupled with the second control signal end, and a first pole and a second pole of the ninth transistor are respectively coupled with the second node and the first power supply end;

The switch module comprises an eighth transistor, wherein a grid electrode of the eighth transistor is coupled with the first control signal end, and a first pole and a second pole of the eighth transistor are respectively coupled with the second node and the second power supply end.

In some embodiments, the signal at the second control signal terminal is the same as the signal at the first control signal terminal.

In some embodiments, the light emitting module includes a light emitting diode chip.

In some embodiments, the reverse bias time of the light emitting module is 4% to 6% of one frame time.

In some embodiments, the drive module includes:

the reset sub-module is respectively coupled with the initial signal end, the third node and the reset signal end and is configured to provide an initial signal of the initial signal end for the third node under the control of the reset signal end;

The writing sub-module is respectively coupled with the data signal end, the scanning signal end, the fourth node, the fifth node and the third node and is configured to provide a data signal of the data signal end for the third node under the control of the scanning signal end;

The storage submodule is coupled with the third node and the first power supply end respectively and is configured to store a data signal of the third node;

A driving sub-module coupled to the third node, the fourth node, and the fifth node, respectively, and configured to provide corresponding electrical signals to the fifth node based on the electrical signals of the fourth node under control of the third node;

The switch control submodule is respectively coupled with the first power supply end, the fourth node, the fifth node, the first node and the first control signal end and is configured to provide driving electric signals for the first node through the fourth node, the driving submodule and the fifth node based on the voltage of the first power supply end under the control of the first control signal end.

In some embodiments, the drive module includes at least one of:

The reset submodule comprises a first transistor, a grid electrode of the first transistor is coupled with a reset signal end, and a first pole and a second pole of the first transistor are respectively coupled with an initial signal end and a third node;

The writing submodule comprises a second transistor and a fourth transistor, the grid electrode of the fourth transistor is coupled with the scanning signal end, and the first pole and the second pole of the second transistor are respectively coupled with the data signal end and the fourth node; the grid electrode of the second transistor is coupled with the scanning signal end, and the first pole and the second pole of the second transistor are respectively coupled with the third node and the fifth node;

the storage submodule comprises a storage capacitor, and a first polar plate and a second polar plate of the storage capacitor are respectively coupled with a first power supply end and a third node;

the driving sub-module comprises a third transistor, wherein the grid electrode of the third transistor is coupled with a third node, and the first pole and the second pole of the third transistor are respectively coupled with a fourth node and a fifth node;

The switch control submodule comprises a fifth transistor and a sixth transistor, the grid electrode of the fifth transistor is coupled with the first control signal end, and the first pole and the second pole of the fifth transistor are respectively coupled with the first power supply end and the fourth node; the gate of the sixth transistor is coupled to the first control signal terminal, and the first and second poles of the sixth transistor are coupled to the first and fifth nodes, respectively.

In some embodiments of the present invention, in some embodiments,

The switch control submodule comprises a fifth transistor and a sixth transistor, the switch module comprises an eighth transistor, and the fifth transistor, the sixth transistor and the eighth transistor are PMOS; the first bias module comprises a seventh transistor, the second bias module comprises a ninth transistor, and the seventh transistor and the ninth transistor are NMOS; or alternatively

The switch control submodule comprises a fifth transistor and a sixth transistor, the switch module comprises an eighth transistor, and the fifth transistor, the sixth transistor and the eighth transistor are NMOS; the first bias module includes a seventh transistor, and the second bias module includes a ninth transistor, both of which are PMOS.

As a second aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a driving method of a pixel circuit, which is applicable to the pixel circuit in the embodiments of the present disclosure, the method including:

Providing an initial signal of an initial signal end for a third node, providing a signal of a second power end for a first node, and providing a signal of the first power end for the second node;

writing the data signal of the data signal end into a third node, providing the signal of the second power end for the first node, and providing the signal of the first power end for the second node;

the driving electric signal is provided to the first node, and the signal of the second power supply terminal is provided to the second node.

As a third aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a display device including the pixel circuit in the embodiments of the present disclosure.

According to the technical scheme, the light-emitting module can be in a reverse bias state in a non-light-emitting stage, so that holes and electrons in the light-emitting module are released, the defect number is reduced, the light-emitting module can be restored to an initial state when emitting light next time, the reduction of the brightness of the light-emitting module due to long-time maintenance of high brightness is avoided, the brightness difference of different area positions of the display panel when displaying a high-brightness picture is relieved, and the picture quality is improved.

The foregoing summary is for the purpose of the specification only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present disclosure will become apparent by reference to the drawings and the following detailed description.

Drawings

In the drawings, the same reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily drawn to scale. It is appreciated that these drawings depict only some embodiments according to the disclosure and are not to be considered limiting of its scope.

FIG. 1 is a schematic view of a display screen of a display panel;

Fig. 2 is a structure of a pixel circuit in the related art;

FIG. 3 is a schematic diagram of a driving timing diagram of the pixel circuit shown in FIG. 1;

FIG. 4 is a schematic diagram of a pixel circuit according to an embodiment of the disclosure;

FIG. 5 is a schematic diagram of a pixel circuit according to another embodiment of the disclosure;

FIG. 6 is a timing diagram of a pixel circuit according to an embodiment of the disclosure;

FIG. 7A is a schematic diagram illustrating an operation state of the pixel circuit shown in FIG. 5 in a first stage;

FIG. 7B is a schematic diagram illustrating the pixel circuit of FIG. 5 in a second stage;

FIG. 7C is a schematic diagram illustrating an operation state of the pixel circuit shown in FIG. 5 in a third stage;

fig. 8 is a schematic diagram of a driving method of a pixel circuit according to an embodiment of the disclosure.

Reference numerals illustrate:

10. a driving module; 11. a reset sub-module; 12. writing a sub-module; 13. a storage sub-module; 14. a drive sub-module; 15. a switch control sub-module; 20. a first bias module; 30. a second bias module; 40. a light-on module; 50. and a light emitting module.

Detailed Description

Hereinafter, only certain exemplary embodiments are briefly described. As will be recognized by those of skill in the pertinent art, the described embodiments may be modified in various different ways without departing from the spirit or scope of the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive.

The transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices of the same characteristics, and the transistors used in embodiments of the present invention are mainly switching transistors according to the role in the circuit. Since the source and drain of the switching transistor used herein are symmetrical, the source and drain are interchangeable. In the embodiment of the present invention, the source (source electrode) is referred to as a first pole, the drain (drain electrode) is referred to as a second pole, or the drain may be referred to as a first pole, and the source is referred to as a second pole. In the embodiment shown in the drawings, the middle terminal of the transistor is defined as a gate (may also be called a gate electrode), the signal input terminal is defined as a source, and the signal output terminal is defined as a drain. The switching transistor adopted by the embodiment of the invention can be a P-type switching transistor or an N-type switching transistor, wherein the P-type switching transistor is turned on when the grid electrode is in a low level, and turned off when the grid electrode is in a high level; the N-type transistor is turned on when the gate is high and turned off when the gate is low. In addition, the plurality of signals in the various embodiments of the present invention each correspond to a first potential and a second potential. The first potential and the second potential only represent 2 different potential state quantities of the signal, and do not represent that the first potential or the second potential has a specific value in the whole text. In the embodiment of the present invention, the first potential is taken as an effective potential as an example.

Wherein the coupling may comprise: the two ends are in direct physical contact or are connected indirectly (such as by a signal line). The coupling manner between the two ends is not limited in the embodiment of the invention.

It has been found that the LED has a 20% drop in brightness when the LED is maintained at a high brightness for a long period of time. This causes a difference in brightness between the two positions of the frame on the display panel, which is switched from the low gray level to the high gray level, and the frame which is maintained at the high gray level for a long time. For example, fig. 1 is a schematic view of a display screen of a display panel, in which, as shown in fig. 1, the screens of the first area A1 and the third area A3 are switched from a low gray level to a high gray level, and the screen of the second area A2 is maintained at the high gray level for a long time. Although the first, second and third areas A1, A2 and A3 are all high gray scale pictures, the brightness of the second area A2 is reduced by about 20% because the LEDs of the second area A2 maintain high brightness for a long time. This causes a difference in brightness between the picture of the second area A2 and the pictures of the first area A1 and the third area A3, resulting in a degradation of the picture quality of the display panel. While restarting the display panel may alleviate the brightness difference, it is not practical to require the user to restart the display panel.

Fig. 2 is a structure of a pixel circuit in the related art, fig. 3 is a schematic diagram of a driving timing of the pixel circuit shown in fig. 1, and fig. 3 shows a timing within a Frame (1 Frame) time.

Referring to fig. 2 and 3, in the first stage ①, i.e., the reset stage, the first control signal terminal EM is an inactive level signal (e.g., a high level signal), the reset signal terminal Rst is an active level signal (e.g., a low level signal), and the scan signal terminal Gate is an inactive level signal (e.g., a high level signal). The fifth transistor M5 and the sixth transistor M6 are turned off, the first transistor M1 and the seventh transistor M7 are turned on, and an initial signal of the initial signal terminal Vinit is provided to both the third node N3 and the first node N1, so that the reset of the pixel circuit is realized.

Referring to fig. 2 and 3, in the second stage ②, i.e., the write data stage, the first control signal terminal EM is an inactive level signal (e.g., a high level signal), the reset signal terminal Rst is an inactive level signal (e.g., a high level signal), and the scan signal terminal Gate is an active level signal (e.g., a low level signal). The fifth transistor M5 and the sixth transistor M6 remain turned off, the first transistor M1 and the seventh transistor M7 are turned off, the second transistor M2 and the fourth transistor M4 are turned on, and the Data signal of the Data signal terminal Data is written into the third node N3 and stored.

Referring to fig. 2 and 3, in the third stage ③, i.e., the light-emitting stage, the first control signal terminal EM is an active level signal (e.g., a low level signal), the reset signal terminal Rst is an inactive level signal (e.g., a high level signal), and the scan signal terminal Gate is an inactive level signal (e.g., a high level signal). The first transistor M1 and the seventh transistor M7 remain turned off, the second transistor M2 and the fourth transistor M4 are turned off, and the fifth transistor M5 and the sixth transistor M6 are turned on, and supply a driving electric signal to the first node N1 to drive the light emitting module 50 to emit light.

In order to solve the problems in the related art, the embodiment of the present disclosure provides a pixel circuit.

Fig. 4 is a schematic structural diagram of a pixel circuit according to an embodiment of the disclosure. In one embodiment, as shown in fig. 4, the pixel circuit may include a driving module 10, a first bias module 20, a second bias module 30, a switching module 40, and a light emitting module 50.

The driving module 10 is coupled to the first power source terminal VDD, the Data signal terminal Data, the scan signal terminal Gate, the reset signal terminal Rst, the first control signal terminal EM, the initial signal terminal Vinit and the first node N1, respectively. The driving module 10 is configured to supply a driving electric signal to the first node N1 based on the first power supply terminal VDD, the Data signal terminal Data, and the initial signal terminal Vinit under the control of the scan signal terminal Gate, the reset signal terminal Rst, and the first control signal terminal EM.

The first bias module 20 is coupled to the first node N1, the second control signal terminal EM2, and the second power terminal VSS, respectively. The first bias module 20 is configured to supply the signal of the second power supply terminal VSS to the first node N1 under the control of the second control signal terminal EM 2.

The second bias module 30 is coupled to the second node N2, the second control signal terminal EM2, and the first power terminal VDD, respectively. The second bias module 30 is configured to supply the signal of the first power supply terminal VDD to the second node N2 under the control of the second control signal terminal EM 2.

The switch module 40 is coupled to the second node N2, the first control signal terminal EM and the second power terminal VSS, respectively.

In case of supplying the driving electric signal to the first node N1, the switching module 40 is configured to be turned on under the control of the first control signal terminal EM to supply the signal of the second power supply terminal VSS to the second node N2.

In the case of providing the signal of the second power source terminal VSS to the first node N1 and the signal of the first power source terminal VDD to the second node N2, the switching module 40 is configured to be turned off under the control of the first control signal terminal EM, cutting off the coupling between the second power source terminal VSS and the second node N2.

The light emitting module 50 is coupled with the first node N1 and the second node N2, respectively. The light emitting module 50 is configured to emit light under the driving of the first node N1 and the second node N2 in the case where a driving electric signal is supplied to the first node N1. The light emitting module 50 is further configured to be in a reverse bias state in a case where a signal of the second power source terminal VSS is supplied to the first node N1, and a signal of the first power source terminal VDD is supplied to the second node N2.

In the pixel circuit of the embodiment of the present disclosure, when the driving electrical signal is supplied to the first node N1, the switching module 40 is turned on under the control of the first control signal terminal EM, and supplies the signal of the second power supply terminal VSS to the second node N2. Thus, the light emitting module 50 may emit light under the combined action of the driving electric signal of the first node N1 and the signal of the second power source terminal VSS.

In the case that the signal of the second power source terminal VSS is supplied to the first node N1 and the signal of the first power source terminal VDD is supplied to the second node N2, the switching module 40 is turned off under the control of the first control signal terminal EM, cuts off the coupling between the second power source terminal VSS and the second node N2, and no signal of the second power source terminal VSS is supplied to the second node N2. Thus, the signal of the second power source terminal VSS is supplied to the first node N1, and the signal of the first power source terminal VDD is supplied to the second node N2, so that the light emitting module 50 is in a reverse bias state. The reverse bias of the light emitting module 50 can release holes and electrons in the light emitting module 50, so that the defect number is reduced, the light emitting module 50 can be restored to an initial state when emitting light for the next time, the brightness reduction of the light emitting module 50 due to long-time maintenance of high brightness is avoided, the brightness difference of different area positions of the display panel when displaying high-brightness pictures is relieved, and the picture quality is improved.

Illustratively, the light emitting module 50 may be a light emitting diode chip (LED), for example, the light emitting module 50 may be a Mini-LED or a Micro-LED. Illustratively, the p-pole of the light emitting module 50 may be coupled with the first node N1, and the N-pole of the light emitting module 50 may be coupled with the second node N2.

Illustratively, the light emitting module 50 includes at least one light emitting device, which in the embodiment of the present application may be a Micro-LED or a Mini-LED, but the present application is not limited thereto, and the light emitting device may be other light emitting devices displaying brightness, such as an OLED, a QLED. The light emitting module 50 may include a plurality of light emitting devices connected in series or a plurality of light emitting devices connected in parallel or a plurality of light emitting devices combined in series and parallel.

In one embodiment, the signal of the second control signal terminal EM2 may be the same as the signal of the first control signal terminal EM. In such a setting manner, the first bias module 20 and the second bias module 30 can be controlled by directly adopting the signal of the first control signal end EM, and no new control signal line is required to be additionally arranged, so that the number of signal lines required by the pixel circuit can be reduced, and the circuit wiring is simplified.

Fig. 5 is a schematic structural diagram of a pixel circuit according to another embodiment of the disclosure. In one embodiment, as shown in fig. 5, the first bias module 20 includes a seventh transistor M7, wherein a gate of the seventh transistor M7 is coupled to the second control signal terminal EM2, and a first pole and a second pole of the seventh transistor M7 are respectively coupled to the first node N1 and the second power terminal VSS.

In one embodiment, as shown in fig. 5, the second bias module 30 includes a ninth transistor M9, a gate of the ninth transistor M9 is coupled to the second control signal terminal EM2, and a first pole and a second pole of the ninth transistor M9 are respectively coupled to the second node N2 and the first power terminal VDD.

In one embodiment, as shown in fig. 5, the switch module 40 includes an eighth transistor M8, wherein a gate of the eighth transistor M8 is coupled to the first control signal terminal EM, and a first pole and a second pole of the eighth transistor M8 are respectively coupled to the second node N2 and the second power terminal VSS.

It should be noted that, fig. 5 illustrates an exemplary structure of the first bias module 20, the second bias module 30, and the switch module 40, and those skilled in the art will understand that the first bias module 20, the second bias module 30, and the switch module 40 are not limited to the structure illustrated in fig. 5, as long as the functions thereof can be implemented.

In one embodiment, as shown in fig. 5, the driving module 10 may include a reset sub-module 11, a write sub-module 12, a storage sub-module 13, a driving sub-module 14, and a switching control sub-module 15.

In one embodiment, as shown in fig. 5, the reset submodule 11 is coupled to the initial signal terminal Vinit, the third node N3 and the reset signal terminal Rst, respectively, and is configured to provide the initial signal of the initial signal terminal Vinit to the third node N3 under the control of the reset signal terminal Rst.

In one embodiment, as shown in fig. 5, the writing sub-module 12 is coupled to the Data signal terminal Data, the scan signal terminal Gate, the fourth node N4, the fifth node N5 and the third node N3, respectively, and is configured to provide the Data signal of the Data signal terminal Data to the third node N3 under the control of the scan signal terminal Gate.

In one embodiment, as shown in fig. 5, the storage sub-module 13 is coupled to the third node N3 and the first power supply terminal VDD, respectively, and is configured to store the data signal of the third node N3.

In one embodiment, as shown in FIG. 5, the drive sub-module 14 is coupled to the third node N3, the fourth node N4, and the fifth node N5, respectively, and is configured to provide corresponding electrical signals to the fifth node N5 based on the electrical signal of the fourth node N4 under the control of the third node N3.

In one embodiment, as shown in fig. 5, the switch control sub-module 15 is coupled to the first power supply terminal VDD, the fourth node N4, the fifth node N5, the first node N1, and the first control signal terminal EM, respectively, and is configured to provide a driving electrical signal to the first node N1 through the fourth node N4, the driving sub-module 14, and the fifth node N5 based on a voltage of the first power supply terminal VDD under the control of the first control signal terminal EM.

In the embodiment of the present disclosure, in the reset stage, an initial signal of an initial signal terminal Vinit is provided to the third node N3 by the reset submodule 11, so as to realize the reset of the third node N3; in the Data writing stage, the writing sub-module 12 writes the Data signal of the Data signal end Data into the third node N3, and the storage sub-module 13 stores the Data signal of the third node N3; in the light emitting stage, the switch control sub-module 15 provides an electrical signal to the fourth node N4 based on the voltage of the first power supply terminal VDD under the control of the first control signal terminal EM, the driving sub-module 14 provides a corresponding electrical signal to the fifth node N5 based on the electrical signal of the fourth node N4 under the control of the third node N3, and the electrical signal of the fifth node N5 provides a driving electrical signal to the first node N1 through the switch control sub-module 15 to drive the light emitting module 50 to emit light.

In one embodiment, as shown in fig. 5, the reset submodule 11 includes a first transistor M1, a gate of the first transistor M1 is coupled to the reset signal terminal Rst, and a first pole and a second pole of the first transistor M1 are coupled to the initial signal terminal Vinit and the third node N3, respectively.

In one embodiment, as shown in fig. 5, the writing sub-module 12 includes a second transistor M2 and a fourth transistor M4, the Gate of the fourth transistor M4 is coupled to the scan signal terminal Gate, and the first and second poles of the second transistor M2 are coupled to the Data signal terminal Data and the fourth node N4, respectively; the Gate of the second transistor M2 is coupled to the scan signal terminal Gate, and the first and second poles of the second transistor M2 are coupled to the third and fifth nodes N3 and N5, respectively.

In one embodiment, as shown in fig. 5, the storage sub-module 13 includes a storage capacitor Cs, and a first plate and a second plate of the storage capacitor Cs are coupled to the first power supply terminal VDD and the third node N3, respectively.

In one embodiment, as shown in fig. 5, the driving sub-module 14 includes a third transistor M3, a gate of the third transistor M3 is coupled to a third node N3, and a first pole and a second pole of the third transistor M3 are coupled to a fourth node N4 and a fifth node N5, respectively.

In one embodiment, as shown in fig. 5, the switch control sub-module 15 includes a fifth transistor M5 and a sixth transistor M6, wherein a gate of the fifth transistor M5 is coupled to the first control signal terminal EM, and a first pole and a second pole of the fifth transistor M5 are respectively coupled to the first power terminal VDD and the fourth node N4. The gate of the sixth transistor M6 is coupled to the first control signal terminal EM, and the first and second poles of the sixth transistor M6 are coupled to the fourth node N4 and the fifth node N5, respectively.

It should be noted that, in fig. 5, an exemplary structure of the reset sub-module 11, the write sub-module 12, the storage sub-module 13, the drive sub-module 14, and the switch control sub-module 15 is shown, and those skilled in the art will understand that the reset sub-module 11, the write sub-module 12, the storage sub-module 13, the drive sub-module 14, and the switch control sub-module 15 are not limited to the structure shown in fig. 5, as long as the functions thereof can be implemented.

In one embodiment, as shown in fig. 5, the switch control sub-module 15 includes a fifth transistor M5 and a sixth transistor M6. The gate of the fifth transistor M5 is coupled to the first control signal terminal EM, and the first and second poles of the fifth transistor M5 are coupled to the first power terminal VDD and the fourth node N4, respectively. The gate of the sixth transistor M6 is coupled to the first control signal terminal EM, and the first and second poles of the sixth transistor M6 are coupled to the first node N1 and the fifth node N5, respectively.

The first bias module 20 includes a seventh transistor M7. The gate of the seventh transistor M7 is coupled to the second control signal terminal EM2, and the first and second poles of the seventh transistor M7 are coupled to the first node N1 and the second power terminal VSS, respectively. The second bias module 30 includes a ninth transistor M9. The gate of the ninth transistor M9 is coupled to the second control signal terminal EM2, and the first and second poles of the ninth transistor M9 are coupled to the second node N2 and the first power terminal VDD, respectively. The switching module 40 includes an eighth transistor M8. The gate of the eighth transistor M8 is coupled to the first control signal terminal EM, and the first and second poles of the eighth transistor M8 are coupled to the second node N2 and the second power terminal VSS, respectively.

In one embodiment, the fifth transistor M5, the sixth transistor M6, and the eighth transistor M8 are of the same type, and the seventh transistor M7 and the ninth transistor M9 are of the same type. The types of the fifth transistor M5, the sixth transistor M6, and the eighth transistor M8 are different from those of the seventh transistor M7 and the ninth transistor M9.

In this arrangement, the signal of the second control signal terminal EM2 and the signal of the first control signal terminal EM may be the same, so that, in the case where the first control signal terminal EM is a pull-up signal (high level signal), for example, the pixel circuit is in a reset phase and a data writing phase, the fifth transistor M5, the sixth transistor M6, and the eighth transistor M8 may be turned off under the control of the signal of the first control signal terminal EM, and the light emitting module 50 stops emitting light. The seventh transistor M7 and the ninth transistor M9 may be turned on under the signal control of the first control signal terminal EM, the signal of the second power supply terminal VSS is provided to the first node N1 through the seventh transistor M7, the signal of the first power supply terminal VDD is provided to the second node N2 through the ninth transistor M9, so that the light emitting module 50 enters the reverse bias state, and thus, the light emitting module 50 enters the detrapping state. In the detrapping state of the light emitting module 50, holes and electrons in the light emitting module 50 are released, so that the number of defects is reduced.

In this arrangement, the reverse bias state of the light emitting module 50 is in the reset phase and the data writing phase, and the time for additionally setting the reverse bias state for the light emitting module 50 is not required, so that the frame time of the display device is not affected.

In one embodiment, the fifth transistor M5, the sixth transistor M6, and the eighth transistor M8 may all be PMOS. The seventh transistor M7 and the ninth transistor M9 are both NMOS. Or the fifth transistor M5, the sixth transistor M6, and the eighth transistor M8 may all be NMOS. The seventh transistor M7 and the ninth transistor M9 are PMOS.

The driving module 10 in the pixel circuit shown in fig. 5 has a 6T1C structure, and it is understood that the driving module 10 is not limited to the 6T1C structure, and the driving module 10 may adopt a driving circuit capable of supplying a driving electric signal to the first node N1 in the related art as long as the function thereof can be realized.

In one embodiment, the fifth transistor M5, the sixth transistor M6, and the eighth transistor M8 may be the same type, the first to fourth transistors M1 to M4 may be the same type as the fifth transistor M5, or the first to fourth transistors M1 to M4 may be different type from the fifth transistor M5. For example, the first to fourth transistors M1 to M4, the fifth transistor M5, the sixth transistor M6, and the eighth transistor M8 may be PMOS, or the first to fourth transistors M1 to M4, the fifth transistor M5, the sixth transistor M6, and the eighth transistor M8 may be NMOS. The same type of transistor is adopted in the pixel circuit, so that the process flow can be simplified, the process difficulty is reduced, and the yield of products is improved. For example, the P-type transistor may be implemented by a low-temperature polysilicon thin film transistor or an amorphous silicon thin film transistor, and the N-type transistor may be implemented by an oxide thin film transistor or an amorphous silicon thin film transistor.

In one embodiment, the reverse bias time of the light emitting module 50 may be 4% to 6% of one frame time. That is, the time for supplying the signal of the second power source terminal VSS to the first node N1 and the signal of the first power source terminal VDD to the second node N2 may be 4% to 6% of one frame time. Illustratively, the time for which the light emitting module 50 is reverse biased may be 4%, 5% or 6% of one frame time.

The time for reversely biasing the light emitting module 50 can be 4% -6% of one frame time, so that the display duration of the light emitting module 50 is not affected, enough reverse bias time can be provided, the sufficient release of holes and electrons in the light emitting module 50 is ensured, the defect number is reduced to the maximum extent, the light emitting module 50 can be restored to an initial state when emitting light next time, the brightness difference of different area positions of the display panel when displaying a high-brightness picture is avoided, and the picture quality is improved.

It will be appreciated that the relationship between the reverse bias time and the frame time of the light emitting module 50 can be set according to the specific situation for different pixel circuits and display requirements, and is not limited herein.

FIG. 6 is a timing diagram of a pixel circuit according to an embodiment of the disclosure. The operation principle of the pixel circuit according to the embodiment of the present disclosure is described in detail below with reference to fig. 5 and 6.

The pixel circuit of the embodiment of the present disclosure may include a first stage T1 (may be called a reset stage), a second stage T2 (may be called a write data stage), and a third stage T3 (may be called a light emitting stage).

Fig. 7A is a schematic diagram illustrating an operation state of the pixel circuit shown in fig. 5 in a first stage. In the first stage ①, as shown in fig. 7A and 6, the signal of the first control signal terminal EM is a high level signal, the signal of the reset signal terminal Rst is an active level signal (e.g., a low level signal), and the signal of the scan signal terminal Gate is an inactive level signal (e.g., a high level signal). The first transistor M1 is turned on, and the first transistor M1 provides an initial signal of the initial signal terminal Vinit to the third node N3, so as to reset the third node N3. The second transistor M2 and the fourth transistor M4 are turned off, and the fifth transistor M5, the sixth transistor M6, and the eighth transistor M8 are turned off. The seventh transistor M7 and the ninth transistor M9 are turned on to supply the signal of the second power supply terminal VSS to the first node N1, for example, the anode (p-pole) of the light emitting module 50, and to supply the signal of the first power supply terminal VDD to the second node N2, for example, the cathode (N-pole) of the light emitting module 50, so that the light emitting module 50 is in a reverse bias state. Illustratively, the duration that the light emitting module 50 is in the reverse bias state may be controlled by controlling the duration that the first control signal terminal EM is a high level signal.

Fig. 7B is a schematic diagram illustrating an operating state of the pixel circuit shown in fig. 5 in a second stage. In the second stage ②, as shown in fig. 7B and 6, the signal of the first control signal terminal EM is kept as a high level signal, the signal of the reset signal terminal Rst is an inactive level signal (e.g., a high level signal), and the signal of the scan signal terminal Gate is an active level signal (e.g., a low level signal). The first transistor M1 is turned off, the second transistor M2 and the fourth transistor M4 are turned on under the control of the signal of the scan signal terminal Gate, the Data signal of the Data signal terminal Data is written into the third node N3, and the storage sub-module 13 stores the Data signal of the third node N3. The fifth transistor M5, the sixth transistor M6, and the eighth transistor M8 remain in an off state. The seventh transistor M7 and the ninth transistor M9 remain turned on so that the light emitting module 50 maintains a reverse bias state.

Fig. 7C is a schematic diagram illustrating an operating state of the pixel circuit shown in fig. 5 in a third stage. In the third stage ③, as shown in fig. 7C and 6, the signal of the first control signal terminal EM is a low level signal, the signal of the reset signal terminal Rst is kept as an inactive level signal (e.g., a high level signal), and the signal of the scan signal terminal Gate is an inactive level signal (e.g., a high level signal). The first transistor M1 is turned off, and the second transistor M2 and the fourth transistor M4 are turned off. The seventh transistor M7 and the ninth transistor M9 are turned off, and the reverse bias state of the light emitting module 50 ends. The fifth transistor M5, the sixth transistor M6, and the eighth transistor M8 are turned on, and supply the driving electric signal to the first node N1, the signal of the second power source terminal VSS to the second node N2, and the light emitting module 50 emits light.

In the pixel circuit of the embodiment of the disclosure, in the reset phase and the data writing phase, the light emitting module 50 is in a reverse bias state, so that holes and electrons in the light emitting module 50 are released, the defect number is reduced, the light emitting module 50 can be restored to an initial state when the light emitting module emits light next time, and the brightness drop of the light emitting module 50 due to the long-time maintenance of high brightness is avoided.

The test verifies that: the heating stage is used for providing a high-temperature environment of 60 ℃, and one frame time of the LEDs is 120s. The brightness of the LED drops by about 2.32% after 120s of lighting. The LED reverse bias voltage driving sequence is as follows: the forward voltage turns on the LED 90% of the time of a frame (e.g., p 4V for the LED and n 0V for the LED), and the reverse bias is 5% of the time (bias voltage is-4V for the LED and 0V for the n). With bias driving, the brightness of the LED drops by about 0.27% after 120s, and the problem of brightness drop is improved by 88.5%. After verification by experiments, the pixel circuit of the embodiment of the disclosure can improve the brightness degradation of the light emitting module 50 caused by long-time maintenance of high brightness, and improve the picture quality.

Fig. 8 is a schematic diagram of a driving method of a pixel circuit according to an embodiment of the disclosure. The embodiment of the disclosure also provides a driving method of the pixel circuit, which is suitable for the pixel circuit in the embodiment of the disclosure. As shown in fig. 8, the driving method of the pixel circuit may include: providing an initial signal of an initial signal terminal Vinit to the third node N3, providing a signal of a second power terminal VSS to the first node N1, and providing a signal of a first power terminal VDD to the second node N2; writing a Data signal of the Data signal terminal Data into the third node N3, providing a signal of the second power terminal VSS to the first node N1, and providing a signal of the first power terminal VDD to the second node N2; the driving electric signal is supplied to the first node N1, and the signal of the second power source terminal VSS is supplied to the second node N2.

In one embodiment, referring to fig. 6 and 7A, in the first phase, i.e., the reset phase, the reset sub-module 11 provides an initial signal of the initial signal terminal Vinit to the third node N3, resets the third node N3, and resets the driving sub-module 14; the signal of the second power supply terminal VSS is supplied to the first node N1 through the first bias module 20, and the signal of the first power supply terminal VDD is supplied to the second node N2 through the second bias module 30, so that the light emitting module 50 is in a reverse bias state. In the second phase, i.e., the Data writing phase, referring to fig. 6 and 7B, the Data signal of the Data signal terminal Data is written into the third node N3 and stored through the writing sub-module 12 and the driving sub-module 14; the light emitting module 50 maintains a reverse bias state. In the third stage, i.e., the light emitting stage, referring to fig. 6 and 7C, the light emitting module 50 is controlled to emit light by supplying a driving electric signal to the first node N1 and a signal of the second power source terminal VSS to the second node N2 through the switching control sub-module 15 and the driving sub-module 14.

It will be appreciated that in fig. 6 and fig. 7A to 7C, the operation principle and the driving process of the pixel circuit are described in detail, and are not described herein.

Based on the inventive concepts of the foregoing embodiments, the embodiments of the present disclosure also provide a display device including the pixel circuit in any one of the embodiments of the present disclosure. The display device may be an OLED display device or an LED display device, etc. The display device may be: any product or component with display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

In the description of the present specification, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present disclosure.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present disclosure, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

In the present disclosure, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; the device can be mechanically connected, electrically connected and communicated; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art as the case may be.

In this disclosure, unless expressly stated or limited otherwise, a first feature being "above" or "below" a second feature may include both the first and second features being in direct contact, as well as the first and second features not being in direct contact but being in contact with each other by way of additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is less level than the second feature.

The above disclosure provides many different embodiments or examples for implementing different structures of the disclosure. The components and arrangements of specific examples are described above in order to simplify the present disclosure. Of course, they are merely examples and are not intended to limit the present disclosure. Furthermore, the present disclosure may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not themselves indicate the relationship between the various embodiments and/or arrangements discussed.

The above is merely a specific embodiment of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think of various changes or substitutions within the technical scope of the disclosure, which should be covered in the protection scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A pixel circuit, comprising:

A first bias module coupled to the first node, the second control signal terminal, and the second power terminal, respectively, and configured to provide a signal of the second power terminal to the first node under control of the second control signal terminal;

A second bias module coupled to a second node, the second control signal terminal, and the first power terminal, respectively, and configured to provide a signal of the first power terminal to the second node under control of the second control signal terminal;

The switching module is respectively coupled with the second node, the first control signal end and the second power end, and is configured to be conducted under the control of the first control signal end to provide a signal of the second power end for the second node under the condition that a driving electric signal is provided for the first node; in the case of providing the signal of the second power supply terminal to the first node, providing the signal of the first power supply terminal to the second node, the switching module is configured to disconnect under control of the first control signal terminal, disconnecting the coupling between the second power supply terminal and the second node;

2. The pixel circuit of claim 1, wherein the pixel circuit comprises at least one of:

The first bias module comprises a seventh transistor, a grid electrode of the seventh transistor is coupled with the second control signal end, and a first pole and a second pole of the seventh transistor are respectively coupled with the first node and the second power end;

The second bias module comprises a ninth transistor, a grid electrode of the ninth transistor is coupled with the second control signal end, and a first pole and a second pole of the ninth transistor are respectively coupled with the second node and the first power end;

3. The pixel circuit of claim 1, wherein the signal at the second control signal terminal is the same as the signal at the first control signal terminal.

4. The pixel circuit of claim 1, wherein the light emitting module comprises a light emitting diode chip.

5. The pixel circuit of claim 1, wherein the reverse bias time of the light emitting module is 4% to 6% of a frame time.

6. The pixel circuit according to any one of claims 1 to 5, wherein the driving module comprises:

A reset sub-module respectively coupled to the initial signal terminal, the third node and the reset signal terminal, and configured to provide an initial signal of the initial signal terminal to the third node under control of the reset signal terminal;

A writing sub-module respectively coupled to the data signal terminal, the scanning signal terminal, the fourth node, the fifth node and the third node, and configured to provide a data signal of the data signal terminal to the third node under control of the scanning signal terminal;

A storage sub-module coupled to the third node and the first power supply terminal, respectively, and configured to store a data signal of the third node;

The switch control sub-module is coupled with the first power supply end, the fourth node, the fifth node, the first node and the first control signal end respectively, and is configured to provide driving electric signals to the first node through the fourth node, the driving sub-module and the fifth node based on the voltage of the first power supply end under the control of the first control signal end.

7. The pixel circuit of claim 6, wherein the drive module comprises at least one of:

the reset submodule comprises a first transistor, a grid electrode of the first transistor is coupled with the reset signal end, and a first pole and a second pole of the first transistor are respectively coupled with the initial signal end and the third node;

the storage submodule comprises a storage capacitor, and a first polar plate and a second polar plate of the storage capacitor are respectively coupled with the first power supply end and the third node;

The driving sub-module comprises a third transistor, a gate of the third transistor is coupled with the third node, and a first pole and a second pole of the third transistor are respectively coupled with the fourth node and the fifth node;

8. The pixel circuit of claim 6, wherein,

9. A driving method of a pixel circuit, characterized in that it is applied to the pixel circuit according to any one of claims 6 to 8, the method comprising:

Writing a data signal of a data signal end into the third node, providing a signal of the second power end for the first node, and providing a signal of the first power end for the second node;

And providing a driving electric signal for the first node and providing a signal of the second power supply terminal for the second node.

10. A display device comprising the pixel circuit according to any one of claims 1 to 8.